SYSRST_CTRL Simulation Results

Saturday March 25 2023 07:06:46 UTC

GitHub Revision: 8b50eb41f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2145637544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.370s 2.115ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 7.860s 2.407ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.600s 2.404ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 7.670s 2.511ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 11.310s 4.018ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.520s 2.057ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.677m 45.231ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 11.050s 3.008ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.320s 2.101ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.520s 2.057ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.050s 3.008ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 7.246m 157.051ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 5.519m 126.590ms 100 100 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 8.490m 181.399ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 23.394m 1.254s 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.700s 2.512ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.390s 2.259ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 4.885m 230.770ms 50 50 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 7.960s 2.614ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 4.283m 1.620s 50 50 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 43.270s 31.148ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 22.519m 796.245ms 46 50 92.00
V2 alert_test sysrst_ctrl_alert_test 5.980s 2.010ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.250s 2.009ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 7.570s 2.117ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 7.570s 2.117ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 11.310s 4.018ms 5 5 100.00
sysrst_ctrl_csr_rw 6.520s 2.057ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.050s 3.008ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 34.200s 6.969ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 11.310s 4.018ms 5 5 100.00
sysrst_ctrl_csr_rw 6.520s 2.057ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.050s 3.008ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 34.200s 6.969ms 20 20 100.00
V2 TOTAL 688 692 99.42
V2S tl_intg_err sysrst_ctrl_sec_cm 1.765m 42.011ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.924m 42.407ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.924m 42.407ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 7.124m 1.440s 35 50 70.00
V3 TOTAL 35 50 70.00
TOTAL 913 932 97.96

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 14 93.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.32 99.44 96.09 100.00 98.72 98.78 99.81 88.37

Failure Buckets

Past Results