8b50eb41f
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | sysrst_ctrl_smoke | 6.370s | 2.115ms | 50 | 50 | 100.00 |
V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 7.860s | 2.407ms | 50 | 50 | 100.00 |
V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 6.600s | 2.404ms | 5 | 5 | 100.00 |
V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 7.670s | 2.511ms | 5 | 5 | 100.00 |
V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 11.310s | 4.018ms | 5 | 5 | 100.00 |
V1 | csr_rw | sysrst_ctrl_csr_rw | 6.520s | 2.057ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 1.677m | 45.231ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 11.050s | 3.008ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 6.320s | 2.101ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 6.520s | 2.057ms | 20 | 20 | 100.00 |
sysrst_ctrl_csr_aliasing | 11.050s | 3.008ms | 5 | 5 | 100.00 | ||
V1 | TOTAL | 165 | 165 | 100.00 | |||
V2 | combo_detect | sysrst_ctrl_combo_detect | 7.246m | 157.051ms | 50 | 50 | 100.00 |
V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 5.519m | 126.590ms | 100 | 100 | 100.00 |
V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 8.490m | 181.399ms | 50 | 50 | 100.00 |
V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 23.394m | 1.254s | 50 | 50 | 100.00 |
V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 7.700s | 2.512ms | 50 | 50 | 100.00 |
V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 6.390s | 2.259ms | 50 | 50 | 100.00 |
V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 4.885m | 230.770ms | 50 | 50 | 100.00 |
V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 7.960s | 2.614ms | 50 | 50 | 100.00 |
V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 4.283m | 1.620s | 50 | 50 | 100.00 |
V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 43.270s | 31.148ms | 2 | 2 | 100.00 |
V2 | stress_all | sysrst_ctrl_stress_all | 22.519m | 796.245ms | 46 | 50 | 92.00 |
V2 | alert_test | sysrst_ctrl_alert_test | 5.980s | 2.010ms | 50 | 50 | 100.00 |
V2 | intr_test | sysrst_ctrl_intr_test | 6.250s | 2.009ms | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 7.570s | 2.117ms | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 7.570s | 2.117ms | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 11.310s | 4.018ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.520s | 2.057ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 11.050s | 3.008ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 34.200s | 6.969ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 11.310s | 4.018ms | 5 | 5 | 100.00 |
sysrst_ctrl_csr_rw | 6.520s | 2.057ms | 20 | 20 | 100.00 | ||
sysrst_ctrl_csr_aliasing | 11.050s | 3.008ms | 5 | 5 | 100.00 | ||
sysrst_ctrl_same_csr_outstanding | 34.200s | 6.969ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 688 | 692 | 99.42 | |||
V2S | tl_intg_err | sysrst_ctrl_sec_cm | 1.765m | 42.011ms | 5 | 5 | 100.00 |
sysrst_ctrl_tl_intg_err | 1.924m | 42.407ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 1.924m | 42.407ms | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 7.124m | 1.440s | 35 | 50 | 70.00 |
V3 | TOTAL | 35 | 50 | 70.00 | |||
TOTAL | 913 | 932 | 97.96 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 15 | 15 | 14 | 93.33 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.32 | 99.44 | 96.09 | 100.00 | 98.72 | 98.78 | 99.81 | 88.37 |
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
has 18 failures:
0.sysrst_ctrl_stress_all_with_rand_reset.4236644019
Line 545, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18782760135 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 19057760135 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 19057760135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.sysrst_ctrl_stress_all_with_rand_reset.3613889827
Line 546, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 17035910072 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_ERROR @ 17075910072 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 17075910072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.sysrst_ctrl_stress_all.1536004415
Line 531, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 10192335435 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 10619363602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.sysrst_ctrl_stress_all.1214699442
Line 537, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 11261782525 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:108) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 13319831759 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_auto_blk_key_output_vseq
UVM_INFO @ 15319311759 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:76) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Starting the body from auto_blk_key_output_vseq
UVM_INFO @ 15319351759 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 5e
UVM_INFO @ 15824282525 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:89
... and 2 more failures.
UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*])
has 1 failures:
2.sysrst_ctrl_stress_all_with_rand_reset.1101572604
Line 581, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 32570932540 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 32572977179 ps: (cip_base_vseq.sv:719) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
Stress w/ reset is done for run 5/5
UVM_INFO @ 32598449270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---