SYSRST_CTRL Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.550s 2.112ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 8.150s 2.475ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.840s 2.415ms 4 5 80.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.110s 2.349ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 16.930s 6.039ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.740s 2.041ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 3.457m 38.975ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 12.100s 3.337ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.950s 2.136ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.740s 2.041ms 20 20 100.00
sysrst_ctrl_csr_aliasing 12.100s 3.337ms 5 5 100.00
V1 TOTAL 164 165 99.39
V2 combo_detect sysrst_ctrl_combo_detect 8.725m 194.154ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 7.889m 170.015ms 98 100 98.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 8.365m 188.633ms 50 50 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 8.746m 1.181s 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.970s 2.512ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.780s 2.237ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 50.706m 1.123s 49 50 98.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 8.200s 2.611ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 11.716m 3.135s 45 50 90.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 26.280s 39.716ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 9.521m 226.150ms 50 50 100.00
V2 alert_test sysrst_ctrl_alert_test 6.110s 2.011ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.270s 2.013ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 8.240s 2.146ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 8.240s 2.146ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 16.930s 6.039ms 5 5 100.00
sysrst_ctrl_csr_rw 6.740s 2.041ms 20 20 100.00
sysrst_ctrl_csr_aliasing 12.100s 3.337ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 47.630s 10.984ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 16.930s 6.039ms 5 5 100.00
sysrst_ctrl_csr_rw 6.740s 2.041ms 20 20 100.00
sysrst_ctrl_csr_aliasing 12.100s 3.337ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 47.630s 10.984ms 20 20 100.00
V2 TOTAL 684 692 98.84
V2S tl_intg_err sysrst_ctrl_sec_cm 1.894m 42.012ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.993m 42.407ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.993m 42.407ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 4.396m 1.419s 42 50 84.00
V3 TOTAL 42 50 84.00
TOTAL 915 932 98.18

Testplan Progress

Items Total Written Passing Progress
V1 9 9 8 88.89
V2 15 15 12 80.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.10 99.44 96.81 100.00 98.08 98.93 99.71 93.70

Failure Buckets

Past Results