Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
951 |
1 |
|
|
T31 |
13 |
|
T66 |
12 |
|
T80 |
13 |
| auto[1] |
889 |
1 |
|
|
T31 |
7 |
|
T66 |
8 |
|
T80 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T31 |
12 |
|
T66 |
10 |
|
T80 |
9 |
| auto[1] |
931 |
1 |
|
|
T31 |
8 |
|
T66 |
10 |
|
T80 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T31 |
11 |
|
T66 |
8 |
|
T80 |
9 |
| auto[1] |
941 |
1 |
|
|
T31 |
9 |
|
T66 |
12 |
|
T80 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T31 |
12 |
|
T66 |
11 |
|
T80 |
9 |
| auto[1] |
939 |
1 |
|
|
T31 |
8 |
|
T66 |
9 |
|
T80 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T31 |
7 |
|
T66 |
13 |
|
T80 |
9 |
| auto[1] |
923 |
1 |
|
|
T31 |
13 |
|
T66 |
7 |
|
T80 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
962 |
1 |
|
|
T31 |
9 |
|
T66 |
12 |
|
T80 |
15 |
| auto[1] |
878 |
1 |
|
|
T31 |
11 |
|
T66 |
8 |
|
T80 |
5 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T31 |
9 |
|
T66 |
10 |
|
T80 |
8 |
| auto[1] |
923 |
1 |
|
|
T31 |
11 |
|
T66 |
10 |
|
T80 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
916 |
1 |
|
|
T31 |
13 |
|
T66 |
5 |
|
T80 |
9 |
| auto[1] |
924 |
1 |
|
|
T31 |
7 |
|
T66 |
15 |
|
T80 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T31 |
6 |
|
T66 |
11 |
|
T80 |
9 |
| auto[1] |
926 |
1 |
|
|
T31 |
14 |
|
T66 |
9 |
|
T80 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
879 |
1 |
|
|
T31 |
12 |
|
T66 |
10 |
|
T80 |
10 |
| auto[1] |
961 |
1 |
|
|
T31 |
8 |
|
T66 |
10 |
|
T80 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T31 |
2 |
|
T66 |
14 |
|
T80 |
8 |
| auto[1] |
931 |
1 |
|
|
T31 |
18 |
|
T66 |
6 |
|
T80 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
918 |
1 |
|
|
T31 |
10 |
|
T66 |
11 |
|
T80 |
10 |
| auto[1] |
922 |
1 |
|
|
T31 |
10 |
|
T66 |
9 |
|
T80 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
949 |
1 |
|
|
T31 |
9 |
|
T66 |
9 |
|
T80 |
7 |
| auto[1] |
891 |
1 |
|
|
T31 |
11 |
|
T66 |
11 |
|
T80 |
13 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T31 |
12 |
|
T66 |
10 |
|
T80 |
9 |
| auto[1] |
931 |
1 |
|
|
T31 |
8 |
|
T66 |
10 |
|
T80 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
932 |
1 |
|
|
T31 |
10 |
|
T66 |
9 |
|
T80 |
12 |
| auto[1] |
908 |
1 |
|
|
T31 |
10 |
|
T66 |
11 |
|
T80 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
936 |
1 |
|
|
T31 |
15 |
|
T66 |
10 |
|
T80 |
14 |
| auto[1] |
904 |
1 |
|
|
T31 |
5 |
|
T66 |
10 |
|
T80 |
6 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
925 |
1 |
|
|
T31 |
9 |
|
T66 |
8 |
|
T80 |
8 |
| auto[1] |
915 |
1 |
|
|
T31 |
11 |
|
T66 |
12 |
|
T80 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
910 |
1 |
|
|
T31 |
7 |
|
T66 |
9 |
|
T80 |
8 |
| auto[1] |
930 |
1 |
|
|
T31 |
13 |
|
T66 |
11 |
|
T80 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
909 |
1 |
|
|
T31 |
12 |
|
T66 |
9 |
|
T80 |
10 |
| auto[1] |
931 |
1 |
|
|
T31 |
8 |
|
T66 |
11 |
|
T80 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T31 |
10 |
|
T66 |
8 |
|
T80 |
9 |
| auto[1] |
936 |
1 |
|
|
T31 |
10 |
|
T66 |
12 |
|
T80 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
932 |
1 |
|
|
T31 |
13 |
|
T66 |
8 |
|
T80 |
11 |
| auto[1] |
908 |
1 |
|
|
T31 |
7 |
|
T66 |
12 |
|
T80 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
937 |
1 |
|
|
T31 |
14 |
|
T66 |
10 |
|
T80 |
13 |
| auto[1] |
903 |
1 |
|
|
T31 |
6 |
|
T66 |
10 |
|
T80 |
7 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
935 |
1 |
|
|
T31 |
8 |
|
T66 |
10 |
|
T80 |
9 |
| auto[1] |
905 |
1 |
|
|
T31 |
12 |
|
T66 |
10 |
|
T80 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
918 |
1 |
|
|
T31 |
10 |
|
T66 |
11 |
|
T80 |
10 |
| auto[1] |
922 |
1 |
|
|
T31 |
10 |
|
T66 |
9 |
|
T80 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
454 |
1 |
|
|
T31 |
6 |
|
T66 |
1 |
|
T80 |
5 |
| auto[0] |
auto[1] |
478 |
1 |
|
|
T31 |
4 |
|
T66 |
8 |
|
T80 |
7 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T31 |
5 |
|
T66 |
7 |
|
T80 |
4 |
| auto[1] |
auto[1] |
463 |
1 |
|
|
T31 |
5 |
|
T66 |
4 |
|
T80 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
457 |
1 |
|
|
T31 |
9 |
|
T66 |
3 |
|
T80 |
6 |
| auto[0] |
auto[1] |
479 |
1 |
|
|
T31 |
6 |
|
T66 |
7 |
|
T80 |
8 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T31 |
3 |
|
T66 |
8 |
|
T80 |
3 |
| auto[1] |
auto[1] |
460 |
1 |
|
|
T31 |
2 |
|
T66 |
2 |
|
T80 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
473 |
1 |
|
|
T31 |
2 |
|
T66 |
7 |
|
T80 |
3 |
| auto[0] |
auto[1] |
452 |
1 |
|
|
T31 |
7 |
|
T66 |
1 |
|
T80 |
5 |
| auto[1] |
auto[0] |
444 |
1 |
|
|
T31 |
5 |
|
T66 |
6 |
|
T80 |
6 |
| auto[1] |
auto[1] |
471 |
1 |
|
|
T31 |
6 |
|
T66 |
6 |
|
T80 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
488 |
1 |
|
|
T31 |
2 |
|
T66 |
7 |
|
T80 |
6 |
| auto[0] |
auto[1] |
422 |
1 |
|
|
T31 |
5 |
|
T66 |
2 |
|
T80 |
2 |
| auto[1] |
auto[0] |
474 |
1 |
|
|
T31 |
7 |
|
T66 |
5 |
|
T80 |
9 |
| auto[1] |
auto[1] |
456 |
1 |
|
|
T31 |
6 |
|
T66 |
6 |
|
T80 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
464 |
1 |
|
|
T31 |
6 |
|
T66 |
4 |
|
T80 |
6 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T31 |
6 |
|
T66 |
5 |
|
T80 |
4 |
| auto[1] |
auto[0] |
453 |
1 |
|
|
T31 |
3 |
|
T66 |
6 |
|
T80 |
2 |
| auto[1] |
auto[1] |
478 |
1 |
|
|
T31 |
5 |
|
T66 |
5 |
|
T80 |
8 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
461 |
1 |
|
|
T31 |
7 |
|
T66 |
1 |
|
T80 |
6 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T31 |
3 |
|
T66 |
7 |
|
T80 |
3 |
| auto[1] |
auto[0] |
455 |
1 |
|
|
T31 |
6 |
|
T66 |
4 |
|
T80 |
3 |
| auto[1] |
auto[1] |
481 |
1 |
|
|
T31 |
4 |
|
T66 |
8 |
|
T80 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
454 |
1 |
|
|
T31 |
9 |
|
T66 |
4 |
|
T80 |
6 |
| auto[0] |
auto[1] |
483 |
1 |
|
|
T31 |
5 |
|
T66 |
6 |
|
T80 |
7 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T31 |
3 |
|
T66 |
6 |
|
T80 |
4 |
| auto[1] |
auto[1] |
478 |
1 |
|
|
T31 |
3 |
|
T66 |
4 |
|
T80 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
468 |
1 |
|
|
T31 |
1 |
|
T66 |
6 |
|
T80 |
3 |
| auto[0] |
auto[1] |
467 |
1 |
|
|
T31 |
7 |
|
T66 |
4 |
|
T80 |
6 |
| auto[1] |
auto[0] |
441 |
1 |
|
|
T31 |
1 |
|
T66 |
8 |
|
T80 |
5 |
| auto[1] |
auto[1] |
464 |
1 |
|
|
T31 |
11 |
|
T66 |
2 |
|
T80 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
499 |
1 |
|
|
T31 |
5 |
|
T66 |
5 |
|
T80 |
6 |
| auto[0] |
auto[1] |
450 |
1 |
|
|
T31 |
4 |
|
T66 |
4 |
|
T80 |
1 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T31 |
8 |
|
T66 |
7 |
|
T80 |
7 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T31 |
3 |
|
T66 |
4 |
|
T80 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
909 |
1 |
|
|
T31 |
12 |
|
T66 |
10 |
|
T80 |
9 |
| auto[1] |
auto[1] |
931 |
1 |
|
|
T31 |
8 |
|
T66 |
10 |
|
T80 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
476 |
1 |
|
|
T31 |
4 |
|
T66 |
6 |
|
T80 |
7 |
| auto[0] |
auto[1] |
456 |
1 |
|
|
T31 |
9 |
|
T66 |
2 |
|
T80 |
4 |
| auto[1] |
auto[0] |
438 |
1 |
|
|
T31 |
2 |
|
T66 |
5 |
|
T80 |
2 |
| auto[1] |
auto[1] |
470 |
1 |
|
|
T31 |
5 |
|
T66 |
7 |
|
T80 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
918 |
1 |
|
|
T31 |
10 |
|
T66 |
11 |
|
T80 |
10 |
| auto[1] |
auto[1] |
922 |
1 |
|
|
T31 |
10 |
|
T66 |
9 |
|
T80 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T21 |
10 |
|
T54 |
10 |
|
T45 |
10 |
| auto[1] |
181 |
1 |
|
|
T21 |
10 |
|
T54 |
10 |
|
T45 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T21 |
12 |
|
T54 |
10 |
|
T45 |
11 |
| auto[1] |
189 |
1 |
|
|
T21 |
8 |
|
T54 |
10 |
|
T45 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T21 |
8 |
|
T54 |
9 |
|
T45 |
9 |
| auto[1] |
178 |
1 |
|
|
T21 |
12 |
|
T54 |
11 |
|
T45 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T21 |
12 |
|
T54 |
9 |
|
T45 |
10 |
| auto[1] |
179 |
1 |
|
|
T21 |
8 |
|
T54 |
11 |
|
T45 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
187 |
1 |
|
|
T21 |
12 |
|
T54 |
11 |
|
T45 |
9 |
| auto[1] |
173 |
1 |
|
|
T21 |
8 |
|
T54 |
9 |
|
T45 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T21 |
9 |
|
T54 |
14 |
|
T45 |
12 |
| auto[1] |
185 |
1 |
|
|
T21 |
11 |
|
T54 |
6 |
|
T45 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
177 |
1 |
|
|
T21 |
12 |
|
T54 |
10 |
|
T45 |
8 |
| auto[1] |
183 |
1 |
|
|
T21 |
8 |
|
T54 |
10 |
|
T45 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
193 |
1 |
|
|
T21 |
11 |
|
T54 |
11 |
|
T45 |
10 |
| auto[1] |
167 |
1 |
|
|
T21 |
9 |
|
T54 |
9 |
|
T45 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
185 |
1 |
|
|
T21 |
12 |
|
T54 |
9 |
|
T45 |
7 |
| auto[1] |
175 |
1 |
|
|
T21 |
8 |
|
T54 |
11 |
|
T45 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T21 |
10 |
|
T54 |
9 |
|
T45 |
12 |
| auto[1] |
186 |
1 |
|
|
T21 |
10 |
|
T54 |
11 |
|
T45 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
184 |
1 |
|
|
T21 |
10 |
|
T54 |
11 |
|
T45 |
13 |
| auto[1] |
176 |
1 |
|
|
T21 |
10 |
|
T54 |
9 |
|
T45 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T21 |
8 |
|
T54 |
12 |
|
T45 |
14 |
| auto[1] |
187 |
1 |
|
|
T21 |
12 |
|
T54 |
8 |
|
T45 |
6 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T21 |
9 |
|
T54 |
8 |
|
T45 |
10 |
| auto[1] |
177 |
1 |
|
|
T21 |
11 |
|
T54 |
12 |
|
T45 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T21 |
12 |
|
T54 |
10 |
|
T45 |
11 |
| auto[1] |
189 |
1 |
|
|
T21 |
8 |
|
T54 |
10 |
|
T45 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T21 |
8 |
|
T54 |
9 |
|
T45 |
11 |
| auto[1] |
186 |
1 |
|
|
T21 |
12 |
|
T54 |
11 |
|
T45 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T21 |
8 |
|
T54 |
13 |
|
T45 |
8 |
| auto[1] |
177 |
1 |
|
|
T21 |
12 |
|
T54 |
7 |
|
T45 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
185 |
1 |
|
|
T21 |
9 |
|
T54 |
11 |
|
T45 |
11 |
| auto[1] |
175 |
1 |
|
|
T21 |
11 |
|
T54 |
9 |
|
T45 |
9 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T21 |
10 |
|
T54 |
10 |
|
T45 |
8 |
| auto[1] |
189 |
1 |
|
|
T21 |
10 |
|
T54 |
10 |
|
T45 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
168 |
1 |
|
|
T21 |
10 |
|
T54 |
10 |
|
T45 |
11 |
| auto[1] |
192 |
1 |
|
|
T21 |
10 |
|
T54 |
10 |
|
T45 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
198 |
1 |
|
|
T21 |
9 |
|
T54 |
13 |
|
T45 |
13 |
| auto[1] |
162 |
1 |
|
|
T21 |
11 |
|
T54 |
7 |
|
T45 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T21 |
10 |
|
T54 |
11 |
|
T45 |
8 |
| auto[1] |
191 |
1 |
|
|
T21 |
10 |
|
T54 |
9 |
|
T45 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T21 |
10 |
|
T54 |
12 |
|
T45 |
11 |
| auto[1] |
185 |
1 |
|
|
T21 |
10 |
|
T54 |
8 |
|
T45 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
189 |
1 |
|
|
T21 |
12 |
|
T54 |
10 |
|
T45 |
10 |
| auto[1] |
171 |
1 |
|
|
T21 |
8 |
|
T54 |
10 |
|
T45 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T21 |
8 |
|
T54 |
12 |
|
T45 |
14 |
| auto[1] |
187 |
1 |
|
|
T21 |
12 |
|
T54 |
8 |
|
T45 |
6 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
88 |
1 |
|
|
T21 |
3 |
|
T54 |
3 |
|
T45 |
4 |
| auto[0] |
auto[1] |
86 |
1 |
|
|
T21 |
5 |
|
T54 |
6 |
|
T45 |
7 |
| auto[1] |
auto[0] |
94 |
1 |
|
|
T21 |
5 |
|
T54 |
6 |
|
T45 |
5 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T21 |
7 |
|
T54 |
5 |
|
T45 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
92 |
1 |
|
|
T21 |
5 |
|
T54 |
5 |
|
T45 |
3 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T21 |
3 |
|
T54 |
8 |
|
T45 |
5 |
| auto[1] |
auto[0] |
89 |
1 |
|
|
T21 |
7 |
|
T54 |
4 |
|
T45 |
7 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T21 |
5 |
|
T54 |
3 |
|
T45 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
87 |
1 |
|
|
T21 |
6 |
|
T54 |
7 |
|
T45 |
4 |
| auto[0] |
auto[1] |
98 |
1 |
|
|
T21 |
3 |
|
T54 |
4 |
|
T45 |
7 |
| auto[1] |
auto[0] |
100 |
1 |
|
|
T21 |
6 |
|
T54 |
4 |
|
T45 |
5 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T21 |
5 |
|
T54 |
5 |
|
T45 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T21 |
5 |
|
T54 |
8 |
|
T45 |
4 |
| auto[0] |
auto[1] |
97 |
1 |
|
|
T21 |
5 |
|
T54 |
2 |
|
T45 |
4 |
| auto[1] |
auto[0] |
101 |
1 |
|
|
T21 |
4 |
|
T54 |
6 |
|
T45 |
8 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T21 |
6 |
|
T54 |
4 |
|
T45 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T21 |
4 |
|
T54 |
5 |
|
T45 |
3 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T21 |
6 |
|
T54 |
5 |
|
T45 |
8 |
| auto[1] |
auto[0] |
100 |
1 |
|
|
T21 |
8 |
|
T54 |
5 |
|
T45 |
5 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T21 |
2 |
|
T54 |
5 |
|
T45 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
100 |
1 |
|
|
T21 |
3 |
|
T54 |
7 |
|
T45 |
5 |
| auto[0] |
auto[1] |
98 |
1 |
|
|
T21 |
6 |
|
T54 |
6 |
|
T45 |
8 |
| auto[1] |
auto[0] |
93 |
1 |
|
|
T21 |
8 |
|
T54 |
4 |
|
T45 |
5 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T21 |
3 |
|
T54 |
3 |
|
T45 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
96 |
1 |
|
|
T21 |
8 |
|
T54 |
6 |
|
T45 |
7 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T21 |
2 |
|
T54 |
6 |
|
T45 |
4 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T21 |
2 |
|
T54 |
3 |
|
T45 |
5 |
| auto[1] |
auto[1] |
107 |
1 |
|
|
T21 |
8 |
|
T54 |
5 |
|
T45 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
108 |
1 |
|
|
T21 |
9 |
|
T54 |
6 |
|
T45 |
7 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T21 |
3 |
|
T54 |
4 |
|
T45 |
3 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T21 |
1 |
|
T54 |
5 |
|
T45 |
6 |
| auto[1] |
auto[1] |
95 |
1 |
|
|
T21 |
7 |
|
T54 |
5 |
|
T45 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
94 |
1 |
|
|
T21 |
3 |
|
T54 |
5 |
|
T45 |
6 |
| auto[0] |
auto[1] |
89 |
1 |
|
|
T21 |
6 |
|
T54 |
3 |
|
T45 |
4 |
| auto[1] |
auto[0] |
85 |
1 |
|
|
T21 |
7 |
|
T54 |
5 |
|
T45 |
4 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T21 |
4 |
|
T54 |
7 |
|
T45 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
171 |
1 |
|
|
T21 |
12 |
|
T54 |
10 |
|
T45 |
11 |
| auto[1] |
auto[1] |
189 |
1 |
|
|
T21 |
8 |
|
T54 |
10 |
|
T45 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T21 |
7 |
|
T54 |
6 |
|
T45 |
1 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T21 |
3 |
|
T54 |
5 |
|
T45 |
7 |
| auto[1] |
auto[0] |
95 |
1 |
|
|
T21 |
5 |
|
T54 |
3 |
|
T45 |
6 |
| auto[1] |
auto[1] |
96 |
1 |
|
|
T21 |
5 |
|
T54 |
6 |
|
T45 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
173 |
1 |
|
|
T21 |
8 |
|
T54 |
12 |
|
T45 |
14 |
| auto[1] |
auto[1] |
187 |
1 |
|
|
T21 |
12 |
|
T54 |
8 |
|
T45 |
6 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T206 |
13 |
|
T210 |
7 |
|
T94 |
11 |
| auto[1] |
76 |
1 |
|
|
T206 |
7 |
|
T210 |
13 |
|
T94 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
76 |
1 |
|
|
T206 |
12 |
|
T210 |
11 |
|
T94 |
8 |
| auto[1] |
84 |
1 |
|
|
T206 |
8 |
|
T210 |
9 |
|
T94 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T206 |
9 |
|
T210 |
12 |
|
T94 |
11 |
| auto[1] |
77 |
1 |
|
|
T206 |
11 |
|
T210 |
8 |
|
T94 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T206 |
5 |
|
T210 |
9 |
|
T94 |
10 |
| auto[1] |
90 |
1 |
|
|
T206 |
15 |
|
T210 |
11 |
|
T94 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T206 |
12 |
|
T210 |
10 |
|
T94 |
13 |
| auto[1] |
75 |
1 |
|
|
T206 |
8 |
|
T210 |
10 |
|
T94 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T206 |
8 |
|
T210 |
9 |
|
T94 |
11 |
| auto[1] |
79 |
1 |
|
|
T206 |
12 |
|
T210 |
11 |
|
T94 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T206 |
7 |
|
T210 |
9 |
|
T94 |
12 |
| auto[1] |
82 |
1 |
|
|
T206 |
13 |
|
T210 |
11 |
|
T94 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T206 |
11 |
|
T210 |
11 |
|
T94 |
8 |
| auto[1] |
66 |
1 |
|
|
T206 |
9 |
|
T210 |
9 |
|
T94 |
12 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T206 |
9 |
|
T210 |
8 |
|
T94 |
12 |
| auto[1] |
75 |
1 |
|
|
T206 |
11 |
|
T210 |
12 |
|
T94 |
8 |