Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.55 99.29 96.26 100.00 95.51 98.68 99.34 93.79


Total tests in report: 914
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
54.15 54.15 72.36 72.36 66.17 66.17 87.02 87.02 0.00 0.00 75.84 75.84 57.49 57.49 20.15 20.15 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1715846982
68.20 14.05 72.41 0.05 67.29 1.12 87.02 0.00 95.51 95.51 75.88 0.03 57.68 0.19 21.59 1.44 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1647984451
77.90 9.71 86.23 13.82 78.57 11.28 93.62 6.61 95.51 0.00 87.16 11.28 74.53 16.85 29.69 8.10 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.2378675997
83.51 5.60 90.24 4.01 82.88 4.31 95.67 2.05 95.51 0.00 90.08 2.92 82.21 7.68 47.95 18.26 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.185328396
85.88 2.37 92.33 2.08 84.84 1.95 96.13 0.46 95.51 0.00 91.79 1.71 87.08 4.87 53.49 5.54 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2461138787
88.00 2.12 94.55 2.22 86.60 1.76 97.95 1.82 95.51 0.00 93.32 1.53 90.82 3.75 57.23 3.74 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3542234909
90.08 2.08 94.63 0.09 86.65 0.05 97.95 0.00 95.51 0.00 93.49 0.17 90.92 0.09 71.38 14.15 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.4285394240
91.36 1.28 96.25 1.61 88.10 1.45 97.95 0.00 95.51 0.00 94.81 1.32 95.04 4.12 71.85 0.46 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.702029729
92.53 1.17 96.60 0.35 89.96 1.86 99.09 1.14 95.51 0.00 95.37 0.56 95.22 0.19 75.95 4.10 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3015789675
93.41 0.89 97.20 0.61 93.97 4.00 99.09 0.00 95.51 0.00 96.21 0.84 95.97 0.75 75.95 0.00 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1494422724
93.96 0.54 97.26 0.05 94.16 0.19 99.09 0.00 95.51 0.00 96.24 0.03 96.07 0.09 79.38 3.44 /workspace/coverage/default/45.sysrst_ctrl_stress_all.817951842
94.38 0.42 97.33 0.07 94.23 0.07 99.09 0.00 95.51 0.00 96.35 0.10 96.07 0.00 82.10 2.72 /workspace/coverage/default/1.sysrst_ctrl_stress_all.131924817
94.73 0.35 97.34 0.02 94.45 0.21 99.32 0.23 95.51 0.00 96.41 0.07 96.07 0.00 84.00 1.90 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2168080030
95.06 0.33 98.35 1.01 94.66 0.21 99.32 0.00 95.51 0.00 97.49 1.08 96.07 0.00 84.00 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.4035432768
95.31 0.25 98.37 0.02 94.83 0.17 99.32 0.00 95.51 0.00 97.56 0.07 96.16 0.09 85.44 1.44 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.419220928
95.50 0.19 98.58 0.21 95.04 0.21 99.32 0.00 95.51 0.00 97.84 0.28 96.72 0.56 85.49 0.05 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1641253290
95.68 0.18 98.78 0.21 95.18 0.14 99.32 0.00 95.51 0.00 98.02 0.17 97.38 0.66 85.54 0.05 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3027909809
95.82 0.15 98.89 0.10 95.26 0.07 99.32 0.00 95.51 0.00 98.12 0.10 97.66 0.28 86.00 0.46 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1646571993
95.96 0.14 98.92 0.03 95.30 0.05 99.32 0.00 95.51 0.00 98.16 0.03 97.85 0.19 86.67 0.67 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1041890154
96.09 0.13 98.92 0.00 95.33 0.02 100.00 0.68 95.51 0.00 98.16 0.00 97.94 0.09 86.77 0.10 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2649189902
96.22 0.13 98.92 0.00 95.33 0.00 100.00 0.00 95.51 0.00 98.16 0.00 98.41 0.47 87.18 0.41 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2206482119
96.32 0.10 98.92 0.00 95.33 0.00 100.00 0.00 95.51 0.00 98.16 0.00 98.41 0.00 87.90 0.72 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1698610615
96.42 0.10 99.01 0.09 95.47 0.14 100.00 0.00 95.51 0.00 98.33 0.17 98.69 0.28 87.90 0.00 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1171915283
96.51 0.10 99.01 0.00 95.47 0.00 100.00 0.00 95.51 0.00 98.33 0.00 98.69 0.00 88.56 0.67 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.1011914420
96.60 0.09 99.01 0.00 95.47 0.00 100.00 0.00 95.51 0.00 98.33 0.00 98.69 0.00 89.18 0.62 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2546349230
96.67 0.07 99.01 0.00 95.49 0.02 100.00 0.00 95.51 0.00 98.33 0.00 98.69 0.00 89.64 0.46 /workspace/coverage/default/20.sysrst_ctrl_stress_all.2737100397
96.73 0.07 99.01 0.00 95.49 0.00 100.00 0.00 95.51 0.00 98.33 0.00 98.69 0.00 90.10 0.46 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1698139934
96.80 0.06 99.04 0.03 95.52 0.02 100.00 0.00 95.51 0.00 98.36 0.03 98.78 0.09 90.36 0.26 /workspace/coverage/default/35.sysrst_ctrl_stress_all.3609569471
96.86 0.06 99.04 0.00 95.52 0.00 100.00 0.00 95.51 0.00 98.36 0.00 98.78 0.00 90.77 0.41 /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1016900500
96.91 0.06 99.04 0.00 95.52 0.00 100.00 0.00 95.51 0.00 98.36 0.00 98.78 0.00 91.18 0.41 /workspace/coverage/default/5.sysrst_ctrl_stress_all.3100226076
96.97 0.05 99.04 0.00 95.90 0.38 100.00 0.00 95.51 0.00 98.36 0.00 98.78 0.00 91.18 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2782153986
97.02 0.05 99.10 0.05 95.92 0.02 100.00 0.00 95.51 0.00 98.43 0.07 98.88 0.09 91.28 0.10 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2412795318
97.06 0.04 99.10 0.00 95.92 0.00 100.00 0.00 95.51 0.00 98.43 0.00 98.88 0.00 91.59 0.31 /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3870958108
97.11 0.04 99.10 0.00 95.92 0.00 100.00 0.00 95.51 0.00 98.43 0.00 98.88 0.00 91.90 0.31 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.4017346772
97.14 0.03 99.15 0.05 95.95 0.02 100.00 0.00 95.51 0.00 98.50 0.07 98.97 0.09 91.90 0.00 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1537152376
97.17 0.03 99.18 0.03 95.97 0.02 100.00 0.00 95.51 0.00 98.54 0.03 99.06 0.09 91.95 0.05 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.10187579
97.20 0.03 99.18 0.00 95.97 0.00 100.00 0.00 95.51 0.00 98.54 0.00 99.06 0.00 92.15 0.21 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.2487627270
97.23 0.03 99.18 0.00 95.97 0.00 100.00 0.00 95.51 0.00 98.54 0.00 99.06 0.00 92.36 0.21 /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.2868975637
97.26 0.03 99.22 0.03 96.00 0.02 100.00 0.00 95.51 0.00 98.57 0.03 99.16 0.09 92.36 0.00 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.4008894506
97.29 0.03 99.25 0.03 96.02 0.02 100.00 0.00 95.51 0.00 98.61 0.03 99.25 0.09 92.36 0.00 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2500702359
97.31 0.02 99.25 0.00 96.02 0.00 100.00 0.00 95.51 0.00 98.61 0.00 99.25 0.00 92.51 0.15 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2526369253
97.33 0.02 99.25 0.00 96.02 0.00 100.00 0.00 95.51 0.00 98.61 0.00 99.25 0.00 92.67 0.15 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1390551737
97.35 0.02 99.25 0.00 96.02 0.00 100.00 0.00 95.51 0.00 98.61 0.00 99.25 0.00 92.82 0.15 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2868663184
97.37 0.01 99.25 0.00 96.02 0.00 100.00 0.00 95.51 0.00 98.61 0.00 99.25 0.00 92.92 0.10 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.4275159502
97.38 0.01 99.25 0.00 96.02 0.00 100.00 0.00 95.51 0.00 98.61 0.00 99.25 0.00 93.03 0.10 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3471183691
97.40 0.01 99.25 0.00 96.02 0.00 100.00 0.00 95.51 0.00 98.61 0.00 99.25 0.00 93.13 0.10 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2930787665
97.41 0.01 99.25 0.00 96.11 0.10 100.00 0.00 95.51 0.00 98.61 0.00 99.25 0.00 93.13 0.00 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2217427099
97.42 0.01 99.25 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.61 0.00 99.34 0.09 93.13 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3772759041
97.43 0.01 99.27 0.02 96.11 0.00 100.00 0.00 95.51 0.00 98.64 0.03 99.34 0.00 93.13 0.00 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.2659371304
97.44 0.01 99.29 0.02 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.03 99.34 0.00 93.13 0.00 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.4020784592
97.45 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.18 0.05 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.639830853
97.45 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.23 0.05 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.967393184
97.46 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.28 0.05 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.1419551398
97.47 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.33 0.05 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.218294322
97.47 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.38 0.05 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1920031109
97.48 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.44 0.05 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.4066275454
97.49 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.49 0.05 /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3899765233
97.50 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.54 0.05 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2315602205
97.50 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.59 0.05 /workspace/coverage/default/44.sysrst_ctrl_stress_all.1908193904
97.51 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.64 0.05 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1359473480
97.52 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.69 0.05 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2511838129
97.53 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.74 0.05 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.4118560825
97.53 0.01 99.29 0.00 96.11 0.00 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.79 0.05 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2057074519
97.54 0.01 99.29 0.00 96.16 0.05 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.79 0.00 /workspace/coverage/default/10.sysrst_ctrl_alert_test.3969874269
97.54 0.01 99.29 0.00 96.19 0.02 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.79 0.00 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2905510857
97.55 0.01 99.29 0.00 96.21 0.02 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.79 0.00 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3063219162
97.55 0.01 99.29 0.00 96.23 0.02 100.00 0.00 95.51 0.00 98.68 0.00 99.34 0.00 93.79 0.00 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.531254640

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1116969924
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3633943162
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1144124606
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3553140376
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4247296319
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1907508158
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.460711933
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2749694586
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2720135042
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3713590827
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.76984151
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2440620710
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.729591450
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2337386032
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.756251073
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.156105774
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3540316207
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1348983320
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.254511501
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2884570355
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2243338391
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3629473937
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2980275132
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.85713751
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3196263993
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3810726767
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.281642323
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2010993715
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.39782128
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3189615534
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.639100017
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3852907936
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2333279258
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.557962702
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.1478574947
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3669374946
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1418587430
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2420757918
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2202054026
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3932889461
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2430414554
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2241765783
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2662712133
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2363810041
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3991742975
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1321937756
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3584937998
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.619598009
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.58425692
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1500798454
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2559358832
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2468392121
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2443223856
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.30867415
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2651257365
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1801780008
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3139425567
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3914229716
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2163533952
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1838832889
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.78850587
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3424583833
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2995443875
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.858422838
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2569235022
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.3505768824
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2441873440
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3647201499
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.321450533
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1292799650
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4072222338
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1117625056
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1651706206
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2225962119
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3878394635
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1403064649
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1872459674
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2943155182
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3373009657
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.210388080
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1521048603
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2381082040
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2069790034
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/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3247752846
/workspace/coverage/default/42.sysrst_ctrl_alert_test.549435111
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.893216681
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.193730715
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3432819498
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2458666592
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4128769926
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.998991085
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.2732914255
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.3230774308
/workspace/coverage/default/42.sysrst_ctrl_smoke.1582741003
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1363402748
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3077341587
/workspace/coverage/default/43.sysrst_ctrl_alert_test.2932199641
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2215673043
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.2626295195
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2159755456
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2277096633
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3236895794
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3786837238
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.1879760028
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.2245379773
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2970333068
/workspace/coverage/default/43.sysrst_ctrl_smoke.2094186007
/workspace/coverage/default/43.sysrst_ctrl_stress_all.880321846
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.815144301
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1495942292
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1043424880
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1908201059
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.370403094
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3854586570
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3478516178
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3662114689
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.239932128
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.907639360
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2863352768
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.4291905644
/workspace/coverage/default/44.sysrst_ctrl_smoke.2296763956
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2897737860
/workspace/coverage/default/45.sysrst_ctrl_alert_test.979558896
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.899785016
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3570589580
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1695258998
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.412316056
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.70856077
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2911459189
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4215631846
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.922741237
/workspace/coverage/default/45.sysrst_ctrl_smoke.2528333770
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2693861510
/workspace/coverage/default/46.sysrst_ctrl_alert_test.2576461834
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3762432274
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1146269616
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2312992543
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3804435006
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3434192565
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2235030946
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2814788633
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.641079419
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.4268825086
/workspace/coverage/default/46.sysrst_ctrl_smoke.913888843
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2263300724
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1927856018
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2220222749
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3319969341
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.138975558
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3730685528
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.4258061845
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3396654603
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.339969691
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.939472614
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2685664475
/workspace/coverage/default/47.sysrst_ctrl_smoke.343877265
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2893470875
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.895318896
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3429883209
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.763966678
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.736622178
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4004051695
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2836308508
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1154385516
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3347751100
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2840040621
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.514989853
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3589484671
/workspace/coverage/default/48.sysrst_ctrl_smoke.300056347
/workspace/coverage/default/48.sysrst_ctrl_stress_all.2973242456
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2943669498
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2149018527
/workspace/coverage/default/49.sysrst_ctrl_alert_test.3054614423
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2882101787
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1399677609
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3387345304
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1171948260
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3271360315
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2102854532
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.1723386048
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3177557734
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3292809310
/workspace/coverage/default/49.sysrst_ctrl_smoke.1106797119
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2068923334
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.4041599572
/workspace/coverage/default/5.sysrst_ctrl_alert_test.958487234
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.4012316924
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1549239421
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1816027095
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3821774697
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3404798872
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3263558065
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2186232429
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3656638586
/workspace/coverage/default/5.sysrst_ctrl_smoke.667751691
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1959902622
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1955863608
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.4095709096
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.979914140
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.720374508
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3849366091
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.118754021
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3867733268
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3666029171
/workspace/coverage/default/6.sysrst_ctrl_alert_test.261320825
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1947807046
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.4216010095
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3688784682
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4070524290
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.790147962
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3551511266
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.1259158393
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.768741542
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.4129351456
/workspace/coverage/default/6.sysrst_ctrl_smoke.1012324565
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3688456414
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4202468728
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3516789909
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2096415748
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.549095160
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.881244447
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2787612599
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4027087945
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1917535102
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.2245660106
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.1976400921
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1404816621
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.2450406379
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.988009292
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2473016121
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2375826160
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1780902503
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2282449515
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3505059036
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.2210120856
/workspace/coverage/default/7.sysrst_ctrl_smoke.2936265317
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2534617349
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2444104989
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2326589888
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3656386710
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.4095097662
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1062267228
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.22321746
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1465052609
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.4188120421
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.70839931
/workspace/coverage/default/8.sysrst_ctrl_alert_test.3296875874
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2873653327
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.2609240318
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.435989586
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2364623570
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2466307040
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2444810615
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2173000707
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.2650795403
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3716378378
/workspace/coverage/default/8.sysrst_ctrl_smoke.921288176
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3663526406
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1401403911
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2311077463
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2047601154
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2175661412
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.3081722620
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1465324134
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.159743372
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.2397810811
/workspace/coverage/default/9.sysrst_ctrl_alert_test.244720569
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2944299583
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1014210626
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2087983393
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.298087873
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3301464580
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3504053352
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1360218094
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.346252779
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2831431777
/workspace/coverage/default/9.sysrst_ctrl_smoke.3912266467
/workspace/coverage/default/9.sysrst_ctrl_stress_all.3102461541
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1241059847
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3783374953
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.476942950
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3903915857
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2263508088
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2358258995
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1175748999
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.324253321
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1433298363
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.657096437



Total test records in report: 914
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T4 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1647984451 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:32 PM PDT 23 2432633509 ps
T5 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.429784286 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:30 PM PDT 23 2028841569 ps
T1 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1494422724 Oct 11 12:32:40 PM PDT 23 Oct 11 12:32:52 PM PDT 23 11065401080 ps
T2 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.729591450 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:34 PM PDT 23 2062996928 ps
T3 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3424583833 Oct 11 12:32:15 PM PDT 23 Oct 11 12:32:19 PM PDT 23 2059090210 ps
T23 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.639100017 Oct 11 12:32:45 PM PDT 23 Oct 11 12:32:48 PM PDT 23 2127290459 ps
T6 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2720135042 Oct 11 12:32:13 PM PDT 23 Oct 11 12:32:25 PM PDT 23 3329120465 ps
T7 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2351425897 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:38 PM PDT 23 8400230476 ps
T24 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3713590827 Oct 11 12:32:37 PM PDT 23 Oct 11 12:32:57 PM PDT 23 39705654628 ps
T8 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1715846982 Oct 11 12:32:31 PM PDT 23 Oct 11 12:33:02 PM PDT 23 22292600560 ps
T25 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2504856467 Oct 11 12:32:04 PM PDT 23 Oct 11 12:33:25 PM PDT 23 75428436187 ps
T9 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2830312630 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:30 PM PDT 23 2157253997 ps
T42 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2168080030 Oct 11 12:32:35 PM PDT 23 Oct 11 12:32:41 PM PDT 23 2014794712 ps
T295 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2662712133 Oct 11 12:32:46 PM PDT 23 Oct 11 12:32:53 PM PDT 23 2042286929 ps
T43 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2468392121 Oct 11 12:32:43 PM PDT 23 Oct 11 12:32:45 PM PDT 23 2030504310 ps
T10 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2225962119 Oct 11 12:32:25 PM PDT 23 Oct 11 12:32:34 PM PDT 23 6051061082 ps
T315 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3760866302 Oct 11 12:32:40 PM PDT 23 Oct 11 12:32:44 PM PDT 23 2016663434 ps
T11 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2206482119 Oct 11 12:32:22 PM PDT 23 Oct 11 12:32:29 PM PDT 23 2045672425 ps
T12 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3647201499 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:35 PM PDT 23 2052384957 ps
T317 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.1321937756 Oct 11 12:32:31 PM PDT 23 Oct 11 12:32:37 PM PDT 23 2014969167 ps
T307 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1651706206 Oct 11 12:32:33 PM PDT 23 Oct 11 12:36:10 PM PDT 23 38273248690 ps
T299 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3196263993 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:35 PM PDT 23 2159768821 ps
T310 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3633943162 Oct 11 12:32:55 PM PDT 23 Oct 11 12:32:59 PM PDT 23 4050350918 ps
T326 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.123220401 Oct 11 12:32:26 PM PDT 23 Oct 11 12:32:33 PM PDT 23 2011628461 ps
T33 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3584937998 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:31 PM PDT 23 4677692227 ps
T366 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2498801229 Oct 11 12:32:07 PM PDT 23 Oct 11 12:32:09 PM PDT 23 2028936935 ps
T318 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.822594792 Oct 11 12:32:31 PM PDT 23 Oct 11 12:32:34 PM PDT 23 2052739866 ps
T311 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1519204500 Oct 11 12:32:21 PM PDT 23 Oct 11 12:32:39 PM PDT 23 6041720594 ps
T301 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.616705912 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:35 PM PDT 23 2059962429 ps
T34 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.889225684 Oct 11 12:32:31 PM PDT 23 Oct 11 12:32:48 PM PDT 23 22432142713 ps
T298 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.4072222338 Oct 11 12:32:32 PM PDT 23 Oct 11 12:33:30 PM PDT 23 22196562474 ps
T300 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2814819919 Oct 11 12:32:21 PM PDT 23 Oct 11 12:32:25 PM PDT 23 2162805684 ps
T319 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.3608288097 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:31 PM PDT 23 2016076041 ps
T303 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2472473258 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:37 PM PDT 23 2039142544 ps
T312 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1500798454 Oct 11 12:32:45 PM PDT 23 Oct 11 12:32:52 PM PDT 23 2120425995 ps
T321 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1801780008 Oct 11 12:32:29 PM PDT 23 Oct 11 12:32:35 PM PDT 23 2044918789 ps
T367 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.308996081 Oct 11 12:32:40 PM PDT 23 Oct 11 12:32:43 PM PDT 23 2040724862 ps
T313 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1698139934 Oct 11 12:32:19 PM PDT 23 Oct 11 12:34:02 PM PDT 23 42430543535 ps
T322 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2010993715 Oct 11 12:32:20 PM PDT 23 Oct 11 12:32:27 PM PDT 23 2060172692 ps
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T382 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3540316207 Oct 11 12:32:38 PM PDT 23 Oct 11 12:32:45 PM PDT 23 2012117742 ps
T314 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3402479716 Oct 11 12:32:30 PM PDT 23 Oct 11 12:32:33 PM PDT 23 2189691757 ps
T383 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.156105774 Oct 11 12:32:20 PM PDT 23 Oct 11 12:32:28 PM PDT 23 2067190029 ps
T384 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1358611231 Oct 11 12:32:57 PM PDT 23 Oct 11 12:32:59 PM PDT 23 2042540492 ps
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T35 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.773673595 Oct 11 12:32:17 PM PDT 23 Oct 11 12:32:19 PM PDT 23 2071935329 ps
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T36 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.210388080 Oct 11 12:32:30 PM PDT 23 Oct 11 12:32:41 PM PDT 23 22338696581 ps
T37 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1117625056 Oct 11 12:32:19 PM PDT 23 Oct 11 12:32:29 PM PDT 23 2323773223 ps
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T38 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.727383944 Oct 11 12:32:23 PM PDT 23 Oct 11 12:32:51 PM PDT 23 42874224165 ps
T39 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.473155069 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:56 PM PDT 23 42897136894 ps
T388 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.78850587 Oct 11 12:32:39 PM PDT 23 Oct 11 12:32:41 PM PDT 23 2082418224 ps
T316 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3553140376 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:30 PM PDT 23 2061774462 ps
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T344 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.58425692 Oct 11 12:32:57 PM PDT 23 Oct 11 12:33:54 PM PDT 23 42471151535 ps
T389 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2430414554 Oct 11 12:32:35 PM PDT 23 Oct 11 12:32:37 PM PDT 23 2038606408 ps
T320 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.76984151 Oct 11 12:32:20 PM PDT 23 Oct 11 12:32:26 PM PDT 23 6095085846 ps
T390 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.3955296666 Oct 11 12:32:16 PM PDT 23 Oct 11 12:32:20 PM PDT 23 2020754986 ps
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T392 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.542754678 Oct 11 12:32:18 PM PDT 23 Oct 11 12:32:22 PM PDT 23 2027867686 ps
T393 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2559358832 Oct 11 12:32:18 PM PDT 23 Oct 11 12:32:29 PM PDT 23 2034464933 ps
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T302 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2569235022 Oct 11 12:32:15 PM PDT 23 Oct 11 12:32:19 PM PDT 23 2085449464 ps
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T398 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1521048603 Oct 11 12:33:01 PM PDT 23 Oct 11 12:33:07 PM PDT 23 2011502124 ps
T399 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.2243338391 Oct 11 12:32:26 PM PDT 23 Oct 11 12:32:33 PM PDT 23 2118570942 ps
T400 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3669374946 Oct 11 12:32:22 PM PDT 23 Oct 11 12:32:40 PM PDT 23 9354115578 ps
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T401 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2995443875 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:34 PM PDT 23 2012663853 ps
T380 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2651257365 Oct 11 12:32:16 PM PDT 23 Oct 11 12:32:18 PM PDT 23 2111106577 ps
T402 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.638556234 Oct 11 12:32:25 PM PDT 23 Oct 11 12:32:29 PM PDT 23 2214564478 ps
T403 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3941861966 Oct 11 12:32:26 PM PDT 23 Oct 11 12:32:28 PM PDT 23 2026415505 ps
T404 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1838832889 Oct 11 12:32:26 PM PDT 23 Oct 11 12:33:00 PM PDT 23 42502217197 ps
T325 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3932889461 Oct 11 12:32:18 PM PDT 23 Oct 11 12:32:21 PM PDT 23 2069067720 ps
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T407 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.2587591152 Oct 11 12:32:14 PM PDT 23 Oct 11 12:32:38 PM PDT 23 5776132873 ps
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T327 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3772759041 Oct 11 12:32:20 PM PDT 23 Oct 11 12:32:26 PM PDT 23 2123739560 ps
T409 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3510413107 Oct 11 12:32:05 PM PDT 23 Oct 11 12:32:20 PM PDT 23 22465775167 ps
T410 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3751774169 Oct 11 12:32:23 PM PDT 23 Oct 11 12:32:28 PM PDT 23 2013094522 ps
T411 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.541313299 Oct 11 12:32:31 PM PDT 23 Oct 11 12:32:34 PM PDT 23 2029695069 ps
T412 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.756251073 Oct 11 12:32:56 PM PDT 23 Oct 11 12:33:14 PM PDT 23 22269078618 ps
T413 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.3127435382 Oct 11 12:32:42 PM PDT 23 Oct 11 12:32:48 PM PDT 23 2014107602 ps
T414 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2533234294 Oct 11 12:32:34 PM PDT 23 Oct 11 12:33:19 PM PDT 23 42431086633 ps
T305 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.619598009 Oct 11 12:32:45 PM PDT 23 Oct 11 12:32:49 PM PDT 23 2157304275 ps
T415 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.3991711512 Oct 11 12:32:32 PM PDT 23 Oct 11 12:32:35 PM PDT 23 2048663407 ps
T416 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.3914956021 Oct 11 12:32:32 PM PDT 23 Oct 11 12:33:51 PM PDT 23 33193982144 ps
T417 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.3373009657 Oct 11 12:32:18 PM PDT 23 Oct 11 12:32:27 PM PDT 23 2039389706 ps
T418 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.557962702 Oct 11 12:32:34 PM PDT 23 Oct 11 12:32:39 PM PDT 23 2056849609 ps
T328 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4229040319 Oct 11 12:32:36 PM PDT 23 Oct 11 12:32:42 PM PDT 23 2057850914 ps
T419 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.872525020 Oct 11 12:32:26 PM PDT 23 Oct 11 12:33:27 PM PDT 23 22207769410 ps
T420 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2333279258 Oct 11 12:32:38 PM PDT 23 Oct 11 12:32:45 PM PDT 23 2047290000 ps
T421 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2217427099 Oct 11 12:32:17 PM PDT 23 Oct 11 12:32:25 PM PDT 23 2147709828 ps
T422 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.849778145 Oct 11 12:32:19 PM PDT 23 Oct 11 12:32:29 PM PDT 23 22327316316 ps
T423 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.911322208 Oct 11 12:32:32 PM PDT 23 Oct 11 12:32:39 PM PDT 23 2015358943 ps
T424 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.793594313 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:32 PM PDT 23 2206175491 ps
T425 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.722993794 Oct 11 12:32:21 PM PDT 23 Oct 11 12:32:38 PM PDT 23 3166755057 ps
T426 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.606472670 Oct 11 12:32:50 PM PDT 23 Oct 11 12:32:54 PM PDT 23 2034618998 ps
T427 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1144124606 Oct 11 12:32:29 PM PDT 23 Oct 11 12:32:35 PM PDT 23 2066322041 ps
T428 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3852907936 Oct 11 12:32:17 PM PDT 23 Oct 11 12:32:28 PM PDT 23 23425995751 ps
T429 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1937072510 Oct 11 12:32:15 PM PDT 23 Oct 11 12:32:21 PM PDT 23 2055916520 ps
T430 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1415085308 Oct 11 12:32:16 PM PDT 23 Oct 11 12:32:22 PM PDT 23 2017912686 ps
T431 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1231024264 Oct 11 12:32:28 PM PDT 23 Oct 11 12:32:32 PM PDT 23 2322096606 ps
T432 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2443223856 Oct 11 12:32:27 PM PDT 23 Oct 11 12:32:33 PM PDT 23 5273550063 ps
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T434 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.39782128 Oct 11 12:32:46 PM PDT 23 Oct 11 12:32:52 PM PDT 23 2015816997 ps
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T436 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3129428739 Oct 11 12:32:17 PM PDT 23 Oct 11 12:32:22 PM PDT 23 2085983825 ps
T437 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2380216075 Oct 11 12:32:21 PM PDT 23 Oct 11 12:32:28 PM PDT 23 5974916597 ps
T40 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3704795813 Oct 11 12:33:56 PM PDT 23 Oct 11 12:43:37 PM PDT 23 230596525125 ps
T41 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.75885185 Oct 11 12:33:24 PM PDT 23 Oct 11 12:33:32 PM PDT 23 2611988098 ps
T13 /workspace/coverage/default/46.sysrst_ctrl_stress_all.2263300724 Oct 11 12:34:13 PM PDT 23 Oct 11 12:34:25 PM PDT 23 10774950901 ps
T26 /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.601096013 Oct 11 12:34:05 PM PDT 23 Oct 11 12:55:09 PM PDT 23 496133857832 ps
T27 /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.3015789675 Oct 11 12:32:50 PM PDT 23 Oct 11 12:32:59 PM PDT 23 2513631281 ps
T28 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1816027095 Oct 11 12:32:41 PM PDT 23 Oct 11 12:32:51 PM PDT 23 3300778394 ps
T14 /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2783005918 Oct 11 12:33:17 PM PDT 23 Oct 11 12:33:26 PM PDT 23 2845480904 ps
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T29 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2365624019 Oct 11 12:33:29 PM PDT 23 Oct 11 12:33:34 PM PDT 23 2930428210 ps
T30 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3432819498 Oct 11 12:34:04 PM PDT 23 Oct 11 12:34:13 PM PDT 23 2740617441 ps
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T32 /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1646571993 Oct 11 12:34:37 PM PDT 23 Oct 11 12:36:14 PM PDT 23 39948102724 ps
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T68 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3804435006 Oct 11 12:34:01 PM PDT 23 Oct 11 12:34:10 PM PDT 23 3153982807 ps
T69 /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3650578703 Oct 11 12:34:07 PM PDT 23 Oct 11 12:34:09 PM PDT 23 2552380891 ps
T104 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.922741237 Oct 11 12:34:30 PM PDT 23 Oct 11 12:34:38 PM PDT 23 2513313156 ps
T90 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3471183691 Oct 11 12:34:06 PM PDT 23 Oct 11 12:35:12 PM PDT 23 24352150618 ps
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T17 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1614968213 Oct 11 12:32:20 PM PDT 23 Oct 11 12:32:23 PM PDT 23 8242467755 ps
T70 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.2186232429 Oct 11 12:33:18 PM PDT 23 Oct 11 12:33:25 PM PDT 23 2227873097 ps
T18 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1927856018 Oct 11 12:34:09 PM PDT 23 Oct 11 12:34:30 PM PDT 23 318777058519 ps
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T19 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2159755456 Oct 11 12:34:23 PM PDT 23 Oct 11 12:35:45 PM PDT 23 119520761169 ps
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T20 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3006824035 Oct 11 12:33:40 PM PDT 23 Oct 11 12:33:50 PM PDT 23 3349576519 ps
T79 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1908201059 Oct 11 12:34:03 PM PDT 23 Oct 11 12:34:05 PM PDT 23 3902211923 ps
T80 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3859570404 Oct 11 12:34:13 PM PDT 23 Oct 11 12:34:21 PM PDT 23 2482476382 ps
T21 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.419220928 Oct 11 12:33:14 PM PDT 23 Oct 11 12:33:40 PM PDT 23 168146979023 ps
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T54 /workspace/coverage/default/27.sysrst_ctrl_stress_all.3865187734 Oct 11 12:33:25 PM PDT 23 Oct 11 12:33:42 PM PDT 23 14370110844 ps
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T45 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.185328396 Oct 11 12:33:25 PM PDT 23 Oct 11 12:36:46 PM PDT 23 511033308594 ps
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T174 /workspace/coverage/default/19.sysrst_ctrl_alert_test.2322990538 Oct 11 12:33:28 PM PDT 23 Oct 11 12:33:30 PM PDT 23 2056444550 ps
T175 /workspace/coverage/default/34.sysrst_ctrl_smoke.831403252 Oct 11 12:34:20 PM PDT 23 Oct 11 12:34:23 PM PDT 23 2122250455 ps
T44 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2813104583 Oct 11 12:33:40 PM PDT 23 Oct 11 12:33:43 PM PDT 23 5697721494 ps
T46 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.3542234909 Oct 11 12:33:50 PM PDT 23 Oct 11 12:34:48 PM PDT 23 93018586294 ps
T101 /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3690455151 Oct 11 12:34:22 PM PDT 23 Oct 11 12:34:32 PM PDT 23 3593221044 ps
T207 /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.124205336 Oct 11 12:33:19 PM PDT 23 Oct 11 12:33:22 PM PDT 23 2477739560 ps
T252 /workspace/coverage/default/29.sysrst_ctrl_stress_all.1982319961 Oct 11 12:33:29 PM PDT 23 Oct 11 12:33:35 PM PDT 23 6666731777 ps
T439 /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3505059036 Oct 11 12:33:20 PM PDT 23 Oct 11 12:33:24 PM PDT 23 2229166095 ps
T376 /workspace/coverage/default/20.sysrst_ctrl_stress_all.2737100397 Oct 11 12:33:37 PM PDT 23 Oct 11 12:34:10 PM PDT 23 9571143624 ps
T440 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1471489160 Oct 11 12:33:04 PM PDT 23 Oct 11 12:33:06 PM PDT 23 2635965490 ps
T377 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.943309254 Oct 11 12:33:10 PM PDT 23 Oct 11 12:33:13 PM PDT 23 2547917404 ps
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T77 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1942238644 Oct 11 12:33:59 PM PDT 23 Oct 11 12:34:06 PM PDT 23 6068012109 ps
T459 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.3059787104 Oct 11 12:33:01 PM PDT 23 Oct 11 12:33:06 PM PDT 23 2439504447 ps
T460 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.424784015 Oct 11 12:34:01 PM PDT 23 Oct 11 12:34:05 PM PDT 23 7108312060 ps
T374 /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.4124520314 Oct 11 12:34:00 PM PDT 23 Oct 11 01:09:02 PM PDT 23 778867402431 ps
T461 /workspace/coverage/default/45.sysrst_ctrl_alert_test.979558896 Oct 11 12:34:56 PM PDT 23 Oct 11 12:34:59 PM PDT 23 2062860193 ps
T138 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3199576700 Oct 11 12:33:25 PM PDT 23 Oct 11 12:33:30 PM PDT 23 3042998322 ps
T278 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.3347189669 Oct 11 12:33:19 PM PDT 23 Oct 11 12:33:52 PM PDT 23 25516201902 ps
T276 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.476942950 Oct 11 12:34:16 PM PDT 23 Oct 11 12:34:47 PM PDT 23 46409343438 ps
T462 /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.939472614 Oct 11 12:34:19 PM PDT 23 Oct 11 12:34:23 PM PDT 23 2188395139 ps
T463 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.494375339 Oct 11 12:33:51 PM PDT 23 Oct 11 12:34:01 PM PDT 23 3255708041 ps
T464 /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.4076748162 Oct 11 12:33:18 PM PDT 23 Oct 11 12:33:21 PM PDT 23 2488847428 ps
T465 /workspace/coverage/default/15.sysrst_ctrl_alert_test.1426138326 Oct 11 12:33:05 PM PDT 23 Oct 11 12:33:10 PM PDT 23 2016961050 ps
T466 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3867090940 Oct 11 12:34:00 PM PDT 23 Oct 11 12:34:03 PM PDT 23 2043058659 ps
T55 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.647638740 Oct 11 12:34:34 PM PDT 23 Oct 11 12:34:38 PM PDT 23 4844633733 ps
T212 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.622195159 Oct 11 12:34:17 PM PDT 23 Oct 11 12:34:20 PM PDT 23 2523491362 ps
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