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 LINE       6850
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       6852
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T299,T301
1	1	1	Covered	T1,T2,T3

 LINE       6854
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       6856
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T23,T299
1	1	1	Covered	T1,T2,T3

 LINE       6869
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       6886
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T23,T300
1	1	1	Covered	T1,T2,T3

 LINE       6895
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T23,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       6904
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T23,T300
1	1	1	Covered	T1,T2,T3

 LINE       6919
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T299,T301
1	1	1	Covered	T1,T2,T3

 LINE       6921
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T299,T300
1	1	1	Covered	T1,T2,T3

 LINE       6924
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T23,T8
1	1	1	Covered	T1,T2,T3

 LINE       6931
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T23,T295
1	1	1	Covered	T1,T2,T3

 LINE       6937
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T299,T300
1	1	1	Covered	T1,T2,T3

 LINE       6943
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T300,T303
1	1	1	Covered	T1,T2,T3

 LINE       6949
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T301,T300,T303
1	1	1	Covered	T1,T2,T3

 LINE       6955
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T23,T295
1	1	1	Covered	T1,T2,T3

 LINE       6957
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T23,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       6959
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T304,T305
1	1	1	Covered	T1,T2,T3

 LINE       6961
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T299,T300
1	1	1	Covered	T1,T2,T3

 LINE       6963
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T23,T295
1	1	1	Covered	T1,T2,T3

 LINE       6969
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T299,T301
1	1	1	Covered	T1,T2,T3

 LINE       6975
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T23,T299
1	1	1	Covered	T1,T2,T3

 LINE       6981
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T295,T300
1	1	1	Covered	T1,T2,T3

 LINE       6987
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T300,T303
1	1	1	Covered	T1,T2,T3

 LINE       6989
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       6991
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T23,T299
1	1	1	Covered	T1,T2,T3

 LINE       6993
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       6995
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T295,T299,T300
1	1	1	Covered	T1,T2,T3

 LINE       7000
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       7005
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T299,T301
1	1	1	Covered	T1,T2,T3

 LINE       7010
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T1,T2
1	1	0	Covered	T4,T299,T303
1	1	1	Covered	T1,T2,T3

 LINE       7015
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T295,T299
1	1	1	Covered	T1,T2,T3

 LINE       7020
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T1,T2
1	0	1	Covered	T4,T5,T1
1	1	0	Covered	T4,T23,T295
1	1	1	Covered	T1,T2,T3

 LINE       7242
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T1,T2,T3