Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

99291

1

T16

331

T17

5

T18

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132924	1			T16	495		T17	8		T18	8
values[0x0]	38672	1			T16	118		T17	4		T18	4
values[0x1]	42840	1			T16	126		T17	4		T18	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

126226

1

T16

409

T17

9

T18

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	556	1			T96	3		T97	3		T1	12
valid_sources[0x01]	986	1			T27	3		T33	3		T100	3
valid_sources[0x02]	1715	1			T16	11		T22	11		T24	11
valid_sources[0x03]	1542	1			T16	4		T17	2		T18	2
valid_sources[0x04]	950	1			T16	8		T22	8		T24	8
valid_sources[0x05]	620	1			T1	13		T92	12		T4	1
valid_sources[0x06]	1290	1			T16	5		T22	5		T23	1
valid_sources[0x07]	625	1			T1	19		T92	3		T4	3
valid_sources[0x08]	692	1			T40	5		T27	1		T33	1
valid_sources[0x09]	922	1			T27	4		T33	4		T100	4
valid_sources[0x0a]	1160	1			T16	3		T22	3		T24	3
valid_sources[0x0b]	380	1			T92	6		T4	2		T11	6
valid_sources[0x0c]	1707	1			T16	7		T22	7		T24	7
valid_sources[0x0d]	755	1			T27	8		T33	8		T100	8
valid_sources[0x0e]	5364	1			T16	15		T17	7		T18	7
valid_sources[0x0f]	345	1			T1	6		T4	3		T5	6
valid_sources[0x10]	655	1			T16	3		T22	3		T24	3
valid_sources[0x11]	425	1			T1	4		T92	4		T11	4
valid_sources[0x12]	950	1			T1	27		T92	9		T4	1
valid_sources[0x13]	565	1			T27	2		T33	2		T100	2
valid_sources[0x14]	1102	1			T16	9		T22	9		T24	9
valid_sources[0x15]	865	1			T16	5		T22	5		T24	5
valid_sources[0x16]	590	1			T16	5		T22	5		T24	5
valid_sources[0x17]	450	1			T1	3		T92	9		T4	4
valid_sources[0x18]	760	1			T16	7		T22	7		T24	7
valid_sources[0x19]	1050	1			T16	4		T22	4		T24	4
valid_sources[0x1a]	500	1			T16	2		T22	2		T24	2
valid_sources[0x1b]	280	1			T1	6		T92	1		T11	1
valid_sources[0x1c]	334	1			T42	2		T66	2		T67	2
valid_sources[0x1d]	655	1			T16	2		T22	2		T24	2
valid_sources[0x1e]	1630	1			T16	17		T22	17		T24	17
valid_sources[0x1f]	515	1			T1	9		T92	13		T11	13
valid_sources[0x20]	705	1			T27	1		T33	1		T100	1
valid_sources[0x21]	1176	1			T16	2		T22	2		T24	2
valid_sources[0x22]	612	1			T27	2		T33	2		T100	2
valid_sources[0x23]	540	1			T1	4		T92	8		T4	2
valid_sources[0x24]	760	1			T1	23		T2	6		T3	6
valid_sources[0x25]	1904	1			T27	13		T33	13		T100	13
valid_sources[0x26]	430	1			T1	12		T5	12		T7	12
valid_sources[0x27]	857	1			T27	5		T33	5		T100	5
valid_sources[0x28]	280	1			T1	7		T5	7		T7	7
valid_sources[0x29]	555	1			T1	13		T2	10		T92	2
valid_sources[0x2a]	440	1			T1	16		T4	1		T5	16
valid_sources[0x2b]	515	1			T16	4		T22	4		T24	4
valid_sources[0x2c]	1065	1			T27	4		T33	4		T100	4
valid_sources[0x2d]	1525	1			T16	8		T22	8		T24	8
valid_sources[0x2e]	220	1			T16	1		T22	1		T24	1
valid_sources[0x2f]	1290	1			T40	2		T41	2		T42	2
valid_sources[0x30]	625	1			T16	2		T22	2		T24	2
valid_sources[0x31]	930	1			T16	4		T22	4		T24	4
valid_sources[0x32]	675	1			T1	13		T2	6		T92	8
valid_sources[0x33]	540	1			T16	2		T22	2		T24	2
valid_sources[0x34]	1585	1			T16	11		T22	11		T24	11
valid_sources[0x35]	395	1			T1	4		T2	1		T92	3
valid_sources[0x36]	430	1			T1	12		T5	12		T7	12
valid_sources[0x37]	1049	1			T40	3		T23	3		T41	3
valid_sources[0x38]	770	1			T27	4		T33	4		T100	4
valid_sources[0x39]	665	1			T16	9		T22	9		T24	9
valid_sources[0x3a]	564	1			T16	2		T22	2		T24	2
valid_sources[0x3b]	712	1			T27	11		T33	11		T100	11
valid_sources[0x3c]	950	1			T27	7		T33	7		T100	7
valid_sources[0x3d]	540	1			T16	1		T22	1		T24	1
valid_sources[0x3e]	1140	1			T16	1		T22	1		T24	1
valid_sources[0x3f]	2047	1			T16	11		T22	11		T42	1
valid_sources[0x40]	520	1			T16	3		T22	3		T24	3
valid_sources[0x41]	445	1			T1	3		T92	6		T4	1
valid_sources[0x42]	580	1			T16	1		T22	1		T24	1
valid_sources[0x43]	455	1			T27	1		T33	1		T100	1
valid_sources[0x44]	290	1			T92	1		T4	4		T11	1
valid_sources[0x45]	1300	1			T16	14		T22	14		T24	14
valid_sources[0x46]	820	1			T27	4		T33	4		T100	4
valid_sources[0x47]	815	1			T1	7		T92	20		T4	2
valid_sources[0x48]	405	1			T1	10		T92	1		T11	1
valid_sources[0x49]	1189	1			T16	5		T17	2		T18	2
valid_sources[0x4a]	380	1			T1	11		T92	2		T11	2
valid_sources[0x4b]	430	1			T27	1		T33	1		T100	1
valid_sources[0x4c]	1468	1			T16	13		T22	13		T42	3
valid_sources[0x4d]	620	1			T1	15		T92	8		T4	1
valid_sources[0x4e]	815	1			T27	7		T33	7		T100	7
valid_sources[0x4f]	790	1			T16	10		T22	10		T24	10
valid_sources[0x50]	445	1			T28	6		T29	6		T34	6
valid_sources[0x51]	620	1			T16	1		T22	1		T24	1
valid_sources[0x52]	220	1			T1	6		T4	1		T5	6
valid_sources[0x53]	520	1			T16	5		T22	5		T24	5
valid_sources[0x54]	929	1			T96	7		T97	7		T1	9
valid_sources[0x55]	1285	1			T16	6		T22	6		T24	6
valid_sources[0x56]	940	1			T16	2		T22	2		T24	2
valid_sources[0x57]	1116	1			T27	8		T33	8		T100	8
valid_sources[0x58]	520	1			T1	4		T2	1		T92	10
valid_sources[0x59]	745	1			T16	3		T22	3		T24	3
valid_sources[0x5a]	1565	1			T16	5		T22	5		T24	5
valid_sources[0x5b]	1215	1			T16	16		T22	16		T24	16
valid_sources[0x5c]	1745	1			T16	23		T22	23		T24	23
valid_sources[0x5d]	470	1			T1	3		T92	5		T4	8
valid_sources[0x5e]	1249	1			T16	2		T22	2		T40	2
valid_sources[0x5f]	992	1			T27	2		T33	2		T100	2
valid_sources[0x60]	235	1			T92	6		T11	6		T69	6
valid_sources[0x61]	365	1			T1	4		T92	3		T4	1
valid_sources[0x62]	1550	1			T16	19		T22	19		T24	19
valid_sources[0x63]	175	1			T92	5		T11	5		T69	5
valid_sources[0x64]	1090	1			T16	6		T22	6		T24	6
valid_sources[0x65]	1645	1			T16	4		T22	4		T40	4
valid_sources[0x66]	280	1			T16	1		T22	1		T24	1
valid_sources[0x67]	1260	1			T16	10		T22	10		T24	10
valid_sources[0x68]	647	1			T96	1		T97	1		T1	12
valid_sources[0x69]	422	1			T27	4		T33	4		T100	4
valid_sources[0x6a]	565	1			T1	9		T92	4		T4	6
valid_sources[0x6b]	665	1			T16	2		T22	2		T24	2
valid_sources[0x6c]	290	1			T1	6		T4	2		T5	6
valid_sources[0x6d]	530	1			T16	4		T22	4		T24	4
valid_sources[0x6e]	1274	1			T42	6		T66	6		T67	6
valid_sources[0x6f]	495	1			T16	2		T22	2		T24	2
valid_sources[0x70]	780	1			T27	6		T33	6		T100	6
valid_sources[0x71]	720	1			T1	23		T4	1		T5	23
valid_sources[0x72]	966	1			T16	4		T22	4		T23	2
valid_sources[0x73]	560	1			T16	2		T22	2		T24	2
valid_sources[0x74]	810	1			T16	1		T22	1		T24	1
valid_sources[0x75]	1660	1			T40	11		T41	5		T42	4
valid_sources[0x76]	760	1			T16	6		T22	6		T23	3
valid_sources[0x77]	1380	1			T16	1		T22	1		T24	1
valid_sources[0x78]	1342	1			T16	3		T22	3		T42	11
valid_sources[0x79]	840	1			T16	1		T22	1		T24	1
valid_sources[0x7a]	620	1			T27	1		T33	1		T100	1
valid_sources[0x7b]	871	1			T27	9		T33	9		T100	9
valid_sources[0x7c]	785	1			T16	2		T22	2		T24	2
valid_sources[0x7d]	615	1			T27	1		T33	1		T100	1
valid_sources[0x7e]	860	1			T16	10		T22	10		T24	10
valid_sources[0x7f]	1957	1			T16	3		T17	5		T18	5
valid_sources[0x80]	415	1			T16	2		T22	2		T24	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56449

1

T16

246

T17

1

T18

1

values[0x0]

all_enables

biggest_size

23727

1

T16

53

T17

3

T18

3

values[0x1]

all_enables

biggest_size

19115

1

T16

32

T17

1

T18

1