Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T41
1	0	Covered	T16,T22,T41
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T41
1	0	Covered	T19,T20,T21
1	1	Covered	T16,T22,T41

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	125837	0	0
SrcPulseCheck_M	2147483647	127146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	125837
T16	4047448	15
T17	1764100	16
T18	1764100	16
T21	130789	0
T22	5059310	15
T23	2040470	0
T24	5059310	15
T25	0	15
T27	0	27
T28	141936	2
T29	134330	2
T30	130789	0
T31	203230	0
T32	0	15
T33	0	27
T34	0	2
T39	1132670	0
T40	1472290	0
T41	1388360	0
T42	1413660	0
T46	140863	0
T47	112864	0
T65	352820	16
T98	175783	16
T99	0	16
T100	0	9
T101	0	16
T102	0	16
T103	0	16
T104	0	16
T105	0	16
T106	138342	0
T107	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	127146
T16	4047448	15
T17	1764100	16
T18	1764100	16
T21	1037	0
T22	5059310	15
T23	2040470	0
T24	5059310	15
T25	0	15
T27	0	27
T28	506	2
T29	479	2
T30	1037	0
T31	817	0
T32	0	15
T33	0	27
T34	0	2
T39	1132670	0
T40	1472290	0
T41	1388360	0
T42	1413660	0
T46	503	0
T47	403	0
T65	352820	16
T98	627	16
T99	0	16
T100	0	9
T101	0	16
T102	0	16
T103	0	16
T104	0	16
T105	0	16
T106	494	0
T107	884	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T92,T11,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T92,T11,T15
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1932	0	0
SrcPulseCheck_M	754515696	1962	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1932
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T107	0	1
T108	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1962
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T107	0	1
T108	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T92,T11,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T92,T11,T15
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1932	0	0
SrcPulseCheck_M	2727417	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1932
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T107	0	1
T108	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1932
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T107	0	1
T108	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1197
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1238	0	0
SrcPulseCheck_M	754515696	1268	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1238
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1268
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1238	0	0
SrcPulseCheck_M	2727417	1238	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1238
T19	130789	2
T20	130789	2
T21	130789	2
T25	488486	0
T30	130789	2
T37	0	2
T38	0	2
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1238
T19	1037	2
T20	1037	2
T21	1037	2
T25	17445	0
T30	1037	2
T37	0	2
T38	0	2
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T92,T11,T15

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T19,T20,T21
1	0	Covered	T92,T11,T15
1	1	Covered	T19,T20,T21

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	800	0	0
SrcPulseCheck_M	754515696	830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	800
T19	1037	1
T20	1037	1
T21	1037	1
T25	17445	0
T30	1037	1
T37	0	1
T38	0	1
T43	403	0
T44	403	0
T45	8403	0
T46	503	0
T47	403	0
T48	0	1
T49	0	1
T50	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	830
T19	130789	1
T20	130789	1
T21	130789	1
T25	488486	0
T30	130789	1
T37	0	1
T38	0	1
T43	112864	0
T44	112864	0
T45	235306	0
T46	140863	0
T47	112864	0
T48	0	1
T49	0	1
T50	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1510	0	0
SrcPulseCheck_M	754515696	1552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1510
T16	17445	7
T17	627	0
T18	627	0
T19	0	1
T20	0	1
T21	0	1
T22	17445	7
T23	817	0
T24	17445	7
T25	0	7
T27	0	8
T30	0	1
T32	0	7
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1552
T16	488486	7
T17	175783	0
T18	175783	0
T19	0	1
T20	0	1
T21	0	1
T22	488486	7
T23	203230	0
T24	488486	7
T25	0	7
T27	0	8
T28	0	1
T29	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T41
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T22,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T41
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T22,T41

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	3105	0	0
SrcPulseCheck_M	754515696	3135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	3105
T16	17445	20
T17	627	0
T18	627	0
T22	17445	20
T23	817	0
T24	17445	20
T25	0	20
T32	0	20
T39	403	0
T40	523	0
T41	494	20
T42	503	0
T106	0	20
T109	0	20
T110	0	20
T111	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	3135
T16	488486	20
T17	175783	0
T18	175783	0
T22	488486	20
T23	203230	0
T24	488486	20
T25	0	20
T32	0	20
T39	112864	0
T40	146706	0
T41	138342	20
T42	140863	0
T106	0	20
T109	0	20
T110	0	20
T111	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T41
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T22,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T41
1	0	Covered	T16,T22,T41
1	1	Covered	T16,T22,T41

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	3105	0	0
SrcPulseCheck_M	2727417	3105	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	3105
T16	488486	20
T17	175783	0
T18	175783	0
T22	488486	20
T23	203230	0
T24	488486	20
T25	0	20
T32	0	20
T39	112864	0
T40	146706	0
T41	138342	20
T42	140863	0
T106	0	20
T109	0	20
T110	0	20
T111	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	3105
T16	17445	20
T17	627	0
T18	627	0
T22	17445	20
T23	817	0
T24	17445	20
T25	0	20
T32	0	20
T39	403	0
T40	523	0
T41	494	20
T42	503	0
T106	0	20
T109	0	20
T110	0	20
T111	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5170	0	0
SrcPulseCheck_M	754515696	5200	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5170
T16	17445	41
T17	627	0
T18	627	0
T22	17445	41
T23	817	0
T24	17445	41
T25	0	41
T39	403	0
T40	523	20
T41	494	1
T42	503	20
T66	0	20
T67	0	20
T106	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5200
T16	488486	41
T17	175783	0
T18	175783	0
T22	488486	41
T23	203230	0
T24	488486	41
T25	0	41
T39	112864	0
T40	146706	20
T41	138342	1
T42	140863	20
T66	0	20
T67	0	20
T106	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5170	0	0
SrcPulseCheck_M	2727417	5170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5170
T16	488486	41
T17	175783	0
T18	175783	0
T22	488486	41
T23	203230	0
T24	488486	41
T25	0	41
T39	112864	0
T40	146706	20
T41	138342	1
T42	140863	20
T66	0	20
T67	0	20
T106	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5170
T16	17445	41
T17	627	0
T18	627	0
T22	17445	41
T23	817	0
T24	17445	41
T25	0	41
T39	403	0
T40	523	20
T41	494	1
T42	503	20
T66	0	20
T67	0	20
T106	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5967	0	0
SrcPulseCheck_M	754515696	5997	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5967
T16	17445	46
T17	627	0
T18	627	0
T22	17445	46
T23	817	0
T24	17445	46
T25	0	46
T39	403	0
T40	523	20
T41	494	1
T42	503	20
T66	0	20
T67	0	20
T108	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5997
T16	488486	46
T17	175783	0
T18	175783	0
T22	488486	46
T23	203230	0
T24	488486	46
T25	0	46
T39	112864	0
T40	146706	20
T41	138342	1
T42	140863	20
T66	0	20
T67	0	20
T108	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5967	0	0
SrcPulseCheck_M	2727417	5967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5967
T16	488486	46
T17	175783	0
T18	175783	0
T22	488486	46
T23	203230	0
T24	488486	46
T25	0	46
T39	112864	0
T40	146706	20
T41	138342	1
T42	140863	20
T66	0	20
T67	0	20
T108	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5967
T16	17445	46
T17	627	0
T18	627	0
T22	17445	46
T23	817	0
T24	17445	46
T25	0	46
T39	403	0
T40	523	20
T41	494	1
T42	503	20
T66	0	20
T67	0	20
T108	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	4925	0	0
SrcPulseCheck_M	754515696	4955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	4925
T16	17445	40
T17	627	0
T18	627	0
T22	17445	40
T23	817	0
T24	17445	40
T25	0	40
T32	0	40
T39	403	0
T40	523	20
T41	494	0
T42	503	20
T46	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	4955
T16	488486	40
T17	175783	0
T18	175783	0
T22	488486	40
T23	203230	0
T24	488486	40
T25	0	40
T32	0	40
T39	112864	0
T40	146706	20
T41	138342	0
T42	140863	20
T46	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T40
1	0	Covered	T16,T22,T40
1	1	Covered	T16,T22,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	4925	0	0
SrcPulseCheck_M	2727417	4925	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	4925
T16	488486	40
T17	175783	0
T18	175783	0
T22	488486	40
T23	203230	0
T24	488486	40
T25	0	40
T32	0	40
T39	112864	0
T40	146706	20
T41	138342	0
T42	140863	20
T46	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	4925
T16	17445	40
T17	627	0
T18	627	0
T22	17445	40
T23	817	0
T24	17445	40
T25	0	40
T32	0	40
T39	403	0
T40	523	20
T41	494	0
T42	503	20
T46	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T23
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1246	0	0
SrcPulseCheck_M	754515696	1276	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1246
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	1
T24	17445	1
T25	0	1
T26	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1276
T16	488486	1
T17	175783	0
T18	175783	0
T22	488486	1
T23	203230	1
T24	488486	1
T25	0	1
T26	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T23
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1246	0	0
SrcPulseCheck_M	2727417	1246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1246
T16	488486	1
T17	175783	0
T18	175783	0
T22	488486	1
T23	203230	1
T24	488486	1
T25	0	1
T26	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1246
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	1
T24	17445	1
T25	0	1
T26	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T23
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1924	0	0
SrcPulseCheck_M	754515696	1974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1924
T16	17445	6
T17	627	0
T18	627	0
T22	17445	6
T23	817	1
T24	17445	6
T25	0	6
T26	0	1
T27	0	9
T28	0	1
T29	0	1
T31	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1974
T16	488486	6
T17	175783	0
T18	175783	0
T22	488486	6
T23	203230	1
T24	488486	6
T25	0	6
T26	0	1
T27	0	9
T28	0	1
T29	0	1
T31	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T23
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1924	0	0
SrcPulseCheck_M	2727417	1924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1924
T16	488486	6
T17	175783	0
T18	175783	0
T22	488486	6
T23	203230	1
T24	488486	6
T25	0	6
T26	0	1
T27	0	9
T28	0	1
T29	0	1
T31	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1924
T16	17445	6
T17	627	0
T18	627	0
T22	17445	6
T23	817	1
T24	17445	6
T25	0	6
T26	0	1
T27	0	9
T28	0	1
T29	0	1
T31	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1254	0	0
SrcPulseCheck_M	754515696	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1254
T17	627	5
T18	627	5
T22	17445	0
T23	817	0
T24	17445	0
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T65	627	5
T98	0	5
T99	0	5
T101	0	5
T102	0	5
T103	0	5
T104	0	5
T105	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1289
T17	175783	5
T18	175783	5
T22	488486	0
T23	203230	0
T24	488486	0
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T65	175783	5
T98	0	5
T99	0	5
T101	0	5
T102	0	5
T103	0	5
T104	0	5
T105	0	5

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1259	0	0
SrcPulseCheck_M	2727417	1259	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1259
T17	175783	5
T18	175783	5
T22	488486	0
T23	203230	0
T24	488486	0
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T65	175783	5
T98	0	5
T99	0	5
T101	0	5
T102	0	5
T103	0	5
T104	0	5
T105	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1259
T17	627	5
T18	627	5
T22	17445	0
T23	817	0
T24	17445	0
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T65	627	5
T98	0	5
T99	0	5
T101	0	5
T102	0	5
T103	0	5
T104	0	5
T105	0	5

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1192	0	0
SrcPulseCheck_M	754515696	1222	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1192
T17	627	3
T18	627	3
T22	17445	0
T23	817	0
T24	17445	0
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T65	627	3
T98	0	3
T99	0	3
T101	0	3
T102	0	3
T103	0	3
T104	0	3
T105	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1222
T17	175783	3
T18	175783	3
T22	488486	0
T23	203230	0
T24	488486	0
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T65	175783	3
T98	0	3
T99	0	3
T101	0	3
T102	0	3
T103	0	3
T104	0	3
T105	0	3

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T17,T18,T65
1	0	Covered	T17,T18,T65
1	1	Covered	T17,T18,T65

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1192	0	0
SrcPulseCheck_M	2727417	1192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1192
T17	175783	3
T18	175783	3
T22	488486	0
T23	203230	0
T24	488486	0
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T65	175783	3
T98	0	3
T99	0	3
T101	0	3
T102	0	3
T103	0	3
T104	0	3
T105	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1192
T17	627	3
T18	627	3
T22	17445	0
T23	817	0
T24	17445	0
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T65	627	3
T98	0	3
T99	0	3
T101	0	3
T102	0	3
T103	0	3
T104	0	3
T105	0	3

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T28,T34,T95
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T96,T97,T92
1	1	Covered	T28,T34,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1052	0	0
SrcPulseCheck_M	754515696	1102	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1052
T1	0	19
T11	0	13
T21	1037	0
T28	506	1
T29	479	0
T30	1037	0
T31	817	0
T34	0	1
T46	503	0
T47	403	0
T92	0	13
T95	0	1
T96	0	11
T97	0	11
T98	627	0
T106	494	0
T107	884	0
T112	0	1
T113	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1102
T1	0	19
T2	0	2
T21	130789	0
T28	141936	1
T29	134330	0
T30	130789	0
T31	203230	0
T34	0	1
T46	140863	0
T47	112864	0
T92	0	13
T95	0	1
T96	0	11
T97	0	11
T98	175783	0
T106	138342	0
T107	247808	0
T112	0	1
T113	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T28,T34,T95
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T96,T97,T92
1	1	Covered	T28,T34,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1052	0	0
SrcPulseCheck_M	2727417	1052	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1052
T1	0	19
T11	0	13
T21	130789	0
T28	141936	1
T29	134330	0
T30	130789	0
T31	203230	0
T34	0	1
T46	140863	0
T47	112864	0
T92	0	13
T95	0	1
T96	0	11
T97	0	11
T98	175783	0
T106	138342	0
T107	247808	0
T112	0	1
T113	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1052
T1	0	19
T11	0	13
T21	1037	0
T28	506	1
T29	479	0
T30	1037	0
T31	817	0
T34	0	1
T46	503	0
T47	403	0
T92	0	13
T95	0	1
T96	0	11
T97	0	11
T98	627	0
T106	494	0
T107	884	0
T112	0	1
T113	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	982	0	0
SrcPulseCheck_M	754515696	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	982
T1	0	20
T5	0	20
T7	0	20
T11	0	9
T15	0	2
T68	0	2
T69	0	9
T92	0	9
T96	7721	11
T97	0	11
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1012
T1	0	20
T2	0	1
T3	0	1
T5	0	20
T6	0	1
T11	0	9
T15	0	2
T92	0	9
T96	215076	11
T97	0	11
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	982	0	0
SrcPulseCheck_M	2727417	982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	982
T1	0	20
T5	0	20
T7	0	20
T11	0	9
T15	0	2
T68	0	2
T69	0	9
T92	0	9
T96	215076	11
T97	0	11
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	982
T1	0	20
T5	0	20
T7	0	20
T11	0	9
T15	0	2
T68	0	2
T69	0	9
T92	0	9
T96	7721	11
T97	0	11
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1127	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1127
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	7721	11
T97	0	11
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T1	0	20
T2	0	2
T3	0	2
T5	0	20
T6	0	2
T11	0	16
T15	0	2
T92	0	16
T96	215076	11
T97	0	11
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1127	0	0
SrcPulseCheck_M	2727417	1127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1127
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	215076	11
T97	0	11
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1127
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	7721	11
T97	0	11
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T1	0	20
T5	0	20
T7	0	20
T11	0	10
T15	0	2
T68	0	2
T69	0	10
T92	0	10
T96	7721	11
T97	0	11
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T1	0	20
T2	0	1
T3	0	1
T5	0	20
T6	0	1
T11	0	10
T15	0	2
T92	0	10
T96	215076	11
T97	0	11
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T1	0	20
T5	0	20
T7	0	20
T11	0	10
T15	0	2
T68	0	2
T69	0	10
T92	0	10
T96	215076	11
T97	0	11
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T1	0	20
T5	0	20
T7	0	20
T11	0	10
T15	0	2
T68	0	2
T69	0	10
T92	0	10
T96	7721	11
T97	0	11
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T28,T34,T95
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T96,T97,T92
1	1	Covered	T28,T34,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1023	0	0
SrcPulseCheck_M	754515696	1053	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1023
T1	0	20
T11	0	11
T21	1037	0
T28	506	1
T29	479	0
T30	1037	0
T31	817	0
T34	0	1
T46	503	0
T47	403	0
T92	0	11
T95	0	1
T96	0	9
T97	0	9
T98	627	0
T106	494	0
T107	884	0
T112	0	1
T113	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1053
T1	0	20
T2	0	1
T21	130789	0
T28	141936	1
T29	134330	0
T30	130789	0
T31	203230	0
T34	0	1
T46	140863	0
T47	112864	0
T92	0	11
T95	0	1
T96	0	9
T97	0	9
T98	175783	0
T106	138342	0
T107	247808	0
T112	0	1
T113	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T28,T34,T95
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T28,T34,T95
1	0	Covered	T96,T97,T92
1	1	Covered	T28,T34,T95

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1023	0	0
SrcPulseCheck_M	2727417	1023	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1023
T1	0	20
T11	0	11
T21	130789	0
T28	141936	1
T29	134330	0
T30	130789	0
T31	203230	0
T34	0	1
T46	140863	0
T47	112864	0
T92	0	11
T95	0	1
T96	0	9
T97	0	9
T98	175783	0
T106	138342	0
T107	247808	0
T112	0	1
T113	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1023
T1	0	20
T11	0	11
T21	1037	0
T28	506	1
T29	479	0
T30	1037	0
T31	817	0
T34	0	1
T46	503	0
T47	403	0
T92	0	11
T95	0	1
T96	0	9
T97	0	9
T98	627	0
T106	494	0
T107	884	0
T112	0	1
T113	0	1

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1123	0	0
SrcPulseCheck_M	754515696	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1123
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	7721	9
T97	0	9
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1173
T1	0	20
T2	0	2
T3	0	2
T5	0	20
T6	0	2
T11	0	16
T15	0	2
T92	0	16
T96	215076	9
T97	0	9
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1123	0	0
SrcPulseCheck_M	2727417	1123	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1123
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	215076	9
T97	0	9
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1123
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	7721	9
T97	0	9
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1118	0	0
SrcPulseCheck_M	754515696	1168	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1118
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	7721	9
T97	0	9
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1168
T1	0	20
T2	0	2
T3	0	2
T5	0	20
T6	0	2
T11	0	16
T15	0	2
T92	0	16
T96	215076	9
T97	0	9
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1118	0	0
SrcPulseCheck_M	2727417	1118	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1118
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	215076	9
T97	0	9
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1118
T1	0	20
T5	0	20
T7	0	20
T11	0	16
T15	0	2
T68	0	2
T69	0	16
T92	0	16
T96	7721	9
T97	0	9
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1048	0	0
SrcPulseCheck_M	754515696	1078	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1048
T1	0	20
T5	0	20
T7	0	20
T11	0	12
T15	0	2
T68	0	2
T69	0	12
T92	0	12
T96	7721	9
T97	0	9
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1078
T1	0	20
T2	0	1
T3	0	1
T5	0	20
T6	0	1
T11	0	12
T15	0	2
T92	0	12
T96	215076	9
T97	0	9
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T1
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T96,T97,T1
1	0	Covered	T96,T97,T92
1	1	Covered	T96,T97,T1

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1048	0	0
SrcPulseCheck_M	2727417	1048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1048
T1	0	20
T5	0	20
T7	0	20
T11	0	12
T15	0	2
T68	0	2
T69	0	12
T92	0	12
T96	215076	9
T97	0	9
T114	138342	0
T115	140863	0
T116	146706	0
T117	175783	0
T118	175783	0
T119	116176	0
T120	488486	0
T121	488486	0
T122	203230	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1048
T1	0	20
T5	0	20
T7	0	20
T11	0	12
T15	0	2
T68	0	2
T69	0	12
T92	0	12
T96	7721	9
T97	0	9
T114	494	0
T115	503	0
T116	523	0
T117	627	0
T118	627	0
T119	414	0
T120	17445	0
T121	17445	0
T122	817	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1777	0	0
SrcPulseCheck_M	754515696	1827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1777
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1827
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1777	0	0
SrcPulseCheck_M	2727417	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1777
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1777
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1597	0	0
SrcPulseCheck_M	754515696	1627	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1597
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1627
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1597	0	0
SrcPulseCheck_M	2727417	1597	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1597
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1597
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1747	0	0
SrcPulseCheck_M	754515696	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1747
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1777
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1747	0	0
SrcPulseCheck_M	2727417	1747	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1747
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1747
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1692	0	0
SrcPulseCheck_M	754515696	1722	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1692
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1722
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1692	0	0
SrcPulseCheck_M	2727417	1692	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1692
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1692
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1968	0	0
SrcPulseCheck_M	754515696	1998	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1968
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1998
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1968	0	0
SrcPulseCheck_M	2727417	1968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1968
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1968
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1763	0	0
SrcPulseCheck_M	754515696	1793	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1763
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1793
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1763	0	0
SrcPulseCheck_M	2727417	1763	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1763
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1763
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1738	0	0
SrcPulseCheck_M	754515696	1768	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1738
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1768
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1738	0	0
SrcPulseCheck_M	2727417	1738	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1738
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1738
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1813	0	0
SrcPulseCheck_M	754515696	1863	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1813
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1863
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1813	0	0
SrcPulseCheck_M	2727417	1813	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1813
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1813
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1773	0	0
SrcPulseCheck_M	754515696	1803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1773
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1803
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1773	0	0
SrcPulseCheck_M	2727417	1773	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1773
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1773
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T28	0	1
T29	0	1
T32	0	5
T33	0	9
T34	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1663	0	0
SrcPulseCheck_M	754515696	1693	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1663
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1693
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1663	0	0
SrcPulseCheck_M	2727417	1663	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1663
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1663
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1603	0	0
SrcPulseCheck_M	754515696	1633	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1603
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1633
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1603	0	0
SrcPulseCheck_M	2727417	1603	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1603
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1603
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1683	0	0
SrcPulseCheck_M	754515696	1733	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1683
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1733
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T96,T97,T92

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T96,T97,T92
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1683	0	0
SrcPulseCheck_M	2727417	1683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1683
T16	488486	5
T17	175783	0
T18	175783	0
T22	488486	5
T23	203230	0
T24	488486	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0
T100	0	9
T123	0	9
T124	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1683
T16	17445	5
T17	627	0
T18	627	0
T22	17445	5
T23	817	0
T24	17445	5
T25	0	5
T27	0	9
T32	0	5
T33	0	9
T39	403	0
T40	523	0
T41	494	0
T42	503	0
T100	0	9
T123	0	9
T124	0	5

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T24
1	0	Covered	T16,T22,T24
1	1	Covered	T16,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1410	0	0
SrcPulseCheck_M	754515696	1440	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1410
T16	17445	7
T17	627	0
T18	627	0
T22	17445	7
T23	817	0
T24	17445	7
T25	0	7
T27	0	8
T28	0	1
T29	0	1
T32	0	7
T33	0	8
T34	0	1
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1440
T16	488486	7
T17	175783	0
T18	175783	0
T22	488486	7
T23	203230	0
T24	488486	7
T25	0	7
T27	0	8
T28	0	1
T29	0	1
T32	0	7
T33	0	8
T34	0	1
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T16,T22,T23
1	1	Covered	T23,T26,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T16,T17,T18
0	1	Covered	T16,T22,T23
1	0	Covered	T23,T26,T31
1	1	Covered	T16,T22,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	990	0	0
SrcPulseCheck_M	754515696	1022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	990
T16	17445	1
T17	627	0
T18	627	0
T22	17445	1
T23	817	3
T24	17445	1
T25	0	1
T26	0	3
T31	0	3
T32	0	1
T35	0	3
T36	0	3
T39	403	0
T40	523	0
T41	494	0
T42	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1022
T16	488486	1
T17	175783	0
T18	175783	0
T22	488486	1
T23	203230	3
T24	488486	1
T25	0	1
T26	0	3
T31	0	3
T32	0	1
T35	0	3
T36	0	3
T39	112864	0
T40	146706	0
T41	138342	0
T42	140863	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc