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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
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T561 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.37541508740516106201503624027192482550842495251557543879562045721451523620055 Oct 18 12:48:01 PM PDT 23 Oct 18 12:48:06 PM PDT 23 5189470156 ps
T562 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.84547321915130973056797374810454597386535616120537522851194153683716846164980 Oct 18 12:48:26 PM PDT 23 Oct 18 12:48:34 PM PDT 23 4425119128 ps
T563 /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.84627382255838173779997186669354725866095377507962571431051783674029553564683 Oct 18 12:48:00 PM PDT 23 Oct 18 12:48:08 PM PDT 23 4425119128 ps
T564 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.95134548850552365750427025218102772856863537818732424638831908279365683531348 Oct 18 12:49:15 PM PDT 23 Oct 18 12:49:20 PM PDT 23 2619740714 ps
T565 /workspace/coverage/default/17.sysrst_ctrl_stress_all.111514924133396037445787626847486037669689289414776848829136581717974808618753 Oct 18 12:48:28 PM PDT 23 Oct 18 12:50:44 PM PDT 23 87228974549 ps
T566 /workspace/coverage/default/47.sysrst_ctrl_smoke.46484931649743425391255006223995065464165403006674039570631468077098403903260 Oct 18 12:49:08 PM PDT 23 Oct 18 12:49:13 PM PDT 23 2116887594 ps
T567 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.105177202205466550985832806275969506031657261112577895796561284145689488948480 Oct 18 12:48:01 PM PDT 23 Oct 18 12:48:06 PM PDT 23 5189470156 ps
T568 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.89446460605326429349192546248795069974836992188121253312299505273128440881677 Oct 18 12:47:03 PM PDT 23 Oct 18 12:47:08 PM PDT 23 2619740714 ps
T569 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.20396168601683755230911348116737097100026522721911588543463623717267326955890 Oct 18 12:48:18 PM PDT 23 Oct 18 12:48:23 PM PDT 23 2619740714 ps
T570 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.7821112918732406309764958536827306732694814369494078592434781690964552441461 Oct 18 12:47:08 PM PDT 23 Oct 18 12:47:13 PM PDT 23 2074566504 ps
T571 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.16456041470938560545544541432930573271547894107814190571242998635833593377568 Oct 18 12:48:05 PM PDT 23 Oct 18 12:48:12 PM PDT 23 4089103959 ps
T572 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.75796540506885211293228925177236417012883547230649719527317826726603795541100 Oct 18 12:48:22 PM PDT 23 Oct 18 12:48:28 PM PDT 23 5189470156 ps
T573 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.74620372065969551603360437676698024894566278741297443682199029327588770557299 Oct 18 12:48:33 PM PDT 23 Oct 18 12:48:38 PM PDT 23 2515402263 ps
T574 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.104242540042013398735135954657436687823704820900687323273882901790619819821721 Oct 18 12:47:57 PM PDT 23 Oct 18 12:48:04 PM PDT 23 4089103959 ps
T575 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.62498722679247759604165374588945181742056416064804478337308640678851666399969 Oct 18 12:48:30 PM PDT 23 Oct 18 12:48:34 PM PDT 23 2074566504 ps
T576 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.37933558046049622502133291686189377826122164649029922105784716699850404334371 Oct 18 12:48:55 PM PDT 23 Oct 18 12:49:00 PM PDT 23 2619740714 ps
T577 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.61255630605007410525655380648461512880990995757177270175895797133497220785237 Oct 18 12:48:19 PM PDT 23 Oct 18 12:48:25 PM PDT 23 5189470156 ps
T578 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.51758796551992559849850584775075862246068293445119671868647052377774924021054 Oct 18 12:48:23 PM PDT 23 Oct 18 12:48:28 PM PDT 23 5189470156 ps
T579 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.16950030807518832486368669866302140255356182457315576348180322452220152909914 Oct 18 12:49:14 PM PDT 23 Oct 18 12:49:19 PM PDT 23 2619740714 ps
T580 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.65377817515495639499301649622807327537463520759373813193500625987474435303296 Oct 18 12:48:18 PM PDT 23 Oct 18 12:48:23 PM PDT 23 5189470156 ps
T112 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.110775410601171532697201096628913083961587647768497697580009968997790199179880 Oct 18 12:46:46 PM PDT 23 Oct 18 12:46:51 PM PDT 23 2534562824 ps
T581 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.6527437800781475268830924673362381100697954084234450262731709276071133110134 Oct 18 12:48:37 PM PDT 23 Oct 18 12:48:42 PM PDT 23 2619740714 ps
T582 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.54381263857155027516592102139885245012845176139921838337228208878313172468922 Oct 18 12:48:42 PM PDT 23 Oct 18 12:48:48 PM PDT 23 2619740714 ps
T583 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.108590167446006390400297996532542289992501176073827098106299371660261001399075 Oct 18 12:48:16 PM PDT 23 Oct 18 12:48:21 PM PDT 23 5189470156 ps
T584 /workspace/coverage/default/41.sysrst_ctrl_smoke.59726261985577039734737189389696440359989346547422220932073754478697721563050 Oct 18 12:49:08 PM PDT 23 Oct 18 12:49:12 PM PDT 23 2116887594 ps
T585 /workspace/coverage/default/22.sysrst_ctrl_smoke.76740825066410855013412938977866719301094825279403403136106833179519655272560 Oct 18 12:48:08 PM PDT 23 Oct 18 12:48:12 PM PDT 23 2116887594 ps
T586 /workspace/coverage/default/26.sysrst_ctrl_smoke.36726206857143115822380542293292709847307730061257029176947217666985117389961 Oct 18 12:48:33 PM PDT 23 Oct 18 12:48:37 PM PDT 23 2116887594 ps
T587 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.8026790309622121079484570723768586816563607665246154245025424078595972978603 Oct 18 12:47:56 PM PDT 23 Oct 18 12:48:00 PM PDT 23 2074566504 ps
T588 /workspace/coverage/default/2.sysrst_ctrl_smoke.84137134111699665067204426194784701433904737668809684393160522542519629916298 Oct 18 12:47:02 PM PDT 23 Oct 18 12:47:06 PM PDT 23 2116887594 ps
T589 /workspace/coverage/default/43.sysrst_ctrl_stress_all.29005191472231250581000239664144752309307490572345652723166089044601695735117 Oct 18 12:49:15 PM PDT 23 Oct 18 12:51:31 PM PDT 23 87228974549 ps
T590 /workspace/coverage/default/4.sysrst_ctrl_stress_all.60689015668155085741983401065449668024620101083647532530268190790349571494170 Oct 18 12:47:09 PM PDT 23 Oct 18 12:49:25 PM PDT 23 87228974549 ps
T591 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.43070541991143842965316266541960655718256218479293121991894190708392117842351 Oct 18 12:49:09 PM PDT 23 Oct 18 12:49:14 PM PDT 23 2074566504 ps
T592 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.366828364853748486304209050322376205017295384418501877202469657356761443401 Oct 18 12:49:06 PM PDT 23 Oct 18 12:49:14 PM PDT 23 4425119128 ps
T593 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.81848734373894497877541557491555603760415824793648313898501096647399524259753 Oct 18 12:49:17 PM PDT 23 Oct 18 12:49:23 PM PDT 23 2470384766 ps
T594 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.31660778715077707141166088700456135307280675309788878201532345963547817528212 Oct 18 12:48:36 PM PDT 23 Oct 18 12:48:44 PM PDT 23 4425119128 ps
T113 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.60664573616171827595946118299072596082898200835932441481165506025313361694897 Oct 18 12:46:57 PM PDT 23 Oct 18 12:47:02 PM PDT 23 2534562824 ps
T595 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.30924909968671707062653295274994251146464073142340630117318775150759968979511 Oct 18 12:48:58 PM PDT 23 Oct 18 12:49:03 PM PDT 23 2470384766 ps
T596 /workspace/coverage/default/48.sysrst_ctrl_smoke.104253171364606818370047683486463657569971311500138561331270055350758277233494 Oct 18 12:49:21 PM PDT 23 Oct 18 12:49:25 PM PDT 23 2116887594 ps
T597 /workspace/coverage/default/0.sysrst_ctrl_alert_test.43397225374974161775339815126005710663368233481106172716261627311990476749949 Oct 18 12:46:56 PM PDT 23 Oct 18 12:47:00 PM PDT 23 2015424120 ps
T598 /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.82982024331372584724631175313365385284468954157654186172537652076225774849954 Oct 18 12:48:26 PM PDT 23 Oct 18 12:48:31 PM PDT 23 2515402263 ps
T599 /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.99782390408386137369574975343495534806539056544334788689910886274339535074260 Oct 18 12:49:11 PM PDT 23 Oct 18 12:49:16 PM PDT 23 2515402263 ps
T600 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.55490233549112705995909477446322034992757992377518032194884435801599830801625 Oct 18 12:46:51 PM PDT 23 Oct 18 12:46:58 PM PDT 23 4089103959 ps
T601 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.34725746484121897728750847246827202813315913037288547475101204200042222203747 Oct 18 12:49:11 PM PDT 23 Oct 18 12:49:19 PM PDT 23 4425119128 ps
T602 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.34351096991458812033387780804144417854999358348455410459712568321684749156142 Oct 18 12:48:59 PM PDT 23 Oct 18 12:49:07 PM PDT 23 4425119128 ps
T603 /workspace/coverage/default/21.sysrst_ctrl_stress_all.26965260537178489169849387515653561406059359125408990975878541411734039466352 Oct 18 12:48:14 PM PDT 23 Oct 18 12:50:30 PM PDT 23 87228974549 ps
T604 /workspace/coverage/default/18.sysrst_ctrl_stress_all.111545340549644295729126455201696872191932273389914400817803367855941389137994 Oct 18 12:48:24 PM PDT 23 Oct 18 12:50:40 PM PDT 23 87228974549 ps
T605 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.4108600962453752599749672401247651423277383861319969665289688647389955914819 Oct 18 12:48:58 PM PDT 23 Oct 18 12:49:05 PM PDT 23 4089103959 ps
T606 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.94726023095211759711046672673416320075835317568642100596940892812401650447736 Oct 18 12:47:00 PM PDT 23 Oct 18 12:47:08 PM PDT 23 4425119128 ps
T607 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.112700953432069177790649657453949137858542461447874643722886214276464503427901 Oct 18 12:48:38 PM PDT 23 Oct 18 12:48:42 PM PDT 23 2074566504 ps
T608 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.64467621822143508182684891745783208683875675275678144433750955061292659961911 Oct 18 12:48:12 PM PDT 23 Oct 18 12:48:19 PM PDT 23 4089103959 ps
T609 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.26073673311669490122060612846844449753598531409974660005155944668899255828629 Oct 18 12:48:12 PM PDT 23 Oct 18 12:48:16 PM PDT 23 2074566504 ps
T610 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.96973568845828887813863975985364385498695069403495565399800709165104759542147 Oct 18 12:47:58 PM PDT 23 Oct 18 12:48:03 PM PDT 23 2515402263 ps
T611 /workspace/coverage/default/47.sysrst_ctrl_alert_test.97285905759898056072148047680625983168239390170704260417118368214220735395115 Oct 18 12:49:15 PM PDT 23 Oct 18 12:49:19 PM PDT 23 2015424120 ps
T612 /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.85252882677175668542341773908772499576328225908447228510463515532415249914472 Oct 18 12:48:11 PM PDT 23 Oct 18 12:48:17 PM PDT 23 3138968703 ps
T613 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3119413018814953486984341088389138881212364406517453108080406951405478497693 Oct 18 12:49:10 PM PDT 23 Oct 18 12:49:18 PM PDT 23 4425119128 ps
T614 /workspace/coverage/default/10.sysrst_ctrl_alert_test.35185786252732890850459460105731659218118434990653529777894173567168988720761 Oct 18 12:48:04 PM PDT 23 Oct 18 12:48:08 PM PDT 23 2015424120 ps
T615 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.35434897560089924908628863185049485651072534336958097103749135860804206570510 Oct 18 12:47:00 PM PDT 23 Oct 18 12:47:07 PM PDT 23 4089103959 ps
T616 /workspace/coverage/default/49.sysrst_ctrl_smoke.21828211529670358103781473614364490300745730023796581997011543044414932303494 Oct 18 12:49:18 PM PDT 23 Oct 18 12:49:22 PM PDT 23 2116887594 ps
T617 /workspace/coverage/default/42.sysrst_ctrl_smoke.52433682183300100427133464564183781419813083494743360194389414531265599153409 Oct 18 12:49:07 PM PDT 23 Oct 18 12:49:11 PM PDT 23 2116887594 ps
T618 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.111042610128963424617245661356364409888955199051730734074104235678442344853332 Oct 18 12:48:20 PM PDT 23 Oct 18 12:48:25 PM PDT 23 2619740714 ps
T619 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4191798039862508187903108674931297181573446468859725997358249769186972007302 Oct 18 12:48:01 PM PDT 23 Oct 18 12:48:07 PM PDT 23 3138968703 ps
T620 /workspace/coverage/default/40.sysrst_ctrl_smoke.72883797290899690128933365614254682874816062035632228777036055255582665458748 Oct 18 12:49:13 PM PDT 23 Oct 18 12:49:17 PM PDT 23 2116887594 ps
T621 /workspace/coverage/default/12.sysrst_ctrl_stress_all.94307120304977969273447586371667247522860662456871531337499306330734572513281 Oct 18 12:48:01 PM PDT 23 Oct 18 12:50:15 PM PDT 23 87228974549 ps
T622 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.48218930039026904873229146922956673656093175339695214387878488226395875884801 Oct 18 12:47:13 PM PDT 23 Oct 18 12:47:18 PM PDT 23 2619740714 ps
T623 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.71063353001041415056055114077248134044791730140339778644579760642085344838512 Oct 18 12:46:57 PM PDT 23 Oct 18 12:49:59 PM PDT 23 118289458206 ps
T624 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.97996563959056067375168802157093372377124896329523761124405779765916291199871 Oct 18 12:48:12 PM PDT 23 Oct 18 12:51:14 PM PDT 23 118289458206 ps
T625 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.48932566746618778819079850282476747249368451548252084623505359911539992401899 Oct 18 12:47:59 PM PDT 23 Oct 18 12:48:04 PM PDT 23 2619740714 ps
T626 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.83929790203658296409729126743375423405281336503734657062800616971449617377451 Oct 18 12:46:52 PM PDT 23 Oct 18 12:46:57 PM PDT 23 2398742482 ps
T627 /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.61407177866042625545074125369779838314277431513975904735823849051510595402988 Oct 18 12:48:55 PM PDT 23 Oct 18 12:48:59 PM PDT 23 2074566504 ps
T628 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.19737896987605589053699896257408362582634131831710393139856164766752959830517 Oct 18 12:48:13 PM PDT 23 Oct 18 12:51:17 PM PDT 23 118289458206 ps
T629 /workspace/coverage/default/14.sysrst_ctrl_alert_test.110986910442832449316951037457720612893808534601220413070720525426538677085849 Oct 18 12:48:19 PM PDT 23 Oct 18 12:48:23 PM PDT 23 2015424120 ps
T630 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.64517280097718181413339952017411793706993776115803619847067871506529863095771 Oct 18 12:48:31 PM PDT 23 Oct 18 12:48:39 PM PDT 23 4425119128 ps
T631 /workspace/coverage/default/45.sysrst_ctrl_smoke.71063598688800673401532077205593042629697835071841685574720310292217663124553 Oct 18 12:49:18 PM PDT 23 Oct 18 12:49:23 PM PDT 23 2116887594 ps
T632 /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.85156607728337631562068987692668343346786796608618733465005163434209567423987 Oct 18 12:49:13 PM PDT 23 Oct 18 12:49:18 PM PDT 23 2619740714 ps
T633 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.102967538186825438467672507818615013399366138868752638160535814335538179280257 Oct 18 12:48:57 PM PDT 23 Oct 18 12:49:04 PM PDT 23 4089103959 ps
T634 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.69008032726342795257288836862262441886622235077585868659168597834891272190176 Oct 18 12:49:24 PM PDT 23 Oct 18 12:49:29 PM PDT 23 2470384766 ps
T635 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.5895863024010324916139871267036108242461851763077980614092269074956984016560 Oct 18 12:48:11 PM PDT 23 Oct 18 12:48:17 PM PDT 23 3138968703 ps
T636 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.25633124664067942141587920738864149587366056763662572323418534360453626595595 Oct 18 12:48:49 PM PDT 23 Oct 18 12:48:57 PM PDT 23 4425119128 ps
T637 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.55253802779010104807468287186189509480585711233649863402486676401918906446683 Oct 18 12:48:02 PM PDT 23 Oct 18 12:48:07 PM PDT 23 5189470156 ps
T638 /workspace/coverage/default/32.sysrst_ctrl_stress_all.108367809370300552368147312432697684369921218310474000141428995405873954597533 Oct 18 12:49:09 PM PDT 23 Oct 18 12:51:23 PM PDT 23 87228974549 ps
T639 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2736576633793019279279577882710910985743675338403762541369683005808738252057 Oct 18 12:49:24 PM PDT 23 Oct 18 12:52:24 PM PDT 23 118289458206 ps
T640 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.80084735394934079888467329325259092798727218622639393683832554038951244737900 Oct 18 12:48:58 PM PDT 23 Oct 18 12:49:03 PM PDT 23 5189470156 ps
T641 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.15556781520818625217229357478608717238790851513443565860096721441975454380376 Oct 18 12:49:20 PM PDT 23 Oct 18 12:49:27 PM PDT 23 4089103959 ps
T642 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.101428404229292688877146259138876631910572991404388577161943725682326347463192 Oct 18 12:46:59 PM PDT 23 Oct 18 12:47:04 PM PDT 23 2470384766 ps
T643 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.61115585022658001916141479578957238006489773145880695195170855124410045223169 Oct 18 12:48:20 PM PDT 23 Oct 18 12:48:28 PM PDT 23 4425119128 ps
T644 /workspace/coverage/default/35.sysrst_ctrl_edge_detect.88013976777984613237279007975044215886248541205200708133823050399396243009228 Oct 18 12:48:57 PM PDT 23 Oct 18 12:49:04 PM PDT 23 4089103959 ps
T645 /workspace/coverage/default/33.sysrst_ctrl_stress_all.96702525865807032521551516870732305072608166541802377619948336024797147430888 Oct 18 12:48:32 PM PDT 23 Oct 18 12:50:51 PM PDT 23 87228974549 ps
T646 /workspace/coverage/default/47.sysrst_ctrl_stress_all.57105116145083764110396106850934335211743324375262328603896152235017604931824 Oct 18 12:49:20 PM PDT 23 Oct 18 12:51:35 PM PDT 23 87228974549 ps
T647 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.25456928088921894618984319251925815197653025658385616455266804526193031728298 Oct 18 12:48:18 PM PDT 23 Oct 18 12:48:24 PM PDT 23 3138968703 ps
T648 /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.78721074595401986230796061564332158009084985034581644516533872646325503297731 Oct 18 12:48:30 PM PDT 23 Oct 18 12:48:36 PM PDT 23 3138968703 ps
T649 /workspace/coverage/default/7.sysrst_ctrl_alert_test.8740521868870648662346296673924204754484022356620240742289848986252774567030 Oct 18 12:47:04 PM PDT 23 Oct 18 12:47:08 PM PDT 23 2015424120 ps
T650 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.105733261391658126605873052128898708573336005222654437104404963426822467710945 Oct 18 12:46:55 PM PDT 23 Oct 18 12:47:00 PM PDT 23 2398742482 ps
T651 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.72486084032163694129970870535681595461263078332222165955912946344150879836633 Oct 18 12:48:21 PM PDT 23 Oct 18 12:48:27 PM PDT 23 5189470156 ps
T652 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.49549585285827452766076607901687544901036661313244575334994831840805069062055 Oct 18 12:47:05 PM PDT 23 Oct 18 12:47:11 PM PDT 23 3138968703 ps
T653 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.56117929001357500950494158608381389837149045366831872452625649621848171044186 Oct 18 12:48:41 PM PDT 23 Oct 18 12:51:41 PM PDT 23 118289458206 ps
T654 /workspace/coverage/default/23.sysrst_ctrl_stress_all.96075576297357893453540373613073003739216272672498984448279677106822006881267 Oct 18 12:48:09 PM PDT 23 Oct 18 12:50:25 PM PDT 23 87228974549 ps
T655 /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.46691062896935109189851219119897508724584565565990787017571928554606413571593 Oct 18 12:47:01 PM PDT 23 Oct 18 12:47:07 PM PDT 23 3138968703 ps
T656 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.30282412639675472402424094904487722994651202719803723524247810698527273373177 Oct 18 12:48:02 PM PDT 23 Oct 18 12:48:06 PM PDT 23 2515402263 ps
T657 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.90223786065997605518790999317049898433764741300207217860245650559414552720667 Oct 18 12:48:29 PM PDT 23 Oct 18 12:51:31 PM PDT 23 118289458206 ps
T658 /workspace/coverage/default/5.sysrst_ctrl_edge_detect.29238025386618612992153915923954551857656124806957910174735920453241968499669 Oct 18 12:47:02 PM PDT 23 Oct 18 12:47:08 PM PDT 23 4089103959 ps
T659 /workspace/coverage/default/34.sysrst_ctrl_smoke.6844159957536458601854130687797683636053704288220346295712156378627514377093 Oct 18 12:48:35 PM PDT 23 Oct 18 12:48:40 PM PDT 23 2116887594 ps
T660 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.90160103342118873507353161513213041167715711999021324741877632668416363964426 Oct 18 12:48:56 PM PDT 23 Oct 18 12:49:04 PM PDT 23 4425119128 ps
T661 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.67587743758288746859896146329837459635561140528836773030594839273187645374875 Oct 18 12:48:35 PM PDT 23 Oct 18 12:48:41 PM PDT 23 2470384766 ps
T662 /workspace/coverage/default/3.sysrst_ctrl_stress_all.106541219328573767352731901196338310696864027156563470109369333738935690931824 Oct 18 12:47:02 PM PDT 23 Oct 18 12:49:18 PM PDT 23 87228974549 ps
T663 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.115633875090469544150967582414590924889250439455150781215829100964554492438782 Oct 18 12:47:04 PM PDT 23 Oct 18 12:47:09 PM PDT 23 5189470156 ps
T664 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.42877851227575042092768995125999590107833841122521521528415702473212281255746 Oct 18 12:48:52 PM PDT 23 Oct 18 12:48:57 PM PDT 23 2515402263 ps
T665 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.50205747440828589756653577761758069499763874349092432689331755009120088677105 Oct 18 12:47:49 PM PDT 23 Oct 18 12:47:55 PM PDT 23 5189470156 ps
T666 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.66174800773060013187753525632404484239324832562568640854920287413519634005355 Oct 18 12:48:26 PM PDT 23 Oct 18 12:48:31 PM PDT 23 2619740714 ps
T667 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.44704492365810343933092238969594820631181058100578594352812835389672609901078 Oct 18 12:48:12 PM PDT 23 Oct 18 12:48:17 PM PDT 23 2074566504 ps
T668 /workspace/coverage/default/27.sysrst_ctrl_alert_test.20653523663215600221370887279371066871071173053470608771993862417981511741386 Oct 18 12:48:36 PM PDT 23 Oct 18 12:48:40 PM PDT 23 2015424120 ps
T669 /workspace/coverage/default/24.sysrst_ctrl_smoke.7672556395405064328036502567258315896755400341151077760634297038948285241315 Oct 18 12:48:28 PM PDT 23 Oct 18 12:48:32 PM PDT 23 2116887594 ps
T670 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.25423297030806645972873069852245579678849864433110672294801431986289638748641 Oct 18 12:48:51 PM PDT 23 Oct 18 12:48:56 PM PDT 23 5189470156 ps
T671 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.65113301059739278010629842459630230414898433565292663930840388806648565640079 Oct 18 12:48:20 PM PDT 23 Oct 18 12:48:25 PM PDT 23 2515402263 ps
T672 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.29553006259413212383136025491276720390340993912358001905833762226265407002158 Oct 18 12:48:05 PM PDT 23 Oct 18 12:48:10 PM PDT 23 2515402263 ps
T673 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.55553557569444061297118394837359881871977956638030359169138144337357186703184 Oct 18 12:48:37 PM PDT 23 Oct 18 12:51:40 PM PDT 23 118289458206 ps
T674 /workspace/coverage/default/21.sysrst_ctrl_edge_detect.21653186312842341076176183048338686373327293392454803164723980994585906358396 Oct 18 12:48:30 PM PDT 23 Oct 18 12:48:36 PM PDT 23 4089103959 ps
T140 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.87901758778156728138033860810044717335203596028044013236488833522095480670862 Oct 18 12:46:57 PM PDT 23 Oct 18 12:48:03 PM PDT 23 42018621949 ps
T137 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.6857941242882667998364751519145005771814186048831071602766316524142655735312 Oct 18 12:32:03 PM PDT 23 Oct 18 12:32:07 PM PDT 23 2023227629 ps
T1 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.69140321308847187007173398429449637673770544909392891217327064791773652266886 Oct 18 12:32:59 PM PDT 23 Oct 18 12:34:08 PM PDT 23 42510939439 ps
T2 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2313208573332776477940572362837633707801057468164818915136204915228257629777 Oct 18 12:26:10 PM PDT 23 Oct 18 12:26:15 PM PDT 23 2142012393 ps
T138 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.9953619141845776906797087983045240198735913198987357152055909711004334383840 Oct 18 12:31:56 PM PDT 23 Oct 18 12:32:00 PM PDT 23 2023227629 ps
T92 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.78584176414701784564672738432000363673315811360136420501187800916539830104549 Oct 18 12:32:05 PM PDT 23 Oct 18 12:32:29 PM PDT 23 9477310853 ps
T93 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.19378241731292424426142078680598859530336117924045416486448858981786992814831 Oct 18 12:32:09 PM PDT 23 Oct 18 12:32:13 PM PDT 23 2023227629 ps
T3 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.102954136006527525073206377054254584408781515165161124449847063842279319916669 Oct 18 12:33:25 PM PDT 23 Oct 18 12:33:30 PM PDT 23 2142012393 ps
T4 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.114344372690546360288776779343256753958865126416792462381591281577517012532507 Oct 18 12:32:25 PM PDT 23 Oct 18 12:32:31 PM PDT 23 2186637036 ps
T11 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.40480160818030532056369715357288004730441508330516213751893212657626263309427 Oct 18 12:33:21 PM PDT 23 Oct 18 12:33:46 PM PDT 23 9477310853 ps
T12 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.13089691140777483432089127423649805494586689551457859844860097450448222017508 Oct 18 12:31:32 PM PDT 23 Oct 18 12:31:36 PM PDT 23 2023227629 ps
T13 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.96186956408834692581926359573641524948249758337670214878840729342920717222327 Oct 18 12:32:12 PM PDT 23 Oct 18 12:32:17 PM PDT 23 2023227629 ps
T5 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.94335327744959155249165534245383595899638733688428539950377667205076038827912 Oct 18 12:31:57 PM PDT 23 Oct 18 12:33:07 PM PDT 23 42510939439 ps
T14 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.65305258033242057575899335686513866249253931817579227002887811654631544452916 Oct 18 12:31:31 PM PDT 23 Oct 18 12:31:35 PM PDT 23 2023227629 ps
T15 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.49436838319131692668773971375288368406751007715721354105881832994857281282938 Oct 18 12:32:07 PM PDT 23 Oct 18 12:32:12 PM PDT 23 2074977215 ps
T6 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.48917615980813136957635759498076387115859560629197969407033961054662566226476 Oct 18 12:26:34 PM PDT 23 Oct 18 12:26:39 PM PDT 23 2142012393 ps
T55 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.34181516108945705695402729667733138775623184384186942607051655069068487147467 Oct 18 12:32:18 PM PDT 23 Oct 18 12:32:22 PM PDT 23 2023227629 ps
T64 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.107494747335130470297446233549316158545950372195420345592827852071500543423582 Oct 18 12:32:37 PM PDT 23 Oct 18 12:32:42 PM PDT 23 2023227629 ps
T68 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.24020784332083992682403878831144703683188095005899937494203796667553153862867 Oct 18 12:31:34 PM PDT 23 Oct 18 12:31:39 PM PDT 23 2074977215 ps
T7 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.90642344046102748731398121598210486785748394586533309061747065320148306687978 Oct 18 12:26:05 PM PDT 23 Oct 18 12:27:15 PM PDT 23 42510939439 ps
T69 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.73642666929427240588382056890310722443437581706579274974130574684422973107222 Oct 18 12:26:11 PM PDT 23 Oct 18 12:26:41 PM PDT 23 9477310853 ps
T8 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.23600208031139032803710067817414700290457227500930027779879175927580037534 Oct 18 12:32:01 PM PDT 23 Oct 18 12:33:20 PM PDT 23 42510939439 ps
T9 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.112511239711537149821126348089069752511050233082986743249248408370506586742403 Oct 18 12:32:08 PM PDT 23 Oct 18 12:33:18 PM PDT 23 42510939439 ps
T10 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.30646763901259065527525637911315663161079575839422410189983797420995143563794 Oct 18 12:27:51 PM PDT 23 Oct 18 12:29:01 PM PDT 23 42510939439 ps
T675 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.62146135365056021270809957889346165293854642273220726995355183702583351406377 Oct 18 12:31:38 PM PDT 23 Oct 18 12:31:42 PM PDT 23 2023227629 ps
T70 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.92200751991146393948483000098325002939140039140708998973244335832894401600560 Oct 18 12:32:03 PM PDT 23 Oct 18 12:33:55 PM PDT 23 41047879715 ps
T78 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.47863971185358542744351358029047664602357727371650799260362012318150327377993 Oct 18 12:32:05 PM PDT 23 Oct 18 12:32:30 PM PDT 23 9477310853 ps
T79 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.74973689304752076096480354124684151681474371887150210215282907884582419843685 Oct 18 12:31:48 PM PDT 23 Oct 18 12:31:52 PM PDT 23 2023227629 ps
T52 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.81669653620480593485466348863919631591740301025939497764756102611903926482183 Oct 18 12:31:35 PM PDT 23 Oct 18 12:32:46 PM PDT 23 42510939439 ps
T71 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.93079506347657964797138141075049680157157596460682622279704707921759392475110 Oct 18 12:25:17 PM PDT 23 Oct 18 12:25:21 PM PDT 23 2074977215 ps
T80 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4819911824654208139436269123940984077647499162298791781611628999227322023680 Oct 18 12:34:06 PM PDT 23 Oct 18 12:34:12 PM PDT 23 2023227629 ps
T81 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.103233183421387073451857407258114376990587470950623560306458177771490263028081 Oct 18 12:31:50 PM PDT 23 Oct 18 12:31:54 PM PDT 23 2023227629 ps
T72 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.80677928392060125160889683627771799369197812650188749849162998868100615307788 Oct 18 12:31:34 PM PDT 23 Oct 18 12:31:44 PM PDT 23 2074977215 ps
T53 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.72679341669708345211571605031567197771194494310291659049843045592695712675018 Oct 18 12:25:15 PM PDT 23 Oct 18 12:25:21 PM PDT 23 2186637036 ps
T82 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.73429790013116641302678041773484466324652810329425832760788874869985941876578 Oct 18 12:27:34 PM PDT 23 Oct 18 12:27:44 PM PDT 23 2142012393 ps
T54 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.79135609922274468522322146009515656259406185446759351610530890226586703318761 Oct 18 12:26:05 PM PDT 23 Oct 18 12:27:15 PM PDT 23 42510939439 ps
T676 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1231933405065167247064565116314206409149674154396400796663450149156009589089 Oct 18 12:31:49 PM PDT 23 Oct 18 12:31:53 PM PDT 23 2023227629 ps
T73 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.72885239487443909354520619523350253131653821350848467945018740869176578119917 Oct 18 12:28:06 PM PDT 23 Oct 18 12:28:11 PM PDT 23 2074977215 ps
T74 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.55295279325158935601933791633388008991065288778704346433916288167440717312761 Oct 18 12:26:11 PM PDT 23 Oct 18 12:26:22 PM PDT 23 6030981281 ps
T677 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.61436736231834592196685515809826448809947436501133852953050787937956277398151 Oct 18 12:32:21 PM PDT 23 Oct 18 12:32:25 PM PDT 23 2023227629 ps
T678 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.35896214356398141087221206188991065501492462850234922399971605068777217783675 Oct 18 12:31:49 PM PDT 23 Oct 18 12:31:54 PM PDT 23 2142012393 ps
T679 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.68149800049846163293765166448711442259088326885817696857120656801453051440112 Oct 18 12:31:32 PM PDT 23 Oct 18 12:31:36 PM PDT 23 2023227629 ps
T680 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2986601773502945102131059681289377192212558082733465357249010010522992622786 Oct 18 12:32:51 PM PDT 23 Oct 18 12:32:55 PM PDT 23 2023227629 ps
T681 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.51025047778878843391098867215912548858692635033773499395615611614173798976389 Oct 18 12:32:12 PM PDT 23 Oct 18 12:32:16 PM PDT 23 2023227629 ps
T56 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.53948290650056639477996005295914022596266895814232297906707249616254659256904 Oct 18 12:31:46 PM PDT 23 Oct 18 12:31:52 PM PDT 23 2186637036 ps
T57 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.37152952043677085476092546652428590762996589408367890418675878729172747884050 Oct 18 12:31:53 PM PDT 23 Oct 18 12:31:59 PM PDT 23 2186637036 ps
T94 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.23095077172237752901513943581222062926701441221148219240700993491003819265811 Oct 18 12:32:35 PM PDT 23 Oct 18 12:33:01 PM PDT 23 9477310853 ps
T682 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.37749759288301842075013021124768889746618612569007685350764187049355563116969 Oct 18 12:32:20 PM PDT 23 Oct 18 12:32:44 PM PDT 23 9477310853 ps
T75 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.66294272915925293240314929004560927945319896863284410597965653956816048155513 Oct 18 12:32:00 PM PDT 23 Oct 18 12:32:05 PM PDT 23 2074977215 ps
T683 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.10624255531283191768647531376321297919745590965370363393700349046847916866045 Oct 18 12:33:04 PM PDT 23 Oct 18 12:33:09 PM PDT 23 2142012393 ps
T76 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.79361371742636043549708368740977829322271948598933333802564671777704012671841 Oct 18 12:27:25 PM PDT 23 Oct 18 12:29:15 PM PDT 23 41047879715 ps
T684 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.83641522098297646494556101991323492292712472255117826324602062658575394698994 Oct 18 12:32:20 PM PDT 23 Oct 18 12:32:24 PM PDT 23 2023227629 ps
T685 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.44872360518334705214432382233817703953366317816544247694698332624021517611894 Oct 18 12:32:23 PM PDT 23 Oct 18 12:32:29 PM PDT 23 2142012393 ps
T686 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.80603270374567311599596096899511056039223937700929213602972454913408648535314 Oct 18 12:31:50 PM PDT 23 Oct 18 12:31:55 PM PDT 23 2142012393 ps
T687 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.102283099824332467243040245055449514085052977365791065133429686476879320226333 Oct 18 12:31:39 PM PDT 23 Oct 18 12:31:43 PM PDT 23 2023227629 ps
T58 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.79127204078715286921806331353026763012023940711194883902148870061651809785178 Oct 18 12:32:00 PM PDT 23 Oct 18 12:32:06 PM PDT 23 2186637036 ps
T688 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.46510176198571647131204070912690886058565303352061090999288971252052547074805 Oct 18 12:32:38 PM PDT 23 Oct 18 12:32:42 PM PDT 23 2023227629 ps
T59 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.21448469616091095326995333624394326447448693094473680418085184295324965788439 Oct 18 12:31:37 PM PDT 23 Oct 18 12:31:55 PM PDT 23 2186637036 ps
T689 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.16230161095983246379330823770386989788312284658361499504001107003982223009597 Oct 18 12:32:15 PM PDT 23 Oct 18 12:32:19 PM PDT 23 2023227629 ps
T690 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.30507784805390840860621430616915967220624098245022575047422262477068608310682 Oct 18 12:31:38 PM PDT 23 Oct 18 12:32:08 PM PDT 23 9477310853 ps
T60 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.94064021097248008522041669122138655811337641371988050834924147733076062609535 Oct 18 12:32:19 PM PDT 23 Oct 18 12:32:25 PM PDT 23 2186637036 ps
T691 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.37966649387463439381632812676889026607838616799052837534327450308087954667675 Oct 18 12:32:24 PM PDT 23 Oct 18 12:33:33 PM PDT 23 42510939439 ps
T692 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.43145190079952856209137042635231539893838800473295537441791217722469985034389 Oct 18 12:32:19 PM PDT 23 Oct 18 12:32:23 PM PDT 23 2023227629 ps
T77 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.42816337618027283688008096544132184998686022393530933733042887987310517158534 Oct 18 12:27:04 PM PDT 23 Oct 18 12:27:15 PM PDT 23 6030981281 ps
T693 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.17855065147658045996409609044034268127675464290363117742806329730297023131366 Oct 18 12:25:32 PM PDT 23 Oct 18 12:25:36 PM PDT 23 2074977215 ps
T694 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.48388459206412638925592077093312405891827898877124661753600916766453895508744 Oct 18 12:31:42 PM PDT 23 Oct 18 12:31:46 PM PDT 23 2074977215 ps
T695 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.55428455086342987622127103412955051947006465942315541309928340217078034875136 Oct 18 12:31:31 PM PDT 23 Oct 18 12:31:35 PM PDT 23 2023227629 ps
T696 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.14584863453688645070073807336057231535816314027039980665722170070557448064445 Oct 18 12:31:32 PM PDT 23 Oct 18 12:31:56 PM PDT 23 9477310853 ps
T61 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.89396727902580972532280342761948199044139302374638352879731763672928859764042 Oct 18 12:31:53 PM PDT 23 Oct 18 12:31:59 PM PDT 23 2186637036 ps
T697 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.55444388981269443036016987490812263395825372113424351592005678469372186145987 Oct 18 12:31:46 PM PDT 23 Oct 18 12:32:56 PM PDT 23 42510939439 ps
T698 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.103827700010064955556383020511616435113374811122893943487170594927959573270069 Oct 18 12:32:17 PM PDT 23 Oct 18 12:32:22 PM PDT 23 2023227629 ps
T699 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.67640214758334270451473309132138433274124415408772229769596817920595874186620 Oct 18 12:31:49 PM PDT 23 Oct 18 12:31:58 PM PDT 23 2023227629 ps
T700 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1224100237138502214252113942344112435178662000276988134228039804021092346919 Oct 18 12:33:22 PM PDT 23 Oct 18 12:34:30 PM PDT 23 42510939439 ps
T701 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.7902504710827062477790779814576013305960726255904369694772733180454346627961 Oct 18 12:31:34 PM PDT 23 Oct 18 12:31:38 PM PDT 23 2142012393 ps
T62 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.10868861016823677583035094213730496893984090014293411054665262831845532542245 Oct 18 12:23:36 PM PDT 23 Oct 18 12:23:42 PM PDT 23 2186637036 ps
T702 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.112817092054264132850842468008890106013559974742512391587169970646809916244461 Oct 18 12:31:40 PM PDT 23 Oct 18 12:31:44 PM PDT 23 2074977215 ps
T703 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.78252413489198521544469637180191790975711067391995197178714155823724317652497 Oct 18 12:31:39 PM PDT 23 Oct 18 12:31:43 PM PDT 23 2142012393 ps
T704 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.33865881321406674800158813677822599857900710708684689311399615705087832495048 Oct 18 12:32:19 PM PDT 23 Oct 18 12:32:28 PM PDT 23 2023227629 ps
T705 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.75208789980406551737171563979736993557331863544511655045257033434417621411139 Oct 18 12:32:22 PM PDT 23 Oct 18 12:32:26 PM PDT 23 2142012393 ps
T63 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2929833582553176207192957113086572154404553812085730654686849610655905270807 Oct 18 12:32:21 PM PDT 23 Oct 18 12:32:27 PM PDT 23 2186637036 ps
T706 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.31016559452757925310588915608096255442171782467226198061867363109359364302382 Oct 18 12:32:17 PM PDT 23 Oct 18 12:32:22 PM PDT 23 2023227629 ps
T707 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.58061878675244633352627200074960943649268862885943396978935312266866031225408 Oct 18 12:27:54 PM PDT 23 Oct 18 12:28:00 PM PDT 23 2186637036 ps
T708 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.64290487176746960939110831485977139549376506488836458248354377448488085154370 Oct 18 12:33:21 PM PDT 23 Oct 18 12:34:29 PM PDT 23 42510939439 ps
T709 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.16128418496414443867154390570137262285502166047505976591825031093541270241998 Oct 18 12:32:20 PM PDT 23 Oct 18 12:32:45 PM PDT 23 9477310853 ps
T710 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.65185875953956988736123046265788916037182233958000694955160535974348897672018 Oct 18 12:33:21 PM PDT 23 Oct 18 12:33:50 PM PDT 23 9477310853 ps
T711 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.28701233062577832088656468717888379796220763580897801731644833255551421603909 Oct 18 12:31:35 PM PDT 23 Oct 18 12:31:41 PM PDT 23 2142012393 ps
T712 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.104414987534693418526946615822566705538190206183441781590753574874692032368587 Oct 18 12:32:22 PM PDT 23 Oct 18 12:32:28 PM PDT 23 2186637036 ps
T713 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.76106492232763105621744064208468952688312308921436448600405067064326970324056 Oct 18 12:32:13 PM PDT 23 Oct 18 12:33:22 PM PDT 23 42510939439 ps
T714 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.108307703639840265726178546892231296792972009319992237629859585290302399756451 Oct 18 12:31:47 PM PDT 23 Oct 18 12:31:53 PM PDT 23 2186637036 ps
T83 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.61370986918004322862871235246079400878245240856418759270795227046407163968504 Oct 18 12:27:04 PM PDT 23 Oct 18 12:27:14 PM PDT 23 2890827831 ps
T715 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.14639313166984276469145253491452616421165074701552523229061571011451923211354 Oct 18 12:31:33 PM PDT 23 Oct 18 12:32:42 PM PDT 23 42510939439 ps
T716 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.25577332109573837211719006940127592160260473530717192942634260581524688038831 Oct 18 12:31:43 PM PDT 23 Oct 18 12:31:48 PM PDT 23 2074977215 ps
T717 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.92057093386026115448977532794282544889766946364769396689722120265496399334162 Oct 18 12:25:44 PM PDT 23 Oct 18 12:25:49 PM PDT 23 2023227629 ps
T718 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.88724870658387574216234868276927491355207472411772125689422904467398326498518 Oct 18 12:23:55 PM PDT 23 Oct 18 12:24:01 PM PDT 23 2186637036 ps
T719 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.47534563963473612773274698386413801306163998152765335483152471207293058845714 Oct 18 12:32:41 PM PDT 23 Oct 18 12:32:45 PM PDT 23 2023227629 ps
T720 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.66231360735656782756590764883825528643371733675729228774127940961386298683030 Oct 18 12:33:04 PM PDT 23 Oct 18 12:33:09 PM PDT 23 2023227629 ps
T721 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.42906689842229397792961517984096629216919300865538666564099603799378336396913 Oct 18 12:32:16 PM PDT 23 Oct 18 12:32:20 PM PDT 23 2023227629 ps
T84 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.54253887969342551015481801986249546831089306527504794185064503228814385032080 Oct 18 12:27:48 PM PDT 23 Oct 18 12:27:56 PM PDT 23 2890827831 ps
T722 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.41263607681656581841526209119655890098104702352860825042499814636303566985231 Oct 18 12:32:10 PM PDT 23 Oct 18 12:32:14 PM PDT 23 2023227629 ps
T723 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.15847527277999936286132336278950217121576098317177293841581516463857882024741 Oct 18 12:31:47 PM PDT 23 Oct 18 12:31:51 PM PDT 23 2023227629 ps
T724 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.73276893042038493331490182523468546759611532702750511179430292800446270100698 Oct 18 12:32:12 PM PDT 23 Oct 18 12:32:21 PM PDT 23 2023227629 ps
T85 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.26228214620843208288717308255882094635053037159821468433683137165495834675383 Oct 18 12:32:06 PM PDT 23 Oct 18 12:32:15 PM PDT 23 2890827831 ps
T725 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.69185508396913563148011213650093581387835338614542912773722831322503076993010 Oct 18 12:32:17 PM PDT 23 Oct 18 12:32:22 PM PDT 23 2023227629 ps
T86 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.37553731767000346075918923350855566277857519664212637605027384720488999058761 Oct 18 12:25:58 PM PDT 23 Oct 18 12:27:49 PM PDT 23 41047879715 ps
T726 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.63032157906262802629238847794121627574617239079145028296503981393644285116869 Oct 18 12:31:52 PM PDT 23 Oct 18 12:31:57 PM PDT 23 2186637036 ps
T727 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.58796114567234628207375140856733519788532740100062771996719243900605504059247 Oct 18 12:32:18 PM PDT 23 Oct 18 12:32:23 PM PDT 23 2142012393 ps
T728 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.110554752655404463465462824337647174963640920895487071484549348328856439302399 Oct 18 12:31:48 PM PDT 23 Oct 18 12:31:53 PM PDT 23 2074977215 ps
T729 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.34392682442053669445727913011339333428422945243974362217280515746412793460118 Oct 18 12:27:29 PM PDT 23 Oct 18 12:27:55 PM PDT 23 9477310853 ps
T730 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.26021842349734380916237587450066996043195211492722608570746762375770455627452 Oct 18 12:32:02 PM PDT 23 Oct 18 12:32:27 PM PDT 23 9477310853 ps
T731 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.76569440878938055224578207322104558217966362720663885146860284516811365834985 Oct 18 12:32:03 PM PDT 23 Oct 18 12:32:28 PM PDT 23 9477310853 ps
T732 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.61506463282547097356017564308913556919533371242693644745392791171288306381764 Oct 18 12:31:49 PM PDT 23 Oct 18 12:31:54 PM PDT 23 2142012393 ps
T733 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.42456228768209632815229215649513951406960133441748594510308292426274307519613 Oct 18 12:31:50 PM PDT 23 Oct 18 12:32:15 PM PDT 23 9477310853 ps
T734 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.92000744253554081827310672152435043985503788848094303347048814838473565640425 Oct 18 12:32:15 PM PDT 23 Oct 18 12:32:21 PM PDT 23 2186637036 ps
T87 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.63393781590856904139456375155825273638689695044070806908325868579651747199944 Oct 18 12:23:02 PM PDT 23 Oct 18 12:23:12 PM PDT 23 2890827831 ps
T91 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.23354007686905359065638273516800825667887521001726282172454182370813172491580 Oct 18 12:28:21 PM PDT 23 Oct 18 12:28:31 PM PDT 23 6030981281 ps
T735 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1475001037287485778690234815330105618281180912144592661641901198125142664843 Oct 18 12:31:59 PM PDT 23 Oct 18 12:32:03 PM PDT 23 2023227629 ps
T736 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.64820515587833156390662483456529010649235154250320392604208328328835191077188 Oct 18 12:31:41 PM PDT 23 Oct 18 12:31:45 PM PDT 23 2074977215 ps
T737 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.86813398586732208654676590866870059869115664496906872306917303462228247460721 Oct 18 12:31:43 PM PDT 23 Oct 18 12:31:47 PM PDT 23 2142012393 ps
T738 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.46943592069414846818188855789433924883017852636910758038496334555653515671895 Oct 18 12:31:59 PM PDT 23 Oct 18 12:32:24 PM PDT 23 9477310853 ps
T739 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.76727277468349424799405012691809982436423617346807548694224967939602168462557 Oct 18 12:32:12 PM PDT 23 Oct 18 12:32:16 PM PDT 23 2023227629 ps
T740 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.22856270843654994077861023911509232954357445855856885686954091221681119959764 Oct 18 12:32:21 PM PDT 23 Oct 18 12:32:31 PM PDT 23 6030981281 ps
T88 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.82025123600406219521985472165024100408694988872215492143470042284865260026730 Oct 18 12:22:08 PM PDT 23 Oct 18 12:22:17 PM PDT 23 2890827831 ps
T741 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.55461760917184928447060410018487256226750243158507475160285972676763115502105 Oct 18 12:32:12 PM PDT 23 Oct 18 12:33:21 PM PDT 23 42510939439 ps
T742 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.6446962913854077121248749933919501489652265826319577948907622313083328435230 Oct 18 12:31:38 PM PDT 23 Oct 18 12:31:42 PM PDT 23 2142012393 ps
T743 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.56598248050016126722784980709512993687164073072994397777457980192109056952001 Oct 18 12:32:12 PM PDT 23 Oct 18 12:32:16 PM PDT 23 2023227629 ps
T744 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.112715788870524793518389082482762131709245021864785006774788637073743184337619 Oct 18 12:32:16 PM PDT 23 Oct 18 12:32:20 PM PDT 23 2023227629 ps
T745 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.66912537091375403398550311484587858386584520638042968288048089356500703802744 Oct 18 12:32:04 PM PDT 23 Oct 18 12:32:10 PM PDT 23 2186637036 ps
T746 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.14084343780772227284250915756689376928243827937987378247045758985052298886742 Oct 18 12:31:59 PM PDT 23 Oct 18 12:32:03 PM PDT 23 2074977215 ps
T747 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.64369369340686112970788858644361717727968981136767783406337334306629185422081 Oct 18 12:32:15 PM PDT 23 Oct 18 12:32:20 PM PDT 23 2074977215 ps
T748 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.110357458730096941395798234319979492535403137762545506380549568925322124155544 Oct 18 12:31:23 PM PDT 23 Oct 18 12:32:33 PM PDT 23 42510939439 ps
T749 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.48263964181189315620507596287171719665771489062024931689336049534188737453592 Oct 18 12:31:25 PM PDT 23 Oct 18 12:31:41 PM PDT 23 2023227629 ps
T750 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.22363099418660864063452520393449074257299548484465430015820791698616022469211 Oct 18 12:31:25 PM PDT 23 Oct 18 12:31:30 PM PDT 23 2074977215 ps
T751 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.111645889157175921568238294083175535898656062006982769159822741911474527475752 Oct 18 12:31:51 PM PDT 23 Oct 18 12:32:15 PM PDT 23 9477310853 ps
T752 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.25901403771669428229467755569820389807701156585192008788013875623069960079638 Oct 18 12:31:35 PM PDT 23 Oct 18 12:32:49 PM PDT 23 42510939439 ps
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