Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T89 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.29767495331651330321057640545400687788690410503909897673321720465898225012837 Oct 18 12:25:36 PM PDT 23 Oct 18 12:27:26 PM PDT 23 41047879715 ps
T753 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.113449626123506944766163458053864917494845898366075942146970437640021361910939 Oct 18 12:25:26 PM PDT 23 Oct 18 12:25:31 PM PDT 23 2023227629 ps
T754 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.72792393427684964234120693113334587675023407919552864896862815120531988856475 Oct 18 12:31:50 PM PDT 23 Oct 18 12:31:55 PM PDT 23 2142012393 ps
T755 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.84999010039604727310392295800500399354015829222315212234565177509680223348431 Oct 18 12:31:24 PM PDT 23 Oct 18 12:32:33 PM PDT 23 42510939439 ps
T756 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.71307313795427559282823241934405224311877170906266495607201626825536344898043 Oct 18 12:31:32 PM PDT 23 Oct 18 12:31:36 PM PDT 23 2023227629 ps
T757 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.110208587904364223706710717942879095898059692573492423815857103961402635136224 Oct 18 12:32:13 PM PDT 23 Oct 18 12:32:17 PM PDT 23 2023227629 ps
T758 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.73119419406730173109650102438597999723550603588069404834337725431437404897851 Oct 18 12:33:55 PM PDT 23 Oct 18 12:34:00 PM PDT 23 2023227629 ps
T759 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.62503133430559848875415351887594636789765482572285879649973175647007428754540 Oct 18 12:26:00 PM PDT 23 Oct 18 12:26:25 PM PDT 23 9477310853 ps
T760 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.31822565199008963309445518788063177759466653925700449808128619215080433067959 Oct 18 12:31:43 PM PDT 23 Oct 18 12:31:47 PM PDT 23 2142012393 ps
T761 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.96287900015142977843930217317406885155917438423445628953304990474652944573559 Oct 18 12:32:05 PM PDT 23 Oct 18 12:32:09 PM PDT 23 2023227629 ps
T762 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.92517199465156355430824713723745279187234977354569422658842735714066019647896 Oct 18 12:31:42 PM PDT 23 Oct 18 12:31:46 PM PDT 23 2142012393 ps
T763 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.85221276002439147294511255790410743760517196333142452973444615046386908940690 Oct 18 12:33:11 PM PDT 23 Oct 18 12:33:16 PM PDT 23 2023227629 ps
T764 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.39963464573559397932854813629389725696534651003146500166483477100471139793659 Oct 18 12:28:21 PM PDT 23 Oct 18 12:28:25 PM PDT 23 2023227629 ps
T765 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.55857335668135603775745977499937927780759471749550602264552820710363896767998 Oct 18 12:31:31 PM PDT 23 Oct 18 12:31:37 PM PDT 23 2074977215 ps
T766 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.64311902242126412660176101504489572423517801401571323960323347674979753048845 Oct 18 12:32:19 PM PDT 23 Oct 18 12:32:25 PM PDT 23 2186637036 ps
T767 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.65155080607325750859372420718871226765393303456050579350199526768551878808457 Oct 18 12:31:32 PM PDT 23 Oct 18 12:31:36 PM PDT 23 2142012393 ps
T768 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.59828481810832275991219533877776847448612487250492198469467599612821502729377 Oct 18 12:31:25 PM PDT 23 Oct 18 12:31:50 PM PDT 23 9477310853 ps
T769 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.31013778901983575115101169662231378392939711493836486861524515511160518023781 Oct 18 12:31:50 PM PDT 23 Oct 18 12:31:54 PM PDT 23 2074977215 ps
T770 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.13964082385085261044664300014767607403423811457064145207832363258261866564888 Oct 18 12:32:12 PM PDT 23 Oct 18 12:32:16 PM PDT 23 2023227629 ps
T771 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.24137820094554707383704358844033851084529763485954225489502202218975193550862 Oct 18 12:31:50 PM PDT 23 Oct 18 12:31:54 PM PDT 23 2074977215 ps
T772 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.74772240371917622542732404234077049375418498833754519911495895649605457865957 Oct 18 12:27:40 PM PDT 23 Oct 18 12:28:49 PM PDT 23 42510939439 ps
T773 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.91195592723650942844916836065231835391169702235856383894133640600092718348848 Oct 18 12:23:36 PM PDT 23 Oct 18 12:23:40 PM PDT 23 2074977215 ps
T774 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.11651500643209155707187119880898290666762502802630503089466737800771128286396 Oct 18 12:31:30 PM PDT 23 Oct 18 12:31:54 PM PDT 23 9477310853 ps
T775 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.70843300202052242420883707988870079655057740983793739148249713861589951653219 Oct 18 12:31:23 PM PDT 23 Oct 18 12:32:32 PM PDT 23 42510939439 ps
T776 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.50275308693008171096711241559071478549340263772740943052881147382602083949514 Oct 18 12:31:32 PM PDT 23 Oct 18 12:31:38 PM PDT 23 2186637036 ps
T777 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.10374218678586084797671791343459912713334981665445958847602309488987569327526 Oct 18 12:31:54 PM PDT 23 Oct 18 12:32:19 PM PDT 23 9477310853 ps
T778 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.82288725614764206959539944128220911977422783152925288454217623171869045726146 Oct 18 12:32:15 PM PDT 23 Oct 18 12:32:21 PM PDT 23 2186637036 ps
T779 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.90490666410190223758187847111159272181281536035224953569663392128270703220906 Oct 18 12:27:53 PM PDT 23 Oct 18 12:28:04 PM PDT 23 6030981281 ps
T780 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.45988321769838669990019171119664133832724811598706062705941946089420080541563 Oct 18 12:22:41 PM PDT 23 Oct 18 12:22:45 PM PDT 23 2023227629 ps
T781 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.77166358225914960745635378764729569539974308237691164015934796471222936524811 Oct 18 12:33:57 PM PDT 23 Oct 18 12:34:01 PM PDT 23 2023227629 ps
T782 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.112376383130508927432080215427877624336833585261276381440273863154370613312606 Oct 18 12:32:11 PM PDT 23 Oct 18 12:32:15 PM PDT 23 2074977215 ps
T90 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.6174789410893466368958071282399807423636674330809516096213349670415013619710 Oct 18 12:27:31 PM PDT 23 Oct 18 12:29:24 PM PDT 23 41047879715 ps

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.77748239814057403780318091167593967193888065883674670423345677978666590777900
Short name T24
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.96 seconds
Started Oct 18 12:47:02 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201480 kb
Host smart-06fb535e-597e-4ae7-b299-955848f0ec71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77748239814057403780318091167593967193888065883674670423345677978666590777900 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.77748239814057403780318091167593967193888065883674670423345677978666590777900
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.15060460022168258230531845289558489271261653021919702892397293497600237746321
Short name T97
Test name
Test status
Simulation time 38606274248 ps
CPU time 59.73 seconds
Started Oct 18 12:46:54 PM PDT 23
Finished Oct 18 12:47:55 PM PDT 23
Peak memory 201248 kb
Host smart-02a368fb-5b5c-4644-bcd0-d17dde5df912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15060460022168258230531845289558489271261653021919702892397293497600237746321 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.15060460022168258230531845289558489271261653021919702892397293497600237746321
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.21850262834864172820977860005222879325255911084321951130294808898448762980084
Short name T21
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 18 12:46:59 PM PDT 23
Finished Oct 18 12:47:04 PM PDT 23
Peak memory 201216 kb
Host smart-1fe5fd16-246f-41dd-bae4-5c6915629c50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21850262834864172820977860005222879325255911084321951130294808898448762980084 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.2185026283486417282097786000522287932525591108432195113029480
8898448762980084
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.77092126550248190165670848375320844797576297944584807025069481728192058072585
Short name T31
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 18 12:48:02 PM PDT 23
Finished Oct 18 12:48:09 PM PDT 23
Peak memory 201120 kb
Host smart-4a7e1cd4-c47c-422c-9999-fa68331ca959
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77092126550248190165670848375320844797576297944584807025069481728192058072585 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.7709212655024819016567084837532084479757629794458480702506948172
8192058072585
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.69140321308847187007173398429449637673770544909392891217327064791773652266886
Short name T1
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.04 seconds
Started Oct 18 12:32:59 PM PDT 23
Finished Oct 18 12:34:08 PM PDT 23
Peak memory 201108 kb
Host smart-d0a43ee3-39a4-42f7-be01-5ba7f87a2390
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69140321308847187007173398429449637673770544909392891217327064791773652266886 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.69140321308847187007173398429449637673770544909392891217327064
791773652266886
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.40954559832824632915736154566213102131423524101451399995004551437434317158706
Short name T98
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.51 seconds
Started Oct 18 12:48:10 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201312 kb
Host smart-5f94b825-0fbe-4551-a001-6b6f6a6d7abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40954559832824632915736154566213102131423524101451399995004551437434317158706 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.40954559832824632915736154566213102131423524101451399995004551437434317158706
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.66809195346292200393488399150135837655963417371930691542305556293599332857340
Short name T33
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.44 seconds
Started Oct 18 12:48:09 PM PDT 23
Finished Oct 18 12:51:10 PM PDT 23
Peak memory 201304 kb
Host smart-aaaed15e-74c1-42df-bd2e-8d08bf675e7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66809195346292200393488399150135837655963417371930691542305556293599332857340 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.66809195346292200393488399150135837655963417371930691542305556
293599332857340
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.114344372690546360288776779343256753958865126416792462381591281577517012532507
Short name T4
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.53 seconds
Started Oct 18 12:32:25 PM PDT 23
Finished Oct 18 12:32:31 PM PDT 23
Peak memory 201104 kb
Host smart-b42bf453-c548-4cac-b288-47b631fd3f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114344372690546360288776779343256753958865126416792462381591281577517012532507 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.114344372690546360288776779343256753958865126416792462381591281577517012532507
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.23674612610227024854946474896571132940098879282819463984832942998573720758296
Short name T135
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.92 seconds
Started Oct 18 12:47:08 PM PDT 23
Finished Oct 18 12:48:13 PM PDT 23
Peak memory 221544 kb
Host smart-a8f8657a-85b8-4740-84af-4be51443c553
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23674612610227024854946474896571132940098879282819463984832942998573720758296 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.23674612610227024854946474896571132940098879282819463984832942998573720758296
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.73642666929427240588382056890310722443437581706579274974130574684422973107222
Short name T69
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.29 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:41 PM PDT 23
Peak memory 200932 kb
Host smart-ed5b2f5a-ec97-4b91-9639-1634a6784e92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73642666929427240588382056890310722443437581706579274974130574684422973107222
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.736426669294272405883820568903107224434375817
06579274974130574684422973107222
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.45555922265408153732437490061734483076415969664363547803294506854786009581075
Short name T196
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 18 12:46:58 PM PDT 23
Finished Oct 18 12:47:02 PM PDT 23
Peak memory 201180 kb
Host smart-3ef646aa-1804-4922-bc8f-62a55749e680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45555922265408153732437490061734483076415969664363547803294506854786009581075 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.45555922265408153732437490061734483076415969664363547803294506854786009581075
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.65305258033242057575899335686513866249253931817579227002887811654631544452916
Short name T14
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Oct 18 12:31:31 PM PDT 23
Finished Oct 18 12:31:35 PM PDT 23
Peak memory 200884 kb
Host smart-d8c89a6c-7282-4893-b2d6-88802ac4dd67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65305258033242057575899335686513866249253931817579227002887811654631544452916 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.65305258033242057575899335686513866249253931817579227002887811654631544452916
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.79361371742636043549708368740977829322271948598933333802564671777704012671841
Short name T76
Test name
Test status
Simulation time 41047879715 ps
CPU time 109.72 seconds
Started Oct 18 12:27:25 PM PDT 23
Finished Oct 18 12:29:15 PM PDT 23
Peak memory 201116 kb
Host smart-065ec92b-adfd-4707-9a28-f416256bda1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79361371742636043549708368740977829322271948598933333802564671777704012671841 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.79361371742636043549708368740977829322271948598933333802564671777704012671841
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.1742012216559656630669033146610062597847950973486730876686762656977237808947
Short name T194
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.73 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201268 kb
Host smart-3ca9f68c-e955-4a96-8956-f0eac25c6093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742012216559656630669033146610062597847950973486730876686762656977237808947 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.1742012216559656630669033146610062597847950973486730876686762656977237808947
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.11295322180042547275253460104846625223521663895995475274012755373159121563271
Short name T353
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.32 seconds
Started Oct 18 12:46:58 PM PDT 23
Finished Oct 18 12:47:03 PM PDT 23
Peak memory 201220 kb
Host smart-ad3b7006-5fb8-493f-b0e0-a48ae8655048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11295322180042547275253460104846625223521663895995475274012755373159121563271 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.11295322180042547275253460104846625223521663895995475274012755373159121563271
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.27777982613828171660054391317754205210620327316423454946220759457935373631200
Short name T168
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.4 seconds
Started Oct 18 12:48:34 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201180 kb
Host smart-1cd15cfe-a35f-49a1-a52c-a669b9ad80ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27777982613828171660054391317754205210620327316423454946220759457935373631200 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.277779826138281716600543913177542052106203273164234549462207
59457935373631200
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.61370986918004322862871235246079400878245240856418759270795227046407163968504
Short name T83
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.51 seconds
Started Oct 18 12:27:04 PM PDT 23
Finished Oct 18 12:27:14 PM PDT 23
Peak memory 200336 kb
Host smart-6f5c59ae-740a-4172-bd30-22b99174761f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61370986918004322862871235246079400878245240856418759270795227046407163968504 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.61370986918004322862871235246079400878245240856418759270795227046407163968504
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.42816337618027283688008096544132184998686022393530933733042887987310517158534
Short name T77
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.96 seconds
Started Oct 18 12:27:04 PM PDT 23
Finished Oct 18 12:27:15 PM PDT 23
Peak memory 201068 kb
Host smart-a6fa87a8-403f-4c52-af73-9fe620788da5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42816337618027283688008096544132184998686022393530933733042887987310517158534 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.42816337618027283688008096544132184998686022393530933733042887987310517158534
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.48917615980813136957635759498076387115859560629197969407033961054662566226476
Short name T6
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Oct 18 12:26:34 PM PDT 23
Finished Oct 18 12:26:39 PM PDT 23
Peak memory 200952 kb
Host smart-1c3e91ba-812f-4896-94a0-1f874147136f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4891761598081313695763575949807638711585956
0629197969407033961054662566226476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4891
7615980813136957635759498076387115859560629197969407033961054662566226476
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.17855065147658045996409609044034268127675464290363117742806329730297023131366
Short name T693
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Oct 18 12:25:32 PM PDT 23
Finished Oct 18 12:25:36 PM PDT 23
Peak memory 200888 kb
Host smart-86c471d5-9bb8-4c9f-b88d-aa6dfb4bb115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17855065147658045996409609044034268127675464290363117742806329730297023131366 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.17855065147658045996409609044034268127675464290363117742806329730297023131366
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.45988321769838669990019171119664133832724811598706062705941946089420080541563
Short name T780
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 18 12:22:41 PM PDT 23
Finished Oct 18 12:22:45 PM PDT 23
Peak memory 201096 kb
Host smart-a4d6da8e-959c-474f-89ee-f13b7df80a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45988321769838669990019171119664133832724811598706062705941946089420080541563 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.45988321769838669990019171119664133832724811598706062705941946089420080541563
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.62503133430559848875415351887594636789765482572285879649973175647007428754540
Short name T759
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.47 seconds
Started Oct 18 12:26:00 PM PDT 23
Finished Oct 18 12:26:25 PM PDT 23
Peak memory 200848 kb
Host smart-7e002bf5-916b-4a0f-b9bd-a11d5f23d22a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62503133430559848875415351887594636789765482572285879649973175647007428754540
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.625031334305598488754153518875946367897654825
72285879649973175647007428754540
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.88724870658387574216234868276927491355207472411772125689422904467398326498518
Short name T718
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.61 seconds
Started Oct 18 12:23:55 PM PDT 23
Finished Oct 18 12:24:01 PM PDT 23
Peak memory 201044 kb
Host smart-01b0871a-b089-433f-828c-f02cc3f8c090
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88724870658387574216234868276927491355207472411772125689422904467398326498518 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.88724870658387574216234868276927491355207472411772125689422904467398326498518
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.79135609922274468522322146009515656259406185446759351610530890226586703318761
Short name T54
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.14 seconds
Started Oct 18 12:26:05 PM PDT 23
Finished Oct 18 12:27:15 PM PDT 23
Peak memory 201052 kb
Host smart-d0c84aa0-1360-4fd7-bc01-aa6753d84238
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79135609922274468522322146009515656259406185446759351610530890226586703318761 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.791356099222744685223221460095156562594061854467593516105308902
26586703318761
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.82025123600406219521985472165024100408694988872215492143470042284865260026730
Short name T88
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.74 seconds
Started Oct 18 12:22:08 PM PDT 23
Finished Oct 18 12:22:17 PM PDT 23
Peak memory 201336 kb
Host smart-bd1000d7-765d-4e45-8a87-ea24bb7baffd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82025123600406219521985472165024100408694988872215492143470042284865260026730 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.82025123600406219521985472165024100408694988872215492143470042284865260026730
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.29767495331651330321057640545400687788690410503909897673321720465898225012837
Short name T89
Test name
Test status
Simulation time 41047879715 ps
CPU time 109.61 seconds
Started Oct 18 12:25:36 PM PDT 23
Finished Oct 18 12:27:26 PM PDT 23
Peak memory 200964 kb
Host smart-156705f6-277a-48cc-b0f8-08fb36d81453
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767495331651330321057640545400687788690410503909897673321720465898225012837 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.29767495331651330321057640545400687788690410503909897673321720465898225012837
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.23354007686905359065638273516800825667887521001726282172454182370813172491580
Short name T91
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.03 seconds
Started Oct 18 12:28:21 PM PDT 23
Finished Oct 18 12:28:31 PM PDT 23
Peak memory 200964 kb
Host smart-0332a46e-660c-4401-b7cd-b91c56525612
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23354007686905359065638273516800825667887521001726282172454182370813172491580 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.23354007686905359065638273516800825667887521001726282172454182370813172491580
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2313208573332776477940572362837633707801057468164818915136204915228257629777
Short name T2
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Oct 18 12:26:10 PM PDT 23
Finished Oct 18 12:26:15 PM PDT 23
Peak memory 200884 kb
Host smart-bdbfd881-23f2-4542-847e-f20b0084460b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313208573332776477940572362837633707801057
468164818915136204915228257629777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.23132
08573332776477940572362837633707801057468164818915136204915228257629777
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.91195592723650942844916836065231835391169702235856383894133640600092718348848
Short name T773
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Oct 18 12:23:36 PM PDT 23
Finished Oct 18 12:23:40 PM PDT 23
Peak memory 200908 kb
Host smart-868b70cc-10a9-4948-b8a0-969122ceae08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91195592723650942844916836065231835391169702235856383894133640600092718348848 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.91195592723650942844916836065231835391169702235856383894133640600092718348848
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.92057093386026115448977532794282544889766946364769396689722120265496399334162
Short name T717
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.84 seconds
Started Oct 18 12:25:44 PM PDT 23
Finished Oct 18 12:25:49 PM PDT 23
Peak memory 200868 kb
Host smart-3e7c53f3-37a4-44b3-8886-cc7203b4812f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92057093386026115448977532794282544889766946364769396689722120265496399334162 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.92057093386026115448977532794282544889766946364769396689722120265496399334162
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.10868861016823677583035094213730496893984090014293411054665262831845532542245
Short name T62
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.72 seconds
Started Oct 18 12:23:36 PM PDT 23
Finished Oct 18 12:23:42 PM PDT 23
Peak memory 201144 kb
Host smart-a566643a-3595-413d-9a08-081ef4f052be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10868861016823677583035094213730496893984090014293411054665262831845532542245 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.10868861016823677583035094213730496893984090014293411054665262831845532542245
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.90642344046102748731398121598210486785748394586533309061747065320148306687978
Short name T7
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.05 seconds
Started Oct 18 12:26:05 PM PDT 23
Finished Oct 18 12:27:15 PM PDT 23
Peak memory 201060 kb
Host smart-cd122452-c1e6-432c-a545-b1d95dfbec4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90642344046102748731398121598210486785748394586533309061747065320148306687978 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.906423440461027487313981215982104867857483945865333090617470653
20148306687978
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.61506463282547097356017564308913556919533371242693644745392791171288306381764
Short name T732
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.15 seconds
Started Oct 18 12:31:49 PM PDT 23
Finished Oct 18 12:31:54 PM PDT 23
Peak memory 200948 kb
Host smart-b20ba7ca-3e70-47b0-a77e-fed155341dfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6150646328254709735601756430891355691953337
1242693644745392791171288306381764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.615
06463282547097356017564308913556919533371242693644745392791171288306381764
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.64820515587833156390662483456529010649235154250320392604208328328835191077188
Short name T736
Test name
Test status
Simulation time 2074977215 ps
CPU time 4 seconds
Started Oct 18 12:31:41 PM PDT 23
Finished Oct 18 12:31:45 PM PDT 23
Peak memory 200908 kb
Host smart-411e4b35-cd9c-40fb-906f-93e48830680d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64820515587833156390662483456529010649235154250320392604208328328835191077188 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.64820515587833156390662483456529010649235154250320392604208328328835191077188
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1475001037287485778690234815330105618281180912144592661641901198125142664843
Short name T735
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:31:59 PM PDT 23
Finished Oct 18 12:32:03 PM PDT 23
Peak memory 201072 kb
Host smart-2ff1d3cc-01d2-4570-91d4-78911992ff30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475001037287485778690234815330105618281180912144592661641901198125142664843 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.1475001037287485778690234815330105618281180912144592661641901198125142664843
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.10374218678586084797671791343459912713334981665445958847602309488987569327526
Short name T777
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.1 seconds
Started Oct 18 12:31:54 PM PDT 23
Finished Oct 18 12:32:19 PM PDT 23
Peak memory 201076 kb
Host smart-b56fc4f4-796f-4614-88d0-690d21ab9ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10374218678586084797671791343459912713334981665445958847602309488987569327526
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.10374218678586084797671791343459912713334981
665445958847602309488987569327526
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.89396727902580972532280342761948199044139302374638352879731763672928859764042
Short name T61
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.76 seconds
Started Oct 18 12:31:53 PM PDT 23
Finished Oct 18 12:31:59 PM PDT 23
Peak memory 201148 kb
Host smart-6efadc2b-1276-4409-b823-f3df81894d6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89396727902580972532280342761948199044139302374638352879731763672928859764042 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.89396727902580972532280342761948199044139302374638352879731763672928859764042
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.81669653620480593485466348863919631591740301025939497764756102611903926482183
Short name T52
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.71 seconds
Started Oct 18 12:31:35 PM PDT 23
Finished Oct 18 12:32:46 PM PDT 23
Peak memory 201192 kb
Host smart-98486b53-fbc3-411d-ae50-12647baffbe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81669653620480593485466348863919631591740301025939497764756102611903926482183 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.81669653620480593485466348863919631591740301025939497764756102
611903926482183
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.28701233062577832088656468717888379796220763580897801731644833255551421603909
Short name T711
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.31 seconds
Started Oct 18 12:31:35 PM PDT 23
Finished Oct 18 12:31:41 PM PDT 23
Peak memory 201044 kb
Host smart-577743d0-a157-4f33-bd15-726409e0fd29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870123306257783208865646871788837979622076
3580897801731644833255551421603909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.287
01233062577832088656468717888379796220763580897801731644833255551421603909
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.66294272915925293240314929004560927945319896863284410597965653956816048155513
Short name T75
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.01 seconds
Started Oct 18 12:32:00 PM PDT 23
Finished Oct 18 12:32:05 PM PDT 23
Peak memory 200916 kb
Host smart-4cf928d1-9f2a-4190-8512-085588e8798e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66294272915925293240314929004560927945319896863284410597965653956816048155513 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.66294272915925293240314929004560927945319896863284410597965653956816048155513
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.41263607681656581841526209119655890098104702352860825042499814636303566985231
Short name T722
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 18 12:32:10 PM PDT 23
Finished Oct 18 12:32:14 PM PDT 23
Peak memory 200844 kb
Host smart-e1452593-c342-4c15-8685-d86476d56909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41263607681656581841526209119655890098104702352860825042499814636303566985231 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.41263607681656581841526209119655890098104702352860825042499814636303566985231
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.23095077172237752901513943581222062926701441221148219240700993491003819265811
Short name T94
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.64 seconds
Started Oct 18 12:32:35 PM PDT 23
Finished Oct 18 12:33:01 PM PDT 23
Peak memory 201112 kb
Host smart-4a0082e4-8298-477d-9a4b-d40394fe1275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23095077172237752901513943581222062926701441221148219240700993491003819265811
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.23095077172237752901513943581222062926701441
221148219240700993491003819265811
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.37966649387463439381632812676889026607838616799052837534327450308087954667675
Short name T691
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.03 seconds
Started Oct 18 12:32:24 PM PDT 23
Finished Oct 18 12:33:33 PM PDT 23
Peak memory 201176 kb
Host smart-702f28ca-02a2-46de-a9b1-892f829e1aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37966649387463439381632812676889026607838616799052837534327450308087954667675 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.37966649387463439381632812676889026607838616799052837534327450
308087954667675
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.72792393427684964234120693113334587675023407919552864896862815120531988856475
Short name T754
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Oct 18 12:31:50 PM PDT 23
Finished Oct 18 12:31:55 PM PDT 23
Peak memory 200976 kb
Host smart-8aa823d3-5977-4c55-a143-f0c09bee79c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7279239342768496423412069311333458767502340
7919552864896862815120531988856475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.727
92393427684964234120693113334587675023407919552864896862815120531988856475
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.64369369340686112970788858644361717727968981136767783406337334306629185422081
Short name T747
Test name
Test status
Simulation time 2074977215 ps
CPU time 4 seconds
Started Oct 18 12:32:15 PM PDT 23
Finished Oct 18 12:32:20 PM PDT 23
Peak memory 200912 kb
Host smart-ce728e26-b5e6-465c-ad49-0fb1d6a7e9cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64369369340686112970788858644361717727968981136767783406337334306629185422081 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.64369369340686112970788858644361717727968981136767783406337334306629185422081
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.13964082385085261044664300014767607403423811457064145207832363258261866564888
Short name T770
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 18 12:32:12 PM PDT 23
Finished Oct 18 12:32:16 PM PDT 23
Peak memory 200916 kb
Host smart-d8bfc66a-e0ba-43f4-83b5-9b021dfcf1a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964082385085261044664300014767607403423811457064145207832363258261866564888 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.13964082385085261044664300014767607403423811457064145207832363258261866564888
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.26021842349734380916237587450066996043195211492722608570746762375770455627452
Short name T730
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.55 seconds
Started Oct 18 12:32:02 PM PDT 23
Finished Oct 18 12:32:27 PM PDT 23
Peak memory 201144 kb
Host smart-4a5b5a45-43d9-4ead-b548-16034897e1b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26021842349734380916237587450066996043195211492722608570746762375770455627452
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.26021842349734380916237587450066996043195211
492722608570746762375770455627452
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.82288725614764206959539944128220911977422783152925288454217623171869045726146
Short name T778
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.54 seconds
Started Oct 18 12:32:15 PM PDT 23
Finished Oct 18 12:32:21 PM PDT 23
Peak memory 201232 kb
Host smart-320e0991-0e48-4f7d-a774-1c43f6fa0067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82288725614764206959539944128220911977422783152925288454217623171869045726146 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.82288725614764206959539944128220911977422783152925288454217623171869045726146
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.84999010039604727310392295800500399354015829222315212234565177509680223348431
Short name T755
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.89 seconds
Started Oct 18 12:31:24 PM PDT 23
Finished Oct 18 12:32:33 PM PDT 23
Peak memory 201252 kb
Host smart-28dcf974-5867-409d-9d78-9a0b37403db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84999010039604727310392295800500399354015829222315212234565177509680223348431 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.84999010039604727310392295800500399354015829222315212234565177
509680223348431
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.35896214356398141087221206188991065501492462850234922399971605068777217783675
Short name T678
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.13 seconds
Started Oct 18 12:31:49 PM PDT 23
Finished Oct 18 12:31:54 PM PDT 23
Peak memory 200976 kb
Host smart-a175af7b-6e0e-4f3c-9ace-838c8596f45c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589621435639814108722120618899106550149246
2850234922399971605068777217783675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.358
96214356398141087221206188991065501492462850234922399971605068777217783675
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.49436838319131692668773971375288368406751007715721354105881832994857281282938
Short name T15
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.04 seconds
Started Oct 18 12:32:07 PM PDT 23
Finished Oct 18 12:32:12 PM PDT 23
Peak memory 200920 kb
Host smart-9c507cbd-cb1b-4877-96d2-f01aa868cc61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49436838319131692668773971375288368406751007715721354105881832994857281282938 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.49436838319131692668773971375288368406751007715721354105881832994857281282938
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.42906689842229397792961517984096629216919300865538666564099603799378336396913
Short name T721
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:32:16 PM PDT 23
Finished Oct 18 12:32:20 PM PDT 23
Peak memory 200880 kb
Host smart-bd39f71c-7ea7-485b-bdce-f3cf03eaf1b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906689842229397792961517984096629216919300865538666564099603799378336396913 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.42906689842229397792961517984096629216919300865538666564099603799378336396913
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.65185875953956988736123046265788916037182233958000694955160535974348897672018
Short name T710
Test name
Test status
Simulation time 9477310853 ps
CPU time 23.97 seconds
Started Oct 18 12:33:21 PM PDT 23
Finished Oct 18 12:33:50 PM PDT 23
Peak memory 200788 kb
Host smart-950088c0-b996-4219-b181-335594f65f6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65185875953956988736123046265788916037182233958000694955160535974348897672018
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.65185875953956988736123046265788916037182233
958000694955160535974348897672018
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.108307703639840265726178546892231296792972009319992237629859585290302399756451
Short name T714
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.67 seconds
Started Oct 18 12:31:47 PM PDT 23
Finished Oct 18 12:31:53 PM PDT 23
Peak memory 201212 kb
Host smart-e90e4bc8-36e0-4c77-acd2-10927814b483
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108307703639840265726178546892231296792972009319992237629859585290302399756451 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.108307703639840265726178546892231296792972009319992237629859585290302399756451
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.55461760917184928447060410018487256226750243158507475160285972676763115502105
Short name T741
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.62 seconds
Started Oct 18 12:32:12 PM PDT 23
Finished Oct 18 12:33:21 PM PDT 23
Peak memory 201184 kb
Host smart-d3e9bda1-a961-44d9-92d7-9379c9a503ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55461760917184928447060410018487256226750243158507475160285972676763115502105 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.55461760917184928447060410018487256226750243158507475160285972
676763115502105
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.7902504710827062477790779814576013305960726255904369694772733180454346627961
Short name T701
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.13 seconds
Started Oct 18 12:31:34 PM PDT 23
Finished Oct 18 12:31:38 PM PDT 23
Peak memory 201016 kb
Host smart-883c0ac7-f74a-4d5a-8a5c-1e719b947366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7902504710827062477790779814576013305960726
255904369694772733180454346627961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.7902
504710827062477790779814576013305960726255904369694772733180454346627961
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.48388459206412638925592077093312405891827898877124661753600916766453895508744
Short name T694
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Oct 18 12:31:42 PM PDT 23
Finished Oct 18 12:31:46 PM PDT 23
Peak memory 200952 kb
Host smart-0566f1cf-5e5f-42c5-bb71-9882dad87944
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48388459206412638925592077093312405891827898877124661753600916766453895508744 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.48388459206412638925592077093312405891827898877124661753600916766453895508744
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.96287900015142977843930217317406885155917438423445628953304990474652944573559
Short name T761
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 18 12:32:05 PM PDT 23
Finished Oct 18 12:32:09 PM PDT 23
Peak memory 200852 kb
Host smart-ae35abe5-3cf8-449b-b48a-b882302700db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96287900015142977843930217317406885155917438423445628953304990474652944573559 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.96287900015142977843930217317406885155917438423445628953304990474652944573559
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.111645889157175921568238294083175535898656062006982769159822741911474527475752
Short name T751
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.01 seconds
Started Oct 18 12:31:51 PM PDT 23
Finished Oct 18 12:32:15 PM PDT 23
Peak memory 201116 kb
Host smart-a7d53e5c-8dd9-44ea-ad35-82c1601f6879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111645889157175921568238294083175535898656062006982769159822741911474527475752
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.1116458891571759215682382940831755358986560
62006982769159822741911474527475752
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2929833582553176207192957113086572154404553812085730654686849610655905270807
Short name T63
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.6 seconds
Started Oct 18 12:32:21 PM PDT 23
Finished Oct 18 12:32:27 PM PDT 23
Peak memory 201236 kb
Host smart-6d4c9f63-a69a-4732-b8ed-63f142072478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929833582553176207192957113086572154404553812085730654686849610655905270807 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.2929833582553176207192957113086572154404553812085730654686849610655905270807
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.102954136006527525073206377054254584408781515165161124449847063842279319916669
Short name T3
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.17 seconds
Started Oct 18 12:33:25 PM PDT 23
Finished Oct 18 12:33:30 PM PDT 23
Peak memory 200840 kb
Host smart-e91d8afc-86e4-4816-abaf-8fedc791ac75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029541360065275250732063770542545844087815
15165161124449847063842279319916669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.10
2954136006527525073206377054254584408781515165161124449847063842279319916669
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.14084343780772227284250915756689376928243827937987378247045758985052298886742
Short name T746
Test name
Test status
Simulation time 2074977215 ps
CPU time 3.98 seconds
Started Oct 18 12:31:59 PM PDT 23
Finished Oct 18 12:32:03 PM PDT 23
Peak memory 200856 kb
Host smart-b3885c69-272a-47cf-9cab-f629d2770f8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14084343780772227284250915756689376928243827937987378247045758985052298886742 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.14084343780772227284250915756689376928243827937987378247045758985052298886742
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.67640214758334270451473309132138433274124415408772229769596817920595874186620
Short name T699
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:31:49 PM PDT 23
Finished Oct 18 12:31:58 PM PDT 23
Peak memory 200868 kb
Host smart-028d6e38-c56d-464b-8633-e9eaf88138c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67640214758334270451473309132138433274124415408772229769596817920595874186620 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.67640214758334270451473309132138433274124415408772229769596817920595874186620
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.42456228768209632815229215649513951406960133441748594510308292426274307519613
Short name T733
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.39 seconds
Started Oct 18 12:31:50 PM PDT 23
Finished Oct 18 12:32:15 PM PDT 23
Peak memory 201168 kb
Host smart-dd57687a-13c2-409f-9c08-89730769f4de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42456228768209632815229215649513951406960133441748594510308292426274307519613
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.42456228768209632815229215649513951406960133
441748594510308292426274307519613
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.66912537091375403398550311484587858386584520638042968288048089356500703802744
Short name T745
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.65 seconds
Started Oct 18 12:32:04 PM PDT 23
Finished Oct 18 12:32:10 PM PDT 23
Peak memory 201152 kb
Host smart-e776925b-77fe-42a6-b86d-bd7a6897d60c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66912537091375403398550311484587858386584520638042968288048089356500703802744 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.66912537091375403398550311484587858386584520638042968288048089356500703802744
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.94335327744959155249165534245383595899638733688428539950377667205076038827912
Short name T5
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.83 seconds
Started Oct 18 12:31:57 PM PDT 23
Finished Oct 18 12:33:07 PM PDT 23
Peak memory 201196 kb
Host smart-eb54dd41-4534-4454-b53d-38b36a0b276b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94335327744959155249165534245383595899638733688428539950377667205076038827912 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.94335327744959155249165534245383595899638733688428539950377667
205076038827912
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.10624255531283191768647531376321297919745590965370363393700349046847916866045
Short name T683
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.25 seconds
Started Oct 18 12:33:04 PM PDT 23
Finished Oct 18 12:33:09 PM PDT 23
Peak memory 199504 kb
Host smart-ed0faa5a-e988-4505-a286-c24a9cbd3fc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062425553128319176864753137632129791974559
0965370363393700349046847916866045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.106
24255531283191768647531376321297919745590965370363393700349046847916866045
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.24137820094554707383704358844033851084529763485954225489502202218975193550862
Short name T771
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.01 seconds
Started Oct 18 12:31:50 PM PDT 23
Finished Oct 18 12:31:54 PM PDT 23
Peak memory 200880 kb
Host smart-8f17db86-d35a-482f-b3c4-5d484f934e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137820094554707383704358844033851084529763485954225489502202218975193550862 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.24137820094554707383704358844033851084529763485954225489502202218975193550862
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.66231360735656782756590764883825528643371733675729228774127940961386298683030
Short name T720
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 18 12:33:04 PM PDT 23
Finished Oct 18 12:33:09 PM PDT 23
Peak memory 199436 kb
Host smart-78deae59-b609-42a2-9fa9-59237be3d509
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66231360735656782756590764883825528643371733675729228774127940961386298683030 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.66231360735656782756590764883825528643371733675729228774127940961386298683030
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.59828481810832275991219533877776847448612487250492198469467599612821502729377
Short name T768
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.25 seconds
Started Oct 18 12:31:25 PM PDT 23
Finished Oct 18 12:31:50 PM PDT 23
Peak memory 201068 kb
Host smart-22d1dd21-7026-47b6-ba3c-943c079baf56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59828481810832275991219533877776847448612487250492198469467599612821502729377
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.59828481810832275991219533877776847448612487
250492198469467599612821502729377
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.94064021097248008522041669122138655811337641371988050834924147733076062609535
Short name T60
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.51 seconds
Started Oct 18 12:32:19 PM PDT 23
Finished Oct 18 12:32:25 PM PDT 23
Peak memory 201212 kb
Host smart-98542325-6fe8-4e59-9bd2-87b89e31a314
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94064021097248008522041669122138655811337641371988050834924147733076062609535 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.94064021097248008522041669122138655811337641371988050834924147733076062609535
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.112511239711537149821126348089069752511050233082986743249248408370506586742403
Short name T9
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.35 seconds
Started Oct 18 12:32:08 PM PDT 23
Finished Oct 18 12:33:18 PM PDT 23
Peak memory 201176 kb
Host smart-f144a94a-b941-43c2-867f-3a7f82100dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112511239711537149821126348089069752511050233082986743249248408370506586742403 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.1125112397115371498211263480890697525110502330829867432492484
08370506586742403
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.86813398586732208654676590866870059869115664496906872306917303462228247460721
Short name T737
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.23 seconds
Started Oct 18 12:31:43 PM PDT 23
Finished Oct 18 12:31:47 PM PDT 23
Peak memory 200984 kb
Host smart-4a9710a7-7c1d-4ac2-a478-c299f527b961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8681339858673220865467659086687005986911566
4496906872306917303462228247460721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.868
13398586732208654676590866870059869115664496906872306917303462228247460721
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.55857335668135603775745977499937927780759471749550602264552820710363896767998
Short name T765
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.02 seconds
Started Oct 18 12:31:31 PM PDT 23
Finished Oct 18 12:31:37 PM PDT 23
Peak memory 200960 kb
Host smart-aec4e0e4-764e-4689-b5fb-16a8c0d0e050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55857335668135603775745977499937927780759471749550602264552820710363896767998 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.55857335668135603775745977499937927780759471749550602264552820710363896767998
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.76569440878938055224578207322104558217966362720663885146860284516811365834985
Short name T731
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.61 seconds
Started Oct 18 12:32:03 PM PDT 23
Finished Oct 18 12:32:28 PM PDT 23
Peak memory 201132 kb
Host smart-6ba22728-da38-4e2b-8b06-59b410ee0d43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76569440878938055224578207322104558217966362720663885146860284516811365834985
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.76569440878938055224578207322104558217966362
720663885146860284516811365834985
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.63032157906262802629238847794121627574617239079145028296503981393644285116869
Short name T726
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.58 seconds
Started Oct 18 12:31:52 PM PDT 23
Finished Oct 18 12:31:57 PM PDT 23
Peak memory 201028 kb
Host smart-458a4d41-5f1c-40de-9b75-4460bd3e6e1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63032157906262802629238847794121627574617239079145028296503981393644285116869 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.63032157906262802629238847794121627574617239079145028296503981393644285116869
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.64290487176746960939110831485977139549376506488836458248354377448488085154370
Short name T708
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.33 seconds
Started Oct 18 12:33:21 PM PDT 23
Finished Oct 18 12:34:29 PM PDT 23
Peak memory 201052 kb
Host smart-6bb2cb10-6588-4566-b5bf-d712a9f7eba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64290487176746960939110831485977139549376506488836458248354377448488085154370 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.64290487176746960939110831485977139549376506488836458248354377
448488085154370
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.75208789980406551737171563979736993557331863544511655045257033434417621411139
Short name T705
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Oct 18 12:32:22 PM PDT 23
Finished Oct 18 12:32:26 PM PDT 23
Peak memory 200980 kb
Host smart-b6f86425-b78c-43c0-affc-435ff9a2f412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7520878998040655173717156397973699355733186
3544511655045257033434417621411139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.752
08789980406551737171563979736993557331863544511655045257033434417621411139
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.112817092054264132850842468008890106013559974742512391587169970646809916244461
Short name T702
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.04 seconds
Started Oct 18 12:31:40 PM PDT 23
Finished Oct 18 12:31:44 PM PDT 23
Peak memory 200856 kb
Host smart-c545955c-373f-4e9f-a19f-bcf9546c9ba6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112817092054264132850842468008890106013559974742512391587169970646809916244461 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.112817092054264132850842468008890106013559974742512391587169970646809916244461
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.15847527277999936286132336278950217121576098317177293841581516463857882024741
Short name T723
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.65 seconds
Started Oct 18 12:31:47 PM PDT 23
Finished Oct 18 12:31:51 PM PDT 23
Peak memory 200948 kb
Host smart-44dc9097-629a-4207-be25-acf8dedd940f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15847527277999936286132336278950217121576098317177293841581516463857882024741 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.15847527277999936286132336278950217121576098317177293841581516463857882024741
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.47863971185358542744351358029047664602357727371650799260362012318150327377993
Short name T78
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.41 seconds
Started Oct 18 12:32:05 PM PDT 23
Finished Oct 18 12:32:30 PM PDT 23
Peak memory 201140 kb
Host smart-b83e61eb-48c6-41ff-9f87-4099c8f00014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47863971185358542744351358029047664602357727371650799260362012318150327377993
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.47863971185358542744351358029047664602357727
371650799260362012318150327377993
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.21448469616091095326995333624394326447448693094473680418085184295324965788439
Short name T59
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.53 seconds
Started Oct 18 12:31:37 PM PDT 23
Finished Oct 18 12:31:55 PM PDT 23
Peak memory 201224 kb
Host smart-d528b3aa-6784-4096-8d96-61d74c02a679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21448469616091095326995333624394326447448693094473680418085184295324965788439 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.21448469616091095326995333624394326447448693094473680418085184295324965788439
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.110357458730096941395798234319979492535403137762545506380549568925322124155544
Short name T748
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.55 seconds
Started Oct 18 12:31:23 PM PDT 23
Finished Oct 18 12:32:33 PM PDT 23
Peak memory 201160 kb
Host smart-02666ee5-dc5e-40c8-be8d-0c2329168b23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110357458730096941395798234319979492535403137762545506380549568925322124155544 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.1103574587300969413957982343199794925354031377625455063805495
68925322124155544
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.44872360518334705214432382233817703953366317816544247694698332624021517611894
Short name T685
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.13 seconds
Started Oct 18 12:32:23 PM PDT 23
Finished Oct 18 12:32:29 PM PDT 23
Peak memory 200992 kb
Host smart-54206056-98dd-4e39-9c11-6d32a06a4dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4487236051833470521443238223381770395336631
7816544247694698332624021517611894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.448
72360518334705214432382233817703953366317816544247694698332624021517611894
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.24020784332083992682403878831144703683188095005899937494203796667553153862867
Short name T68
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Oct 18 12:31:34 PM PDT 23
Finished Oct 18 12:31:39 PM PDT 23
Peak memory 200960 kb
Host smart-e098a8d6-7e38-47a0-a396-fc229bde37bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24020784332083992682403878831144703683188095005899937494203796667553153862867 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.24020784332083992682403878831144703683188095005899937494203796667553153862867
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.51025047778878843391098867215912548858692635033773499395615611614173798976389
Short name T681
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.85 seconds
Started Oct 18 12:32:12 PM PDT 23
Finished Oct 18 12:32:16 PM PDT 23
Peak memory 200928 kb
Host smart-4906840f-50e6-422b-9d9c-3e961205e64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51025047778878843391098867215912548858692635033773499395615611614173798976389 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.51025047778878843391098867215912548858692635033773499395615611614173798976389
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.37749759288301842075013021124768889746618612569007685350764187049355563116969
Short name T682
Test name
Test status
Simulation time 9477310853 ps
CPU time 23.95 seconds
Started Oct 18 12:32:20 PM PDT 23
Finished Oct 18 12:32:44 PM PDT 23
Peak memory 201144 kb
Host smart-dc15193e-0e43-44c9-b07d-28bffd2af094
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37749759288301842075013021124768889746618612569007685350764187049355563116969
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.37749759288301842075013021124768889746618612
569007685350764187049355563116969
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.64311902242126412660176101504489572423517801401571323960323347674979753048845
Short name T766
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.62 seconds
Started Oct 18 12:32:19 PM PDT 23
Finished Oct 18 12:32:25 PM PDT 23
Peak memory 201120 kb
Host smart-0965d12a-05b8-464e-bf0a-8e6323b373f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64311902242126412660176101504489572423517801401571323960323347674979753048845 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.64311902242126412660176101504489572423517801401571323960323347674979753048845
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.23600208031139032803710067817414700290457227500930027779879175927580037534
Short name T8
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.62 seconds
Started Oct 18 12:32:01 PM PDT 23
Finished Oct 18 12:33:20 PM PDT 23
Peak memory 201104 kb
Host smart-9c5d2744-cb2a-46ea-baa2-32f5d7ad84b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23600208031139032803710067817414700290457227500930027779879175927580037534 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.23600208031139032803710067817414700290457227500930027779879175927580037534
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.63393781590856904139456375155825273638689695044070806908325868579651747199944
Short name T87
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.84 seconds
Started Oct 18 12:23:02 PM PDT 23
Finished Oct 18 12:23:12 PM PDT 23
Peak memory 201400 kb
Host smart-ce74f165-1a1f-4156-bd1d-5ae0f2ebf7a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63393781590856904139456375155825273638689695044070806908325868579651747199944 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.63393781590856904139456375155825273638689695044070806908325868579651747199944
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.37553731767000346075918923350855566277857519664212637605027384720488999058761
Short name T86
Test name
Test status
Simulation time 41047879715 ps
CPU time 110.1 seconds
Started Oct 18 12:25:58 PM PDT 23
Finished Oct 18 12:27:49 PM PDT 23
Peak memory 200408 kb
Host smart-42618a1f-ef72-47b3-ae05-3af4749c54cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37553731767000346075918923350855566277857519664212637605027384720488999058761 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.37553731767000346075918923350855566277857519664212637605027384720488999058761
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.55295279325158935601933791633388008991065288778704346433916288167440717312761
Short name T74
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.98 seconds
Started Oct 18 12:26:11 PM PDT 23
Finished Oct 18 12:26:22 PM PDT 23
Peak memory 200932 kb
Host smart-9291da15-e21c-40ee-8650-1acb4ec7fb1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55295279325158935601933791633388008991065288778704346433916288167440717312761 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.55295279325158935601933791633388008991065288778704346433916288167440717312761
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.73429790013116641302678041773484466324652810329425832760788874869985941876578
Short name T82
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Oct 18 12:27:34 PM PDT 23
Finished Oct 18 12:27:44 PM PDT 23
Peak memory 200860 kb
Host smart-8210c589-01f7-40d1-ab94-834fe4e76416
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7342979001311664130267804177348446632465281
0329425832760788874869985941876578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.7342
9790013116641302678041773484466324652810329425832760788874869985941876578
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.72885239487443909354520619523350253131653821350848467945018740869176578119917
Short name T73
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Oct 18 12:28:06 PM PDT 23
Finished Oct 18 12:28:11 PM PDT 23
Peak memory 200840 kb
Host smart-a11326ba-c0e0-4947-896c-38712b119814
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72885239487443909354520619523350253131653821350848467945018740869176578119917 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.72885239487443909354520619523350253131653821350848467945018740869176578119917
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.39963464573559397932854813629389725696534651003146500166483477100471139793659
Short name T764
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 18 12:28:21 PM PDT 23
Finished Oct 18 12:28:25 PM PDT 23
Peak memory 200808 kb
Host smart-708ba982-2135-4fd9-98a3-742fba6c7f72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963464573559397932854813629389725696534651003146500166483477100471139793659 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.39963464573559397932854813629389725696534651003146500166483477100471139793659
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.34392682442053669445727913011339333428422945243974362217280515746412793460118
Short name T729
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.57 seconds
Started Oct 18 12:27:29 PM PDT 23
Finished Oct 18 12:27:55 PM PDT 23
Peak memory 200340 kb
Host smart-7b4fd848-8d13-4939-b459-c8532b9803bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34392682442053669445727913011339333428422945243974362217280515746412793460118
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.343926824420536694457279130113393334284229452
43974362217280515746412793460118
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.58061878675244633352627200074960943649268862885943396978935312266866031225408
Short name T707
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.54 seconds
Started Oct 18 12:27:54 PM PDT 23
Finished Oct 18 12:28:00 PM PDT 23
Peak memory 201076 kb
Host smart-4877e26b-e485-4ff1-a633-fb4d6a6f4686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58061878675244633352627200074960943649268862885943396978935312266866031225408 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.58061878675244633352627200074960943649268862885943396978935312266866031225408
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.30646763901259065527525637911315663161079575839422410189983797420995143563794
Short name T10
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.1 seconds
Started Oct 18 12:27:51 PM PDT 23
Finished Oct 18 12:29:01 PM PDT 23
Peak memory 201180 kb
Host smart-1c3611e3-7690-41d3-aa94-05c43186ed32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30646763901259065527525637911315663161079575839422410189983797420995143563794 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.306467639012590655275256379113156631610795758394224101899837974
20995143563794
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.9953619141845776906797087983045240198735913198987357152055909711004334383840
Short name T138
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 18 12:31:56 PM PDT 23
Finished Oct 18 12:32:00 PM PDT 23
Peak memory 200884 kb
Host smart-e8a057c8-45b3-4180-a5ce-305287a24853
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9953619141845776906797087983045240198735913198987357152055909711004334383840 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.9953619141845776906797087983045240198735913198987357152055909711004334383840
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.31016559452757925310588915608096255442171782467226198061867363109359364302382
Short name T706
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 18 12:32:17 PM PDT 23
Finished Oct 18 12:32:22 PM PDT 23
Peak memory 200876 kb
Host smart-37d4f976-5e17-4e07-a8ac-1c1e66efb1f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31016559452757925310588915608096255442171782467226198061867363109359364302382 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.31016559452757925310588915608096255442171782467226198061867363109359364302382
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.62146135365056021270809957889346165293854642273220726995355183702583351406377
Short name T675
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 18 12:31:38 PM PDT 23
Finished Oct 18 12:31:42 PM PDT 23
Peak memory 200940 kb
Host smart-863e7ff1-0692-4c3e-9179-8f22cad2cc39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62146135365056021270809957889346165293854642273220726995355183702583351406377 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.62146135365056021270809957889346165293854642273220726995355183702583351406377
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.56598248050016126722784980709512993687164073072994397777457980192109056952001
Short name T743
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.83 seconds
Started Oct 18 12:32:12 PM PDT 23
Finished Oct 18 12:32:16 PM PDT 23
Peak memory 200792 kb
Host smart-508451ae-d5d5-4909-b83c-e93467f3411d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56598248050016126722784980709512993687164073072994397777457980192109056952001 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.56598248050016126722784980709512993687164073072994397777457980192109056952001
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.112715788870524793518389082482762131709245021864785006774788637073743184337619
Short name T744
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.67 seconds
Started Oct 18 12:32:16 PM PDT 23
Finished Oct 18 12:32:20 PM PDT 23
Peak memory 200884 kb
Host smart-31ca4464-1fb8-4f4c-b614-8141f6ab4db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112715788870524793518389082482762131709245021864785006774788637073743184337619 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.112715788870524793518389082482762131709245021864785006774788637073743184337619
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.68149800049846163293765166448711442259088326885817696857120656801453051440112
Short name T679
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 18 12:31:32 PM PDT 23
Finished Oct 18 12:31:36 PM PDT 23
Peak memory 200944 kb
Host smart-a5244d09-9012-4830-809d-91025c1a618f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68149800049846163293765166448711442259088326885817696857120656801453051440112 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.68149800049846163293765166448711442259088326885817696857120656801453051440112
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.107494747335130470297446233549316158545950372195420345592827852071500543423582
Short name T64
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 18 12:32:37 PM PDT 23
Finished Oct 18 12:32:42 PM PDT 23
Peak memory 200936 kb
Host smart-ade631cb-9017-4d0b-88bc-0a53fb7ce606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107494747335130470297446233549316158545950372195420345592827852071500543423582 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.107494747335130470297446233549316158545950372195420345592827852071500543423582
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.85221276002439147294511255790410743760517196333142452973444615046386908940690
Short name T763
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 18 12:33:11 PM PDT 23
Finished Oct 18 12:33:16 PM PDT 23
Peak memory 200944 kb
Host smart-a6569b67-af8d-4ca9-9497-b2798938d64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85221276002439147294511255790410743760517196333142452973444615046386908940690 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.85221276002439147294511255790410743760517196333142452973444615046386908940690
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.69185508396913563148011213650093581387835338614542912773722831322503076993010
Short name T725
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Oct 18 12:32:17 PM PDT 23
Finished Oct 18 12:32:22 PM PDT 23
Peak memory 200876 kb
Host smart-6c47c25f-e3e5-424a-be58-7dce3cc546ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69185508396913563148011213650093581387835338614542912773722831322503076993010 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.69185508396913563148011213650093581387835338614542912773722831322503076993010
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.4819911824654208139436269123940984077647499162298791781611628999227322023680
Short name T80
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 18 12:34:06 PM PDT 23
Finished Oct 18 12:34:12 PM PDT 23
Peak memory 200812 kb
Host smart-12662b7d-f72a-4530-9541-fb72883a47bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4819911824654208139436269123940984077647499162298791781611628999227322023680 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.4819911824654208139436269123940984077647499162298791781611628999227322023680
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.54253887969342551015481801986249546831089306527504794185064503228814385032080
Short name T84
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.35 seconds
Started Oct 18 12:27:48 PM PDT 23
Finished Oct 18 12:27:56 PM PDT 23
Peak memory 200988 kb
Host smart-f3a6a97b-e6ba-4eec-8e87-619aadcc04d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54253887969342551015481801986249546831089306527504794185064503228814385032080 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.54253887969342551015481801986249546831089306527504794185064503228814385032080
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.6174789410893466368958071282399807423636674330809516096213349670415013619710
Short name T90
Test name
Test status
Simulation time 41047879715 ps
CPU time 113.09 seconds
Started Oct 18 12:27:31 PM PDT 23
Finished Oct 18 12:29:24 PM PDT 23
Peak memory 200884 kb
Host smart-c9a81c77-2f82-43da-9e77-439589c6cb7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6174789410893466368958071282399807423636674330809516096213349670415013619710 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.6174789410893466368958071282399807423636674330809516096213349670415013619710
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.90490666410190223758187847111159272181281536035224953569663392128270703220906
Short name T779
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.01 seconds
Started Oct 18 12:27:53 PM PDT 23
Finished Oct 18 12:28:04 PM PDT 23
Peak memory 201040 kb
Host smart-950df341-823e-48cd-8e85-10bb543eda9d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90490666410190223758187847111159272181281536035224953569663392128270703220906 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.90490666410190223758187847111159272181281536035224953569663392128270703220906
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.80603270374567311599596096899511056039223937700929213602972454913408648535314
Short name T686
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.23 seconds
Started Oct 18 12:31:50 PM PDT 23
Finished Oct 18 12:31:55 PM PDT 23
Peak memory 201000 kb
Host smart-47ae78c3-2f0e-4b25-bb45-32a1813b4dd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8060327037456731159959609689951105603922393
7700929213602972454913408648535314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.8060
3270374567311599596096899511056039223937700929213602972454913408648535314
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.93079506347657964797138141075049680157157596460682622279704707921759392475110
Short name T71
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.05 seconds
Started Oct 18 12:25:17 PM PDT 23
Finished Oct 18 12:25:21 PM PDT 23
Peak memory 200876 kb
Host smart-841c172b-1f13-423a-a079-89de49dd5e2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93079506347657964797138141075049680157157596460682622279704707921759392475110 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.93079506347657964797138141075049680157157596460682622279704707921759392475110
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.113449626123506944766163458053864917494845898366075942146970437640021361910939
Short name T753
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Oct 18 12:25:26 PM PDT 23
Finished Oct 18 12:25:31 PM PDT 23
Peak memory 200880 kb
Host smart-ba97ace9-7b17-4092-ae8a-fdf837c7e1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113449626123506944766163458053864917494845898366075942146970437640021361910939 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.113449626123506944766163458053864917494845898366075942146970437640021361910939
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.30507784805390840860621430616915967220624098245022575047422262477068608310682
Short name T690
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.42 seconds
Started Oct 18 12:31:38 PM PDT 23
Finished Oct 18 12:32:08 PM PDT 23
Peak memory 201220 kb
Host smart-35e02dec-d50a-441e-bd86-508a1e456475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30507784805390840860621430616915967220624098245022575047422262477068608310682
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.305077848053908408606214306169159672206240982
45022575047422262477068608310682
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.72679341669708345211571605031567197771194494310291659049843045592695712675018
Short name T53
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.66 seconds
Started Oct 18 12:25:15 PM PDT 23
Finished Oct 18 12:25:21 PM PDT 23
Peak memory 200616 kb
Host smart-45119261-4bfe-4efd-bf0e-32ef84b8d154
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72679341669708345211571605031567197771194494310291659049843045592695712675018 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.72679341669708345211571605031567197771194494310291659049843045592695712675018
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.74772240371917622542732404234077049375418498833754519911495895649605457865957
Short name T772
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.86 seconds
Started Oct 18 12:27:40 PM PDT 23
Finished Oct 18 12:28:49 PM PDT 23
Peak memory 201096 kb
Host smart-f07e09d7-846d-469e-80e0-1e0a4ce18fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74772240371917622542732404234077049375418498833754519911495895649605457865957 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.747722403719176225427324042340770493754184988337545199114958956
49605457865957
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2986601773502945102131059681289377192212558082733465357249010010522992622786
Short name T680
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 18 12:32:51 PM PDT 23
Finished Oct 18 12:32:55 PM PDT 23
Peak memory 200884 kb
Host smart-7c4494e4-1599-4d82-9db5-1f5f706d004f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986601773502945102131059681289377192212558082733465357249010010522992622786 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.2986601773502945102131059681289377192212558082733465357249010010522992622786
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.48263964181189315620507596287171719665771489062024931689336049534188737453592
Short name T749
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Oct 18 12:31:25 PM PDT 23
Finished Oct 18 12:31:41 PM PDT 23
Peak memory 200796 kb
Host smart-4b89e51a-64a3-4e86-8ef0-c05ff2bd491b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48263964181189315620507596287171719665771489062024931689336049534188737453592 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.48263964181189315620507596287171719665771489062024931689336049534188737453592
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.61436736231834592196685515809826448809947436501133852953050787937956277398151
Short name T677
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Oct 18 12:32:21 PM PDT 23
Finished Oct 18 12:32:25 PM PDT 23
Peak memory 200820 kb
Host smart-d5316713-6a38-43bc-8d86-fc8cd3bf4f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61436736231834592196685515809826448809947436501133852953050787937956277398151 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.61436736231834592196685515809826448809947436501133852953050787937956277398151
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.96186956408834692581926359573641524948249758337670214878840729342920717222327
Short name T13
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.78 seconds
Started Oct 18 12:32:12 PM PDT 23
Finished Oct 18 12:32:17 PM PDT 23
Peak memory 200884 kb
Host smart-e8dc37d8-1486-4bfe-a706-aebde35027b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96186956408834692581926359573641524948249758337670214878840729342920717222327 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.96186956408834692581926359573641524948249758337670214878840729342920717222327
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.110208587904364223706710717942879095898059692573492423815857103961402635136224
Short name T757
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 18 12:32:13 PM PDT 23
Finished Oct 18 12:32:17 PM PDT 23
Peak memory 200964 kb
Host smart-c65772cb-fe72-484c-a4b4-4a3cccb3d1c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110208587904364223706710717942879095898059692573492423815857103961402635136224 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.110208587904364223706710717942879095898059692573492423815857103961402635136224
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.76727277468349424799405012691809982436423617346807548694224967939602168462557
Short name T739
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 18 12:32:12 PM PDT 23
Finished Oct 18 12:32:16 PM PDT 23
Peak memory 200876 kb
Host smart-7eea6a3e-a3d8-4e21-9082-596241b55654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76727277468349424799405012691809982436423617346807548694224967939602168462557 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.76727277468349424799405012691809982436423617346807548694224967939602168462557
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.73276893042038493331490182523468546759611532702750511179430292800446270100698
Short name T724
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 18 12:32:12 PM PDT 23
Finished Oct 18 12:32:21 PM PDT 23
Peak memory 200904 kb
Host smart-c7b98629-b722-4c9b-9d30-a612dd96cd5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73276893042038493331490182523468546759611532702750511179430292800446270100698 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.73276893042038493331490182523468546759611532702750511179430292800446270100698
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.34181516108945705695402729667733138775623184384186942607051655069068487147467
Short name T55
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.66 seconds
Started Oct 18 12:32:18 PM PDT 23
Finished Oct 18 12:32:22 PM PDT 23
Peak memory 200884 kb
Host smart-337e36c8-4ed9-47f0-a036-244a7a28746b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34181516108945705695402729667733138775623184384186942607051655069068487147467 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.34181516108945705695402729667733138775623184384186942607051655069068487147467
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.83641522098297646494556101991323492292712472255117826324602062658575394698994
Short name T684
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:32:20 PM PDT 23
Finished Oct 18 12:32:24 PM PDT 23
Peak memory 200844 kb
Host smart-83a86902-1e02-43fd-8607-7ac83bc24099
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83641522098297646494556101991323492292712472255117826324602062658575394698994 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.83641522098297646494556101991323492292712472255117826324602062658575394698994
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.19378241731292424426142078680598859530336117924045416486448858981786992814831
Short name T93
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Oct 18 12:32:09 PM PDT 23
Finished Oct 18 12:32:13 PM PDT 23
Peak memory 200924 kb
Host smart-0ae4b847-f391-453d-846c-a1b3e3607c88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19378241731292424426142078680598859530336117924045416486448858981786992814831 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.19378241731292424426142078680598859530336117924045416486448858981786992814831
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.26228214620843208288717308255882094635053037159821468433683137165495834675383
Short name T85
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.53 seconds
Started Oct 18 12:32:06 PM PDT 23
Finished Oct 18 12:32:15 PM PDT 23
Peak memory 201208 kb
Host smart-6a6f5559-28fe-48f8-8cf6-f4480f7aa2a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26228214620843208288717308255882094635053037159821468433683137165495834675383 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.26228214620843208288717308255882094635053037159821468433683137165495834675383
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.92200751991146393948483000098325002939140039140708998973244335832894401600560
Short name T70
Test name
Test status
Simulation time 41047879715 ps
CPU time 110.92 seconds
Started Oct 18 12:32:03 PM PDT 23
Finished Oct 18 12:33:55 PM PDT 23
Peak memory 201208 kb
Host smart-d5b6930a-138d-41e2-98a0-12a9c92814cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92200751991146393948483000098325002939140039140708998973244335832894401600560 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.92200751991146393948483000098325002939140039140708998973244335832894401600560
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.22856270843654994077861023911509232954357445855856885686954091221681119959764
Short name T740
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.95 seconds
Started Oct 18 12:32:21 PM PDT 23
Finished Oct 18 12:32:31 PM PDT 23
Peak memory 201052 kb
Host smart-8f07599d-b1e6-47b2-a424-9fecbe5ebf46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22856270843654994077861023911509232954357445855856885686954091221681119959764 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.22856270843654994077861023911509232954357445855856885686954091221681119959764
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.58796114567234628207375140856733519788532740100062771996719243900605504059247
Short name T727
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.12 seconds
Started Oct 18 12:32:18 PM PDT 23
Finished Oct 18 12:32:23 PM PDT 23
Peak memory 200972 kb
Host smart-cf01859a-f706-48b5-8335-cc7ad629a475
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5879611456723462820737514085673351978853274
0100062771996719243900605504059247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.5879
6114567234628207375140856733519788532740100062771996719243900605504059247
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.110554752655404463465462824337647174963640920895487071484549348328856439302399
Short name T728
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.07 seconds
Started Oct 18 12:31:48 PM PDT 23
Finished Oct 18 12:31:53 PM PDT 23
Peak memory 200908 kb
Host smart-9b3934cf-6d83-4c93-a835-3d18bdb27487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110554752655404463465462824337647174963640920895487071484549348328856439302399 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.110554752655404463465462824337647174963640920895487071484549348328856439302399
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.46510176198571647131204070912690886058565303352061090999288971252052547074805
Short name T688
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 18 12:32:38 PM PDT 23
Finished Oct 18 12:32:42 PM PDT 23
Peak memory 200928 kb
Host smart-173d1efb-4ab1-4496-a362-cab8aeeff1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46510176198571647131204070912690886058565303352061090999288971252052547074805 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.46510176198571647131204070912690886058565303352061090999288971252052547074805
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.78584176414701784564672738432000363673315811360136420501187800916539830104549
Short name T92
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.26 seconds
Started Oct 18 12:32:05 PM PDT 23
Finished Oct 18 12:32:29 PM PDT 23
Peak memory 201108 kb
Host smart-aed5b418-7f57-4bc0-9666-f924f97fe9b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78584176414701784564672738432000363673315811360136420501187800916539830104549
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.785841764147017845646727384320003636733158113
60136420501187800916539830104549
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.53948290650056639477996005295914022596266895814232297906707249616254659256904
Short name T56
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.73 seconds
Started Oct 18 12:31:46 PM PDT 23
Finished Oct 18 12:31:52 PM PDT 23
Peak memory 201160 kb
Host smart-614e5d4d-55be-4326-9894-57e7a9650991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53948290650056639477996005295914022596266895814232297906707249616254659256904 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.53948290650056639477996005295914022596266895814232297906707249616254659256904
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.14639313166984276469145253491452616421165074701552523229061571011451923211354
Short name T715
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.14 seconds
Started Oct 18 12:31:33 PM PDT 23
Finished Oct 18 12:32:42 PM PDT 23
Peak memory 201120 kb
Host smart-b51d368c-f7a2-424f-9af6-9a6c284cab5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639313166984276469145253491452616421165074701552523229061571011451923211354 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.146393131669842764691452534914526164211650747015525232290615710
11451923211354
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.103233183421387073451857407258114376990587470950623560306458177771490263028081
Short name T81
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:31:50 PM PDT 23
Finished Oct 18 12:31:54 PM PDT 23
Peak memory 200936 kb
Host smart-598cc95f-4732-488e-b0bd-639515db4616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103233183421387073451857407258114376990587470950623560306458177771490263028081 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.103233183421387073451857407258114376990587470950623560306458177771490263028081
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.33865881321406674800158813677822599857900710708684689311399615705087832495048
Short name T704
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.66 seconds
Started Oct 18 12:32:19 PM PDT 23
Finished Oct 18 12:32:28 PM PDT 23
Peak memory 200940 kb
Host smart-38fd6eff-617b-4c74-bfc6-5c558e20e551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33865881321406674800158813677822599857900710708684689311399615705087832495048 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.33865881321406674800158813677822599857900710708684689311399615705087832495048
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.73119419406730173109650102438597999723550603588069404834337725431437404897851
Short name T758
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 18 12:33:55 PM PDT 23
Finished Oct 18 12:34:00 PM PDT 23
Peak memory 200640 kb
Host smart-37576eb8-da35-4f33-9255-4ee3ff1a0912
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73119419406730173109650102438597999723550603588069404834337725431437404897851 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.73119419406730173109650102438597999723550603588069404834337725431437404897851
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.13089691140777483432089127423649805494586689551457859844860097450448222017508
Short name T12
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:31:32 PM PDT 23
Finished Oct 18 12:31:36 PM PDT 23
Peak memory 200928 kb
Host smart-b0667613-0817-448a-b32f-c554e6adc161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13089691140777483432089127423649805494586689551457859844860097450448222017508 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.13089691140777483432089127423649805494586689551457859844860097450448222017508
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.71307313795427559282823241934405224311877170906266495607201626825536344898043
Short name T756
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:31:32 PM PDT 23
Finished Oct 18 12:31:36 PM PDT 23
Peak memory 200860 kb
Host smart-09da3e66-aa6a-46b8-a7f0-8628be9776e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71307313795427559282823241934405224311877170906266495607201626825536344898043 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.71307313795427559282823241934405224311877170906266495607201626825536344898043
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.74973689304752076096480354124684151681474371887150210215282907884582419843685
Short name T79
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 18 12:31:48 PM PDT 23
Finished Oct 18 12:31:52 PM PDT 23
Peak memory 201064 kb
Host smart-11213861-dc05-4d2f-b420-4d0618a6c2a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74973689304752076096480354124684151681474371887150210215282907884582419843685 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.74973689304752076096480354124684151681474371887150210215282907884582419843685
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.77166358225914960745635378764729569539974308237691164015934796471222936524811
Short name T781
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Oct 18 12:33:57 PM PDT 23
Finished Oct 18 12:34:01 PM PDT 23
Peak memory 200720 kb
Host smart-dd82be4a-c7e6-4cdd-bb13-ddd6a70ec6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77166358225914960745635378764729569539974308237691164015934796471222936524811 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.77166358225914960745635378764729569539974308237691164015934796471222936524811
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.6857941242882667998364751519145005771814186048831071602766316524142655735312
Short name T137
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Oct 18 12:32:03 PM PDT 23
Finished Oct 18 12:32:07 PM PDT 23
Peak memory 200880 kb
Host smart-e2ee3406-7085-4d39-8f1b-9fd3d672a119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6857941242882667998364751519145005771814186048831071602766316524142655735312 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.6857941242882667998364751519145005771814186048831071602766316524142655735312
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.16230161095983246379330823770386989788312284658361499504001107003982223009597
Short name T689
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 18 12:32:15 PM PDT 23
Finished Oct 18 12:32:19 PM PDT 23
Peak memory 200928 kb
Host smart-8a8cfdac-e31a-4b4c-97c3-b12aa433bb0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16230161095983246379330823770386989788312284658361499504001107003982223009597 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.16230161095983246379330823770386989788312284658361499504001107003982223009597
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.43145190079952856209137042635231539893838800473295537441791217722469985034389
Short name T692
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.84 seconds
Started Oct 18 12:32:19 PM PDT 23
Finished Oct 18 12:32:23 PM PDT 23
Peak memory 200940 kb
Host smart-b275b99b-c6fe-4e08-89c5-53987848b8c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43145190079952856209137042635231539893838800473295537441791217722469985034389 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.43145190079952856209137042635231539893838800473295537441791217722469985034389
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.31822565199008963309445518788063177759466653925700449808128619215080433067959
Short name T760
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.15 seconds
Started Oct 18 12:31:43 PM PDT 23
Finished Oct 18 12:31:47 PM PDT 23
Peak memory 200976 kb
Host smart-dfa045bb-ee30-4349-b30b-bbdab6c63a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182256519900896330944551878806317775946665
3925700449808128619215080433067959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3182
2565199008963309445518788063177759466653925700449808128619215080433067959
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.31013778901983575115101169662231378392939711493836486861524515511160518023781
Short name T769
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.04 seconds
Started Oct 18 12:31:50 PM PDT 23
Finished Oct 18 12:31:54 PM PDT 23
Peak memory 200932 kb
Host smart-00672062-f433-4bec-b54c-da4b84bdb018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31013778901983575115101169662231378392939711493836486861524515511160518023781 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.31013778901983575115101169662231378392939711493836486861524515511160518023781
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.47534563963473612773274698386413801306163998152765335483152471207293058845714
Short name T719
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 18 12:32:41 PM PDT 23
Finished Oct 18 12:32:45 PM PDT 23
Peak memory 200872 kb
Host smart-7f3fd0d3-a03a-4e77-82e0-b223dcd6ae86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47534563963473612773274698386413801306163998152765335483152471207293058845714 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.47534563963473612773274698386413801306163998152765335483152471207293058845714
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.16128418496414443867154390570137262285502166047505976591825031093541270241998
Short name T709
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.37 seconds
Started Oct 18 12:32:20 PM PDT 23
Finished Oct 18 12:32:45 PM PDT 23
Peak memory 201188 kb
Host smart-b6a85c8a-513e-4ebc-a025-b8252d73870d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128418496414443867154390570137262285502166047505976591825031093541270241998
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.161284184964144438671543905701372622855021660
47505976591825031093541270241998
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.104414987534693418526946615822566705538190206183441781590753574874692032368587
Short name T712
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.53 seconds
Started Oct 18 12:32:22 PM PDT 23
Finished Oct 18 12:32:28 PM PDT 23
Peak memory 201168 kb
Host smart-98ce8e50-f56d-4bf9-aac2-7fd4ca90ce8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104414987534693418526946615822566705538190206183441781590753574874692032368587 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.104414987534693418526946615822566705538190206183441781590753574874692032368587
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.70843300202052242420883707988870079655057740983793739148249713861589951653219
Short name T775
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.71 seconds
Started Oct 18 12:31:23 PM PDT 23
Finished Oct 18 12:32:32 PM PDT 23
Peak memory 201252 kb
Host smart-d60e0813-f41e-443b-9da4-c647dcb33245
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70843300202052242420883707988870079655057740983793739148249713861589951653219 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.708433002020522424208837079888700796550577409837937391482497138
61589951653219
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.65155080607325750859372420718871226765393303456050579350199526768551878808457
Short name T767
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Oct 18 12:31:32 PM PDT 23
Finished Oct 18 12:31:36 PM PDT 23
Peak memory 201028 kb
Host smart-4476635a-1d17-42f4-824d-7d8dbe10fab0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6515508060732575085937242071887122676539330
3456050579350199526768551878808457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.6515
5080607325750859372420718871226765393303456050579350199526768551878808457
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.112376383130508927432080215427877624336833585261276381440273863154370613312606
Short name T782
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Oct 18 12:32:11 PM PDT 23
Finished Oct 18 12:32:15 PM PDT 23
Peak memory 200928 kb
Host smart-d75779f6-3a85-4b83-bbe0-84051b233100
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112376383130508927432080215427877624336833585261276381440273863154370613312606 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.112376383130508927432080215427877624336833585261276381440273863154370613312606
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.102283099824332467243040245055449514085052977365791065133429686476879320226333
Short name T687
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 18 12:31:39 PM PDT 23
Finished Oct 18 12:31:43 PM PDT 23
Peak memory 200952 kb
Host smart-0a0e30ae-1c6c-4c09-882d-bf9ef851d6e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102283099824332467243040245055449514085052977365791065133429686476879320226333 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.102283099824332467243040245055449514085052977365791065133429686476879320226333
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.46943592069414846818188855789433924883017852636910758038496334555653515671895
Short name T738
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.62 seconds
Started Oct 18 12:31:59 PM PDT 23
Finished Oct 18 12:32:24 PM PDT 23
Peak memory 201140 kb
Host smart-441e20f8-bb8e-40a9-ba16-70c1fa868301
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46943592069414846818188855789433924883017852636910758038496334555653515671895
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.469435920694148468181888557894339248830178526
36910758038496334555653515671895
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.79127204078715286921806331353026763012023940711194883902148870061651809785178
Short name T58
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.62 seconds
Started Oct 18 12:32:00 PM PDT 23
Finished Oct 18 12:32:06 PM PDT 23
Peak memory 201156 kb
Host smart-8f113a7b-78ff-4543-ade5-157f29b60f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79127204078715286921806331353026763012023940711194883902148870061651809785178 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.79127204078715286921806331353026763012023940711194883902148870061651809785178
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.55444388981269443036016987490812263395825372113424351592005678469372186145987
Short name T697
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.84 seconds
Started Oct 18 12:31:46 PM PDT 23
Finished Oct 18 12:32:56 PM PDT 23
Peak memory 201240 kb
Host smart-0803d910-eb70-4468-ba8b-951ff8bf0ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55444388981269443036016987490812263395825372113424351592005678469372186145987 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.554443889812694430360169874908122633958253721134243515920056784
69372186145987
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.92517199465156355430824713723745279187234977354569422658842735714066019647896
Short name T762
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Oct 18 12:31:42 PM PDT 23
Finished Oct 18 12:31:46 PM PDT 23
Peak memory 200992 kb
Host smart-2bab234a-948b-4e99-9b03-b24fe77f5822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9251719946515635543082471372374527918723497
7354569422658842735714066019647896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.9251
7199465156355430824713723745279187234977354569422658842735714066019647896
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.80677928392060125160889683627771799369197812650188749849162998868100615307788
Short name T72
Test name
Test status
Simulation time 2074977215 ps
CPU time 4 seconds
Started Oct 18 12:31:34 PM PDT 23
Finished Oct 18 12:31:44 PM PDT 23
Peak memory 200848 kb
Host smart-845990e7-3718-4d64-86a6-b55effd1a39a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80677928392060125160889683627771799369197812650188749849162998868100615307788 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.80677928392060125160889683627771799369197812650188749849162998868100615307788
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1231933405065167247064565116314206409149674154396400796663450149156009589089
Short name T676
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:31:49 PM PDT 23
Finished Oct 18 12:31:53 PM PDT 23
Peak memory 200892 kb
Host smart-1db68c55-820d-4c24-908c-f20fe863c5ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231933405065167247064565116314206409149674154396400796663450149156009589089 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.1231933405065167247064565116314206409149674154396400796663450149156009589089
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.40480160818030532056369715357288004730441508330516213751893212657626263309427
Short name T11
Test name
Test status
Simulation time 9477310853 ps
CPU time 23.97 seconds
Started Oct 18 12:33:21 PM PDT 23
Finished Oct 18 12:33:46 PM PDT 23
Peak memory 200772 kb
Host smart-9dcc516e-4bd1-496e-8022-1725b61ce022
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480160818030532056369715357288004730441508330516213751893212657626263309427
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.404801608180305320563697153572880047304415083
30516213751893212657626263309427
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.92000744253554081827310672152435043985503788848094303347048814838473565640425
Short name T734
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.68 seconds
Started Oct 18 12:32:15 PM PDT 23
Finished Oct 18 12:32:21 PM PDT 23
Peak memory 201204 kb
Host smart-723a92db-126d-437e-b216-605e63d34a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92000744253554081827310672152435043985503788848094303347048814838473565640425 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.92000744253554081827310672152435043985503788848094303347048814838473565640425
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.76106492232763105621744064208468952688312308921436448600405067064326970324056
Short name T713
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.54 seconds
Started Oct 18 12:32:13 PM PDT 23
Finished Oct 18 12:33:22 PM PDT 23
Peak memory 201180 kb
Host smart-4c10e848-beeb-4aa3-8ded-c1a0367a1237
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76106492232763105621744064208468952688312308921436448600405067064326970324056 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.761064922327631056217440642084689526883123089214364486004050670
64326970324056
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.78252413489198521544469637180191790975711067391995197178714155823724317652497
Short name T703
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.17 seconds
Started Oct 18 12:31:39 PM PDT 23
Finished Oct 18 12:31:43 PM PDT 23
Peak memory 200920 kb
Host smart-110eeb49-e036-45e8-9b35-432d7bec36a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7825241348919852154446963718019179097571106
7391995197178714155823724317652497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.7825
2413489198521544469637180191790975711067391995197178714155823724317652497
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.25577332109573837211719006940127592160260473530717192942634260581524688038831
Short name T716
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.07 seconds
Started Oct 18 12:31:43 PM PDT 23
Finished Oct 18 12:31:48 PM PDT 23
Peak memory 200928 kb
Host smart-2342544d-34d5-4fa5-bdc4-a60d1fa69a42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25577332109573837211719006940127592160260473530717192942634260581524688038831 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.25577332109573837211719006940127592160260473530717192942634260581524688038831
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.55428455086342987622127103412955051947006465942315541309928340217078034875136
Short name T695
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 18 12:31:31 PM PDT 23
Finished Oct 18 12:31:35 PM PDT 23
Peak memory 200944 kb
Host smart-cc81865b-7c58-4604-99f2-2f2b07c9f8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55428455086342987622127103412955051947006465942315541309928340217078034875136 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.55428455086342987622127103412955051947006465942315541309928340217078034875136
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.14584863453688645070073807336057231535816314027039980665722170070557448064445
Short name T696
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.41 seconds
Started Oct 18 12:31:32 PM PDT 23
Finished Oct 18 12:31:56 PM PDT 23
Peak memory 201100 kb
Host smart-ff7d1665-7bde-4852-b406-dc521962c57b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584863453688645070073807336057231535816314027039980665722170070557448064445
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.145848634536886450700738073360572315358163140
27039980665722170070557448064445
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.37152952043677085476092546652428590762996589408367890418675878729172747884050
Short name T57
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.64 seconds
Started Oct 18 12:31:53 PM PDT 23
Finished Oct 18 12:31:59 PM PDT 23
Peak memory 201124 kb
Host smart-6409823f-71da-48b5-99ac-bc31c387a543
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37152952043677085476092546652428590762996589408367890418675878729172747884050 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.37152952043677085476092546652428590762996589408367890418675878729172747884050
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1224100237138502214252113942344112435178662000276988134228039804021092346919
Short name T700
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.04 seconds
Started Oct 18 12:33:22 PM PDT 23
Finished Oct 18 12:34:30 PM PDT 23
Peak memory 201044 kb
Host smart-e1753727-29fd-42a0-8c5f-ef42259d13d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224100237138502214252113942344112435178662000276988134228039804021092346919 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.1224100237138502214252113942344112435178662000276988134228039804021092346919
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.6446962913854077121248749933919501489652265826319577948907622313083328435230
Short name T742
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.11 seconds
Started Oct 18 12:31:38 PM PDT 23
Finished Oct 18 12:31:42 PM PDT 23
Peak memory 201052 kb
Host smart-0186627e-6038-4b70-8142-4ddc0bde0e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6446962913854077121248749933919501489652265
826319577948907622313083328435230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.64469
62913854077121248749933919501489652265826319577948907622313083328435230
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.22363099418660864063452520393449074257299548484465430015820791698616022469211
Short name T750
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.04 seconds
Started Oct 18 12:31:25 PM PDT 23
Finished Oct 18 12:31:30 PM PDT 23
Peak memory 200984 kb
Host smart-bc8bda52-ee27-4ae6-b11d-2702c1419dc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22363099418660864063452520393449074257299548484465430015820791698616022469211 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.22363099418660864063452520393449074257299548484465430015820791698616022469211
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.103827700010064955556383020511616435113374811122893943487170594927959573270069
Short name T698
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 18 12:32:17 PM PDT 23
Finished Oct 18 12:32:22 PM PDT 23
Peak memory 201124 kb
Host smart-f239cb85-9fde-4ebf-8b6f-3ae2d44a9ddc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103827700010064955556383020511616435113374811122893943487170594927959573270069 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.103827700010064955556383020511616435113374811122893943487170594927959573270069
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.11651500643209155707187119880898290666762502802630503089466737800771128286396
Short name T774
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.21 seconds
Started Oct 18 12:31:30 PM PDT 23
Finished Oct 18 12:31:54 PM PDT 23
Peak memory 201136 kb
Host smart-2360aab9-a957-4f7c-8b78-c5f98d51050a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11651500643209155707187119880898290666762502802630503089466737800771128286396
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.116515006432091557071871198808982906667625028
02630503089466737800771128286396
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.50275308693008171096711241559071478549340263772740943052881147382602083949514
Short name T776
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.54 seconds
Started Oct 18 12:31:32 PM PDT 23
Finished Oct 18 12:31:38 PM PDT 23
Peak memory 201132 kb
Host smart-93abd2fe-7406-4fb8-a285-d5f62cd30f7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50275308693008171096711241559071478549340263772740943052881147382602083949514 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.50275308693008171096711241559071478549340263772740943052881147382602083949514
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.25901403771669428229467755569820389807701156585192008788013875623069960079638
Short name T752
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.11 seconds
Started Oct 18 12:31:35 PM PDT 23
Finished Oct 18 12:32:49 PM PDT 23
Peak memory 201112 kb
Host smart-3c9ba90e-4121-45f3-8aba-4c7dc5f90897
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25901403771669428229467755569820389807701156585192008788013875623069960079638 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.259014037716694282294677555698203898077011565851920087880138756
23069960079638
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.43397225374974161775339815126005710663368233481106172716261627311990476749949
Short name T597
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:46:56 PM PDT 23
Finished Oct 18 12:47:00 PM PDT 23
Peak memory 201208 kb
Host smart-286779bd-39e0-46a6-8247-4cf01ba29087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43397225374974161775339815126005710663368233481106172716261627311990476749949 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.43397225374974161775339815126005710663368233481106172716261627311990476749949
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.108829575749142535090256210937063123107652336797438127897032996946816387107098
Short name T104
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 18 12:46:54 PM PDT 23
Finished Oct 18 12:47:00 PM PDT 23
Peak memory 201316 kb
Host smart-37a01b4a-59e8-4149-abac-b525352564a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108829575749142535090256210937063123107652336797438127897032996946816387107098 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.108829575749142535090256210937063123107652336797438127897032996946816387107098
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.71063353001041415056055114077248134044791730140339778644579760642085344838512
Short name T623
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.53 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:49:59 PM PDT 23
Peak memory 201460 kb
Host smart-bf07cbf1-93ee-492c-b86c-4bb6c82246f8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71063353001041415056055114077248134044791730140339778644579760642085344838512 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.710633530010414150560551140772481340447917301403397786445797606
42085344838512
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.49446444930690331851411089176060784518005002546771740660640209379845327081869
Short name T34
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.62 seconds
Started Oct 18 12:46:52 PM PDT 23
Finished Oct 18 12:46:57 PM PDT 23
Peak memory 201224 kb
Host smart-0e7c5e9f-7f25-4c88-88d9-524dd156c345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49446444930690331851411089176060784518005002546771740660640209379845327081869 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.49446444930690331851411089176060784518005002546771740
660640209379845327081869
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.110407860208137479098136663221818727067964506163170349003922460058147512475142
Short name T208
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.52 seconds
Started Oct 18 12:46:55 PM PDT 23
Finished Oct 18 12:47:03 PM PDT 23
Peak memory 201172 kb
Host smart-1fd79c66-61ad-4b4c-afdb-c875be3d982c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110407860208137479098136663221818727067964506163170349003922460058147512475142 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.110407860208137479098136663221818727067964506163170349003922
460058147512475142
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.35434897560089924908628863185049485651072534336958097103749135860804206570510
Short name T615
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:07 PM PDT 23
Peak memory 201104 kb
Host smart-3dfcafc1-314c-416e-9b73-982eeaba0813
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35434897560089924908628863185049485651072534336958097103749135860804206570510 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.35434897560089924908628863185049485651072534336958097103749135860804206570510
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.72056643567833667142237431312253436685843427545477434342409097087957322997216
Short name T534
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:09 PM PDT 23
Peak memory 201156 kb
Host smart-1bef8701-2cb0-49a8-9308-53dbd2881e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72056643567833667142237431312253436685843427545477434342409097087957322997216 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.72056643567833667142237431312253436685843427545477434342409097087957322997216
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.101428404229292688877146259138876631910572991404388577161943725682326347463192
Short name T642
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 18 12:46:59 PM PDT 23
Finished Oct 18 12:47:04 PM PDT 23
Peak memory 201244 kb
Host smart-2add9c50-fb3b-4dae-8d89-d5c2826feccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101428404229292688877146259138876631910572991404388577161943725682326347463192 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.101428404229292688877146259138876631910572991404388577161943725682326347463192
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.54126555194739194198090037097909567936420898002590261437716337521625458624294
Short name T459
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Oct 18 12:47:03 PM PDT 23
Finished Oct 18 12:47:18 PM PDT 23
Peak memory 201308 kb
Host smart-51fd57ab-5652-4f20-a94f-a7c4e29b7028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54126555194739194198090037097909567936420898002590261437716337521625458624294 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.54126555194739194198090037097909567936420898002590261437716337521625458624294
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.87901758778156728138033860810044717335203596028044013236488833522095480670862
Short name T140
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.98 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:48:03 PM PDT 23
Peak memory 221528 kb
Host smart-b12b6468-3c29-4845-86a2-ff3d6d7c036f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87901758778156728138033860810044717335203596028044013236488833522095480670862 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.87901758778156728138033860810044717335203596028044013236488833522095480670862
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.39233199439029410652110206380497622845825416058495981809175387676763078504063
Short name T221
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201044 kb
Host smart-221db1f5-53c1-4d2c-b45d-cd9e535732cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39233199439029410652110206380497622845825416058495981809175387676763078504063 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_smoke.39233199439029410652110206380497622845825416058495981809175387676763078504063
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.110844753063003875875325617466399581256392323073824673008561286497245085540165
Short name T125
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.76 seconds
Started Oct 18 12:46:49 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201520 kb
Host smart-bb630262-60a9-4197-a18c-608f50b32fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110844753063003875875325617466399581256392323073824673008561286497245085540165 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.110844753063003875875325617466399581256392323073824673008561286497245085540165
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.70356836917498648065722231465958532505086036403184961244192992487411659301366
Short name T350
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.8 seconds
Started Oct 18 12:46:53 PM PDT 23
Finished Oct 18 12:46:58 PM PDT 23
Peak memory 201132 kb
Host smart-b44d8529-ba55-4628-99e6-f3157ec50b77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70356836917498648065722231465958532505086036403184961244192992487411659301366 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.7035683691749864806572223146595853250508603640318496124419299
2487411659301366
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.80853691969245972926791959837434529917717059441718165793450475009891997049082
Short name T518
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:01 PM PDT 23
Peak memory 201240 kb
Host smart-37c45eca-7dd6-403c-af8c-e58d9276cc03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80853691969245972926791959837434529917717059441718165793450475009891997049082 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.80853691969245972926791959837434529917717059441718165793450475009891997049082
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.15013107754362267511152930503758477628804628539994656508159626450277041619774
Short name T334
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 18 12:46:56 PM PDT 23
Finished Oct 18 12:47:02 PM PDT 23
Peak memory 201276 kb
Host smart-bd9492e7-c636-4d49-9c14-7dc0fb784861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15013107754362267511152930503758477628804628539994656508159626450277041619774 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.15013107754362267511152930503758477628804628539994656508159626450277041619774
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.10571363132982009590252169468746445083439058825580721790054420156286269418192
Short name T467
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.93 seconds
Started Oct 18 12:46:53 PM PDT 23
Finished Oct 18 12:49:56 PM PDT 23
Peak memory 201480 kb
Host smart-bfea6c16-6097-4865-832e-7d730323d7b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10571363132982009590252169468746445083439058825580721790054420156286269418192 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.105713631329820095902521694687464450834390588255807217900544201
56286269418192
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.106672137860561547549848042523303103937933911121424220907367393609509791921533
Short name T29
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.24 seconds
Started Oct 18 12:46:52 PM PDT 23
Finished Oct 18 12:46:56 PM PDT 23
Peak memory 201244 kb
Host smart-93ca4dbe-ca2e-42b6-bbfb-cfd3838992c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106672137860561547549848042523303103937933911121424220907367393609509791921533 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.106672137860561547549848042523303103937933911121424220907367393609509791921533
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.88798668357667974914858364199435844675208110962638654220657822497513070718710
Short name T28
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.42 seconds
Started Oct 18 12:46:51 PM PDT 23
Finished Oct 18 12:46:56 PM PDT 23
Peak memory 201220 kb
Host smart-047c66f7-e4e3-42a8-83f4-4b30cbdb1332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88798668357667974914858364199435844675208110962638654220657822497513070718710 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.88798668357667974914858364199435844675208110962638654
220657822497513070718710
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.111023543004780614731398454108282352049419798603075526837111980358545993141693
Short name T319
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201164 kb
Host smart-ccfa5d63-f082-47da-acfd-c89e3eb2b0e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111023543004780614731398454108282352049419798603075526837111980358545993141693 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.111023543004780614731398454108282352049419798603075526837111
980358545993141693
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.55490233549112705995909477446322034992757992377518032194884435801599830801625
Short name T600
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 18 12:46:51 PM PDT 23
Finished Oct 18 12:46:58 PM PDT 23
Peak memory 201232 kb
Host smart-44d69af5-c0fc-4f28-9d2e-a260964b6804
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55490233549112705995909477446322034992757992377518032194884435801599830801625 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.55490233549112705995909477446322034992757992377518032194884435801599830801625
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.61181511161247725241044377585687296062806425532326094282198783955923531724681
Short name T96
Test name
Test status
Simulation time 38606274248 ps
CPU time 59.69 seconds
Started Oct 18 12:46:51 PM PDT 23
Finished Oct 18 12:47:51 PM PDT 23
Peak memory 201252 kb
Host smart-79f73597-9a75-4737-8ac6-5a18afc212c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61181511161247725241044377585687296062806425532326094282198783955923531724681 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.61181511161247725241044377585687296062806425532326094282198783955923531724681
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.54914490212899061013854153372318877182789080637463116045874918128466046694607
Short name T276
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201148 kb
Host smart-a24e2c38-70e7-46e6-8bbd-128df6eb9259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54914490212899061013854153372318877182789080637463116045874918128466046694607 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.54914490212899061013854153372318877182789080637463116045874918128466046694607
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.75594304722259339214265204543539426779281217875635030621136066182518554907909
Short name T421
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Oct 18 12:46:56 PM PDT 23
Finished Oct 18 12:47:01 PM PDT 23
Peak memory 201284 kb
Host smart-9f74f8d6-436c-4edd-a83c-8b9a3a4829fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75594304722259339214265204543539426779281217875635030621136066182518554907909 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.75594304722259339214265204543539426779281217875635030621136066182518554907909
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.52769132570785629905687873994926717427454473110759539954799127043823065661751
Short name T401
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 18 12:47:11 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201168 kb
Host smart-23477c49-91a1-4018-ad5d-2de71615e40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52769132570785629905687873994926717427454473110759539954799127043823065661751 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.52769132570785629905687873994926717427454473110759539954799127043823065661751
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.57869191632462190539032654248851377491446061515718098999811241563796682577624
Short name T321
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Oct 18 12:46:39 PM PDT 23
Finished Oct 18 12:46:44 PM PDT 23
Peak memory 201148 kb
Host smart-d9640f53-4faa-4e95-a2fd-d30968138cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57869191632462190539032654248851377491446061515718098999811241563796682577624 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.57869191632462190539032654248851377491446061515718098999811241563796682577624
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.28387099242944645414545862753978836991604751520922519350153022127295197822191
Short name T136
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.06 seconds
Started Oct 18 12:46:47 PM PDT 23
Finished Oct 18 12:47:53 PM PDT 23
Peak memory 221636 kb
Host smart-2d32d773-2760-4131-b0a6-34892cd9ccc5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28387099242944645414545862753978836991604751520922519350153022127295197822191 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.28387099242944645414545862753978836991604751520922519350153022127295197822191
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.30204685544865417531173240869299690200859702149431202596964497219115786362827
Short name T541
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201024 kb
Host smart-f71f243c-5169-443d-a784-a5393788717a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30204685544865417531173240869299690200859702149431202596964497219115786362827 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_smoke.30204685544865417531173240869299690200859702149431202596964497219115786362827
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.61102988573200675575345098725057593465985386928625717845109055822042930318529
Short name T405
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:06 PM PDT 23
Peak memory 201212 kb
Host smart-4a65c899-51ec-4220-bfd1-979b9b1851dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61102988573200675575345098725057593465985386928625717845109055822042930318529 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.6110298857320067557534509872505759346598538692862571784510905
5822042930318529
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.35185786252732890850459460105731659218118434990653529777894173567168988720761
Short name T614
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201148 kb
Host smart-4aa1c61a-88a9-4930-a877-23304a4b29c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185786252732890850459460105731659218118434990653529777894173567168988720761 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.35185786252732890850459460105731659218118434990653529777894173567168988720761
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.104824010384528738066245533177152423946837374615627985819031153863819166861694
Short name T486
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 18 12:48:09 PM PDT 23
Finished Oct 18 12:48:15 PM PDT 23
Peak memory 201280 kb
Host smart-86e8f381-a250-4917-8a41-233be0d9aa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104824010384528738066245533177152423946837374615627985819031153863819166861694 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.104824010384528738066245533177152423946837374615627985819031153863819166861694
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.40475599210806779327435871596539532027359452698939298700966665240069512692698
Short name T157
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.13 seconds
Started Oct 18 12:47:55 PM PDT 23
Finished Oct 18 12:50:57 PM PDT 23
Peak memory 201364 kb
Host smart-ee2e4d14-2314-4abf-bcf3-2de1f8086396
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40475599210806779327435871596539532027359452698939298700966665240069512692698 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.40475599210806779327435871596539532027359452698939298700966665
240069512692698
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.111515699890245114951694486288300174582464241693415937409794382465362311939690
Short name T376
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.49 seconds
Started Oct 18 12:48:16 PM PDT 23
Finished Oct 18 12:48:24 PM PDT 23
Peak memory 201244 kb
Host smart-ca8c195c-07af-461b-991e-9e1343f1925d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111515699890245114951694486288300174582464241693415937409794382465362311939690 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.11151569989024511495169448628830017458246424169341593740979
4382465362311939690
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.64467621822143508182684891745783208683875675275678144433750955061292659961911
Short name T608
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:48:19 PM PDT 23
Peak memory 201104 kb
Host smart-344ab120-47e3-4942-8278-4de7f064453a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64467621822143508182684891745783208683875675275678144433750955061292659961911 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.6446762182214350818268489174578320868387567527567814443375095506
1292659961911
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.10253013700885697315757166676208301188665668712059198505064629693691195167703
Short name T298
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Oct 18 12:47:52 PM PDT 23
Finished Oct 18 12:47:57 PM PDT 23
Peak memory 201224 kb
Host smart-dd2430fe-2e72-47e0-b642-87cbda769d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10253013700885697315757166676208301188665668712059198505064629693691195167703 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.10253013700885697315757166676208301188665668712059198505064629693691195167703
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.69303069596513779087225171954919289955442403020694598219511008957149499570372
Short name T195
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:10 PM PDT 23
Peak memory 201228 kb
Host smart-3e62daf1-7418-4136-96d4-65d5016d05ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69303069596513779087225171954919289955442403020694598219511008957149499570372 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.69303069596513779087225171954919289955442403020694598219511008957149499570372
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.8026790309622121079484570723768586816563607665246154245025424078595972978603
Short name T587
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.89 seconds
Started Oct 18 12:47:56 PM PDT 23
Finished Oct 18 12:48:00 PM PDT 23
Peak memory 201184 kb
Host smart-54120fad-cf9e-4c49-bfe4-eca0700be4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8026790309622121079484570723768586816563607665246154245025424078595972978603 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.8026790309622121079484570723768586816563607665246154245025424078595972978603
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.86375462590523615681878806368179661774702550200104706253048280123871379787570
Short name T202
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:05 PM PDT 23
Peak memory 201156 kb
Host smart-66a5014e-854d-4d38-90f9-86d6d0afac48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86375462590523615681878806368179661774702550200104706253048280123871379787570 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.86375462590523615681878806368179661774702550200104706253048280123871379787570
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.98089589536941880259427752268897151031558169594403701606242520167831704118152
Short name T551
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201172 kb
Host smart-4d8d5701-15a1-4707-b6e0-8002415d6e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98089589536941880259427752268897151031558169594403701606242520167831704118152 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_smoke.98089589536941880259427752268897151031558169594403701606242520167831704118152
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.54369781112711096820841128924004576584744261510916517716287670895943666427120
Short name T227
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.42 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:50:25 PM PDT 23
Peak memory 201516 kb
Host smart-fa545c64-ecd7-4a84-9157-9aebc4cad1b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54369781112711096820841128924004576584744261510916517716287670895943666427120 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.54369781112711096820841128924004576584744261510916517716287670895943666427120
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.105177202205466550985832806275969506031657261112577895796561284145689488948480
Short name T567
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 18 12:48:01 PM PDT 23
Finished Oct 18 12:48:06 PM PDT 23
Peak memory 201128 kb
Host smart-96a33d4d-f363-4400-acf5-bb5e91d8f058
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105177202205466550985832806275969506031657261112577895796561284145689488948480 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.10517720220546655098583280627596950603165726111257789579656
1284145689488948480
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.9819675804449306826678861379140144112374802264302413695539943322641175383407
Short name T239
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201252 kb
Host smart-50961439-c91d-46d2-91c3-a7aba8bf11f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9819675804449306826678861379140144112374802264302413695539943322641175383407 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.9819675804449306826678861379140144112374802264302413695539943322641175383407
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.6525828188650563608633690599193694080216925854508434796440183354805082009744
Short name T307
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.69 seconds
Started Oct 18 12:47:43 PM PDT 23
Finished Oct 18 12:47:49 PM PDT 23
Peak memory 201208 kb
Host smart-09ede659-7e59-4604-95cc-66a5dc1ec5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6525828188650563608633690599193694080216925854508434796440183354805082009744 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.6525828188650563608633690599193694080216925854508434796440183354805082009744
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.70449398458270602379263402494219925925433274474386676450099476157371399386910
Short name T457
Test name
Test status
Simulation time 118289458206 ps
CPU time 182 seconds
Started Oct 18 12:48:03 PM PDT 23
Finished Oct 18 12:51:06 PM PDT 23
Peak memory 201472 kb
Host smart-b6ad4de0-4286-4dcd-a3b8-6bff30b924a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70449398458270602379263402494219925925433274474386676450099476157371399386910 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.70449398458270602379263402494219925925433274474386676450099476
157371399386910
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.93751076396419318859136201625602095131567070487294319933092482877257949545926
Short name T504
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 18 12:48:09 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201172 kb
Host smart-b7324222-f7cc-4750-b1a7-d9d72c1f74b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93751076396419318859136201625602095131567070487294319933092482877257949545926 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.937510763964193188591362016256020951315670704872943199330924
82877257949545926
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.104242540042013398735135954657436687823704820900687323273882901790619819821721
Short name T574
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 18 12:47:57 PM PDT 23
Finished Oct 18 12:48:04 PM PDT 23
Peak memory 201156 kb
Host smart-71edd888-55ea-459b-a14a-3310d529c58b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104242540042013398735135954657436687823704820900687323273882901790619819821721 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.104242540042013398735135954657436687823704820900687323273882901
790619819821721
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.115196112385563533488497467270706426288939725449966825253608799352979424263238
Short name T358
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 18 12:48:03 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201208 kb
Host smart-e25cf0a5-3192-492a-afd2-782bd725ac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115196112385563533488497467270706426288939725449966825253608799352979424263238 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.115196112385563533488497467270706426288939725449966825253608799352979424263238
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.20091788459329680653645918413235781274398310082608642194583899783809586971081
Short name T543
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Oct 18 12:47:55 PM PDT 23
Finished Oct 18 12:48:00 PM PDT 23
Peak memory 201208 kb
Host smart-45fe263f-39de-4464-b554-efafd77c4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20091788459329680653645918413235781274398310082608642194583899783809586971081 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.20091788459329680653645918413235781274398310082608642194583899783809586971081
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.95832553066521912354090344604823535301643094110452477708386614987046280089075
Short name T451
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 18 12:48:13 PM PDT 23
Finished Oct 18 12:48:17 PM PDT 23
Peak memory 201180 kb
Host smart-af3784c9-5050-4ed9-b5d9-1616d7e7512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95832553066521912354090344604823535301643094110452477708386614987046280089075 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.95832553066521912354090344604823535301643094110452477708386614987046280089075
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.95143717255489708453320902179249678342385643366949864583230873603601476875475
Short name T491
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 18 12:48:05 PM PDT 23
Finished Oct 18 12:48:10 PM PDT 23
Peak memory 201208 kb
Host smart-ecc61e9e-54c6-4530-811d-419adbd7c613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95143717255489708453320902179249678342385643366949864583230873603601476875475 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.95143717255489708453320902179249678342385643366949864583230873603601476875475
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.97474749064253704384863784915083973617503487635582439807163532713192024955021
Short name T501
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201228 kb
Host smart-7d508800-faa3-4b11-842c-07d53b96d4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97474749064253704384863784915083973617503487635582439807163532713192024955021 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_smoke.97474749064253704384863784915083973617503487635582439807163532713192024955021
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.83329819984434473813023158033571544560980105558014039938786732674519184774083
Short name T127
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.94 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:50:28 PM PDT 23
Peak memory 201424 kb
Host smart-642c13bd-d8aa-4116-bcf7-f366a2f3cbe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83329819984434473813023158033571544560980105558014039938786732674519184774083 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.83329819984434473813023158033571544560980105558014039938786732674519184774083
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.37541508740516106201503624027192482550842495251557543879562045721451523620055
Short name T561
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Oct 18 12:48:01 PM PDT 23
Finished Oct 18 12:48:06 PM PDT 23
Peak memory 201180 kb
Host smart-34849e2c-4fda-4b6e-b558-6049bcdb429a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541508740516106201503624027192482550842495251557543879562045721451523620055 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.375415087405161062015036240271924825508424952515575438795620
45721451523620055
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.5877731774612986266824721515647417431196915429297797882685577123757725491923
Short name T411
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:04 PM PDT 23
Peak memory 201136 kb
Host smart-36be653b-4ce1-44dd-bb03-03eb7ec93e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5877731774612986266824721515647417431196915429297797882685577123757725491923 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.5877731774612986266824721515647417431196915429297797882685577123757725491923
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.26025778624811224343306425929399533769628046304042546763885938215621161055870
Short name T322
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Oct 18 12:47:50 PM PDT 23
Finished Oct 18 12:47:56 PM PDT 23
Peak memory 201288 kb
Host smart-140ac616-52f4-43ff-a0e9-6db6dec523d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26025778624811224343306425929399533769628046304042546763885938215621161055870 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.26025778624811224343306425929399533769628046304042546763885938215621161055870
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.97996563959056067375168802157093372377124896329523761124405779765916291199871
Short name T624
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.94 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:51:14 PM PDT 23
Peak memory 201376 kb
Host smart-63aa2461-b2a1-42c9-975f-c7100953a4e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97996563959056067375168802157093372377124896329523761124405779765916291199871 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.97996563959056067375168802157093372377124896329523761124405779
765916291199871
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.84627382255838173779997186669354725866095377507962571431051783674029553564683
Short name T563
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201168 kb
Host smart-462b43be-7dab-474c-a147-4adb110c0733
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84627382255838173779997186669354725866095377507962571431051783674029553564683 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.846273822558381737799971866693547258660953775079625714310517
83674029553564683
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.48932566746618778819079850282476747249368451548252084623505359911539992401899
Short name T625
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 18 12:47:59 PM PDT 23
Finished Oct 18 12:48:04 PM PDT 23
Peak memory 201244 kb
Host smart-23915bdc-1749-4d29-b674-fa6e5fd6a34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48932566746618778819079850282476747249368451548252084623505359911539992401899 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.48932566746618778819079850282476747249368451548252084623505359911539992401899
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.81837947365277789787837792816476397143259234737163386364946562100981207514861
Short name T378
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Oct 18 12:47:54 PM PDT 23
Finished Oct 18 12:47:59 PM PDT 23
Peak memory 201252 kb
Host smart-4403d3c2-6865-4119-a8f5-da71565a20ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81837947365277789787837792816476397143259234737163386364946562100981207514861 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.81837947365277789787837792816476397143259234737163386364946562100981207514861
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.38865573334304203498646583812310241474440597292565653722336427323412974078282
Short name T260
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 201160 kb
Host smart-fc196ad7-d387-4068-953a-dbaed56b49f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38865573334304203498646583812310241474440597292565653722336427323412974078282 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.38865573334304203498646583812310241474440597292565653722336427323412974078282
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.99443385606546292395949446858092848344484847523034816231224309995160115429747
Short name T422
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 18 12:47:58 PM PDT 23
Finished Oct 18 12:48:03 PM PDT 23
Peak memory 201124 kb
Host smart-515a3b5d-f4c7-4e25-a6e6-a590f4f372d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99443385606546292395949446858092848344484847523034816231224309995160115429747 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.99443385606546292395949446858092848344484847523034816231224309995160115429747
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.9063902747701165977539324214800612801387140435066087795771521394790568175390
Short name T496
Test name
Test status
Simulation time 2116887594 ps
CPU time 4.06 seconds
Started Oct 18 12:47:47 PM PDT 23
Finished Oct 18 12:47:52 PM PDT 23
Peak memory 201156 kb
Host smart-d89097d0-3d74-45c6-9ea6-2667b4817dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9063902747701165977539324214800612801387140435066087795771521394790568175390 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sysrst_ctrl_smoke.9063902747701165977539324214800612801387140435066087795771521394790568175390
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.94307120304977969273447586371667247522860662456871531337499306330734572513281
Short name T621
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.79 seconds
Started Oct 18 12:48:01 PM PDT 23
Finished Oct 18 12:50:15 PM PDT 23
Peak memory 201520 kb
Host smart-6bdc2c61-490e-4021-ab01-bdeb2d716bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94307120304977969273447586371667247522860662456871531337499306330734572513281 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.94307120304977969273447586371667247522860662456871531337499306330734572513281
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.50205747440828589756653577761758069499763874349092432689331755009120088677105
Short name T665
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 18 12:47:49 PM PDT 23
Finished Oct 18 12:47:55 PM PDT 23
Peak memory 201180 kb
Host smart-60a55d9c-6f17-458b-9d4b-e2a0226698ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50205747440828589756653577761758069499763874349092432689331755009120088677105 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.502057474408285897566535777617580694997638743490924326893317
55009120088677105
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.25889080550900989887289117468567558846808286702820576182268202146009758414107
Short name T210
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 18 12:48:02 PM PDT 23
Finished Oct 18 12:48:06 PM PDT 23
Peak memory 201224 kb
Host smart-156b2eb9-df88-46d2-8258-f21db1f71374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889080550900989887289117468567558846808286702820576182268202146009758414107 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.25889080550900989887289117468567558846808286702820576182268202146009758414107
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.81744979488672225358470921356380391470782078545673594164688570534206806338321
Short name T189
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.38 seconds
Started Oct 18 12:48:03 PM PDT 23
Finished Oct 18 12:48:09 PM PDT 23
Peak memory 201200 kb
Host smart-f1d4e576-c4f3-443d-98ef-ab2efd59e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81744979488672225358470921356380391470782078545673594164688570534206806338321 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.81744979488672225358470921356380391470782078545673594164688570534206806338321
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.19737896987605589053699896257408362582634131831710393139856164766752959830517
Short name T628
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.02 seconds
Started Oct 18 12:48:13 PM PDT 23
Finished Oct 18 12:51:17 PM PDT 23
Peak memory 201452 kb
Host smart-54f994c0-e1a5-4a49-8ae2-f4a4540e1bb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19737896987605589053699896257408362582634131831710393139856164766752959830517 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.19737896987605589053699896257408362582634131831710393139856164
766752959830517
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.103259377942051713639127008949251224049311050470220549672985401616211652977534
Short name T352
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Oct 18 12:48:28 PM PDT 23
Finished Oct 18 12:48:36 PM PDT 23
Peak memory 201240 kb
Host smart-786a18aa-e54b-4266-8005-38e9ece884e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103259377942051713639127008949251224049311050470220549672985401616211652977534 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.10325937794205171363912700894925122404931105047022054967298
5401616211652977534
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.94574873524816973951959611055386840531907893677087921845123421781104390133968
Short name T340
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 18 12:48:14 PM PDT 23
Finished Oct 18 12:48:21 PM PDT 23
Peak memory 201232 kb
Host smart-f811f4dc-42f5-446e-b91f-8315b4f0b660
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94574873524816973951959611055386840531907893677087921845123421781104390133968 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.9457487352481697395195961105538684053190789367708792184512342178
1104390133968
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.111042610128963424617245661356364409888955199051730734074104235678442344853332
Short name T618
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:48:25 PM PDT 23
Peak memory 201132 kb
Host smart-fcdf61f2-ebde-48c7-86f0-e25c9e3cf412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111042610128963424617245661356364409888955199051730734074104235678442344853332 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.111042610128963424617245661356364409888955199051730734074104235678442344853332
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.31917838041090467051497114170690754331190696361725505116461865422579347651204
Short name T351
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Oct 18 12:48:01 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201236 kb
Host smart-28c5832a-6f2c-4094-a286-f3650597a689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31917838041090467051497114170690754331190696361725505116461865422579347651204 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.31917838041090467051497114170690754331190696361725505116461865422579347651204
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.89593906043773480619017516799770815537246976330410289141990960465394691602749
Short name T463
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Oct 18 12:47:55 PM PDT 23
Finished Oct 18 12:48:00 PM PDT 23
Peak memory 201184 kb
Host smart-10c9ed7e-8da9-4ae2-a398-f6b90ca1e076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89593906043773480619017516799770815537246976330410289141990960465394691602749 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.89593906043773480619017516799770815537246976330410289141990960465394691602749
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.65113301059739278010629842459630230414898433565292663930840388806648565640079
Short name T671
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:48:25 PM PDT 23
Peak memory 201244 kb
Host smart-547d383a-c450-4937-9016-791538577d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65113301059739278010629842459630230414898433565292663930840388806648565640079 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.65113301059739278010629842459630230414898433565292663930840388806648565640079
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.7017369852342841964319673265602913951695338249686159645144404785939368120395
Short name T199
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 18 12:47:53 PM PDT 23
Finished Oct 18 12:47:57 PM PDT 23
Peak memory 201168 kb
Host smart-ff64c470-77ba-4aeb-90c8-fe85ed950c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7017369852342841964319673265602913951695338249686159645144404785939368120395 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sysrst_ctrl_smoke.7017369852342841964319673265602913951695338249686159645144404785939368120395
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.37806765455340303481578827588603553971760282194988621147581507282690890199381
Short name T483
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.35 seconds
Started Oct 18 12:48:03 PM PDT 23
Finished Oct 18 12:50:19 PM PDT 23
Peak memory 201504 kb
Host smart-22b1c6c5-2fd3-4714-b081-10b02c6bcc9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37806765455340303481578827588603553971760282194988621147581507282690890199381 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.37806765455340303481578827588603553971760282194988621147581507282690890199381
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.108590167446006390400297996532542289992501176073827098106299371660261001399075
Short name T583
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Oct 18 12:48:16 PM PDT 23
Finished Oct 18 12:48:21 PM PDT 23
Peak memory 201112 kb
Host smart-dbc9143d-b83d-498a-8524-2c6cfca327a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108590167446006390400297996532542289992501176073827098106299371660261001399075 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.10859016744600639040029799653254228999250117607382709810629
9371660261001399075
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.110986910442832449316951037457720612893808534601220413070720525426538677085849
Short name T629
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201220 kb
Host smart-3018bff3-95b7-4246-9c08-6f3048816951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110986910442832449316951037457720612893808534601220413070720525426538677085849 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.110986910442832449316951037457720612893808534601220413070720525426538677085849
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.108338303801626572716352715015856387922094720117373748145464736956701728960590
Short name T269
Test name
Test status
Simulation time 118289458206 ps
CPU time 181 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:51:05 PM PDT 23
Peak memory 201488 kb
Host smart-bd1d8381-62e5-4276-b2db-ee02a53a9284
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108338303801626572716352715015856387922094720117373748145464736956701728960590 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.1083383038016265727163527150158563879220947201173737481454647
36956701728960590
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.74392943253742285243299372401115444847322674615394771248656714556539905845253
Short name T400
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:31 PM PDT 23
Peak memory 201164 kb
Host smart-14f48eff-3daf-403a-9d6b-82f1ce7c8977
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74392943253742285243299372401115444847322674615394771248656714556539905845253 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.743929432537422852432993724011154448473226746153947712486567
14556539905845253
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.48041423338310102867622020983748252505027816994462142783513836541570476140446
Short name T132
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Oct 18 12:48:21 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201196 kb
Host smart-a172af1f-5497-47b5-9d31-5786430ca40b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48041423338310102867622020983748252505027816994462142783513836541570476140446 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.4804142333831010286762202098374825250502781699446214278351383654
1570476140446
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.108012891346503997794122277333751704755095150414840582072438553790584114136902
Short name T438
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 18 12:48:25 PM PDT 23
Finished Oct 18 12:48:30 PM PDT 23
Peak memory 201148 kb
Host smart-994bb77b-1a15-4d85-94ff-8cc9b33225cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108012891346503997794122277333751704755095150414840582072438553790584114136902 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.108012891346503997794122277333751704755095150414840582072438553790584114136902
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.22627125595121888984569184824312711184831744773555977986300413804341501456903
Short name T398
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 18 12:48:02 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201256 kb
Host smart-f52dc09f-482b-4080-98db-15a54d3041a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22627125595121888984569184824312711184831744773555977986300413804341501456903 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.22627125595121888984569184824312711184831744773555977986300413804341501456903
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.44704492365810343933092238969594820631181058100578594352812835389672609901078
Short name T667
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:48:17 PM PDT 23
Peak memory 201152 kb
Host smart-7743ce08-dcbf-4dad-9a58-3b0dab491f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44704492365810343933092238969594820631181058100578594352812835389672609901078 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.44704492365810343933092238969594820631181058100578594352812835389672609901078
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.62853866255426296301706396885193150317443240095526885651917560285915017882006
Short name T475
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 18 12:48:17 PM PDT 23
Finished Oct 18 12:48:22 PM PDT 23
Peak memory 201180 kb
Host smart-c7c9f781-e108-42d3-9e62-ae335f789409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62853866255426296301706396885193150317443240095526885651917560285915017882006 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.62853866255426296301706396885193150317443240095526885651917560285915017882006
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.17809266737768464873233996039496300935610116853227466342888248172107619223527
Short name T150
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:37 PM PDT 23
Peak memory 201104 kb
Host smart-f8086ca8-95da-4f8a-8011-dc7a7d0f37e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17809266737768464873233996039496300935610116853227466342888248172107619223527 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sysrst_ctrl_smoke.17809266737768464873233996039496300935610116853227466342888248172107619223527
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.35469511015481063095470951146414852187994100154058867809317939382126306355274
Short name T25
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.64 seconds
Started Oct 18 12:48:42 PM PDT 23
Finished Oct 18 12:50:57 PM PDT 23
Peak memory 201484 kb
Host smart-d93baef4-e3d5-43bd-9e12-66082bd809cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35469511015481063095470951146414852187994100154058867809317939382126306355274 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.35469511015481063095470951146414852187994100154058867809317939382126306355274
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.61255630605007410525655380648461512880990995757177270175895797133497220785237
Short name T577
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:48:25 PM PDT 23
Peak memory 201104 kb
Host smart-d514fb75-33e3-4708-a61c-926ef01af61f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61255630605007410525655380648461512880990995757177270175895797133497220785237 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.612556306050074105256553806484615128809909957571772701758957
97133497220785237
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.53160672414924256401609104899201053973822561104400200468973990168223395070705
Short name T382
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:47:58 PM PDT 23
Finished Oct 18 12:48:01 PM PDT 23
Peak memory 201180 kb
Host smart-b16c3903-5c4c-4906-9d6c-4641a779eaa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53160672414924256401609104899201053973822561104400200468973990168223395070705 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.53160672414924256401609104899201053973822561104400200468973990168223395070705
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.5895863024010324916139871267036108242461851763077980614092269074956984016560
Short name T635
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 18 12:48:11 PM PDT 23
Finished Oct 18 12:48:17 PM PDT 23
Peak memory 201292 kb
Host smart-b10d4b01-6e9c-4655-8257-a955709d8e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5895863024010324916139871267036108242461851763077980614092269074956984016560 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.5895863024010324916139871267036108242461851763077980614092269074956984016560
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.9198097530404181697507960701536869760769851075521843521469843691171611979666
Short name T473
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.53 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:51:15 PM PDT 23
Peak memory 201448 kb
Host smart-c35fd95c-ba9b-4d5f-a7f8-b46f0fcfc340
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9198097530404181697507960701536869760769851075521843521469843691171611979666 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.919809753040418169750796070153686976076985107552184352146984369
1171611979666
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.90801153229263602017989689130709299894549552750635806216369289556311647834475
Short name T337
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:06 PM PDT 23
Peak memory 201196 kb
Host smart-eb76ba8c-7c93-43ab-a2df-3a4576fb1835
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90801153229263602017989689130709299894549552750635806216369289556311647834475 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.9080115322926360201798968913070929989454955275063580621636928955
6311647834475
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.49344720750358651552550815419864516787949541586655517275797101011867055825315
Short name T116
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 18 12:48:06 PM PDT 23
Finished Oct 18 12:48:22 PM PDT 23
Peak memory 201208 kb
Host smart-f98a1efa-6e16-482c-aedf-938584768976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49344720750358651552550815419864516787949541586655517275797101011867055825315 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.49344720750358651552550815419864516787949541586655517275797101011867055825315
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.108829471139330708317248086341061449795847667309850644341126547161515271898577
Short name T317
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:09 PM PDT 23
Peak memory 201084 kb
Host smart-9ef373c8-2672-46c3-aba9-269e24e20405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108829471139330708317248086341061449795847667309850644341126547161515271898577 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.108829471139330708317248086341061449795847667309850644341126547161515271898577
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.39546176013849755638315268997110036987199713611423874230165857844989322302066
Short name T391
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201152 kb
Host smart-84c71995-9df0-4b78-899d-b43992b927b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39546176013849755638315268997110036987199713611423874230165857844989322302066 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.39546176013849755638315268997110036987199713611423874230165857844989322302066
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.36511293091783923118006332996194819921525394339439001715932027457892861313191
Short name T359
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.5 seconds
Started Oct 18 12:48:13 PM PDT 23
Finished Oct 18 12:48:18 PM PDT 23
Peak memory 201252 kb
Host smart-f64e5d0a-6a3b-42e0-acd9-58f3a573f199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36511293091783923118006332996194819921525394339439001715932027457892861313191 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.36511293091783923118006332996194819921525394339439001715932027457892861313191
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.73755945577950243655444656077674639253797249915642645758169100253316279777742
Short name T224
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201060 kb
Host smart-27173b24-efdf-4201-9511-d92f4917df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73755945577950243655444656077674639253797249915642645758169100253316279777742 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sysrst_ctrl_smoke.73755945577950243655444656077674639253797249915642645758169100253316279777742
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.50816106176158824048825159974542553009622490234085874761295087665644538411574
Short name T456
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.67 seconds
Started Oct 18 12:48:07 PM PDT 23
Finished Oct 18 12:50:23 PM PDT 23
Peak memory 201500 kb
Host smart-13d3da14-5e6f-47d9-b4e3-97646e1dc986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50816106176158824048825159974542553009622490234085874761295087665644538411574 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.50816106176158824048825159974542553009622490234085874761295087665644538411574
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.40511698643224247006619947807659993684530625731996631580909780680753813580305
Short name T38
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:05 PM PDT 23
Peak memory 201132 kb
Host smart-e94f684d-8941-4574-895a-93c0caf3d860
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511698643224247006619947807659993684530625731996631580909780680753813580305 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.405116986432242470066199478076599936845306257319966315809097
80680753813580305
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.60146383739010021013101876479265553949954834692969425653514819422279920280272
Short name T402
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:22 PM PDT 23
Peak memory 201240 kb
Host smart-b3cf7cdf-4bab-4958-8fb2-69f2379bfc93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60146383739010021013101876479265553949954834692969425653514819422279920280272 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.60146383739010021013101876479265553949954834692969425653514819422279920280272
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.85252882677175668542341773908772499576328225908447228510463515532415249914472
Short name T612
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.4 seconds
Started Oct 18 12:48:11 PM PDT 23
Finished Oct 18 12:48:17 PM PDT 23
Peak memory 201292 kb
Host smart-cf685c9c-8563-482c-9345-9664a4119e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85252882677175668542341773908772499576328225908447228510463515532415249914472 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.85252882677175668542341773908772499576328225908447228510463515532415249914472
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.93983474608387968962091154780245512373733796781246678923007089969552941585021
Short name T281
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.04 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:51:20 PM PDT 23
Peak memory 201472 kb
Host smart-f90d5510-cc2b-43c9-8c11-be44cd25e5a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93983474608387968962091154780245512373733796781246678923007089969552941585021 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.93983474608387968962091154780245512373733796781246678923007089
969552941585021
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.61115585022658001916141479578957238006489773145880695195170855124410045223169
Short name T643
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.4 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201248 kb
Host smart-8d7e52bc-1ea2-4dda-b0b4-0bfa05d3686a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61115585022658001916141479578957238006489773145880695195170855124410045223169 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.611155850226580019161414795789572380064897731458806951951708
55124410045223169
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.105451215451639779575908933572491428329512111123431800304358924897774773536077
Short name T524
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 18 12:48:10 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201104 kb
Host smart-f0482dea-f5a1-4119-b7f4-0b9bd9b54bd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105451215451639779575908933572491428329512111123431800304358924897774773536077 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.105451215451639779575908933572491428329512111123431800304358924
897774773536077
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.63393972429522026121114756085501672196688367003121304466184719678417968399137
Short name T242
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201244 kb
Host smart-f2200c86-38e6-4195-bb9b-9d71cefd794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63393972429522026121114756085501672196688367003121304466184719678417968399137 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.63393972429522026121114756085501672196688367003121304466184719678417968399137
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.55674910483268163319439379008303948527161152546380934492210789467715120179302
Short name T109
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:48:26 PM PDT 23
Peak memory 201252 kb
Host smart-77c624f1-9c2c-4eb8-8899-012a86ad5297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55674910483268163319439379008303948527161152546380934492210789467715120179302 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.55674910483268163319439379008303948527161152546380934492210789467715120179302
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.114095754086011563892345279297536963269346027548630403507107516717398558446278
Short name T268
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 18 12:48:17 PM PDT 23
Finished Oct 18 12:48:21 PM PDT 23
Peak memory 201116 kb
Host smart-fd7d98ed-257e-45e3-97d3-61a311175726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114095754086011563892345279297536963269346027548630403507107516717398558446278 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.114095754086011563892345279297536963269346027548630403507107516717398558446278
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.50792313207610744125022323257744959875206605275574248158429251415984088353129
Short name T389
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.51 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:48:17 PM PDT 23
Peak memory 201172 kb
Host smart-88cf6dc9-6635-41bb-88b2-cb31a1d35d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50792313207610744125022323257744959875206605275574248158429251415984088353129 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.50792313207610744125022323257744959875206605275574248158429251415984088353129
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.89996900287386025021582805279328793386838190691488240194652322614994892031404
Short name T526
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:48:32 PM PDT 23
Peak memory 201140 kb
Host smart-2fa3dfa1-d023-4f53-88e7-c9055c1642ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89996900287386025021582805279328793386838190691488240194652322614994892031404 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_smoke.89996900287386025021582805279328793386838190691488240194652322614994892031404
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.65130933637055015750294453451505546868816776977645102576399936467342963712710
Short name T403
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.21 seconds
Started Oct 18 12:48:29 PM PDT 23
Finished Oct 18 12:50:45 PM PDT 23
Peak memory 201408 kb
Host smart-0bfdcb43-af84-4748-b304-00a00211d29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65130933637055015750294453451505546868816776977645102576399936467342963712710 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.65130933637055015750294453451505546868816776977645102576399936467342963712710
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.46985851641318455817661089417007278139237207702666950431185413724224378985543
Short name T246
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201104 kb
Host smart-115b679a-4b86-4ceb-bf0c-a100f2867e3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46985851641318455817661089417007278139237207702666950431185413724224378985543 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.469858516413184558176610894170072781392372077026669504311854
13724224378985543
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.30583251446681514560942939716973518484892872257594022585046297499507869302908
Short name T394
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.79 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201240 kb
Host smart-6aaab454-87ef-4660-93b8-dee2d7e94809
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30583251446681514560942939716973518484892872257594022585046297499507869302908 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.30583251446681514560942939716973518484892872257594022585046297499507869302908
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.4191798039862508187903108674931297181573446468859725997358249769186972007302
Short name T619
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 18 12:48:01 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201236 kb
Host smart-9b363445-9d5e-4158-98c2-66572612d14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191798039862508187903108674931297181573446468859725997358249769186972007302 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.4191798039862508187903108674931297181573446468859725997358249769186972007302
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.68883475295883751254584468833514504428968222771667297006792029628427937671845
Short name T231
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.81 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:51:37 PM PDT 23
Peak memory 201476 kb
Host smart-0f191746-a5b3-4905-b7fd-78910c97a427
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68883475295883751254584468833514504428968222771667297006792029628427937671845 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.68883475295883751254584468833514504428968222771667297006792029
628427937671845
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.58792698554095297892331198934516608069797681556459012267592243122954687161117
Short name T291
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.4 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201220 kb
Host smart-a55b533c-a92b-4811-b7b9-88ceb0452524
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58792698554095297892331198934516608069797681556459012267592243122954687161117 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.587926985540952978923311989345166080697976815564590122675922
43122954687161117
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.97579553476604334714692402281709533976285406594708765321504244497846851609053
Short name T204
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 18 12:48:15 PM PDT 23
Finished Oct 18 12:48:21 PM PDT 23
Peak memory 201204 kb
Host smart-0fc95c21-4bda-4505-afc3-2a3101191981
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97579553476604334714692402281709533976285406594708765321504244497846851609053 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.9757955347660433471469240228170953397628540659470876532150424449
7846851609053
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.82879956792162486169773122011376637312398301681639029900895174112478408747969
Short name T341
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:05 PM PDT 23
Peak memory 201236 kb
Host smart-ce9ecf76-f1a9-42b4-8b86-ff7a3550e394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82879956792162486169773122011376637312398301681639029900895174112478408747969 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.82879956792162486169773122011376637312398301681639029900895174112478408747969
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.43738703618461389749555137893440744118013633862512163861235312362065037650676
Short name T167
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.88 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201148 kb
Host smart-9cab3095-2f20-429e-9985-077ec3e1cd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43738703618461389749555137893440744118013633862512163861235312362065037650676 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.43738703618461389749555137893440744118013633862512163861235312362065037650676
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.44020697434637258888975463387934114271366255535145825400100448529688734072380
Short name T248
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 18 12:48:26 PM PDT 23
Finished Oct 18 12:48:30 PM PDT 23
Peak memory 201092 kb
Host smart-20339f0a-9311-41ab-904b-1996865b069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44020697434637258888975463387934114271366255535145825400100448529688734072380 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.44020697434637258888975463387934114271366255535145825400100448529688734072380
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.60545402930751961214133427169674301018326046092482948258347119974514285130633
Short name T328
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 18 12:48:08 PM PDT 23
Finished Oct 18 12:48:13 PM PDT 23
Peak memory 201248 kb
Host smart-a3b4d14a-3d38-46f9-88f1-b5f6ba0c1170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60545402930751961214133427169674301018326046092482948258347119974514285130633 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.60545402930751961214133427169674301018326046092482948258347119974514285130633
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.8506081146427265544228210885211970793608119499528216840541381571326967027087
Short name T371
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:09 PM PDT 23
Peak memory 201144 kb
Host smart-497d2b5a-411d-415a-8ab5-c87135da07a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8506081146427265544228210885211970793608119499528216840541381571326967027087 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sysrst_ctrl_smoke.8506081146427265544228210885211970793608119499528216840541381571326967027087
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.111514924133396037445787626847486037669689289414776848829136581717974808618753
Short name T565
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.75 seconds
Started Oct 18 12:48:28 PM PDT 23
Finished Oct 18 12:50:44 PM PDT 23
Peak memory 201496 kb
Host smart-e14349c9-89d0-49b9-b336-a7cc848e0ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111514924133396037445787626847486037669689289414776848829136581717974808618753 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.111514924133396037445787626847486037669689289414776848829136581717974808618753
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.40688969627653967432668625458977751173343031130335352295238392234119718358343
Short name T440
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:48:25 PM PDT 23
Peak memory 201196 kb
Host smart-8a487d61-9133-45c8-90e7-4574d76ef214
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40688969627653967432668625458977751173343031130335352295238392234119718358343 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.406889696276539674326686254589777511733430311303353522952383
92234119718358343
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.105299849778574510692756479315471577924963736616053834604789437294831962262220
Short name T375
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Oct 18 12:48:06 PM PDT 23
Finished Oct 18 12:48:10 PM PDT 23
Peak memory 201248 kb
Host smart-b417b4f7-4789-4203-ab5d-ff4ed8b3fddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105299849778574510692756479315471577924963736616053834604789437294831962262220 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.105299849778574510692756479315471577924963736616053834604789437294831962262220
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.6116171880708187954966588445157845965903106516264671546429338109783032284352
Short name T439
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201236 kb
Host smart-1cf69451-611d-4e74-b7c4-6e01a8e951e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6116171880708187954966588445157845965903106516264671546429338109783032284352 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.6116171880708187954966588445157845965903106516264671546429338109783032284352
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.38568937213757398877810474256773229543762323058891387785552714414788439360963
Short name T339
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.82 seconds
Started Oct 18 12:48:26 PM PDT 23
Finished Oct 18 12:51:28 PM PDT 23
Peak memory 201464 kb
Host smart-9dc11a3e-ba34-44d7-b30f-3427418a93ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568937213757398877810474256773229543762323058891387785552714414788439360963 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.38568937213757398877810474256773229543762323058891387785552714
414788439360963
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.84547321915130973056797374810454597386535616120537522851194153683716846164980
Short name T562
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:26 PM PDT 23
Finished Oct 18 12:48:34 PM PDT 23
Peak memory 201196 kb
Host smart-3f0e8524-aba2-4741-8856-557bc7bf07da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84547321915130973056797374810454597386535616120537522851194153683716846164980 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.845473219151309730567973748104545973865356161205375228511941
53683716846164980
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.25616648785384511062542828610492270557586411275080268946697262575151525688789
Short name T408
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 18 12:48:05 PM PDT 23
Finished Oct 18 12:48:12 PM PDT 23
Peak memory 201128 kb
Host smart-6550c16f-ac67-4032-8d73-7b14ca664a72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25616648785384511062542828610492270557586411275080268946697262575151525688789 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.2561664878538451106254282861049227055758641127508026894669726257
5151525688789
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.7606822065367947600483711566996540521451461400891842128216269393188971132815
Short name T355
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201220 kb
Host smart-61423a43-e193-4adf-a1d5-5ef6add67bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7606822065367947600483711566996540521451461400891842128216269393188971132815 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.7606822065367947600483711566996540521451461400891842128216269393188971132815
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.102362088467202353311497122173145800863596083219496397667910303130081628909369
Short name T406
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.91 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:48:32 PM PDT 23
Peak memory 201176 kb
Host smart-9a3fd007-3e45-48ea-a232-552494a4bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102362088467202353311497122173145800863596083219496397667910303130081628909369 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.102362088467202353311497122173145800863596083219496397667910303130081628909369
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.97944500946539775803781004017295584832489437471589779740478926984862697903660
Short name T357
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:22 PM PDT 23
Peak memory 201016 kb
Host smart-59795190-9bae-4c9d-8cc2-eb9ca6114889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97944500946539775803781004017295584832489437471589779740478926984862697903660 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.97944500946539775803781004017295584832489437471589779740478926984862697903660
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.59869514746013028606804273379546238000553756346968722870471537906684091436895
Short name T46
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 18 12:48:11 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201232 kb
Host smart-fd277670-2e4b-4d5e-8737-415b7621007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59869514746013028606804273379546238000553756346968722870471537906684091436895 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.59869514746013028606804273379546238000553756346968722870471537906684091436895
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.4703346905592813988354997135419949074192713067366075429479727097642005459072
Short name T436
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 18 12:48:08 PM PDT 23
Finished Oct 18 12:48:12 PM PDT 23
Peak memory 201188 kb
Host smart-9e7ab299-961e-47ef-80c7-11496eca9585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4703346905592813988354997135419949074192713067366075429479727097642005459072 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sysrst_ctrl_smoke.4703346905592813988354997135419949074192713067366075429479727097642005459072
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.111545340549644295729126455201696872191932273389914400817803367855941389137994
Short name T604
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.11 seconds
Started Oct 18 12:48:24 PM PDT 23
Finished Oct 18 12:50:40 PM PDT 23
Peak memory 201468 kb
Host smart-a76a8409-4f05-4454-b30d-7fb89d55c223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111545340549644295729126455201696872191932273389914400817803367855941389137994 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.111545340549644295729126455201696872191932273389914400817803367855941389137994
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.19689521232161190684235224478152955881493541824054536448391873572936884669030
Short name T509
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.92 seconds
Started Oct 18 12:48:21 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201180 kb
Host smart-25739cef-de52-4047-8240-8853b2d3238e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19689521232161190684235224478152955881493541824054536448391873572936884669030 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.196895212321611906842352244781529558814935418240545364483918
73572936884669030
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.38909784207935591521540332170814519530308817694076232248184643556978468768483
Short name T374
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 18 12:48:23 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201272 kb
Host smart-e32e28e6-2561-4bfc-98b9-a41b69d5a9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38909784207935591521540332170814519530308817694076232248184643556978468768483 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.38909784207935591521540332170814519530308817694076232248184643556978468768483
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.68664069634406877178552502207122602840797653786064476455528323831109656416773
Short name T211
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.75 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:51:35 PM PDT 23
Peak memory 201380 kb
Host smart-bb82912a-db5b-407c-8590-f0a7a6384c19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68664069634406877178552502207122602840797653786064476455528323831109656416773 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.68664069634406877178552502207122602840797653786064476455528323
831109656416773
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.19913801517782761701942696085631311438331162046807079789681560996718581114053
Short name T377
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:26 PM PDT 23
Peak memory 201088 kb
Host smart-d8279425-762b-4560-829d-45e0f3fdd8b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19913801517782761701942696085631311438331162046807079789681560996718581114053 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.199138015177827617019426960856313114383311620468070797896815
60996718581114053
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.65740103531991091670819372883257451701824401473664307824272532933173506784838
Short name T130
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 18 12:48:05 PM PDT 23
Finished Oct 18 12:48:12 PM PDT 23
Peak memory 201116 kb
Host smart-c08fd586-74c9-4dce-8b13-38b151cdf4a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65740103531991091670819372883257451701824401473664307824272532933173506784838 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.6574010353199109167081937288325745170182440147366430782427253293
3173506784838
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.39489192307910901309982468671919889569696039249343673034162900792444235484260
Short name T462
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 18 12:48:03 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201124 kb
Host smart-148122b6-1fda-495f-b94e-c804b1fc2566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39489192307910901309982468671919889569696039249343673034162900792444235484260 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.39489192307910901309982468671919889569696039249343673034162900792444235484260
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.10172843115192503751747553232594684222147578334754092520975135135242937985640
Short name T472
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 18 12:48:34 PM PDT 23
Finished Oct 18 12:48:39 PM PDT 23
Peak memory 201152 kb
Host smart-5b02043d-16b7-4e92-9c63-729e7f6dfe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10172843115192503751747553232594684222147578334754092520975135135242937985640 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.10172843115192503751747553232594684222147578334754092520975135135242937985640
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.99310818262907926097308605742741057935264163228737656182868082293120992364591
Short name T184
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.87 seconds
Started Oct 18 12:48:16 PM PDT 23
Finished Oct 18 12:48:20 PM PDT 23
Peak memory 201016 kb
Host smart-15b5d495-f389-4a1d-a958-e6af9e93df4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99310818262907926097308605742741057935264163228737656182868082293120992364591 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.99310818262907926097308605742741057935264163228737656182868082293120992364591
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.30282412639675472402424094904487722994651202719803723524247810698527273373177
Short name T656
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 18 12:48:02 PM PDT 23
Finished Oct 18 12:48:06 PM PDT 23
Peak memory 201124 kb
Host smart-6f082116-53c2-45e9-b9d0-06e0d78678c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30282412639675472402424094904487722994651202719803723524247810698527273373177 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.30282412639675472402424094904487722994651202719803723524247810698527273373177
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.101937754941102036953671286203573783873986959257258837671233380847638199823839
Short name T296
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 18 12:48:28 PM PDT 23
Finished Oct 18 12:48:32 PM PDT 23
Peak memory 201068 kb
Host smart-9148f9fc-9c17-478e-b6d0-29a4e3604b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101937754941102036953671286203573783873986959257258837671233380847638199823839 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.sysrst_ctrl_smoke.101937754941102036953671286203573783873986959257258837671233380847638199823839
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.19039579948993776442712207715838706622857228750241456136857940372198514110889
Short name T508
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.9 seconds
Started Oct 18 12:48:30 PM PDT 23
Finished Oct 18 12:50:47 PM PDT 23
Peak memory 201496 kb
Host smart-789f0752-f5a8-47f2-874e-b114f4f7aef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19039579948993776442712207715838706622857228750241456136857940372198514110889 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.19039579948993776442712207715838706622857228750241456136857940372198514110889
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.79451863447923357797728279771181368742675064715113265597928772838616352040245
Short name T356
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 18 12:48:17 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201228 kb
Host smart-c89324da-af1d-4133-bf88-555777e21de3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79451863447923357797728279771181368742675064715113265597928772838616352040245 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.794518634479233577977282797711813687426750647151132655979287
72838616352040245
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.19182850554501091875314167415380799251201465311412726482197190946416310894579
Short name T39
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:01 PM PDT 23
Peak memory 201240 kb
Host smart-24cb93ee-6a7f-4fab-af6f-2ce0a3807d9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19182850554501091875314167415380799251201465311412726482197190946416310894579 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.19182850554501091875314167415380799251201465311412726482197190946416310894579
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.65478509548998381663721203293412574265321633400488634763362283551356001622756
Short name T17
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Oct 18 12:46:51 PM PDT 23
Finished Oct 18 12:46:57 PM PDT 23
Peak memory 201292 kb
Host smart-c4dbcc6a-2d5e-43e6-a58a-cf44f82d32d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65478509548998381663721203293412574265321633400488634763362283551356001622756 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.65478509548998381663721203293412574265321633400488634763362283551356001622756
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.20864254994404563777269117035663690459357650638067814799949694277102166073644
Short name T395
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.63 seconds
Started Oct 18 12:46:44 PM PDT 23
Finished Oct 18 12:49:47 PM PDT 23
Peak memory 201444 kb
Host smart-05c36051-30af-4bd1-bcaa-17bb3e07d071
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864254994404563777269117035663690459357650638067814799949694277102166073644 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.208642549944045637772691170356636904593576506380678147999496942
77102166073644
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.83929790203658296409729126743375423405281336503734657062800616971449617377451
Short name T626
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.25 seconds
Started Oct 18 12:46:52 PM PDT 23
Finished Oct 18 12:46:57 PM PDT 23
Peak memory 201232 kb
Host smart-e84c46a7-da4a-4491-a774-c946ccdc1b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83929790203658296409729126743375423405281336503734657062800616971449617377451 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.83929790203658296409729126743375423405281336503734657062800616971449617377451
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.110775410601171532697201096628913083961587647768497697580009968997790199179880
Short name T112
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.44 seconds
Started Oct 18 12:46:46 PM PDT 23
Finished Oct 18 12:46:51 PM PDT 23
Peak memory 201304 kb
Host smart-37818365-67ec-42cd-975a-4d9d611f9c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110775410601171532697201096628913083961587647768497697580009968997790199179880 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1107754106011715326972010966289130839615876477684976
97580009968997790199179880
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.53607211447003954243076273398535495316756906993470853556737497005132052475358
Short name T464
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Oct 18 12:46:48 PM PDT 23
Finished Oct 18 12:46:55 PM PDT 23
Peak memory 201152 kb
Host smart-1f6fd12c-8123-49ba-9d3d-51b6df0414d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53607211447003954243076273398535495316756906993470853556737497005132052475358 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.5360721144700395424307627339853549531675690699347085355673749
7005132052475358
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.82018919574242374226298084698433604653510527841395137764580556443717044195990
Short name T133
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.47 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:04 PM PDT 23
Peak memory 201124 kb
Host smart-8f7e96d3-75c8-45cb-b2ff-20c9b3a0577a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82018919574242374226298084698433604653510527841395137764580556443717044195990 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.82018919574242374226298084698433604653510527841395137764580556443717044195990
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.50042450469033317259939765305055336833118836360008289543788815960392866205789
Short name T530
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 18 12:46:58 PM PDT 23
Finished Oct 18 12:47:03 PM PDT 23
Peak memory 201208 kb
Host smart-d03c0a53-ef99-4589-8fed-530c37d9afed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50042450469033317259939765305055336833118836360008289543788815960392866205789 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.50042450469033317259939765305055336833118836360008289543788815960392866205789
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.66930950439468675853203346383910255964463043407902933282069955714981031642404
Short name T537
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.85 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:47:11 PM PDT 23
Peak memory 201080 kb
Host smart-6856e154-813b-42ef-abc9-f5a99693e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66930950439468675853203346383910255964463043407902933282069955714981031642404 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.66930950439468675853203346383910255964463043407902933282069955714981031642404
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.103252450048683373991644701271653039765813688748995263254999365190015657958170
Short name T477
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 18 12:46:50 PM PDT 23
Finished Oct 18 12:46:55 PM PDT 23
Peak memory 201208 kb
Host smart-840d3bad-fb84-4e30-a468-c1c124b9deb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103252450048683373991644701271653039765813688748995263254999365190015657958170 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.103252450048683373991644701271653039765813688748995263254999365190015657958170
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.101247449508230612325273099540263382069167446056108067376495536032604447887104
Short name T392
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 18 12:46:58 PM PDT 23
Finished Oct 18 12:47:03 PM PDT 23
Peak memory 201208 kb
Host smart-1a62a8da-67ac-4bfa-a538-8e5b9a4774ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101247449508230612325273099540263382069167446056108067376495536032604447887104 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.101247449508230612325273099540263382069167446056108067376495536032604447887104
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.84137134111699665067204426194784701433904737668809684393160522542519629916298
Short name T588
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 18 12:47:02 PM PDT 23
Finished Oct 18 12:47:06 PM PDT 23
Peak memory 201044 kb
Host smart-d065010a-f8c4-4a48-95e6-b0784a94228a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84137134111699665067204426194784701433904737668809684393160522542519629916298 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_smoke.84137134111699665067204426194784701433904737668809684393160522542519629916298
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.101487775713930109533910647677721917728629791578385958522296868445060439983183
Short name T538
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.35 seconds
Started Oct 18 12:46:53 PM PDT 23
Finished Oct 18 12:49:09 PM PDT 23
Peak memory 201508 kb
Host smart-b6d5f07a-60e1-4bf5-895a-b06e2a59517f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101487775713930109533910647677721917728629791578385958522296868445060439983183 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.101487775713930109533910647677721917728629791578385958522296868445060439983183
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.23938005750418775084666901128754907927913186621572991510157480458649479791769
Short name T558
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:02 PM PDT 23
Peak memory 201240 kb
Host smart-58215610-6aba-4778-ad25-b9849d5769c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938005750418775084666901128754907927913186621572991510157480458649479791769 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.2393800575041877508466690112875490792791318662157299151015748
0458649479791769
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.44099100459885692036077993243360913588340251439345192219797020414211172054408
Short name T499
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 18 12:48:38 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201228 kb
Host smart-b9237c3a-c1d9-4e73-9090-bc828e364163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44099100459885692036077993243360913588340251439345192219797020414211172054408 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.44099100459885692036077993243360913588340251439345192219797020414211172054408
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.15673666847864638838410327649403126248613239204684891301372614023579126127942
Short name T523
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:41 PM PDT 23
Peak memory 201308 kb
Host smart-c51b5479-a450-4760-a17a-52ab01aa9a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15673666847864638838410327649403126248613239204684891301372614023579126127942 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.15673666847864638838410327649403126248613239204684891301372614023579126127942
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.7739861165818915529196116663345944330871964313915742811773670124344001364724
Short name T217
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.13 seconds
Started Oct 18 12:48:23 PM PDT 23
Finished Oct 18 12:51:26 PM PDT 23
Peak memory 201456 kb
Host smart-7307c0d2-bc8d-42d8-a912-dee6d1690ded
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7739861165818915529196116663345944330871964313915742811773670124344001364724 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.773986116581891552919611666334594433087196431391574281177367012
4344001364724
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.38327584891454523684363913295609216952199307082799358506008056017462663793558
Short name T346
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201224 kb
Host smart-ef90dd16-152d-481e-9df5-8330e0ccbd37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38327584891454523684363913295609216952199307082799358506008056017462663793558 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.383275848914545236843639132956092169521993070827993585060080
56017462663793558
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.14991715668278352358744763893708448465678909458800052720535629792602467776673
Short name T134
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 18 12:48:39 PM PDT 23
Finished Oct 18 12:48:46 PM PDT 23
Peak memory 201216 kb
Host smart-e5ca030b-0ee2-4c5b-bed8-698bc7a89b19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14991715668278352358744763893708448465678909458800052720535629792602467776673 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.1499171566827835235874476389370844846567890945880005272053562979
2602467776673
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.12074573174935498714774391574344058145582878308395666972004492227381711832962
Short name T192
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.81 seconds
Started Oct 18 12:48:31 PM PDT 23
Finished Oct 18 12:48:36 PM PDT 23
Peak memory 201228 kb
Host smart-520f7fc5-6f4c-434b-97d1-114b7d12e9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12074573174935498714774391574344058145582878308395666972004492227381711832962 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.12074573174935498714774391574344058145582878308395666972004492227381711832962
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.71563438316816380347872321276868442375384160249545466174153806950003528842207
Short name T272
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Oct 18 12:48:10 PM PDT 23
Finished Oct 18 12:48:15 PM PDT 23
Peak memory 201260 kb
Host smart-808aab5d-5cc8-4a13-bb5f-cd070b52ede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71563438316816380347872321276868442375384160249545466174153806950003528842207 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.71563438316816380347872321276868442375384160249545466174153806950003528842207
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.59119541274599930542689202259036579957735645332959367963377873028821068999301
Short name T255
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:22 PM PDT 23
Peak memory 201088 kb
Host smart-1cbb7413-8331-4178-9013-069bfb588cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59119541274599930542689202259036579957735645332959367963377873028821068999301 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.59119541274599930542689202259036579957735645332959367963377873028821068999301
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.44162606691590859775764563868186762099119326178140944849561009763999960589232
Short name T372
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201240 kb
Host smart-05eb561d-e382-4591-86dd-1a3feaba16bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44162606691590859775764563868186762099119326178140944849561009763999960589232 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.44162606691590859775764563868186762099119326178140944849561009763999960589232
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.67000479231087662938345483111664287338009339616635043020869141467253073253722
Short name T324
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 18 12:48:39 PM PDT 23
Finished Oct 18 12:48:43 PM PDT 23
Peak memory 201096 kb
Host smart-c6de9fa1-a020-4c3a-bfe0-fadeb27cf7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67000479231087662938345483111664287338009339616635043020869141467253073253722 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_smoke.67000479231087662938345483111664287338009339616635043020869141467253073253722
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.15454019901275830272080329502855718795135651703952527706006665127958470950884
Short name T536
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.33 seconds
Started Oct 18 12:48:36 PM PDT 23
Finished Oct 18 12:50:52 PM PDT 23
Peak memory 201532 kb
Host smart-4a00c8d1-82bb-4313-9726-a11fafece9dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15454019901275830272080329502855718795135651703952527706006665127958470950884 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.15454019901275830272080329502855718795135651703952527706006665127958470950884
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.38756369633392504620534910870467520857944103069400838290884946888502358993985
Short name T476
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 18 12:48:30 PM PDT 23
Finished Oct 18 12:48:35 PM PDT 23
Peak memory 201208 kb
Host smart-7753fb5d-b5d5-4a61-9139-254ffe9548ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38756369633392504620534910870467520857944103069400838290884946888502358993985 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.387563696333925046205349108704675208579441030694008382908849
46888502358993985
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.73331463934781365316715511035486973359097734389636663418848443764594564909745
Short name T235
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 18 12:48:17 PM PDT 23
Finished Oct 18 12:48:21 PM PDT 23
Peak memory 201236 kb
Host smart-a5fc7746-2a1f-498e-b76f-85532787e7e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73331463934781365316715511035486973359097734389636663418848443764594564909745 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.73331463934781365316715511035486973359097734389636663418848443764594564909745
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.20879035889209004368659102739695895747268493391952605511820573903969398146504
Short name T387
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Oct 18 12:48:36 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201192 kb
Host smart-dd461a07-a137-49c5-b85b-aec66c17a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20879035889209004368659102739695895747268493391952605511820573903969398146504 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.20879035889209004368659102739695895747268493391952605511820573903969398146504
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.55553557569444061297118394837359881871977956638030359169138144337357186703184
Short name T673
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.47 seconds
Started Oct 18 12:48:37 PM PDT 23
Finished Oct 18 12:51:40 PM PDT 23
Peak memory 201460 kb
Host smart-943ca5ab-6336-4998-8a7a-5e017b5878e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55553557569444061297118394837359881871977956638030359169138144337357186703184 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.55553557569444061297118394837359881871977956638030359169138144
337357186703184
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.49350547417481389042999519612757163196676660776947284187927081402795201701927
Short name T368
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201272 kb
Host smart-aec863a8-e7c6-489b-9518-928f04a0c209
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49350547417481389042999519612757163196676660776947284187927081402795201701927 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.493505474174813890429995196127571631966766607769472841879270
81402795201701927
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.21653186312842341076176183048338686373327293392454803164723980994585906358396
Short name T674
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 18 12:48:30 PM PDT 23
Finished Oct 18 12:48:36 PM PDT 23
Peak memory 201224 kb
Host smart-081a7ea1-47d5-4d94-82e5-b03b9b39b9da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21653186312842341076176183048338686373327293392454803164723980994585906358396 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.2165318631284234107617618304833868637332729339245480316472398099
4585906358396
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.54381263857155027516592102139885245012845176139921838337228208878313172468922
Short name T582
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Oct 18 12:48:42 PM PDT 23
Finished Oct 18 12:48:48 PM PDT 23
Peak memory 201244 kb
Host smart-0f8349dd-c1b3-4ef9-8078-fc9331dcc443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54381263857155027516592102139885245012845176139921838337228208878313172468922 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.54381263857155027516592102139885245012845176139921838337228208878313172468922
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.67587743758288746859896146329837459635561140528836773030594839273187645374875
Short name T661
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:41 PM PDT 23
Peak memory 201184 kb
Host smart-561a4345-399e-4f98-a4eb-7826c37a677a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67587743758288746859896146329837459635561140528836773030594839273187645374875 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.67587743758288746859896146329837459635561140528836773030594839273187645374875
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2893653957986216992507770328530607544193729601119175693859376555464783124570
Short name T320
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 18 12:48:44 PM PDT 23
Finished Oct 18 12:48:48 PM PDT 23
Peak memory 201056 kb
Host smart-a5ed6e2f-e258-47d8-aef1-5421b81c0537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893653957986216992507770328530607544193729601119175693859376555464783124570 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2893653957986216992507770328530607544193729601119175693859376555464783124570
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.82982024331372584724631175313365385284468954157654186172537652076225774849954
Short name T598
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 18 12:48:26 PM PDT 23
Finished Oct 18 12:48:31 PM PDT 23
Peak memory 201100 kb
Host smart-27955954-c339-48c2-904a-14998a70de82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82982024331372584724631175313365385284468954157654186172537652076225774849954 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.82982024331372584724631175313365385284468954157654186172537652076225774849954
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.44858426012699580778846667595716582527548821732819952776075780510991286405296
Short name T169
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201028 kb
Host smart-a9f10d4c-c5cf-47b1-bf67-5802b6e518cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44858426012699580778846667595716582527548821732819952776075780510991286405296 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_smoke.44858426012699580778846667595716582527548821732819952776075780510991286405296
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.26965260537178489169849387515653561406059359125408990975878541411734039466352
Short name T603
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.21 seconds
Started Oct 18 12:48:14 PM PDT 23
Finished Oct 18 12:50:30 PM PDT 23
Peak memory 201508 kb
Host smart-99032de0-51cc-474b-8f9f-ed010ea5c633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26965260537178489169849387515653561406059359125408990975878541411734039466352 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.26965260537178489169849387515653561406059359125408990975878541411734039466352
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.84065344184204783432520092938098010000133477813995704441550751103888377647929
Short name T49
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 18 12:48:47 PM PDT 23
Finished Oct 18 12:48:53 PM PDT 23
Peak memory 201128 kb
Host smart-14b85f7a-03ff-4983-ba14-23ce74ac2845
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84065344184204783432520092938098010000133477813995704441550751103888377647929 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.840653441842047834325200929380980100001334778139957044415507
51103888377647929
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.1624850013105920855116914755701256074009723005279944844924955081369459322211
Short name T222
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201164 kb
Host smart-0305d0fb-82f3-497c-b5d2-79037aa5ad08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624850013105920855116914755701256074009723005279944844924955081369459322211 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.1624850013105920855116914755701256074009723005279944844924955081369459322211
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.67306687730217700498411011239772262425789000627167309386482721759520373343801
Short name T183
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 18 12:47:58 PM PDT 23
Finished Oct 18 12:48:04 PM PDT 23
Peak memory 201200 kb
Host smart-8c41d6ac-0509-43a5-9eb6-9bbb80d5ff54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67306687730217700498411011239772262425789000627167309386482721759520373343801 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.67306687730217700498411011239772262425789000627167309386482721759520373343801
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.110009046606849456651928205589007721838615564341039555852928564057483929629565
Short name T497
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.16 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:51:35 PM PDT 23
Peak memory 201432 kb
Host smart-7df3846b-3edd-455a-baef-dce440055ce3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110009046606849456651928205589007721838615564341039555852928564057483929629565 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.1100090466068494566519282055890077218386155643410395558529285
64057483929629565
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.44677647879172426683491455374749013329299552825058504014452484093175324287943
Short name T332
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:28 PM PDT 23
Finished Oct 18 12:48:36 PM PDT 23
Peak memory 201220 kb
Host smart-52ba9e4f-a7a2-4e35-88c4-66d54fde96c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44677647879172426683491455374749013329299552825058504014452484093175324287943 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.446776478791724266834914553747490133292995528250585040144524
84093175324287943
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.66104261949593170395005584544660084968596374772707862254844410252772530089737
Short name T453
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:30 PM PDT 23
Peak memory 201248 kb
Host smart-ffd8ad49-09e1-413c-a884-b348d60574b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66104261949593170395005584544660084968596374772707862254844410252772530089737 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.6610426194959317039500558454466008496859637477270786225484441025
2772530089737
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.68716720363816493287997503604780430410481609696550006471168454813969858734520
Short name T521
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Oct 18 12:48:16 PM PDT 23
Finished Oct 18 12:48:21 PM PDT 23
Peak memory 201212 kb
Host smart-a713445f-099d-4950-98da-b915951c8c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68716720363816493287997503604780430410481609696550006471168454813969858734520 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.68716720363816493287997503604780430410481609696550006471168454813969858734520
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.45632686576015485825421252853492799298166855672129348087836221729641312954784
Short name T336
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201268 kb
Host smart-c982bf4d-0f39-4722-b732-1dff69ed7e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45632686576015485825421252853492799298166855672129348087836221729641312954784 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.45632686576015485825421252853492799298166855672129348087836221729641312954784
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.71085469657148015430159445370905586542489977388151749108942204473176641632096
Short name T506
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 18 12:48:13 PM PDT 23
Finished Oct 18 12:48:17 PM PDT 23
Peak memory 201080 kb
Host smart-1177f006-e581-41a4-8305-e1423bf1b355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71085469657148015430159445370905586542489977388151749108942204473176641632096 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.71085469657148015430159445370905586542489977388151749108942204473176641632096
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.56667825652919995497368403926167624818796975943858021998839624991347997551115
Short name T67
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 18 12:48:36 PM PDT 23
Finished Oct 18 12:48:41 PM PDT 23
Peak memory 201212 kb
Host smart-fd42e91f-3a12-44c0-b546-60017e72b14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56667825652919995497368403926167624818796975943858021998839624991347997551115 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.56667825652919995497368403926167624818796975943858021998839624991347997551115
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.76740825066410855013412938977866719301094825279403403136106833179519655272560
Short name T585
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 18 12:48:08 PM PDT 23
Finished Oct 18 12:48:12 PM PDT 23
Peak memory 201124 kb
Host smart-ce93c04a-b979-4cad-9f9e-9ce32773977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76740825066410855013412938977866719301094825279403403136106833179519655272560 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_smoke.76740825066410855013412938977866719301094825279403403136106833179519655272560
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.24450434635738852577222661905457577924310801139593209115714639965843299821690
Short name T384
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.03 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:50:37 PM PDT 23
Peak memory 201424 kb
Host smart-f669337b-8ce6-4ecb-82f9-683153530128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24450434635738852577222661905457577924310801139593209115714639965843299821690 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.24450434635738852577222661905457577924310801139593209115714639965843299821690
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.75796540506885211293228925177236417012883547230649719527317826726603795541100
Short name T572
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201188 kb
Host smart-ed9f7736-3cbe-411e-a1a0-a8188f11ec22
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75796540506885211293228925177236417012883547230649719527317826726603795541100 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.757965405068852112932289251772364170128835472306497195273178
26726603795541100
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.33383628133586968912746929085965533714788469211994339769604891797374642995797
Short name T461
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:27 PM PDT 23
Peak memory 201132 kb
Host smart-0d9ea970-bb0a-4a83-a3ee-e4338496398b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33383628133586968912746929085965533714788469211994339769604891797374642995797 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.33383628133586968912746929085965533714788469211994339769604891797374642995797
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.101765751695238548185814558797269208071756968638833585609341650408450015344243
Short name T345
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.54 seconds
Started Oct 18 12:48:30 PM PDT 23
Finished Oct 18 12:48:36 PM PDT 23
Peak memory 201312 kb
Host smart-8437abfe-aeec-4620-9b13-68b0b4db885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101765751695238548185814558797269208071756968638833585609341650408450015344243 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.101765751695238548185814558797269208071756968638833585609341650408450015344243
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.9150482228442611791172449534414560711595515510898422258578870865959042068108
Short name T552
Test name
Test status
Simulation time 118289458206 ps
CPU time 179.74 seconds
Started Oct 18 12:48:31 PM PDT 23
Finished Oct 18 12:51:31 PM PDT 23
Peak memory 201368 kb
Host smart-5f46001f-c89c-4cbf-a18a-0c84f7c2f9df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9150482228442611791172449534414560711595515510898422258578870865959042068108 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.915048222844261179117244953441456071159551551089842225857887086
5959042068108
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.47147576063172384240318048827031944524828728377926947989747344525818711560266
Short name T414
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Oct 18 12:48:04 PM PDT 23
Finished Oct 18 12:48:12 PM PDT 23
Peak memory 201204 kb
Host smart-e8fe9424-c05b-458e-ba8b-e3cf6d006ddd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47147576063172384240318048827031944524828728377926947989747344525818711560266 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.471475760631723842403180488270319445248287283779269479897473
44525818711560266
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.16456041470938560545544541432930573271547894107814190571242998635833593377568
Short name T571
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 18 12:48:05 PM PDT 23
Finished Oct 18 12:48:12 PM PDT 23
Peak memory 201220 kb
Host smart-7e7c2da5-90bc-483b-8f81-fd9085927aaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16456041470938560545544541432930573271547894107814190571242998635833593377568 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.1645604147093856054554454143293057327154789410781419057124299863
5833593377568
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.41164319138381445586676605978142319931641769619799877555246361409112997330112
Short name T409
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201236 kb
Host smart-b916de0b-af00-4d0b-a1d5-a1be959a855d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41164319138381445586676605978142319931641769619799877555246361409112997330112 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.41164319138381445586676605978142319931641769619799877555246361409112997330112
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.64047534505642214869973693472433564027746203544758699908408015665633571137713
Short name T489
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.69 seconds
Started Oct 18 12:48:05 PM PDT 23
Finished Oct 18 12:48:10 PM PDT 23
Peak memory 201236 kb
Host smart-67b91ffc-8581-4655-8b83-8d077b2b169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64047534505642214869973693472433564027746203544758699908408015665633571137713 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.64047534505642214869973693472433564027746203544758699908408015665633571137713
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.26073673311669490122060612846844449753598531409974660005155944668899255828629
Short name T609
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 18 12:48:12 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201184 kb
Host smart-aad88fd6-47a6-4f06-a1b1-5ae16c8b4c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26073673311669490122060612846844449753598531409974660005155944668899255828629 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.26073673311669490122060612846844449753598531409974660005155944668899255828629
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.51194305590115835120819521344895191854029071523193432728177172492746420222164
Short name T258
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201252 kb
Host smart-e7585444-703d-4878-b17b-3c8ab6cd34b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51194305590115835120819521344895191854029071523193432728177172492746420222164 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.51194305590115835120819521344895191854029071523193432728177172492746420222164
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.67709698509058400554787008096862278523086122126110053311453711563231733752837
Short name T207
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 18 12:48:39 PM PDT 23
Finished Oct 18 12:48:43 PM PDT 23
Peak memory 201060 kb
Host smart-10fd0c19-a957-4e69-b59d-a25e0a7fbbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67709698509058400554787008096862278523086122126110053311453711563231733752837 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sysrst_ctrl_smoke.67709698509058400554787008096862278523086122126110053311453711563231733752837
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.96075576297357893453540373613073003739216272672498984448279677106822006881267
Short name T654
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.86 seconds
Started Oct 18 12:48:09 PM PDT 23
Finished Oct 18 12:50:25 PM PDT 23
Peak memory 201520 kb
Host smart-fb4d5385-f7ee-4bd2-8225-9fad3030c347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96075576297357893453540373613073003739216272672498984448279677106822006881267 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.96075576297357893453540373613073003739216272672498984448279677106822006881267
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.36292631900976058830609086078392244046037625079831703475280992535097933182656
Short name T236
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 18 12:48:21 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201220 kb
Host smart-fa020dd8-7b4d-4df6-ad25-21fcf1d81c18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36292631900976058830609086078392244046037625079831703475280992535097933182656 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.362926319009760588306090860783922440460376250798317034752809
92535097933182656
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.8621315340608595445232265920509267440105475346540028459914594271929464088426
Short name T282
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 18 12:48:25 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201160 kb
Host smart-ef3fb001-8657-4389-ac8e-c6189f724d1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8621315340608595445232265920509267440105475346540028459914594271929464088426 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.8621315340608595445232265920509267440105475346540028459914594271929464088426
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.72134215378206000041795045000578206963055011642773478318850509084305696705185
Short name T65
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 18 12:48:31 PM PDT 23
Finished Oct 18 12:48:37 PM PDT 23
Peak memory 201312 kb
Host smart-a1c5c5df-8be0-4905-a026-01e83667dc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72134215378206000041795045000578206963055011642773478318850509084305696705185 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.72134215378206000041795045000578206963055011642773478318850509084305696705185
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.45108856769788794374981181311895622205245828511438391221416375176635601863327
Short name T164
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.29 seconds
Started Oct 18 12:47:57 PM PDT 23
Finished Oct 18 12:48:05 PM PDT 23
Peak memory 201248 kb
Host smart-86ce9b4a-68ba-455f-adbe-bc85ae9cdcbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45108856769788794374981181311895622205245828511438391221416375176635601863327 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.451088567697887943749811813118956222052458285114383912214163
75176635601863327
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.108569874450553120275071437782629481962161512036505756005113147354600014602477
Short name T218
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Oct 18 12:48:16 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201248 kb
Host smart-00c798ec-23db-4685-a0bc-fc3f2c58d7f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108569874450553120275071437782629481962161512036505756005113147354600014602477 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.108569874450553120275071437782629481962161512036505756005113147
354600014602477
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.66174800773060013187753525632404484239324832562568640854920287413519634005355
Short name T666
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 18 12:48:26 PM PDT 23
Finished Oct 18 12:48:31 PM PDT 23
Peak memory 201256 kb
Host smart-ac33ec74-221b-403f-840d-eb86d9883c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66174800773060013187753525632404484239324832562568640854920287413519634005355 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.66174800773060013187753525632404484239324832562568640854920287413519634005355
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.20112207479344657840819320744181911061308248377203999442864353658254410936763
Short name T419
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.94 seconds
Started Oct 18 12:48:23 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201220 kb
Host smart-8e3a3ac0-9083-44a6-ade5-3f3d7dfe716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20112207479344657840819320744181911061308248377203999442864353658254410936763 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.20112207479344657840819320744181911061308248377203999442864353658254410936763
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.69318378540158892855016543730103553972588872944081209205631928366334678366276
Short name T397
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.82 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201180 kb
Host smart-c6ad0a5a-d177-4fe0-a358-ffb9d0463277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69318378540158892855016543730103553972588872944081209205631928366334678366276 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.69318378540158892855016543730103553972588872944081209205631928366334678366276
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.95947711099560153202112732611009931869154773643385430626047402261212621901312
Short name T252
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 18 12:48:02 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201208 kb
Host smart-e577ebc3-cfac-4bdb-9a41-9d5ae11c0505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95947711099560153202112732611009931869154773643385430626047402261212621901312 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.95947711099560153202112732611009931869154773643385430626047402261212621901312
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.7672556395405064328036502567258315896755400341151077760634297038948285241315
Short name T669
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 18 12:48:28 PM PDT 23
Finished Oct 18 12:48:32 PM PDT 23
Peak memory 201140 kb
Host smart-9b985dd1-49a7-4dc6-82ad-a78cc9ddbccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7672556395405064328036502567258315896755400341151077760634297038948285241315 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sysrst_ctrl_smoke.7672556395405064328036502567258315896755400341151077760634297038948285241315
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.11432452292782874025971253770308162330213881774429816995171391358117342652841
Short name T124
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.79 seconds
Started Oct 18 12:48:09 PM PDT 23
Finished Oct 18 12:50:24 PM PDT 23
Peak memory 201388 kb
Host smart-c2067fc3-abfc-4a6c-a4c9-6f48ad2b1743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11432452292782874025971253770308162330213881774429816995171391358117342652841 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.11432452292782874025971253770308162330213881774429816995171391358117342652841
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.37577553648289455768466249551300848097839896706546910608260422721003057534083
Short name T254
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.85 seconds
Started Oct 18 12:48:14 PM PDT 23
Finished Oct 18 12:48:19 PM PDT 23
Peak memory 201224 kb
Host smart-e09b0ba7-165b-408a-a175-8b24da88c102
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577553648289455768466249551300848097839896706546910608260422721003057534083 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.375775536482894557684662495513008480978398967065469106082604
22721003057534083
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.39660453668271071961284397016995330421217779544411645442212999834700503314353
Short name T370
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 18 12:48:31 PM PDT 23
Finished Oct 18 12:48:35 PM PDT 23
Peak memory 201140 kb
Host smart-dfc3330f-9387-4e5c-8702-5aedc998cfa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39660453668271071961284397016995330421217779544411645442212999834700503314353 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.39660453668271071961284397016995330421217779544411645442212999834700503314353
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.62484186195925210809689367611249292122785991329735192134075701071252208342737
Short name T560
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Oct 18 12:48:08 PM PDT 23
Finished Oct 18 12:48:14 PM PDT 23
Peak memory 201180 kb
Host smart-f70675d1-d8b3-4e4f-bfc2-8d9853a88413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62484186195925210809689367611249292122785991329735192134075701071252208342737 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.62484186195925210809689367611249292122785991329735192134075701071252208342737
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.71285366268043119460136881687719180840748480657238781780091155362936380002126
Short name T27
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.87 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:51:29 PM PDT 23
Peak memory 201380 kb
Host smart-9fd647f2-d8c6-4c2f-8c88-ab8a6c8b5856
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71285366268043119460136881687719180840748480657238781780091155362936380002126 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.71285366268043119460136881687719180840748480657238781780091155
362936380002126
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.79433003630814161466897444813508646734855125125312586886586278316727057467161
Short name T163
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:48:27 PM PDT 23
Peak memory 201252 kb
Host smart-7e5aec51-2b90-486a-a3fc-a3857ffe953a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79433003630814161466897444813508646734855125125312586886586278316727057467161 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.794330036308141614668974448135086467348551251253125868865862
78316727057467161
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3556012030075081232607979794045839972496904448617584813068395624236515818076
Short name T206
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:48:06 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201140 kb
Host smart-0d3698a0-3d58-4828-91bf-bd8353c749ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556012030075081232607979794045839972496904448617584813068395624236515818076 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.3556012030075081232607979794045839972496904448617584813068395624236515818076
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.49642900371563132952184036414906202188350794544617922681143499038763976327559
Short name T285
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201120 kb
Host smart-ecbc5fdd-f0f3-45bb-b83f-c08920f26d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49642900371563132952184036414906202188350794544617922681143499038763976327559 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.49642900371563132952184036414906202188350794544617922681143499038763976327559
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.25008321829399612529080120457317290302146908163258008973263481319368635085590
Short name T237
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 18 12:48:24 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201288 kb
Host smart-9cf39245-1537-4e33-9fe0-5972773c615e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25008321829399612529080120457317290302146908163258008973263481319368635085590 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.25008321829399612529080120457317290302146908163258008973263481319368635085590
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.41807252780645897340928881747317676070492339703522994051372431827003529426223
Short name T147
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 18 12:48:16 PM PDT 23
Finished Oct 18 12:48:20 PM PDT 23
Peak memory 201016 kb
Host smart-b21b1f5c-93ae-46dd-9f00-3b49383bf645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41807252780645897340928881747317676070492339703522994051372431827003529426223 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.41807252780645897340928881747317676070492339703522994051372431827003529426223
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.29671852495170203856987696840713470326283504034701935108084211017582059045314
Short name T512
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:48:32 PM PDT 23
Peak memory 201252 kb
Host smart-450b8d40-3e55-48e3-89cd-791aade732b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29671852495170203856987696840713470326283504034701935108084211017582059045314 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.29671852495170203856987696840713470326283504034701935108084211017582059045314
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.14119799716223400693437534840155608889276939388580198560276739767137013901074
Short name T181
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:48:31 PM PDT 23
Peak memory 201120 kb
Host smart-339943b0-649f-4cf6-8a5a-e227f8966433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14119799716223400693437534840155608889276939388580198560276739767137013901074 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_smoke.14119799716223400693437534840155608889276939388580198560276739767137013901074
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.52089709684333933363703636246581822818041964952464164243180446273907450785196
Short name T129
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.2 seconds
Started Oct 18 12:48:31 PM PDT 23
Finished Oct 18 12:50:45 PM PDT 23
Peak memory 201416 kb
Host smart-e661a54c-9ac5-49d0-a3f7-61dfa68f11e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52089709684333933363703636246581822818041964952464164243180446273907450785196 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.52089709684333933363703636246581822818041964952464164243180446273907450785196
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.55253802779010104807468287186189509480585711233649863402486676401918906446683
Short name T637
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 18 12:48:02 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201220 kb
Host smart-8f5496b4-8404-4383-b52e-44869e7b028b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55253802779010104807468287186189509480585711233649863402486676401918906446683 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.552538027790101048074682871861895094805857112336498634024866
76401918906446683
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.29073517230521030554866311287032888092254567693896867205860903110121296267233
Short name T312
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 18 12:48:34 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201216 kb
Host smart-bfa7db8e-eef1-40b2-aec6-0ef9c4c4e257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29073517230521030554866311287032888092254567693896867205860903110121296267233 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.29073517230521030554866311287032888092254567693896867205860903110121296267233
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.55705418145639281339785735565031309701991978089717945983174270215351465888362
Short name T101
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 18 12:48:31 PM PDT 23
Finished Oct 18 12:48:37 PM PDT 23
Peak memory 201108 kb
Host smart-ed2f9871-8d77-45ac-842e-a4d5cfde4bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55705418145639281339785735565031309701991978089717945983174270215351465888362 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.55705418145639281339785735565031309701991978089717945983174270215351465888362
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.90223786065997605518790999317049898433764741300207217860245650559414552720667
Short name T657
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.62 seconds
Started Oct 18 12:48:29 PM PDT 23
Finished Oct 18 12:51:31 PM PDT 23
Peak memory 201296 kb
Host smart-0e4537fb-553e-4284-936d-7c839f01d6ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90223786065997605518790999317049898433764741300207217860245650559414552720667 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.90223786065997605518790999317049898433764741300207217860245650
559414552720667
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.31660778715077707141166088700456135307280675309788878201532345963547817528212
Short name T594
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.45 seconds
Started Oct 18 12:48:36 PM PDT 23
Finished Oct 18 12:48:44 PM PDT 23
Peak memory 201228 kb
Host smart-2298cc0a-eedb-41b9-a042-203ef4b4443d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660778715077707141166088700456135307280675309788878201532345963547817528212 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.316607787150777071411660887004561353072806753097888782015323
45963547817528212
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2458374359127949066054334871237896578014281163718399395595803133149797879892
Short name T335
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:48:27 PM PDT 23
Peak memory 201220 kb
Host smart-dd481e6c-5396-4d0d-8eae-77c35d4f4670
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458374359127949066054334871237896578014281163718399395595803133149797879892 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.2458374359127949066054334871237896578014281163718399395595803133149797879892
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.20396168601683755230911348116737097100026522721911588543463623717267326955890
Short name T569
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201100 kb
Host smart-e99d410c-df52-4bba-b245-bc058eb3bea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20396168601683755230911348116737097100026522721911588543463623717267326955890 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.20396168601683755230911348116737097100026522721911588543463623717267326955890
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.22520880368700369727395328595233859164972895836131286962355681247839465872531
Short name T493
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 18 12:48:21 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201264 kb
Host smart-d7135a82-0613-4dc9-9728-5190c1c15daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22520880368700369727395328595233859164972895836131286962355681247839465872531 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.22520880368700369727395328595233859164972895836131286962355681247839465872531
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.112700953432069177790649657453949137858542461447874643722886214276464503427901
Short name T607
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 18 12:48:38 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201116 kb
Host smart-ada8a9a0-0777-4f21-b7c4-4c4e7a17caa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112700953432069177790649657453949137858542461447874643722886214276464503427901 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.112700953432069177790649657453949137858542461447874643722886214276464503427901
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.59216285429586480567744828160277540244106290102531863395827295440874741551129
Short name T177
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:48:24 PM PDT 23
Peak memory 201128 kb
Host smart-9b1ebd91-1c94-49db-9dc7-ee27a493b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59216285429586480567744828160277540244106290102531863395827295440874741551129 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.59216285429586480567744828160277540244106290102531863395827295440874741551129
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.36726206857143115822380542293292709847307730061257029176947217666985117389961
Short name T586
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:37 PM PDT 23
Peak memory 201052 kb
Host smart-18412735-b699-4508-a94d-09e1603dd8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36726206857143115822380542293292709847307730061257029176947217666985117389961 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_smoke.36726206857143115822380542293292709847307730061257029176947217666985117389961
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.18324724610391635878587929556187891682870400753143335619269532427180603011122
Short name T416
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.49 seconds
Started Oct 18 12:48:55 PM PDT 23
Finished Oct 18 12:51:09 PM PDT 23
Peak memory 201404 kb
Host smart-1050911f-10a0-4a68-b6ed-64684a1f3e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18324724610391635878587929556187891682870400753143335619269532427180603011122 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.18324724610391635878587929556187891682870400753143335619269532427180603011122
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.72486084032163694129970870535681595461263078332222165955912946344150879836633
Short name T651
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.8 seconds
Started Oct 18 12:48:21 PM PDT 23
Finished Oct 18 12:48:27 PM PDT 23
Peak memory 201216 kb
Host smart-e5304999-309c-4dc2-9ced-bdd4e6553ced
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72486084032163694129970870535681595461263078332222165955912946344150879836633 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.724860840321636941299708705356815954612630783322221659559129
46344150879836633
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.20653523663215600221370887279371066871071173053470608771993862417981511741386
Short name T668
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 18 12:48:36 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201232 kb
Host smart-027f5d7b-ddb4-4195-8acb-fed29fafb2d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20653523663215600221370887279371066871071173053470608771993862417981511741386 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.20653523663215600221370887279371066871071173053470608771993862417981511741386
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.25456928088921894618984319251925815197653025658385616455266804526193031728298
Short name T647
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.57 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:24 PM PDT 23
Peak memory 201272 kb
Host smart-d9cbfdc8-9a66-4672-af1a-ff2da0087b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25456928088921894618984319251925815197653025658385616455266804526193031728298 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.25456928088921894618984319251925815197653025658385616455266804526193031728298
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.13111379973052389477714460403025004857273246948199107832979203334476527371492
Short name T187
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.45 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:51:22 PM PDT 23
Peak memory 201368 kb
Host smart-e5282ed3-0857-41ed-94f4-be0345d30e0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13111379973052389477714460403025004857273246948199107832979203334476527371492 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.13111379973052389477714460403025004857273246948199107832979203
334476527371492
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.4505678229797145021856555849633876429773232346476760626277835263059712070680
Short name T240
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:43 PM PDT 23
Peak memory 201244 kb
Host smart-b6874b5a-d5a7-4fb9-91f3-9b72aab9f23d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4505678229797145021856555849633876429773232346476760626277835263059712070680 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.4505678229797145021856555849633876429773232346476760626277835
263059712070680
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.89524800601463379747414773962199296025298039182604557381285089276773692493498
Short name T280
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 18 12:48:43 PM PDT 23
Finished Oct 18 12:48:50 PM PDT 23
Peak memory 201216 kb
Host smart-ddcd20ac-f949-4667-b4d2-6d4fda632aba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89524800601463379747414773962199296025298039182604557381285089276773692493498 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.8952480060146337974741477396219929602529803918260455738128508927
6773692493498
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.28168731378252710130520156443948906293776945491704559662461841716983192310763
Short name T399
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 18 12:48:37 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201140 kb
Host smart-d2a0aad9-f3a3-4abf-ab58-674c9d2f8af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28168731378252710130520156443948906293776945491704559662461841716983192310763 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.28168731378252710130520156443948906293776945491704559662461841716983192310763
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.99393451575794039817942810975990187101623065158306089891054712189334859261588
Short name T484
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 18 12:48:24 PM PDT 23
Finished Oct 18 12:48:30 PM PDT 23
Peak memory 201232 kb
Host smart-224f16e5-c38c-4ba7-b8b4-609c13540827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99393451575794039817942810975990187101623065158306089891054712189334859261588 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.99393451575794039817942810975990187101623065158306089891054712189334859261588
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.62498722679247759604165374588945181742056416064804478337308640678851666399969
Short name T575
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 18 12:48:30 PM PDT 23
Finished Oct 18 12:48:34 PM PDT 23
Peak memory 201192 kb
Host smart-1f6e674c-54a8-4ace-9657-b9caf0298b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62498722679247759604165374588945181742056416064804478337308640678851666399969 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.62498722679247759604165374588945181742056416064804478337308640678851666399969
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.448135041274303433950516334383629281817405626798191504770206985835881170780
Short name T430
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201316 kb
Host smart-6deb38d7-12c9-468a-bd64-a6e79e9d4b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448135041274303433950516334383629281817405626798191504770206985835881170780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.448135041274303433950516334383629281817405626798191504770206985835881170780
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.114013964665958835198955939969031461477123173017271216603423639942486848283751
Short name T148
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:39 PM PDT 23
Peak memory 201060 kb
Host smart-dd5ad3ce-404c-448b-8e80-8c36377c6296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114013964665958835198955939969031461477123173017271216603423639942486848283751 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.sysrst_ctrl_smoke.114013964665958835198955939969031461477123173017271216603423639942486848283751
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.34566256799026256436317472075816890289713305354460344327225560183521538569891
Short name T233
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.8 seconds
Started Oct 18 12:48:08 PM PDT 23
Finished Oct 18 12:50:24 PM PDT 23
Peak memory 201416 kb
Host smart-5db6e428-9d05-4e9d-bd7a-68b67adcd91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34566256799026256436317472075816890289713305354460344327225560183521538569891 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.34566256799026256436317472075816890289713305354460344327225560183521538569891
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.65377817515495639499301649622807327537463520759373813193500625987474435303296
Short name T580
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 18 12:48:18 PM PDT 23
Finished Oct 18 12:48:23 PM PDT 23
Peak memory 201204 kb
Host smart-43804988-5f02-4135-a5ed-e70372245b8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65377817515495639499301649622807327537463520759373813193500625987474435303296 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.653778175154956394993016496228073275374635207593738131935006
25987474435303296
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.107795875011760032666274834017937878996247001096502574819574204906679393425825
Short name T158
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 18 12:48:22 PM PDT 23
Finished Oct 18 12:48:27 PM PDT 23
Peak memory 201216 kb
Host smart-8949a319-bdb4-4601-b96c-f56794fcb105
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107795875011760032666274834017937878996247001096502574819574204906679393425825 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.107795875011760032666274834017937878996247001096502574819574204906679393425825
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.77803465526871780698628247573169167561262793806975371400936450976546247899185
Short name T117
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:05 PM PDT 23
Peak memory 201300 kb
Host smart-39df0817-775e-4941-9d7b-8bf2f872aef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77803465526871780698628247573169167561262793806975371400936450976546247899185 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.77803465526871780698628247573169167561262793806975371400936450976546247899185
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.49922646993234538682626619947871487850459659509942770672825141616659937285380
Short name T273
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.59 seconds
Started Oct 18 12:48:37 PM PDT 23
Finished Oct 18 12:51:40 PM PDT 23
Peak memory 201456 kb
Host smart-aa8289db-1996-45c4-a1dd-648a557e9663
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49922646993234538682626619947871487850459659509942770672825141616659937285380 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.49922646993234538682626619947871487850459659509942770672825141
616659937285380
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.15153690203773382106043443073847531218961058048164098835838742306615819323550
Short name T151
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:10 PM PDT 23
Finished Oct 18 12:48:18 PM PDT 23
Peak memory 201240 kb
Host smart-15334fd2-1f8b-49ae-92ae-9afd8d23e464
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15153690203773382106043443073847531218961058048164098835838742306615819323550 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.151536902037733821060434430738475312189610580481640988358387
42306615819323550
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.30267707471040552483547560567957301501067081665741307506890865183061933734241
Short name T316
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 18 12:48:25 PM PDT 23
Finished Oct 18 12:48:32 PM PDT 23
Peak memory 201128 kb
Host smart-b5f2d8aa-f79c-42da-9f70-b157877195da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267707471040552483547560567957301501067081665741307506890865183061933734241 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.3026770747104055248354756056795730150106708166574130750689086518
3061933734241
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.20282028190693976303182865596254169858130601144719947436927529504296774093314
Short name T141
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Oct 18 12:48:13 PM PDT 23
Finished Oct 18 12:48:18 PM PDT 23
Peak memory 201220 kb
Host smart-b30a84ab-ee02-4bd6-8c83-c5a945af43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20282028190693976303182865596254169858130601144719947436927529504296774093314 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.20282028190693976303182865596254169858130601144719947436927529504296774093314
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.29994429542215115063285947854223135441940429853239874487883145319927874307379
Short name T360
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.73 seconds
Started Oct 18 12:48:10 PM PDT 23
Finished Oct 18 12:48:15 PM PDT 23
Peak memory 201268 kb
Host smart-a3874480-b95e-4677-a1df-4a5cbe7d1888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29994429542215115063285947854223135441940429853239874487883145319927874307379 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.29994429542215115063285947854223135441940429853239874487883145319927874307379
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.88744119528235325747320116098799131234671900600584278396526985294513367335186
Short name T182
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:48:31 PM PDT 23
Peak memory 201088 kb
Host smart-14ac823f-d095-401b-9803-70885b856080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88744119528235325747320116098799131234671900600584278396526985294513367335186 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.88744119528235325747320116098799131234671900600584278396526985294513367335186
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.29553006259413212383136025491276720390340993912358001905833762226265407002158
Short name T672
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 18 12:48:05 PM PDT 23
Finished Oct 18 12:48:10 PM PDT 23
Peak memory 201052 kb
Host smart-cbe63824-d5bd-43f8-9da0-6b3545fc6abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29553006259413212383136025491276720390340993912358001905833762226265407002158 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.29553006259413212383136025491276720390340993912358001905833762226265407002158
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.35240820799036687504136924822513985863786432569943656358742200405801890313396
Short name T474
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 18 12:48:23 PM PDT 23
Finished Oct 18 12:48:27 PM PDT 23
Peak memory 201156 kb
Host smart-205116fd-8ad5-4232-9937-a5b2ac170cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35240820799036687504136924822513985863786432569943656358742200405801890313396 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_smoke.35240820799036687504136924822513985863786432569943656358742200405801890313396
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.38292997245035551645996214915210226860645463270712831968929897199574959810389
Short name T274
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.19 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:50:37 PM PDT 23
Peak memory 201420 kb
Host smart-c4029434-b9c8-45fc-a53d-75fa1757cedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38292997245035551645996214915210226860645463270712831968929897199574959810389 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.38292997245035551645996214915210226860645463270712831968929897199574959810389
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.51758796551992559849850584775075862246068293445119671868647052377774924021054
Short name T578
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Oct 18 12:48:23 PM PDT 23
Finished Oct 18 12:48:28 PM PDT 23
Peak memory 201104 kb
Host smart-b5ec31ab-1ac7-441e-8390-bcf1331d4890
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51758796551992559849850584775075862246068293445119671868647052377774924021054 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.517587965519925598498505847750758622460682934451196718686470
52377774924021054
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.18453047575955743101543258096486313822499271879806899547736289873746065458898
Short name T265
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 18 12:48:05 PM PDT 23
Finished Oct 18 12:48:09 PM PDT 23
Peak memory 201220 kb
Host smart-25edfb77-e064-427c-897b-e22b07f49eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453047575955743101543258096486313822499271879806899547736289873746065458898 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.18453047575955743101543258096486313822499271879806899547736289873746065458898
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.88122270362729571961447526801190575396935688647299540809034517015746460905177
Short name T145
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:41 PM PDT 23
Peak memory 201184 kb
Host smart-fafdae00-b26c-4087-a0d5-543b5cc35d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88122270362729571961447526801190575396935688647299540809034517015746460905177 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.88122270362729571961447526801190575396935688647299540809034517015746460905177
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.81296602160348181252229193785127104971693225044210310663361246157862442951602
Short name T185
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.38 seconds
Started Oct 18 12:48:23 PM PDT 23
Finished Oct 18 12:51:24 PM PDT 23
Peak memory 201368 kb
Host smart-645c0fa8-4b9b-4ac3-a6c4-84ea307cea62
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81296602160348181252229193785127104971693225044210310663361246157862442951602 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.81296602160348181252229193785127104971693225044210310663361246
157862442951602
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.64517280097718181413339952017411793706993776115803619847067871506529863095771
Short name T630
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.54 seconds
Started Oct 18 12:48:31 PM PDT 23
Finished Oct 18 12:48:39 PM PDT 23
Peak memory 201412 kb
Host smart-74dd55b0-5d86-4c3f-b77b-616fd353a29e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64517280097718181413339952017411793706993776115803619847067871506529863095771 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.645172800977181814133399520174117937069937761158036198470678
71506529863095771
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.76502166975293429277396211457354471169488280570000821093113586643687656115675
Short name T266
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 18 12:48:38 PM PDT 23
Finished Oct 18 12:48:44 PM PDT 23
Peak memory 201128 kb
Host smart-f588c63c-dc47-4610-a529-b77900545539
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76502166975293429277396211457354471169488280570000821093113586643687656115675 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.7650216697529342927739621145735447116948828057000082109311358664
3687656115675
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.14820676037740747590262631640294433661646398545406353970574026769497757906264
Short name T166
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 18 12:48:24 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201140 kb
Host smart-7c885e42-91b6-4db9-9871-2c93a535fda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14820676037740747590262631640294433661646398545406353970574026769497757906264 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.14820676037740747590262631640294433661646398545406353970574026769497757906264
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.106137265040101895528020533831585848344527106526008143170319216605739127645927
Short name T154
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Oct 18 12:48:06 PM PDT 23
Finished Oct 18 12:48:12 PM PDT 23
Peak memory 201236 kb
Host smart-1021b72c-dd64-4c98-9d8b-5a4992ee029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106137265040101895528020533831585848344527106526008143170319216605739127645927 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.106137265040101895528020533831585848344527106526008143170319216605739127645927
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.15893024987338386208637080638961460217646335522826148042640117435837097914691
Short name T146
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 18 12:48:11 PM PDT 23
Finished Oct 18 12:48:15 PM PDT 23
Peak memory 201168 kb
Host smart-f114b564-017c-4d56-9a1c-137f0000dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15893024987338386208637080638961460217646335522826148042640117435837097914691 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.15893024987338386208637080638961460217646335522826148042640117435837097914691
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.48887359316418766508502578511208728791439351546124765493236334747925933402568
Short name T262
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Oct 18 12:48:21 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201100 kb
Host smart-0f74d3a1-009c-4087-9785-41835852f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48887359316418766508502578511208728791439351546124765493236334747925933402568 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.48887359316418766508502578511208728791439351546124765493236334747925933402568
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.35313691281025259521732295182255824690573853724015495519232474934910066012550
Short name T450
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:48:26 PM PDT 23
Peak memory 201136 kb
Host smart-cca68d31-0661-41c4-84d2-112f232f4357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35313691281025259521732295182255824690573853724015495519232474934910066012550 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_smoke.35313691281025259521732295182255824690573853724015495519232474934910066012550
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.19743426001943160287127469117037570152916999243076579446105600599637455857717
Short name T128
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.29 seconds
Started Oct 18 12:48:20 PM PDT 23
Finished Oct 18 12:50:38 PM PDT 23
Peak memory 201496 kb
Host smart-386a728f-a0d8-47b3-b99e-4a21e889070a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19743426001943160287127469117037570152916999243076579446105600599637455857717 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.19743426001943160287127469117037570152916999243076579446105600599637455857717
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.97818401593552423998858279021146248642956786358647649715808574476784909161249
Short name T344
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 18 12:48:11 PM PDT 23
Finished Oct 18 12:48:16 PM PDT 23
Peak memory 201120 kb
Host smart-6c8ef8ee-d5e7-47a8-97f7-8c8ccedd36d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97818401593552423998858279021146248642956786358647649715808574476784909161249 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.978184015935524239988582790211462486429567863586476497158085
74476784909161249
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.59026310935907038391711808234501405569164600489406700197922696281748021867756
Short name T455
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:46:51 PM PDT 23
Finished Oct 18 12:46:55 PM PDT 23
Peak memory 201144 kb
Host smart-c5e01a12-1fd5-441b-9361-f8a89ad3b6e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59026310935907038391711808234501405569164600489406700197922696281748021867756 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.59026310935907038391711808234501405569164600489406700197922696281748021867756
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.34333643894398748890855617064005422957540276795405881204997361411036312973170
Short name T495
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 18 12:47:08 PM PDT 23
Finished Oct 18 12:47:14 PM PDT 23
Peak memory 201268 kb
Host smart-cc722a7e-fd0d-4468-8bdd-c3a4e2d2f97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34333643894398748890855617064005422957540276795405881204997361411036312973170 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.34333643894398748890855617064005422957540276795405881204997361411036312973170
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.73507964949434440144603321778729682508825532164535210091929795796479051175884
Short name T333
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.39 seconds
Started Oct 18 12:47:07 PM PDT 23
Finished Oct 18 12:50:07 PM PDT 23
Peak memory 201352 kb
Host smart-0fafec75-49d0-4ffe-a3bf-2a92cfed350b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73507964949434440144603321778729682508825532164535210091929795796479051175884 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.735079649494344401446033217787296825088255321645352100919297957
96479051175884
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.105733261391658126605873052128898708573336005222654437104404963426822467710945
Short name T650
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.33 seconds
Started Oct 18 12:46:55 PM PDT 23
Finished Oct 18 12:47:00 PM PDT 23
Peak memory 201264 kb
Host smart-5945948c-f001-49f4-bad8-0b9474a54f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105733261391658126605873052128898708573336005222654437104404963426822467710945 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.105733261391658126605873052128898708573336005222654437104404963426822467710945
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.60664573616171827595946118299072596082898200835932441481165506025313361694897
Short name T113
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.57 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:02 PM PDT 23
Peak memory 201136 kb
Host smart-cde38d8d-a5a8-4ea8-9531-15f038915831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60664573616171827595946118299072596082898200835932441481165506025313361694897 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.60664573616171827595946118299072596082898200835932441
481165506025313361694897
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.40704884544718742634261373700898131157305198639648303779683962852117535374758
Short name T108
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Oct 18 12:46:58 PM PDT 23
Finished Oct 18 12:47:06 PM PDT 23
Peak memory 201164 kb
Host smart-45084fd7-39ec-4c69-b50e-24e040f20d0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40704884544718742634261373700898131157305198639648303779683962852117535374758 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.4070488454471874263426137370089813115730519863964830377968396
2852117535374758
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.91107255342555466401916869940922266378553152946137902372187709709418956736422
Short name T549
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.35 seconds
Started Oct 18 12:46:55 PM PDT 23
Finished Oct 18 12:47:02 PM PDT 23
Peak memory 201172 kb
Host smart-9c646c91-1292-4917-8762-b56b9a618292
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91107255342555466401916869940922266378553152946137902372187709709418956736422 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.91107255342555466401916869940922266378553152946137902372187709709418956736422
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.20342140792826793968552124525068662890866288562887184433842681015001378789311
Short name T198
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.73 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201152 kb
Host smart-b3bfd5d5-2edb-485a-b494-74c90e45aad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20342140792826793968552124525068662890866288562887184433842681015001378789311 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.20342140792826793968552124525068662890866288562887184433842681015001378789311
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.94002388558629091113149163907551692528861121349665902663234070120105375041121
Short name T301
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201200 kb
Host smart-df7ffb01-5241-4491-bd6c-627bcaede184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94002388558629091113149163907551692528861121349665902663234070120105375041121 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.94002388558629091113149163907551692528861121349665902663234070120105375041121
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1948988467404063029285072882483922484686179135589821073087934242582685803526
Short name T429
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 18 12:46:56 PM PDT 23
Finished Oct 18 12:47:00 PM PDT 23
Peak memory 201124 kb
Host smart-21f09b7b-a84b-42f6-95ca-46e476651568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948988467404063029285072882483922484686179135589821073087934242582685803526 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.1948988467404063029285072882483922484686179135589821073087934242582685803526
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.52221722885748850386314377018481493204786171352778776381001169190739179816537
Short name T223
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 18 12:46:52 PM PDT 23
Finished Oct 18 12:46:57 PM PDT 23
Peak memory 201256 kb
Host smart-ad0ba2a4-ffdb-4077-8d22-f9aa983bb93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52221722885748850386314377018481493204786171352778776381001169190739179816537 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.52221722885748850386314377018481493204786171352778776381001169190739179816537
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.8094094097363282407619918661540840648983932088345101877745194869445999103812
Short name T139
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.66 seconds
Started Oct 18 12:47:02 PM PDT 23
Finished Oct 18 12:48:08 PM PDT 23
Peak memory 221636 kb
Host smart-5514d523-ae20-48dd-aa1f-53fc90574230
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8094094097363282407619918661540840648983932088345101877745194869445999103812 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.8094094097363282407619918661540840648983932088345101877745194869445999103812
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.34061506579211328047275434566270735318828986837658135403369636542731133394270
Short name T412
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201052 kb
Host smart-9ea3d83f-cd6e-4638-96b4-5a5554dd3903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34061506579211328047275434566270735318828986837658135403369636542731133394270 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sysrst_ctrl_smoke.34061506579211328047275434566270735318828986837658135403369636542731133394270
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.106541219328573767352731901196338310696864027156563470109369333738935690931824
Short name T662
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.29 seconds
Started Oct 18 12:47:02 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201412 kb
Host smart-d57771d3-0ae3-4969-8ed5-11b5a4ef0ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106541219328573767352731901196338310696864027156563470109369333738935690931824 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.106541219328573767352731901196338310696864027156563470109369333738935690931824
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.7295024233634032889979595970753360785366006028409497415429248716993104440584
Short name T270
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:50 PM PDT 23
Peak memory 201236 kb
Host smart-72fb1306-4ec8-41ac-91d3-87a4656dd55d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7295024233634032889979595970753360785366006028409497415429248716993104440584 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.7295024233634032889979595970753360785366006028409497415429248716993104440584
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.47805592972013715311370812085104199992282327898833786989470481434135784810048
Short name T253
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:48:33 PM PDT 23
Peak memory 201232 kb
Host smart-397ea0cf-88c7-4eed-a87e-cfcb9bfeb86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47805592972013715311370812085104199992282327898833786989470481434135784810048 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.47805592972013715311370812085104199992282327898833786989470481434135784810048
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.56117929001357500950494158608381389837149045366831872452625649621848171044186
Short name T653
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.53 seconds
Started Oct 18 12:48:41 PM PDT 23
Finished Oct 18 12:51:41 PM PDT 23
Peak memory 201432 kb
Host smart-bcb1dc41-2fc9-47fc-93f0-7fc8c6e5643a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56117929001357500950494158608381389837149045366831872452625649621848171044186 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.56117929001357500950494158608381389837149045366831872452625649
621848171044186
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.86848636779266980260670142320536471692859600035985129586276330802159391820482
Short name T142
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Oct 18 12:48:40 PM PDT 23
Finished Oct 18 12:48:48 PM PDT 23
Peak memory 201228 kb
Host smart-8b75b556-887f-491d-9f4b-34dd317ba15a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86848636779266980260670142320536471692859600035985129586276330802159391820482 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.868486367792669802606701423205364716928596000359851295862763
30802159391820482
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.85276891484123784245266863852694109728213542346898169130832943000645119349343
Short name T122
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.37 seconds
Started Oct 18 12:48:39 PM PDT 23
Finished Oct 18 12:48:46 PM PDT 23
Peak memory 201120 kb
Host smart-a8d55647-5baa-41db-98b2-9ff8a0c1283c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85276891484123784245266863852694109728213542346898169130832943000645119349343 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.8527689148412378424526686385269410972821354234689816913083294300
0645119349343
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.16206379649961900946112734131145020555510374894148576812425341304772575377054
Short name T503
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.77 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201136 kb
Host smart-8329674b-1c8e-4784-80a7-e9378119431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16206379649961900946112734131145020555510374894148576812425341304772575377054 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.16206379649961900946112734131145020555510374894148576812425341304772575377054
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.87293921845706868014653256035317152557305799879925137121595392845485822425013
Short name T338
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.72 seconds
Started Oct 18 12:48:19 PM PDT 23
Finished Oct 18 12:48:25 PM PDT 23
Peak memory 201236 kb
Host smart-8783b5d7-7772-4494-865f-4f2a5ff87bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87293921845706868014653256035317152557305799879925137121595392845485822425013 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.87293921845706868014653256035317152557305799879925137121595392845485822425013
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.6066601622778485459466218727265526228553454798864626677055895999145287690010
Short name T407
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 18 12:48:29 PM PDT 23
Finished Oct 18 12:48:33 PM PDT 23
Peak memory 201092 kb
Host smart-eca2ac1d-60f1-4a21-bcc0-e6f0ce4cc5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6066601622778485459466218727265526228553454798864626677055895999145287690010 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.6066601622778485459466218727265526228553454798864626677055895999145287690010
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.74620372065969551603360437676698024894566278741297443682199029327588770557299
Short name T573
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201228 kb
Host smart-f9596032-4570-4f34-bba5-6e14fb8a207c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74620372065969551603360437676698024894566278741297443682199029327588770557299 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.74620372065969551603360437676698024894566278741297443682199029327588770557299
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.109869801078690577938143067824931032084207396851459423198289857751837144239778
Short name T171
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 18 12:48:44 PM PDT 23
Finished Oct 18 12:48:48 PM PDT 23
Peak memory 201072 kb
Host smart-2cb7ad6d-6ad0-4f6e-8222-13b933c522b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109869801078690577938143067824931032084207396851459423198289857751837144239778 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 30.sysrst_ctrl_smoke.109869801078690577938143067824931032084207396851459423198289857751837144239778
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.97112924240667334868611106383098464485483142850370687673294521055872694929433
Short name T205
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.33 seconds
Started Oct 18 12:48:27 PM PDT 23
Finished Oct 18 12:50:44 PM PDT 23
Peak memory 201520 kb
Host smart-e1b2e546-bdbf-47a2-b341-f1c37a078058
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97112924240667334868611106383098464485483142850370687673294521055872694929433 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.97112924240667334868611106383098464485483142850370687673294521055872694929433
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.16103424534598025664622123649614142840843723221648388573658779841974445297093
Short name T267
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Oct 18 12:48:57 PM PDT 23
Finished Oct 18 12:49:02 PM PDT 23
Peak memory 201212 kb
Host smart-5c06aa3e-9058-4881-8dfe-55f05436c480
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16103424534598025664622123649614142840843723221648388573658779841974445297093 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.161034245345980256646221236496141428408437232216483885736587
79841974445297093
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.3523045143275768766630070777001592753508924093448921370489309594500467087281
Short name T500
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:48:56 PM PDT 23
Peak memory 201216 kb
Host smart-bf78b0bf-9ec6-48c8-b9c8-d6128ba2fa92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523045143275768766630070777001592753508924093448921370489309594500467087281 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.3523045143275768766630070777001592753508924093448921370489309594500467087281
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.78721074595401986230796061564332158009084985034581644516533872646325503297731
Short name T648
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 18 12:48:30 PM PDT 23
Finished Oct 18 12:48:36 PM PDT 23
Peak memory 201304 kb
Host smart-452936b5-87df-40e9-9bd6-8da5e05e29dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78721074595401986230796061564332158009084985034581644516533872646325503297731 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.78721074595401986230796061564332158009084985034581644516533872646325503297731
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.65736405136666171685668690430695660393372536229042717952670528036739434429757
Short name T179
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.21 seconds
Started Oct 18 12:49:03 PM PDT 23
Finished Oct 18 12:52:03 PM PDT 23
Peak memory 201460 kb
Host smart-1c6fcf03-ab6f-4d1e-9b2f-d4e24cf978eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65736405136666171685668690430695660393372536229042717952670528036739434429757 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.65736405136666171685668690430695660393372536229042717952670528
036739434429757
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.44829382985183019923222183073504191271465932098810905868601155346827917411264
Short name T234
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:46 PM PDT 23
Finished Oct 18 12:48:54 PM PDT 23
Peak memory 201272 kb
Host smart-d1bb9066-1947-4c4a-b873-1a79dad51fc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44829382985183019923222183073504191271465932098810905868601155346827917411264 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.448293829851830199232221830735041912714659320988109058686011
55346827917411264
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.88576545033428475618430120170207764404326135198417501340431709065479599102175
Short name T203
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201224 kb
Host smart-84296fc5-cd26-4485-b0c4-f8a0ba79e1af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88576545033428475618430120170207764404326135198417501340431709065479599102175 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.8857654503342847561843012017020776440432613519841750134043170906
5479599102175
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.64594156204226513921273270801653759665686416230957489385111583483208953182771
Short name T505
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Oct 18 12:48:24 PM PDT 23
Finished Oct 18 12:48:29 PM PDT 23
Peak memory 201212 kb
Host smart-9eec5aa4-9912-4ff9-86df-eb5adc406ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64594156204226513921273270801653759665686416230957489385111583483208953182771 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.64594156204226513921273270801653759665686416230957489385111583483208953182771
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.66990440380228643985689535440994002701957925579316453328336444935313219803586
Short name T305
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:51 PM PDT 23
Peak memory 201276 kb
Host smart-534e1d77-57f6-4e0c-af55-553910392db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66990440380228643985689535440994002701957925579316453328336444935313219803586 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.66990440380228643985689535440994002701957925579316453328336444935313219803586
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.103737554645337830742454996221861585344287796750647015212230544603479675145783
Short name T545
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 18 12:48:47 PM PDT 23
Finished Oct 18 12:48:51 PM PDT 23
Peak memory 201068 kb
Host smart-ec058247-3de1-4247-8990-cce03710daa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103737554645337830742454996221861585344287796750647015212230544603479675145783 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.103737554645337830742454996221861585344287796750647015212230544603479675145783
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.42877851227575042092768995125999590107833841122521521528415702473212281255746
Short name T664
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:48:57 PM PDT 23
Peak memory 201228 kb
Host smart-e8158459-1382-4da3-922f-b95f283ac613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42877851227575042092768995125999590107833841122521521528415702473212281255746 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.42877851227575042092768995125999590107833841122521521528415702473212281255746
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.84118739297284492335599686993019588125972585019057632667407814530312199080862
Short name T535
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 18 12:48:34 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201144 kb
Host smart-84abe956-37a3-4aa3-9a55-e533f2f5f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84118739297284492335599686993019588125972585019057632667407814530312199080862 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_smoke.84118739297284492335599686993019588125972585019057632667407814530312199080862
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.105726029139886040470759914191684369151419541796671073453504794241674241156134
Short name T435
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.04 seconds
Started Oct 18 12:48:42 PM PDT 23
Finished Oct 18 12:50:58 PM PDT 23
Peak memory 201400 kb
Host smart-a4398176-f5f8-43c9-84c7-9833ff305829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105726029139886040470759914191684369151419541796671073453504794241674241156134 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.105726029139886040470759914191684369151419541796671073453504794241674241156134
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.86825489215662357992433420820143563907443713267013337800286893439855316283142
Short name T347
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Oct 18 12:49:00 PM PDT 23
Finished Oct 18 12:49:05 PM PDT 23
Peak memory 201196 kb
Host smart-4500eab9-2810-466a-8650-793586b06c8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86825489215662357992433420820143563907443713267013337800286893439855316283142 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.868254892156623579924334208201435639074437132670133378002868
93439855316283142
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.64406344306519071826028295586426476544566843772702048955369715111581676606959
Short name T442
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.78 seconds
Started Oct 18 12:49:07 PM PDT 23
Finished Oct 18 12:49:11 PM PDT 23
Peak memory 201220 kb
Host smart-03367182-d7fa-456b-84df-c558ca4b3e9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64406344306519071826028295586426476544566843772702048955369715111581676606959 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.64406344306519071826028295586426476544566843772702048955369715111581676606959
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.19672502049365157341073159005972754853591764753544976707229092990953567324987
Short name T103
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 18 12:48:41 PM PDT 23
Finished Oct 18 12:48:47 PM PDT 23
Peak memory 201308 kb
Host smart-6f51f107-da33-4610-b2c4-2172b85017c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19672502049365157341073159005972754853591764753544976707229092990953567324987 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.19672502049365157341073159005972754853591764753544976707229092990953567324987
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.30262216955930250473845139076666666278370559900433564187712723285626125458936
Short name T437
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.55 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:51:53 PM PDT 23
Peak memory 201456 kb
Host smart-69db1871-7fdc-44cd-97ed-62324c2e5a8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30262216955930250473845139076666666278370559900433564187712723285626125458936 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.30262216955930250473845139076666666278370559900433564187712723
285626125458936
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.64335646829516147058942184426906347904309440945056025272158168322635585138526
Short name T302
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:51 PM PDT 23
Finished Oct 18 12:48:59 PM PDT 23
Peak memory 201228 kb
Host smart-11342e1f-0ab3-4e99-8eec-0285c126868f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64335646829516147058942184426906347904309440945056025272158168322635585138526 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.643356468295161470589421844269063479043094409450560252721581
68322635585138526
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.30966525487521981929804242726955556217516489203751725063924256641627203324260
Short name T480
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Oct 18 12:48:54 PM PDT 23
Finished Oct 18 12:49:00 PM PDT 23
Peak memory 201224 kb
Host smart-972b0930-12ac-4b2e-b2c8-cb2776ba2f8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30966525487521981929804242726955556217516489203751725063924256641627203324260 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.3096652548752198192980424272695555621751648920375172506392425664
1627203324260
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.91211405319845096496262990610558605193111234385928476822212122600097847755727
Short name T156
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:48:37 PM PDT 23
Peak memory 201212 kb
Host smart-fc81f235-fa25-4e2e-a5cb-0e93d53538d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91211405319845096496262990610558605193111234385928476822212122600097847755727 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.91211405319845096496262990610558605193111234385928476822212122600097847755727
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.9572347496284742850878190140841253941096214682450216749338588879994090460423
Short name T106
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.85 seconds
Started Oct 18 12:48:54 PM PDT 23
Finished Oct 18 12:49:00 PM PDT 23
Peak memory 201268 kb
Host smart-e292156a-4db5-40c5-8565-32cb1288f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9572347496284742850878190140841253941096214682450216749338588879994090460423 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.9572347496284742850878190140841253941096214682450216749338588879994090460423
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.83512604023636525315000497272368210597313286985691527518517537313124237377849
Short name T294
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:50 PM PDT 23
Peak memory 201148 kb
Host smart-34e72d05-388b-43e2-be47-b5bbc86ef7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83512604023636525315000497272368210597313286985691527518517537313124237377849 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.83512604023636525315000497272368210597313286985691527518517537313124237377849
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.2030143845793744602288116828931588062103929238061814453259583842141877153644
Short name T277
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201216 kb
Host smart-4aba7e96-0a0c-4ff3-96dc-1d7facd621da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030143845793744602288116828931588062103929238061814453259583842141877153644 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2030143845793744602288116828931588062103929238061814453259583842141877153644
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.104272624708822156430643685811738054556636420775583553487593434011879036683092
Short name T447
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Oct 18 12:48:34 PM PDT 23
Finished Oct 18 12:48:38 PM PDT 23
Peak memory 201172 kb
Host smart-84cc3c70-6843-426d-a5b8-d1efb54e3101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104272624708822156430643685811738054556636420775583553487593434011879036683092 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 32.sysrst_ctrl_smoke.104272624708822156430643685811738054556636420775583553487593434011879036683092
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.108367809370300552368147312432697684369921218310474000141428995405873954597533
Short name T638
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.68 seconds
Started Oct 18 12:49:09 PM PDT 23
Finished Oct 18 12:51:23 PM PDT 23
Peak memory 201484 kb
Host smart-10d80cd1-2bb0-4a62-91f2-b0752de4f100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108367809370300552368147312432697684369921218310474000141428995405873954597533 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.108367809370300552368147312432697684369921218310474000141428995405873954597533
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.19981174974586332816704344087130594242961022603075232414240840785618350198793
Short name T431
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201240 kb
Host smart-f0f08efe-88c0-4723-a0db-1aec83988cad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981174974586332816704344087130594242961022603075232414240840785618350198793 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.199811749745863328167043440871305942429610226030752324142408
40785618350198793
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.63418894276808657235026439675668067861270210669982032502751959720750928250469
Short name T44
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:48:54 PM PDT 23
Finished Oct 18 12:48:58 PM PDT 23
Peak memory 201296 kb
Host smart-441f3f70-a00e-498b-911c-2e6792d65b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63418894276808657235026439675668067861270210669982032502751959720750928250469 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.63418894276808657235026439675668067861270210669982032502751959720750928250469
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.97090495911837365084403230709360091054378536552965229040885440846666235282152
Short name T468
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 18 12:49:04 PM PDT 23
Finished Oct 18 12:49:10 PM PDT 23
Peak memory 201184 kb
Host smart-7a4f630c-b348-4296-9e61-7fd8d2b5cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97090495911837365084403230709360091054378536552965229040885440846666235282152 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.97090495911837365084403230709360091054378536552965229040885440846666235282152
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.82984213197432599273775285168118980669103222144781389646077436150727243371568
Short name T427
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.21 seconds
Started Oct 18 12:48:49 PM PDT 23
Finished Oct 18 12:51:50 PM PDT 23
Peak memory 201380 kb
Host smart-a4913d71-0523-413e-a653-27efe7e51faf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82984213197432599273775285168118980669103222144781389646077436150727243371568 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.82984213197432599273775285168118980669103222144781389646077436
150727243371568
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.93394184795317551045216323410706172397846484514838894974706450672376618210309
Short name T219
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Oct 18 12:48:37 PM PDT 23
Finished Oct 18 12:48:45 PM PDT 23
Peak memory 201164 kb
Host smart-70252d78-0ec9-4056-a89a-74faee2a2fdb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93394184795317551045216323410706172397846484514838894974706450672376618210309 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.933941847953175510452163234107061723978464845148388949747064
50672376618210309
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.87905675879274073729076356142818719024362806779992168593158229583262233450885
Short name T510
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.4 seconds
Started Oct 18 12:48:48 PM PDT 23
Finished Oct 18 12:48:55 PM PDT 23
Peak memory 201228 kb
Host smart-59b237a3-fc98-44bc-a624-365f5184af55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87905675879274073729076356142818719024362806779992168593158229583262233450885 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.8790567587927407372907635614281871902436280677999216859315822958
3262233450885
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.101399141091838292739284407494554706783207335858217404278445353556959981833411
Short name T415
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201136 kb
Host smart-ff055fa5-8cb9-4dae-bd16-52b9c9cb081c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101399141091838292739284407494554706783207335858217404278445353556959981833411 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.101399141091838292739284407494554706783207335858217404278445353556959981833411
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.38364568512333770126385216622737734040038112937358472528171413602478289081006
Short name T114
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.95 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:41 PM PDT 23
Peak memory 201244 kb
Host smart-a5a23243-0b1d-478d-aa4d-cd229ea08979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38364568512333770126385216622737734040038112937358472528171413602478289081006 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.38364568512333770126385216622737734040038112937358472528171413602478289081006
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.20557488244655488194235200436006305893273937092150343581577365914422349246125
Short name T329
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.83 seconds
Started Oct 18 12:48:37 PM PDT 23
Finished Oct 18 12:48:41 PM PDT 23
Peak memory 201172 kb
Host smart-7e3789e2-a094-4161-9ba3-d1488bdcadb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20557488244655488194235200436006305893273937092150343581577365914422349246125 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.20557488244655488194235200436006305893273937092150343581577365914422349246125
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.54972601098239584170062695221056369523814539769265089556978544110217724750209
Short name T428
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201208 kb
Host smart-bbea7422-9bee-45f7-b5a4-eb91d4bc4545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54972601098239584170062695221056369523814539769265089556978544110217724750209 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.54972601098239584170062695221056369523814539769265089556978544110217724750209
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.110030940089689152935381004875098838096685094153750092758223639734014544187224
Short name T155
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:48:36 PM PDT 23
Peak memory 201176 kb
Host smart-3c5b80dd-c85e-42fc-a1f2-16df72df9cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110030940089689152935381004875098838096685094153750092758223639734014544187224 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 33.sysrst_ctrl_smoke.110030940089689152935381004875098838096685094153750092758223639734014544187224
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.96702525865807032521551516870732305072608166541802377619948336024797147430888
Short name T645
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.17 seconds
Started Oct 18 12:48:32 PM PDT 23
Finished Oct 18 12:50:51 PM PDT 23
Peak memory 201412 kb
Host smart-d53037b1-0204-4c64-beb7-8d8017fad2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96702525865807032521551516870732305072608166541802377619948336024797147430888 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.96702525865807032521551516870732305072608166541802377619948336024797147430888
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.75070862394185031434253619125473185913569783966022857076048676534929507357318
Short name T290
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Oct 18 12:48:43 PM PDT 23
Finished Oct 18 12:48:49 PM PDT 23
Peak memory 201212 kb
Host smart-f897e541-3be4-4dc3-9a0d-75ab19c7421b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75070862394185031434253619125473185913569783966022857076048676534929507357318 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.750708623941850314342536191254731859135697839660228570760486
76534929507357318
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.67367431448367645861520159974238418367210852745419733353388569757059399580850
Short name T271
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 18 12:48:48 PM PDT 23
Finished Oct 18 12:48:52 PM PDT 23
Peak memory 201188 kb
Host smart-c4910e9b-3ff9-455d-b2cb-85d4424a261c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67367431448367645861520159974238418367210852745419733353388569757059399580850 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.67367431448367645861520159974238418367210852745419733353388569757059399580850
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.88218315143493961178710428003211529025554076856251863869514709048816351919151
Short name T249
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:52 PM PDT 23
Peak memory 201156 kb
Host smart-d94706af-2e11-4ca1-a025-657ee30b35f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88218315143493961178710428003211529025554076856251863869514709048816351919151 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.88218315143493961178710428003211529025554076856251863869514709048816351919151
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.100291443457109155060311578568824459362306682530155752006979464546404488373645
Short name T354
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.18 seconds
Started Oct 18 12:49:01 PM PDT 23
Finished Oct 18 12:52:03 PM PDT 23
Peak memory 201476 kb
Host smart-c37d4812-39d3-4cfe-8017-34dd52f030a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100291443457109155060311578568824459362306682530155752006979464546404488373645 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.1002914434571091550603115785688244593623066825301557520069794
64546404488373645
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.36129757896444506616865619605409824131307253586311259082515101947674279625818
Short name T554
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.27 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:49:00 PM PDT 23
Peak memory 201148 kb
Host smart-1822e8ac-2273-487d-a785-0b01d3ff79f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36129757896444506616865619605409824131307253586311259082515101947674279625818 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.361297578964445066168656196054098241313072535863112590825151
01947674279625818
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.108626399730957359822614425093054175139368135053294659745502918471620044832034
Short name T35
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:53 PM PDT 23
Peak memory 201212 kb
Host smart-38fd6b42-587a-404c-88df-935bb1c59d8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108626399730957359822614425093054175139368135053294659745502918471620044832034 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.108626399730957359822614425093054175139368135053294659745502918
471620044832034
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.6527437800781475268830924673362381100697954084234450262731709276071133110134
Short name T581
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 18 12:48:37 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201220 kb
Host smart-00c6487b-23ee-4750-82cd-9a0b9aea2db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6527437800781475268830924673362381100697954084234450262731709276071133110134 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.6527437800781475268830924673362381100697954084234450262731709276071133110134
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.112002503315076350626552412277971328249359608052524242626404734629645762360266
Short name T519
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 18 12:49:10 PM PDT 23
Finished Oct 18 12:49:16 PM PDT 23
Peak memory 201272 kb
Host smart-ff087faf-8375-4f56-9f6c-93a986186e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112002503315076350626552412277971328249359608052524242626404734629645762360266 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.112002503315076350626552412277971328249359608052524242626404734629645762360266
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.89950006982779973559069161947808700180650802484929556277709605374875919264849
Short name T309
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 18 12:48:54 PM PDT 23
Finished Oct 18 12:48:59 PM PDT 23
Peak memory 201172 kb
Host smart-ee5c4bf9-d060-4361-b56e-b22806c0159c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89950006982779973559069161947808700180650802484929556277709605374875919264849 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.89950006982779973559069161947808700180650802484929556277709605374875919264849
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.57279801024711511685457429552289254529825750354471385887723066125357367823381
Short name T386
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.49 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201248 kb
Host smart-7600f5d8-48e9-46d6-8b48-c5a7d8bc146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57279801024711511685457429552289254529825750354471385887723066125357367823381 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.57279801024711511685457429552289254529825750354471385887723066125357367823381
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.6844159957536458601854130687797683636053704288220346295712156378627514377093
Short name T659
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201152 kb
Host smart-64673165-2905-41b3-bbd2-c481f81751db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6844159957536458601854130687797683636053704288220346295712156378627514377093 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sysrst_ctrl_smoke.6844159957536458601854130687797683636053704288220346295712156378627514377093
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.112259826726514186773493789535566040186637397892793687074145716804281845622646
Short name T16
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.25 seconds
Started Oct 18 12:48:48 PM PDT 23
Finished Oct 18 12:51:04 PM PDT 23
Peak memory 201428 kb
Host smart-07f95937-962e-41fb-bd42-b9899b0fca1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112259826726514186773493789535566040186637397892793687074145716804281845622646 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.112259826726514186773493789535566040186637397892793687074145716804281845622646
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.107948088161587411287583559890267361998834340216926683624582970680015638758622
Short name T507
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 18 12:48:47 PM PDT 23
Finished Oct 18 12:48:53 PM PDT 23
Peak memory 201192 kb
Host smart-7258cc6e-0dad-4c7b-8b61-f85881bd02b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107948088161587411287583559890267361998834340216926683624582970680015638758622 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.10794808816158741128758355989026736199883434021692668362458
2970680015638758622
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.17123193589270745348306160199888393797397030478825940961329703706019684708608
Short name T515
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 18 12:48:42 PM PDT 23
Finished Oct 18 12:48:47 PM PDT 23
Peak memory 201228 kb
Host smart-a7a849b6-e0f7-4dc3-a57b-dd70242d6a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17123193589270745348306160199888393797397030478825940961329703706019684708608 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.17123193589270745348306160199888393797397030478825940961329703706019684708608
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.71611803180401276282482041716933787426160030278862986262695251081997719069628
Short name T214
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 18 12:48:49 PM PDT 23
Finished Oct 18 12:48:55 PM PDT 23
Peak memory 201308 kb
Host smart-fea79947-f869-4839-9784-7983dd63046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71611803180401276282482041716933787426160030278862986262695251081997719069628 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.71611803180401276282482041716933787426160030278862986262695251081997719069628
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.23844510978284312558961795499629765475954465080502205440858077665208980764638
Short name T527
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.02 seconds
Started Oct 18 12:48:42 PM PDT 23
Finished Oct 18 12:51:48 PM PDT 23
Peak memory 201456 kb
Host smart-0b2c6761-adec-402c-bb80-d860d13f7b91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23844510978284312558961795499629765475954465080502205440858077665208980764638 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.23844510978284312558961795499629765475954465080502205440858077
665208980764638
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.39127388968879345967155281176913485199654641568415475147430780920887581473362
Short name T212
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 18 12:48:47 PM PDT 23
Finished Oct 18 12:48:54 PM PDT 23
Peak memory 201252 kb
Host smart-ace23b3d-da2c-462c-9aa7-c2f7b29b2adc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39127388968879345967155281176913485199654641568415475147430780920887581473362 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.391273889688793459671552811769134851996546415684154751474307
80920887581473362
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.88013976777984613237279007975044215886248541205200708133823050399396243009228
Short name T644
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.36 seconds
Started Oct 18 12:48:57 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201224 kb
Host smart-5bac3310-a2e3-4f48-979a-5aafe85dd264
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88013976777984613237279007975044215886248541205200708133823050399396243009228 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.8801397677798461323727900797504421588624854120520070813382305039
9396243009228
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.105793786216821479723083319870586945156232433739805951233348153112023685508192
Short name T481
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 18 12:49:01 PM PDT 23
Finished Oct 18 12:49:06 PM PDT 23
Peak memory 201248 kb
Host smart-6ff54f5a-9316-4011-bade-c5bad6a3fede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105793786216821479723083319870586945156232433739805951233348153112023685508192 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.105793786216821479723083319870586945156232433739805951233348153112023685508192
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.39836369793311738777478429640289025498611157258268809380339985841159668205290
Short name T498
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Oct 18 12:48:38 PM PDT 23
Finished Oct 18 12:48:43 PM PDT 23
Peak memory 201236 kb
Host smart-194be71b-a86e-4f6d-8df8-ff712c1506ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39836369793311738777478429640289025498611157258268809380339985841159668205290 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.39836369793311738777478429640289025498611157258268809380339985841159668205290
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.107687112095299995463266177691903236887214980892902760705790826344054150588853
Short name T119
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.82 seconds
Started Oct 18 12:48:48 PM PDT 23
Finished Oct 18 12:48:52 PM PDT 23
Peak memory 201280 kb
Host smart-50368192-4246-49dc-aee4-e44c7763918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107687112095299995463266177691903236887214980892902760705790826344054150588853 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.107687112095299995463266177691903236887214980892902760705790826344054150588853
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.98039899867872410797700663125610836941676244191464997755367749833325169729316
Short name T465
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 18 12:48:35 PM PDT 23
Finished Oct 18 12:48:40 PM PDT 23
Peak memory 201100 kb
Host smart-ba394b4b-34f6-406f-bd6e-ab5ecd68517f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98039899867872410797700663125610836941676244191464997755367749833325169729316 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.98039899867872410797700663125610836941676244191464997755367749833325169729316
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.82326768366865961777982019464361652114147207573516489219018855210179426663579
Short name T441
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 18 12:48:49 PM PDT 23
Finished Oct 18 12:48:53 PM PDT 23
Peak memory 201144 kb
Host smart-e1cc8837-01b4-4a44-9c07-6606357d39a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82326768366865961777982019464361652114147207573516489219018855210179426663579 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_smoke.82326768366865961777982019464361652114147207573516489219018855210179426663579
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.5329951244293916959445245321028634061504090080381811495891638083516005094876
Short name T449
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.79 seconds
Started Oct 18 12:49:06 PM PDT 23
Finished Oct 18 12:51:24 PM PDT 23
Peak memory 201516 kb
Host smart-99cc362a-81b5-465a-b8b1-95eea1c96265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5329951244293916959445245321028634061504090080381811495891638083516005094876 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.5329951244293916959445245321028634061504090080381811495891638083516005094876
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.46693062923943461977985342260342645998037178505631950594031102585624633728543
Short name T284
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 18 12:48:37 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201128 kb
Host smart-891dea69-6c14-4a6c-ad40-3226c5525b5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46693062923943461977985342260342645998037178505631950594031102585624633728543 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.466930629239434619779853422603426459980371785056319505940311
02585624633728543
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.111610834042527644710165553313332823980383611967100357606417339380624609789941
Short name T43
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 18 12:48:38 PM PDT 23
Finished Oct 18 12:48:42 PM PDT 23
Peak memory 201132 kb
Host smart-9d89d6ec-d029-42c1-9aa7-b53231c359b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111610834042527644710165553313332823980383611967100357606417339380624609789941 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.111610834042527644710165553313332823980383611967100357606417339380624609789941
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.43778505527446490336594389812328595653991624715884790691665168803300347198847
Short name T102
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 18 12:48:33 PM PDT 23
Finished Oct 18 12:48:39 PM PDT 23
Peak memory 201288 kb
Host smart-a1a861b9-6065-493d-8ea6-cc54e6651515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43778505527446490336594389812328595653991624715884790691665168803300347198847 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.43778505527446490336594389812328595653991624715884790691665168803300347198847
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.76126797400667230159599184362378134420586054533141993926432517897468303251192
Short name T244
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.85 seconds
Started Oct 18 12:48:48 PM PDT 23
Finished Oct 18 12:51:50 PM PDT 23
Peak memory 201468 kb
Host smart-b90f76b1-a9e7-4612-848a-5335fe12cdc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76126797400667230159599184362378134420586054533141993926432517897468303251192 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.76126797400667230159599184362378134420586054533141993926432517
897468303251192
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.90160103342118873507353161513213041167715711999021324741877632668416363964426
Short name T660
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Oct 18 12:48:56 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201136 kb
Host smart-48d4bb6d-e58d-475c-9c58-7b1e9de00230
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90160103342118873507353161513213041167715711999021324741877632668416363964426 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.901601033421188735073531615132130411677157119990213247418776
32668416363964426
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.105920547725239064491266389890602976151569995842491279789139077978724472257145
Short name T432
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:49:04 PM PDT 23
Finished Oct 18 12:49:11 PM PDT 23
Peak memory 201116 kb
Host smart-a7484a48-5541-493b-95d0-b587a071cd70
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105920547725239064491266389890602976151569995842491279789139077978724472257145 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.105920547725239064491266389890602976151569995842491279789139077
978724472257145
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.59302885761634015549008854057646605180262638740389437794524835677339836994809
Short name T313
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:51 PM PDT 23
Peak memory 201228 kb
Host smart-322c601c-144f-4e34-a3ef-6647e1fad31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59302885761634015549008854057646605180262638740389437794524835677339836994809 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.59302885761634015549008854057646605180262638740389437794524835677339836994809
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.112944439642847619496482325875088183784999364046117653585933508390179819317196
Short name T366
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Oct 18 12:49:03 PM PDT 23
Finished Oct 18 12:49:08 PM PDT 23
Peak memory 201148 kb
Host smart-f2c307d2-9913-4dc1-82d2-031cdce7e78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112944439642847619496482325875088183784999364046117653585933508390179819317196 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.112944439642847619496482325875088183784999364046117653585933508390179819317196
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.54509390635293724987453287279334382923125734287026001121514110190459050997188
Short name T126
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 18 12:48:50 PM PDT 23
Finished Oct 18 12:48:54 PM PDT 23
Peak memory 201340 kb
Host smart-f436b0fd-e227-4361-b828-7179c26c575a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54509390635293724987453287279334382923125734287026001121514110190459050997188 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.54509390635293724987453287279334382923125734287026001121514110190459050997188
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.104577017101988003311694791508132012250770249332235340209065195898072861762284
Short name T295
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 18 12:48:57 PM PDT 23
Finished Oct 18 12:49:02 PM PDT 23
Peak memory 201200 kb
Host smart-35cd0ffb-68b0-4ecd-928f-78336eacb5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104577017101988003311694791508132012250770249332235340209065195898072861762284 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.104577017101988003311694791508132012250770249332235340209065195898072861762284
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.98046664804212412786369594007060157994230488646694346806021044708525331039142
Short name T466
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 18 12:48:53 PM PDT 23
Finished Oct 18 12:48:57 PM PDT 23
Peak memory 201044 kb
Host smart-71a2c549-9902-4c2e-9043-2245ab6a2a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98046664804212412786369594007060157994230488646694346806021044708525331039142 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sysrst_ctrl_smoke.98046664804212412786369594007060157994230488646694346806021044708525331039142
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.49101642387007994814052224335935010362297047266190297494511966063491446752482
Short name T293
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.46 seconds
Started Oct 18 12:49:03 PM PDT 23
Finished Oct 18 12:51:21 PM PDT 23
Peak memory 201664 kb
Host smart-0e3154e1-0ee0-4000-a4a2-9019d6d591a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49101642387007994814052224335935010362297047266190297494511966063491446752482 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.49101642387007994814052224335935010362297047266190297494511966063491446752482
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.21457878452737988332727754828810495348448605365925295005572755806826374694405
Short name T20
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Oct 18 12:48:56 PM PDT 23
Finished Oct 18 12:49:01 PM PDT 23
Peak memory 201196 kb
Host smart-71404a97-d883-4ba1-bc35-fa447ade1d80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457878452737988332727754828810495348448605365925295005572755806826374694405 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.214578784527379883327277548288104953484486053659252950055727
55806826374694405
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.114879285226361239560316049034910963239490913985802424945317431567676296721865
Short name T161
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 18 12:48:40 PM PDT 23
Finished Oct 18 12:48:44 PM PDT 23
Peak memory 201140 kb
Host smart-e2254c6d-6b00-4495-9418-3cf894ca6b1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114879285226361239560316049034910963239490913985802424945317431567676296721865 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.114879285226361239560316049034910963239490913985802424945317431567676296721865
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.44763115100113093332387192149616724797943244307499972182021337760961656045553
Short name T105
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 18 12:48:42 PM PDT 23
Finished Oct 18 12:48:53 PM PDT 23
Peak memory 201308 kb
Host smart-cb2d25d4-c48b-4b7c-8cf1-1c3f313daae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44763115100113093332387192149616724797943244307499972182021337760961656045553 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.44763115100113093332387192149616724797943244307499972182021337760961656045553
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3948028935973609730712820443876350227687996378564606907510754827617825602039
Short name T513
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.45 seconds
Started Oct 18 12:49:09 PM PDT 23
Finished Oct 18 12:52:10 PM PDT 23
Peak memory 201452 kb
Host smart-c9a59890-eb00-4757-bb91-743893b01a6d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948028935973609730712820443876350227687996378564606907510754827617825602039 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.394802893597360973071282044387635022768799637856460690751075482
7617825602039
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.61040491687751121975402097394316366871576135181492251897654119476035182918742
Short name T107
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:49:00 PM PDT 23
Peak memory 201232 kb
Host smart-fe80c6a9-76a9-472c-ba88-96d6e6567e8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61040491687751121975402097394316366871576135181492251897654119476035182918742 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.610404916877511219754020973943163668715761351814922518976541
19476035182918742
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.66364138727439595153156691455253720744827765655966962960134872644647470718830
Short name T288
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Oct 18 12:48:49 PM PDT 23
Finished Oct 18 12:48:55 PM PDT 23
Peak memory 201220 kb
Host smart-436c05de-63dc-4ab7-b253-ace69bcf27d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66364138727439595153156691455253720744827765655966962960134872644647470718830 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.6636413872743959515315669145525372074482776565596696296013487264
4647470718830
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.75705467497953386244887380959974813096070082672082925185460150666924637529215
Short name T149
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.58 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:49:02 PM PDT 23
Peak memory 201232 kb
Host smart-87e01b29-d3ae-499c-ab92-c47d5b507e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75705467497953386244887380959974813096070082672082925185460150666924637529215 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.75705467497953386244887380959974813096070082672082925185460150666924637529215
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.30924909968671707062653295274994251146464073142340630117318775150759968979511
Short name T595
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Oct 18 12:48:58 PM PDT 23
Finished Oct 18 12:49:03 PM PDT 23
Peak memory 201140 kb
Host smart-a94c0c01-a357-40f0-b262-5e97cfd32b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30924909968671707062653295274994251146464073142340630117318775150759968979511 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.30924909968671707062653295274994251146464073142340630117318775150759968979511
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.68962508142011299498357033879452517281561135635296790906383128307430478179648
Short name T446
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.69 seconds
Started Oct 18 12:48:47 PM PDT 23
Finished Oct 18 12:48:52 PM PDT 23
Peak memory 201188 kb
Host smart-9a0b1b5a-6c64-44f9-9429-a6494afc4020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68962508142011299498357033879452517281561135635296790906383128307430478179648 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.68962508142011299498357033879452517281561135635296790906383128307430478179648
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.15277628063896452957716270982476389838648023867092586557639644363595930261771
Short name T283
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 18 12:48:43 PM PDT 23
Finished Oct 18 12:48:48 PM PDT 23
Peak memory 201108 kb
Host smart-0f306304-1a46-4987-854c-309755196e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15277628063896452957716270982476389838648023867092586557639644363595930261771 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.15277628063896452957716270982476389838648023867092586557639644363595930261771
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.12026449684955397694747294041780993676584595121353880669938493239445905872839
Short name T544
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:50 PM PDT 23
Peak memory 201120 kb
Host smart-c11d91ab-5a41-4156-be00-5ecf9c01a2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12026449684955397694747294041780993676584595121353880669938493239445905872839 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_smoke.12026449684955397694747294041780993676584595121353880669938493239445905872839
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.114642417224973511097560672160604121060973746883650895730161230866322754194849
Short name T420
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.67 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:51:07 PM PDT 23
Peak memory 201524 kb
Host smart-0b7f2709-7558-47e5-9ff2-332790856e60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114642417224973511097560672160604121060973746883650895730161230866322754194849 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.114642417224973511097560672160604121060973746883650895730161230866322754194849
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.80084735394934079888467329325259092798727218622639393683832554038951244737900
Short name T640
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Oct 18 12:48:58 PM PDT 23
Finished Oct 18 12:49:03 PM PDT 23
Peak memory 201204 kb
Host smart-4cf5dc3d-a1fd-4259-ac12-9e5fd97c50de
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80084735394934079888467329325259092798727218622639393683832554038951244737900 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.800847353949340798884673293252590927987272186226393936838325
54038951244737900
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.24977104386267662325384644485882159879361792888651865982706642220586951878910
Short name T478
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 18 12:48:55 PM PDT 23
Finished Oct 18 12:48:59 PM PDT 23
Peak memory 201228 kb
Host smart-91565d93-3034-4d15-8b04-88463fe6804f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24977104386267662325384644485882159879361792888651865982706642220586951878910 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.24977104386267662325384644485882159879361792888651865982706642220586951878910
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.41399602985527625010328619715940440824650272918515513773414774313139989028876
Short name T287
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.74 seconds
Started Oct 18 12:49:01 PM PDT 23
Finished Oct 18 12:49:07 PM PDT 23
Peak memory 201312 kb
Host smart-d7245128-ffd5-47cf-8cc0-0d1311b1ee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41399602985527625010328619715940440824650272918515513773414774313139989028876 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.41399602985527625010328619715940440824650272918515513773414774313139989028876
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.35723241448548856636871888710492576292186603972878503899220948456352664866244
Short name T532
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.97 seconds
Started Oct 18 12:48:55 PM PDT 23
Finished Oct 18 12:51:59 PM PDT 23
Peak memory 201472 kb
Host smart-5d84bc5f-737e-4612-9df0-5e62e54e165d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35723241448548856636871888710492576292186603972878503899220948456352664866244 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.35723241448548856636871888710492576292186603972878503899220948
456352664866244
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.14434101459594919755106466399713415018006514229340459178095482503256833131394
Short name T383
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.52 seconds
Started Oct 18 12:49:02 PM PDT 23
Finished Oct 18 12:49:10 PM PDT 23
Peak memory 201252 kb
Host smart-e9d57a03-3d20-426b-be8d-c270d9132eef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14434101459594919755106466399713415018006514229340459178095482503256833131394 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.144341014595949197551064663997134150180065142293404591780954
82503256833131394
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.11618636022205759520116290101203642571608409188361980924012969221035326547294
Short name T379
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Oct 18 12:48:52 PM PDT 23
Finished Oct 18 12:48:58 PM PDT 23
Peak memory 201172 kb
Host smart-c0c1f38c-07f2-4d93-82f8-1beeaf022a53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11618636022205759520116290101203642571608409188361980924012969221035326547294 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.1161863602220575952011629010120364257160840918836198092401296922
1035326547294
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.67503959480220086989734139504325236825133463706378525841686268457719508129451
Short name T40
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:51 PM PDT 23
Peak memory 201108 kb
Host smart-7123e4b8-ca7e-4793-92b8-fdc1c4235a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67503959480220086989734139504325236825133463706378525841686268457719508129451 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.67503959480220086989734139504325236825133463706378525841686268457719508129451
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.87247058232953961057791464034984778936122067287401462067772101856632330684399
Short name T110
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Oct 18 12:48:58 PM PDT 23
Finished Oct 18 12:49:03 PM PDT 23
Peak memory 201176 kb
Host smart-281e9cf6-634e-4b3c-95cb-bf0ba4456ebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87247058232953961057791464034984778936122067287401462067772101856632330684399 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.87247058232953961057791464034984778936122067287401462067772101856632330684399
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.9895911581844695360089592419893994190369141643874472040712738611419644510298
Short name T471
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.7 seconds
Started Oct 18 12:49:05 PM PDT 23
Finished Oct 18 12:49:09 PM PDT 23
Peak memory 201072 kb
Host smart-946779f4-3b70-46d8-a965-e4b63a96f057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9895911581844695360089592419893994190369141643874472040712738611419644510298 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.9895911581844695360089592419893994190369141643874472040712738611419644510298
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.80135539085366971557032707519338073073985512080393766281156827322526561848355
Short name T256
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.48 seconds
Started Oct 18 12:48:51 PM PDT 23
Finished Oct 18 12:48:56 PM PDT 23
Peak memory 201232 kb
Host smart-8ff74443-c438-4580-93e0-2ae0b7b0702f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80135539085366971557032707519338073073985512080393766281156827322526561848355 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.80135539085366971557032707519338073073985512080393766281156827322526561848355
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.65639822391386632676230588953278969235203389143558001841201521339592175386562
Short name T485
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 18 12:48:41 PM PDT 23
Finished Oct 18 12:48:45 PM PDT 23
Peak memory 201164 kb
Host smart-435a4c9f-cc58-482a-80a9-75a801c100c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65639822391386632676230588953278969235203389143558001841201521339592175386562 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_smoke.65639822391386632676230588953278969235203389143558001841201521339592175386562
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.88891514113977389742329138478369227598782917866196555756435049958590005172796
Short name T120
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.91 seconds
Started Oct 18 12:48:53 PM PDT 23
Finished Oct 18 12:51:08 PM PDT 23
Peak memory 201512 kb
Host smart-37b7c915-2305-4e3d-b997-945e097cac2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88891514113977389742329138478369227598782917866196555756435049958590005172796 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.88891514113977389742329138478369227598782917866196555756435049958590005172796
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.25423297030806645972873069852245579678849864433110672294801431986289638748641
Short name T670
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 18 12:48:51 PM PDT 23
Finished Oct 18 12:48:56 PM PDT 23
Peak memory 201128 kb
Host smart-4649aff5-9ad2-43f0-a172-e29bc46714ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25423297030806645972873069852245579678849864433110672294801431986289638748641 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.254232970308066459728730698522455796788498644331106722948014
31986289638748641
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.8825947247820460946753532431916443483523458617617019328148075395220387537038
Short name T520
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 18 12:48:55 PM PDT 23
Finished Oct 18 12:48:59 PM PDT 23
Peak memory 201248 kb
Host smart-813c1360-57b7-4754-824d-32d19291ffd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8825947247820460946753532431916443483523458617617019328148075395220387537038 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.8825947247820460946753532431916443483523458617617019328148075395220387537038
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.65692112276445720204067528680321711976294332703171375135083070990361410109758
Short name T487
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 18 12:49:02 PM PDT 23
Finished Oct 18 12:49:08 PM PDT 23
Peak memory 201288 kb
Host smart-3ca6909b-162b-49e4-b7a0-3477e70f2e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65692112276445720204067528680321711976294332703171375135083070990361410109758 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.65692112276445720204067528680321711976294332703171375135083070990361410109758
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.39096304333840203011018560500112601885994133028433278994213576022832044003330
Short name T348
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.56 seconds
Started Oct 18 12:48:58 PM PDT 23
Finished Oct 18 12:52:02 PM PDT 23
Peak memory 201384 kb
Host smart-4141869d-b785-403f-8899-c291639388c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39096304333840203011018560500112601885994133028433278994213576022832044003330 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.39096304333840203011018560500112601885994133028433278994213576
022832044003330
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.75023748324291031003708350319956393379214722114229201859347815536694430962060
Short name T289
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.48 seconds
Started Oct 18 12:48:47 PM PDT 23
Finished Oct 18 12:48:56 PM PDT 23
Peak memory 201216 kb
Host smart-d95081a3-4fed-4436-b698-7161452b753e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75023748324291031003708350319956393379214722114229201859347815536694430962060 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.750237483242910310037083503199563933792147221142292018593478
15536694430962060
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3001448718790835127048011652961502068761334287656964642968657099779016287140
Short name T299
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:06 PM PDT 23
Peak memory 201136 kb
Host smart-dce2b169-f6d2-420d-b004-c52d7c3e1373
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001448718790835127048011652961502068761334287656964642968657099779016287140 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.3001448718790835127048011652961502068761334287656964642968657099779016287140
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.16950030807518832486368669866302140255356182457315576348180322452220152909914
Short name T579
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 18 12:49:14 PM PDT 23
Finished Oct 18 12:49:19 PM PDT 23
Peak memory 201124 kb
Host smart-278e0723-6062-435d-b992-19952b233410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16950030807518832486368669866302140255356182457315576348180322452220152909914 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.16950030807518832486368669866302140255356182457315576348180322452220152909914
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.69008032726342795257288836862262441886622235077585868659168597834891272190176
Short name T634
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 18 12:49:24 PM PDT 23
Finished Oct 18 12:49:29 PM PDT 23
Peak memory 201328 kb
Host smart-41e1b29f-aaa1-48e1-9b4a-8d28d1bc7c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69008032726342795257288836862262441886622235077585868659168597834891272190176 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.69008032726342795257288836862262441886622235077585868659168597834891272190176
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.61407177866042625545074125369779838314277431513975904735823849051510595402988
Short name T627
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.81 seconds
Started Oct 18 12:48:55 PM PDT 23
Finished Oct 18 12:48:59 PM PDT 23
Peak memory 201128 kb
Host smart-bc89e182-c6ec-4e10-b24f-d579685b4985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61407177866042625545074125369779838314277431513975904735823849051510595402988 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.61407177866042625545074125369779838314277431513975904735823849051510595402988
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.38569743304292145736619318020448696404330285413610505664842430033476329977759
Short name T542
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 18 12:48:58 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201264 kb
Host smart-bb7fb4f9-391d-48f2-b95d-32c2cd88df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38569743304292145736619318020448696404330285413610505664842430033476329977759 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.38569743304292145736619318020448696404330285413610505664842430033476329977759
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.33809759080121277499775257340637192765942736334777823885270981123268286487088
Short name T286
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:03 PM PDT 23
Peak memory 201140 kb
Host smart-d136f0bf-77c7-4a3b-b0a0-88646ec074b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33809759080121277499775257340637192765942736334777823885270981123268286487088 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sysrst_ctrl_smoke.33809759080121277499775257340637192765942736334777823885270981123268286487088
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.103217947384896216839395880723026877741599876066424695393336176177466514947011
Short name T425
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.62 seconds
Started Oct 18 12:48:54 PM PDT 23
Finished Oct 18 12:51:08 PM PDT 23
Peak memory 201568 kb
Host smart-85a2b563-fb92-41f9-8b19-d8c97d6a493e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103217947384896216839395880723026877741599876066424695393336176177466514947011 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.103217947384896216839395880723026877741599876066424695393336176177466514947011
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.74280859121528283728415938087950772907279721892357104118626860237911193144872
Short name T263
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.66 seconds
Started Oct 18 12:48:56 PM PDT 23
Finished Oct 18 12:49:01 PM PDT 23
Peak memory 201288 kb
Host smart-7b5e89bc-17d3-4528-99ba-63beeb3d8cd7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74280859121528283728415938087950772907279721892357104118626860237911193144872 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.742808591215282837284159380879507729072797218923571041186268
60237911193144872
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.39807756273207155700887233368701551078569143128407347245783980723181350394313
Short name T445
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 18 12:47:11 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201200 kb
Host smart-e54a6b80-6818-474b-95d0-bc09c99e314a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39807756273207155700887233368701551078569143128407347245783980723181350394313 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.39807756273207155700887233368701551078569143128407347245783980723181350394313
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.46691062896935109189851219119897508724584565565990787017571928554606413571593
Short name T655
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:07 PM PDT 23
Peak memory 201276 kb
Host smart-2d9ed2e8-b1df-4f62-827a-f9afa12ada54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46691062896935109189851219119897508724584565565990787017571928554606413571593 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.46691062896935109189851219119897508724584565565990787017571928554606413571593
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.26430109546967083998669953031148456758001678774103387541337336759770398305964
Short name T327
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.18 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:50:07 PM PDT 23
Peak memory 201476 kb
Host smart-10005de4-7f87-4c68-913f-1f866af5898f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26430109546967083998669953031148456758001678774103387541337336759770398305964 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.264301095469670839986699530311484567580016787741033875413373367
59770398305964
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.52253489737328909027121250167713421532341261136795648451260103139561067935945
Short name T550
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.27 seconds
Started Oct 18 12:46:52 PM PDT 23
Finished Oct 18 12:46:57 PM PDT 23
Peak memory 201208 kb
Host smart-a2984fbd-fb87-463d-b8d6-b3a52b6de8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52253489737328909027121250167713421532341261136795648451260103139561067935945 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.52253489737328909027121250167713421532341261136795648451260103139561067935945
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.73072967618449684371702327934709037515093964644713979563570222984399433682200
Short name T95
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.49 seconds
Started Oct 18 12:47:03 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201124 kb
Host smart-1a35aedc-2ef0-457a-aca3-0dfaa5d0cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73072967618449684371702327934709037515093964644713979563570222984399433682200 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.73072967618449684371702327934709037515093964644713979
563570222984399433682200
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.94726023095211759711046672673416320075835317568642100596940892812401650447736
Short name T606
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201240 kb
Host smart-f7dd9ce2-9537-4970-939f-dd3c62081a3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94726023095211759711046672673416320075835317568642100596940892812401650447736 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.9472602309521175971104667267341632007583531756864210059694089
2812401650447736
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.65140719494126936486272146444897913846570282567486563649845237764298404415473
Short name T380
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 18 12:47:08 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201216 kb
Host smart-98b4b208-de65-42d6-9e20-d6d01fe005a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65140719494126936486272146444897913846570282567486563649845237764298404415473 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.65140719494126936486272146444897913846570282567486563649845237764298404415473
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.75119808776585850114097760286661798312623718492157576363413070590574595092379
Short name T516
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:02 PM PDT 23
Peak memory 201204 kb
Host smart-3f3b9ef4-c529-4355-b1aa-c272d03d562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75119808776585850114097760286661798312623718492157576363413070590574595092379 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.75119808776585850114097760286661798312623718492157576363413070590574595092379
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.106549130121748495617653176145943379278191751791718484205363791951285763438808
Short name T247
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Oct 18 12:46:57 PM PDT 23
Finished Oct 18 12:47:03 PM PDT 23
Peak memory 201292 kb
Host smart-5f9bc7b4-30bb-4d43-98d7-0bfeecb09785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106549130121748495617653176145943379278191751791718484205363791951285763438808 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.106549130121748495617653176145943379278191751791718484205363791951285763438808
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.67777718788274506577915602161473157721182434850441611317923987783320820453944
Short name T502
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 18 12:47:03 PM PDT 23
Finished Oct 18 12:47:07 PM PDT 23
Peak memory 201176 kb
Host smart-5949e6fa-e31e-4d5d-bca0-c3e259fa22cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67777718788274506577915602161473157721182434850441611317923987783320820453944 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.67777718788274506577915602161473157721182434850441611317923987783320820453944
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.67281345895411242353382513623117107674557981988088805644430440849793871983977
Short name T264
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Oct 18 12:46:58 PM PDT 23
Finished Oct 18 12:47:03 PM PDT 23
Peak memory 201216 kb
Host smart-7bddbfc3-0f97-4529-b7dc-5a56c20a1c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67281345895411242353382513623117107674557981988088805644430440849793871983977 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.67281345895411242353382513623117107674557981988088805644430440849793871983977
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.94013322938563526694420896005239963859104323542843543001027364743334586654403
Short name T45
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.9 seconds
Started Oct 18 12:47:16 PM PDT 23
Finished Oct 18 12:48:22 PM PDT 23
Peak memory 221608 kb
Host smart-823fa5df-33b3-4292-8ab7-66c8f00af77b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94013322938563526694420896005239963859104323542843543001027364743334586654403 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.94013322938563526694420896005239963859104323542843543001027364743334586654403
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.42863245650715530746057141826381177821248432248899060357439263527048445362300
Short name T517
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Oct 18 12:46:51 PM PDT 23
Finished Oct 18 12:46:55 PM PDT 23
Peak memory 201048 kb
Host smart-4088e122-1288-454f-8596-ef0181416e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42863245650715530746057141826381177821248432248899060357439263527048445362300 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_smoke.42863245650715530746057141826381177821248432248899060357439263527048445362300
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.60689015668155085741983401065449668024620101083647532530268190790349571494170
Short name T590
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.13 seconds
Started Oct 18 12:47:09 PM PDT 23
Finished Oct 18 12:49:25 PM PDT 23
Peak memory 201496 kb
Host smart-3aa570b1-3560-41b2-bc4f-89d587b85c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60689015668155085741983401065449668024620101083647532530268190790349571494170 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.60689015668155085741983401065449668024620101083647532530268190790349571494170
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.27212964670545029192515489109525165823191482800296393785145622255031318762396
Short name T19
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 18 12:46:41 PM PDT 23
Finished Oct 18 12:46:46 PM PDT 23
Peak memory 201284 kb
Host smart-74cdfaf7-50d3-466d-84a6-18ec0c7df10c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27212964670545029192515489109525165823191482800296393785145622255031318762396 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.2721296467054502919251548910952516582319148280029639378514562
2255031318762396
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.44859580508483300861253384102330791132284333823919386169141914900232301362641
Short name T170
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:17 PM PDT 23
Peak memory 201148 kb
Host smart-2ae7ef55-3ba0-4097-a0c3-76942afd2e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44859580508483300861253384102330791132284333823919386169141914900232301362641 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.44859580508483300861253384102330791132284333823919386169141914900232301362641
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.90495739758947917212982752108483923864449768888498413088863738291071508063581
Short name T278
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 18 12:48:51 PM PDT 23
Finished Oct 18 12:48:57 PM PDT 23
Peak memory 201180 kb
Host smart-753b48be-348d-4ba4-8674-09fdee2542b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90495739758947917212982752108483923864449768888498413088863738291071508063581 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.90495739758947917212982752108483923864449768888498413088863738291071508063581
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.93077670062319995268713875198535394990752430992515251447279419845618622298170
Short name T191
Test name
Test status
Simulation time 118289458206 ps
CPU time 179.61 seconds
Started Oct 18 12:48:57 PM PDT 23
Finished Oct 18 12:51:58 PM PDT 23
Peak memory 201376 kb
Host smart-6be447b1-0372-4e14-9c0c-9431a0791c59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93077670062319995268713875198535394990752430992515251447279419845618622298170 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.93077670062319995268713875198535394990752430992515251447279419
845618622298170
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.82388970422281431379258175386255557664186270086764211455002325121596206899799
Short name T404
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.55 seconds
Started Oct 18 12:49:11 PM PDT 23
Finished Oct 18 12:49:20 PM PDT 23
Peak memory 201156 kb
Host smart-5236c17f-7aa8-49e6-90fc-c923a3d92a35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82388970422281431379258175386255557664186270086764211455002325121596206899799 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.823889704222814313792581753862555576641862700867642114550023
25121596206899799
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.102967538186825438467672507818615013399366138868752638160535814335538179280257
Short name T633
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:48:57 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201232 kb
Host smart-3955fc0f-38ab-4592-8964-eeb8405e4df4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102967538186825438467672507818615013399366138868752638160535814335538179280257 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.102967538186825438467672507818615013399366138868752638160535814
335538179280257
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.37933558046049622502133291686189377826122164649029922105784716699850404334371
Short name T576
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 18 12:48:55 PM PDT 23
Finished Oct 18 12:49:00 PM PDT 23
Peak memory 201236 kb
Host smart-6650fac9-8d97-42a3-b910-8712591ca147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37933558046049622502133291686189377826122164649029922105784716699850404334371 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.37933558046049622502133291686189377826122164649029922105784716699850404334371
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.5794828005462794716025612511707962204643773648997105600976977981273831864217
Short name T201
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 18 12:48:45 PM PDT 23
Finished Oct 18 12:48:51 PM PDT 23
Peak memory 201108 kb
Host smart-a4744c62-e6ed-4d89-b8c1-8af5636a3134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5794828005462794716025612511707962204643773648997105600976977981273831864217 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.5794828005462794716025612511707962204643773648997105600976977981273831864217
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.23571527800820281262957089210099272520450089430939968113823320047385549726456
Short name T373
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:17 PM PDT 23
Peak memory 201172 kb
Host smart-994bdda3-35d8-4459-8595-562839d7f332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23571527800820281262957089210099272520450089430939968113823320047385549726456 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.23571527800820281262957089210099272520450089430939968113823320047385549726456
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.86733976723162858256309860540956172473437722478705817726939764806381633759450
Short name T193
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 18 12:48:49 PM PDT 23
Finished Oct 18 12:48:54 PM PDT 23
Peak memory 201128 kb
Host smart-18b17375-3805-46fd-ae00-a499c2cd2545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86733976723162858256309860540956172473437722478705817726939764806381633759450 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.86733976723162858256309860540956172473437722478705817726939764806381633759450
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.72883797290899690128933365614254682874816062035632228777036055255582665458748
Short name T620
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:17 PM PDT 23
Peak memory 201148 kb
Host smart-05e9f183-d7c4-4731-a40b-02ec917a0dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72883797290899690128933365614254682874816062035632228777036055255582665458748 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sysrst_ctrl_smoke.72883797290899690128933365614254682874816062035632228777036055255582665458748
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.110856423289842554176623337140416805582785141087648596357908977262918099386967
Short name T311
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.69 seconds
Started Oct 18 12:49:12 PM PDT 23
Finished Oct 18 12:51:28 PM PDT 23
Peak memory 201396 kb
Host smart-d6c1fbea-5d5a-4f57-9118-99cfcd6e2e4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110856423289842554176623337140416805582785141087648596357908977262918099386967 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.110856423289842554176623337140416805582785141087648596357908977262918099386967
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.18295496466619530257951743052251657911843502204387480630144325123426874810605
Short name T555
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:13 PM PDT 23
Peak memory 201204 kb
Host smart-af786f05-f69c-447a-9010-a888e4c4ae5c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18295496466619530257951743052251657911843502204387480630144325123426874810605 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.182954964666195302579517430522516579118435022043874806301443
25123426874810605
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.25902110863570828515205714478527506841046143786072502840543429205884210289080
Short name T279
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Oct 18 12:49:00 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201236 kb
Host smart-0f0a29fa-a354-4a5c-843d-97337e9a2cf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25902110863570828515205714478527506841046143786072502840543429205884210289080 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.25902110863570828515205714478527506841046143786072502840543429205884210289080
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.44577928935021456225528578890982603862545923578092798985186790495489473176303
Short name T18
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:14 PM PDT 23
Peak memory 201260 kb
Host smart-99e4f894-5c1e-4081-bdba-f2ad7ef8b953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44577928935021456225528578890982603862545923578092798985186790495489473176303 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.44577928935021456225528578890982603862545923578092798985186790495489473176303
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.2736576633793019279279577882710910985743675338403762541369683005808738252057
Short name T639
Test name
Test status
Simulation time 118289458206 ps
CPU time 179.68 seconds
Started Oct 18 12:49:24 PM PDT 23
Finished Oct 18 12:52:24 PM PDT 23
Peak memory 201432 kb
Host smart-90fac59c-b4df-48d7-8dbd-316ec7e975b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736576633793019279279577882710910985743675338403762541369683005808738252057 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.273657663379301927927957788271091098574367533840376254136968300
5808738252057
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.34725746484121897728750847246827202813315913037288547475101204200042222203747
Short name T601
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.5 seconds
Started Oct 18 12:49:11 PM PDT 23
Finished Oct 18 12:49:19 PM PDT 23
Peak memory 201220 kb
Host smart-75426ff9-1340-4b51-b226-93cb0c0c9d53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34725746484121897728750847246827202813315913037288547475101204200042222203747 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.347257464841218977287508472468272028133159130372885474751012
04200042222203747
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.15556781520818625217229357478608717238790851513443565860096721441975454380376
Short name T641
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Oct 18 12:49:20 PM PDT 23
Finished Oct 18 12:49:27 PM PDT 23
Peak memory 201284 kb
Host smart-d7d7e039-f04f-4c05-97db-b19bee2ee710
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15556781520818625217229357478608717238790851513443565860096721441975454380376 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.1555678152081862521722935747860871723879085151344356586009672144
1975454380376
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.25835842711219006353425130631814468005285989901012621485842466804827646133215
Short name T143
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.79 seconds
Started Oct 18 12:48:48 PM PDT 23
Finished Oct 18 12:48:54 PM PDT 23
Peak memory 201220 kb
Host smart-91c5e84d-7507-4d9e-ae60-96f07296f879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25835842711219006353425130631814468005285989901012621485842466804827646133215 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.25835842711219006353425130631814468005285989901012621485842466804827646133215
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.74321246955287197100273534972584307726854769728680400634976103349735875379430
Short name T369
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 18 12:48:55 PM PDT 23
Finished Oct 18 12:49:01 PM PDT 23
Peak memory 201328 kb
Host smart-5bf51c48-d699-4081-b9fb-28f7dc2f6f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74321246955287197100273534972584307726854769728680400634976103349735875379430 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.74321246955287197100273534972584307726854769728680400634976103349735875379430
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.49617182022686173631702643139629959517641850043987069782820140899557830488870
Short name T216
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:12 PM PDT 23
Peak memory 201164 kb
Host smart-a40da212-7d6c-4c14-b73b-60b871760703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49617182022686173631702643139629959517641850043987069782820140899557830488870 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.49617182022686173631702643139629959517641850043987069782820140899557830488870
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.96758547219566167459292032657643578409137711286639802867384336799333588292364
Short name T482
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 18 12:49:16 PM PDT 23
Finished Oct 18 12:49:21 PM PDT 23
Peak memory 201156 kb
Host smart-00c73ded-6f1f-4ca0-946e-ab85e8275c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96758547219566167459292032657643578409137711286639802867384336799333588292364 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.96758547219566167459292032657643578409137711286639802867384336799333588292364
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.59726261985577039734737189389696440359989346547422220932073754478697721563050
Short name T584
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:12 PM PDT 23
Peak memory 201160 kb
Host smart-593f0c03-b44e-488d-90f7-f3f4819028e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59726261985577039734737189389696440359989346547422220932073754478697721563050 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_smoke.59726261985577039734737189389696440359989346547422220932073754478697721563050
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.39082912857477009331729495122235990904197083796044902761434133672296981445909
Short name T245
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.98 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:51:30 PM PDT 23
Peak memory 201492 kb
Host smart-596cffa9-54ea-4147-898a-1c65914d5964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39082912857477009331729495122235990904197083796044902761434133672296981445909 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.39082912857477009331729495122235990904197083796044902761434133672296981445909
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.35006961984432472223629454584797691046504382565014287377140958434197633614887
Short name T37
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201204 kb
Host smart-9ee77cc9-5507-4d69-a3e9-2b359e568e13
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35006961984432472223629454584797691046504382565014287377140958434197633614887 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.350069619844324722236294545847976910465043825650142873771409
58434197633614887
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.79078399167188140436807475633487307440329817925922178813667533324319837238207
Short name T250
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:03 PM PDT 23
Peak memory 201212 kb
Host smart-4920a347-466f-4748-9d77-32ed98103f6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79078399167188140436807475633487307440329817925922178813667533324319837238207 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.79078399167188140436807475633487307440329817925922178813667533324319837238207
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.72896950489618491347841706817664739337986594609433512214734002945262066690622
Short name T365
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 18 12:49:10 PM PDT 23
Finished Oct 18 12:49:16 PM PDT 23
Peak memory 201352 kb
Host smart-d4ffa5f5-5100-4015-af5f-d5cca1a0d5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72896950489618491347841706817664739337986594609433512214734002945262066690622 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.72896950489618491347841706817664739337986594609433512214734002945262066690622
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.78305385013759834212900170910148904593334747918232830628546983876803629508827
Short name T243
Test name
Test status
Simulation time 118289458206 ps
CPU time 179.29 seconds
Started Oct 18 12:49:12 PM PDT 23
Finished Oct 18 12:52:12 PM PDT 23
Peak memory 200412 kb
Host smart-9b0ac15f-9277-4cb1-89a3-468c7256ffb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78305385013759834212900170910148904593334747918232830628546983876803629508827 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.78305385013759834212900170910148904593334747918232830628546983
876803629508827
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.25633124664067942141587920738864149587366056763662572323418534360453626595595
Short name T636
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Oct 18 12:48:49 PM PDT 23
Finished Oct 18 12:48:57 PM PDT 23
Peak memory 201240 kb
Host smart-d199160a-8f13-4cf3-95e6-65bac11f75cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25633124664067942141587920738864149587366056763662572323418534360453626595595 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.256331246640679421415879207388641495873660567636625723234185
34360453626595595
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.4108600962453752599749672401247651423277383861319969665289688647389955914819
Short name T605
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:48:58 PM PDT 23
Finished Oct 18 12:49:05 PM PDT 23
Peak memory 201288 kb
Host smart-6e6a5343-9aa9-4206-8ab1-bf0c9d64bb86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108600962453752599749672401247651423277383861319969665289688647389955914819 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.4108600962453752599749672401247651423277383861319969665289688647389955914819
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.23989278986397098586915319854780122564388608832697554022256297119216802578215
Short name T418
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 18 12:49:22 PM PDT 23
Finished Oct 18 12:49:27 PM PDT 23
Peak memory 201064 kb
Host smart-8c9933f7-eb44-4c60-9007-e7fc7e762954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23989278986397098586915319854780122564388608832697554022256297119216802578215 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.23989278986397098586915319854780122564388608832697554022256297119216802578215
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.31888953310573654466846247448125054538454730224455097715303840723676605373975
Short name T41
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 18 12:49:19 PM PDT 23
Finished Oct 18 12:49:24 PM PDT 23
Peak memory 201248 kb
Host smart-b2088682-4000-4b35-8758-3e0c4c4339f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31888953310573654466846247448125054538454730224455097715303840723676605373975 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.31888953310573654466846247448125054538454730224455097715303840723676605373975
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.43070541991143842965316266541960655718256218479293121991894190708392117842351
Short name T591
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 18 12:49:09 PM PDT 23
Finished Oct 18 12:49:14 PM PDT 23
Peak memory 201080 kb
Host smart-a9d034f9-447e-4486-9e36-0c8932d262d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43070541991143842965316266541960655718256218479293121991894190708392117842351 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.43070541991143842965316266541960655718256218479293121991894190708392117842351
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.107445812244588096386477110046023640892312703234228485455043884298877524421592
Short name T174
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 18 12:49:10 PM PDT 23
Finished Oct 18 12:49:16 PM PDT 23
Peak memory 201168 kb
Host smart-2e76c66d-c616-4f9f-a135-285a9b0171a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107445812244588096386477110046023640892312703234228485455043884298877524421592 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.107445812244588096386477110046023640892312703234228485455043884298877524421592
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.52433682183300100427133464564183781419813083494743360194389414531265599153409
Short name T617
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 18 12:49:07 PM PDT 23
Finished Oct 18 12:49:11 PM PDT 23
Peak memory 201140 kb
Host smart-aff26d92-f4b0-4f25-b796-6d9e078c2424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52433682183300100427133464564183781419813083494743360194389414531265599153409 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sysrst_ctrl_smoke.52433682183300100427133464564183781419813083494743360194389414531265599153409
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.114573238049124538627279712432876989053944336392015387399885446752407017643939
Short name T557
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.54 seconds
Started Oct 18 12:49:20 PM PDT 23
Finished Oct 18 12:51:36 PM PDT 23
Peak memory 201420 kb
Host smart-98c75a90-db27-4ad6-9c8a-2a66af98f18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114573238049124538627279712432876989053944336392015387399885446752407017643939 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.114573238049124538627279712432876989053944336392015387399885446752407017643939
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.96049510783156754810498839403589970880235352130456898278643228114110866572441
Short name T553
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:09 PM PDT 23
Peak memory 201220 kb
Host smart-cbf050e8-f8cd-4ddb-ac35-a0cab5fe32ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96049510783156754810498839403589970880235352130456898278643228114110866572441 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.960495107831567548104988394035899708802353521304568982786432
28114110866572441
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.35444998932873788206830939247518337970842333908814227574775220442144797098033
Short name T47
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 18 12:49:03 PM PDT 23
Finished Oct 18 12:49:07 PM PDT 23
Peak memory 201244 kb
Host smart-e19c62b5-abf0-47fb-abfa-748e9487f48c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35444998932873788206830939247518337970842333908814227574775220442144797098033 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.35444998932873788206830939247518337970842333908814227574775220442144797098033
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.102110349360948073042150841415585813790110055840667498466085777166808143951626
Short name T423
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Oct 18 12:49:22 PM PDT 23
Finished Oct 18 12:49:27 PM PDT 23
Peak memory 201148 kb
Host smart-a42871b0-3d2c-4c3b-9406-31a6a0e67a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102110349360948073042150841415585813790110055840667498466085777166808143951626 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.102110349360948073042150841415585813790110055840667498466085777166808143951626
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.59851019466573330419848868709406599730491210496913511741414371741607789655730
Short name T230
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.3 seconds
Started Oct 18 12:49:11 PM PDT 23
Finished Oct 18 12:52:14 PM PDT 23
Peak memory 201364 kb
Host smart-08d33926-e7de-4a12-a650-b73279369f68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59851019466573330419848868709406599730491210496913511741414371741607789655730 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.59851019466573330419848868709406599730491210496913511741414371
741607789655730
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.34351096991458812033387780804144417854999358348455410459712568321684749156142
Short name T602
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.44 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:07 PM PDT 23
Peak memory 201140 kb
Host smart-d6c34704-a1fd-44f0-aa9f-6ed323d12470
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34351096991458812033387780804144417854999358348455410459712568321684749156142 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.343510969914588120333877808041444178549993583484554104597125
68321684749156142
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.103270870509837398236010815462354809178066494453166614251847331588899560178237
Short name T26
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 18 12:49:11 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201188 kb
Host smart-c34586a8-5c7c-40ce-a2c8-a10d3350034f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103270870509837398236010815462354809178066494453166614251847331588899560178237 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.103270870509837398236010815462354809178066494453166614251847331
588899560178237
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.17345919701628831529390384155042677423742650496563282024835850932180179456957
Short name T153
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201136 kb
Host smart-3a5ac2b4-c541-44a7-af5f-6a24f9fc2aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17345919701628831529390384155042677423742650496563282024835850932180179456957 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.17345919701628831529390384155042677423742650496563282024835850932180179456957
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.97631587461617842700294393603779270765114226146725399959321019934500114914874
Short name T190
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:13 PM PDT 23
Peak memory 201284 kb
Host smart-5e519058-5ab3-49bd-8ce6-6b9830b220bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97631587461617842700294393603779270765114226146725399959321019934500114914874 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.97631587461617842700294393603779270765114226146725399959321019934500114914874
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.87374387110585307814927176071488805266937350934635024351645843642652193434988
Short name T232
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 18 12:48:41 PM PDT 23
Finished Oct 18 12:48:45 PM PDT 23
Peak memory 201092 kb
Host smart-3d19e245-c5bb-48a0-bfe0-9245bc2fae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87374387110585307814927176071488805266937350934635024351645843642652193434988 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.87374387110585307814927176071488805266937350934635024351645843642652193434988
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.32968659941351569151194093031841461284026688114697072927182812507753638040712
Short name T261
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:13 PM PDT 23
Peak memory 201192 kb
Host smart-6decd62e-a374-4090-adbe-86ab4a352cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32968659941351569151194093031841461284026688114697072927182812507753638040712 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.32968659941351569151194093031841461284026688114697072927182812507753638040712
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.5138749110893794279571071633720044331333801974827367952904792345958542308442
Short name T458
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 18 12:49:17 PM PDT 23
Finished Oct 18 12:49:21 PM PDT 23
Peak memory 201124 kb
Host smart-e71853bb-ca89-4b6e-b1c6-7b62d2013bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5138749110893794279571071633720044331333801974827367952904792345958542308442 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sysrst_ctrl_smoke.5138749110893794279571071633720044331333801974827367952904792345958542308442
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.29005191472231250581000239664144752309307490572345652723166089044601695735117
Short name T589
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.75 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:51:31 PM PDT 23
Peak memory 201472 kb
Host smart-b37d21b6-2a9c-4598-9e2e-7f771c6bc7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29005191472231250581000239664144752309307490572345652723166089044601695735117 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.29005191472231250581000239664144752309307490572345652723166089044601695735117
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.24342752874966823153420588647472502070604855158403362176682797745767743804136
Short name T460
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 18 12:48:59 PM PDT 23
Finished Oct 18 12:49:04 PM PDT 23
Peak memory 201192 kb
Host smart-fb71f855-f33b-41de-8924-cda676d41350
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24342752874966823153420588647472502070604855158403362176682797745767743804136 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.243427528749668231534205886474725020706048551584033621766827
97745767743804136
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.30054077387542911596111884604638426749072932862263529692147317380178996183842
Short name T152
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Oct 18 12:49:11 PM PDT 23
Finished Oct 18 12:49:15 PM PDT 23
Peak memory 201132 kb
Host smart-82ded39c-47df-4f1f-8636-62288eb7cd07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30054077387542911596111884604638426749072932862263529692147317380178996183842 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.30054077387542911596111884604638426749072932862263529692147317380178996183842
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2507884516611676178023669013372138865427274436372368240131258334617241198028
Short name T469
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:49:21 PM PDT 23
Peak memory 201280 kb
Host smart-f6be04e6-ba63-4e1c-bd6d-4fbd69fb85c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507884516611676178023669013372138865427274436372368240131258334617241198028 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.2507884516611676178023669013372138865427274436372368240131258334617241198028
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.42052797769479282458027908480765597462916346256258081441098019847491597433209
Short name T315
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.63 seconds
Started Oct 18 12:49:10 PM PDT 23
Finished Oct 18 12:52:12 PM PDT 23
Peak memory 201456 kb
Host smart-bb6de2cc-fce8-4ba1-98db-671fe5a7c627
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42052797769479282458027908480765597462916346256258081441098019847491597433209 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.42052797769479282458027908480765597462916346256258081441098019
847491597433209
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.24504702848725566389592540052546249141123453668058405460311629647518618645477
Short name T511
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.47 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:49:23 PM PDT 23
Peak memory 201172 kb
Host smart-2821bfce-d4f0-42f0-87a7-a9af8966362c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24504702848725566389592540052546249141123453668058405460311629647518618645477 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.245047028487255663895925400525462491411234536680584054603116
29647518618645477
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.25568954837895277091221017465676842132404480354757796017439591537126664102900
Short name T479
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 18 12:49:18 PM PDT 23
Finished Oct 18 12:49:25 PM PDT 23
Peak memory 201224 kb
Host smart-27d37e97-1d5b-45c3-b621-ab84817853fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25568954837895277091221017465676842132404480354757796017439591537126664102900 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.2556895483789527709122101746567684213240448035475779601743959153
7126664102900
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.95134548850552365750427025218102772856863537818732424638831908279365683531348
Short name T564
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:49:20 PM PDT 23
Peak memory 201136 kb
Host smart-fbe21fc3-3c15-43ad-81a5-76ef5ff3a892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95134548850552365750427025218102772856863537818732424638831908279365683531348 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.95134548850552365750427025218102772856863537818732424638831908279365683531348
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.100797413612929622372337238552902975542203365299642445596336959666889876891856
Short name T209
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 18 12:49:07 PM PDT 23
Finished Oct 18 12:49:12 PM PDT 23
Peak memory 201236 kb
Host smart-0d14351e-6c1a-4a6e-b1e6-4c9c6b365491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100797413612929622372337238552902975542203365299642445596336959666889876891856 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.100797413612929622372337238552902975542203365299642445596336959666889876891856
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.102214237729610224571867429463149437997098420268271680802346994476357916519997
Short name T533
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.82 seconds
Started Oct 18 12:49:05 PM PDT 23
Finished Oct 18 12:49:09 PM PDT 23
Peak memory 201164 kb
Host smart-49c83380-36ac-4a0d-9a51-68c32e61fc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102214237729610224571867429463149437997098420268271680802346994476357916519997 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.102214237729610224571867429463149437997098420268271680802346994476357916519997
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.42385953084707409744218610869592276144668309951737237751004342460197177302205
Short name T241
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 18 12:49:16 PM PDT 23
Finished Oct 18 12:49:21 PM PDT 23
Peak memory 201208 kb
Host smart-be961649-d6d0-4669-9da1-c4a61931acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42385953084707409744218610869592276144668309951737237751004342460197177302205 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.42385953084707409744218610869592276144668309951737237751004342460197177302205
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.33166238343888198385797130805200925573139247428780404874039453610521239755431
Short name T540
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 18 12:49:11 PM PDT 23
Finished Oct 18 12:49:15 PM PDT 23
Peak memory 201140 kb
Host smart-226df88d-cedb-4a83-9dab-9753c4b43e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33166238343888198385797130805200925573139247428780404874039453610521239755431 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sysrst_ctrl_smoke.33166238343888198385797130805200925573139247428780404874039453610521239755431
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.17419007592594129336358983234768179019716577115747686603387235361503332664709
Short name T539
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.8 seconds
Started Oct 18 12:49:06 PM PDT 23
Finished Oct 18 12:51:21 PM PDT 23
Peak memory 201508 kb
Host smart-999334fc-4188-401d-8f53-e6f3ab377856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17419007592594129336358983234768179019716577115747686603387235361503332664709 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.17419007592594129336358983234768179019716577115747686603387235361503332664709
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.73666386089823315559156922044175436642894925298671132315795706910733106893149
Short name T448
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:13 PM PDT 23
Peak memory 201192 kb
Host smart-43c9d7c4-da77-4bf1-9a12-7d0a291f899d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73666386089823315559156922044175436642894925298671132315795706910733106893149 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.736663860898233155591569220441754366428949252986711323157957
06910733106893149
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.33449071819275060557523239869109942309808960897535874408631045276213663274375
Short name T548
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Oct 18 12:49:09 PM PDT 23
Finished Oct 18 12:49:14 PM PDT 23
Peak memory 201196 kb
Host smart-be19b2f2-2c05-4a30-96df-620a625c71bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33449071819275060557523239869109942309808960897535874408631045276213663274375 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.33449071819275060557523239869109942309808960897535874408631045276213663274375
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.46769990624778929455994658203555332010809288973940250138742160008401930886081
Short name T361
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 18 12:48:58 PM PDT 23
Finished Oct 18 12:49:05 PM PDT 23
Peak memory 201296 kb
Host smart-9aef9f11-5487-4163-8ab0-6630c71d34c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46769990624778929455994658203555332010809288973940250138742160008401930886081 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.46769990624778929455994658203555332010809288973940250138742160008401930886081
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.108151217053597163846376510075748534916980699501357634807321870686752076475260
Short name T176
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.89 seconds
Started Oct 18 12:49:10 PM PDT 23
Finished Oct 18 12:52:12 PM PDT 23
Peak memory 201380 kb
Host smart-fb139316-2f78-4e4e-a62d-a5e02fe9d0cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108151217053597163846376510075748534916980699501357634807321870686752076475260 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.1081512170535971638463765100757485349169806995013576348073218
70686752076475260
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.366828364853748486304209050322376205017295384418501877202469657356761443401
Short name T592
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.45 seconds
Started Oct 18 12:49:06 PM PDT 23
Finished Oct 18 12:49:14 PM PDT 23
Peak memory 201240 kb
Host smart-4d861dc2-f3b0-4c78-9d45-c698f65aff5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366828364853748486304209050322376205017295384418501877202469657356761443401 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.36682836485374848630420905032237620501729538441850187720246965
7356761443401
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.29246070912998065036717370553631729845783194428708614144953586032333383900095
Short name T488
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:15 PM PDT 23
Peak memory 201116 kb
Host smart-d38430f7-c8da-4ea4-9406-b6ea18d49c59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29246070912998065036717370553631729845783194428708614144953586032333383900095 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.2924607091299806503671737055363172984578319442870861414495358603
2333383900095
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.112865110058695389616887995025078199234170246169004901410646426538060922430965
Short name T188
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201296 kb
Host smart-9b2ba5d6-c7c7-4015-a2ab-850e1675cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112865110058695389616887995025078199234170246169004901410646426538060922430965 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.112865110058695389616887995025078199234170246169004901410646426538060922430965
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.79329348272820858945837243218798690046950623209600242840625600359959695998493
Short name T257
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 18 12:49:01 PM PDT 23
Finished Oct 18 12:49:06 PM PDT 23
Peak memory 201132 kb
Host smart-ca8c74ed-387c-4e94-a3e7-75dac56d132e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79329348272820858945837243218798690046950623209600242840625600359959695998493 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.79329348272820858945837243218798690046950623209600242840625600359959695998493
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.74170259545165012906880061031161411536443656215346168776784113016802785705674
Short name T381
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 18 12:49:02 PM PDT 23
Finished Oct 18 12:49:06 PM PDT 23
Peak memory 201088 kb
Host smart-b685a19b-4f0c-4453-8268-192fc49bcabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74170259545165012906880061031161411536443656215346168776784113016802785705674 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.74170259545165012906880061031161411536443656215346168776784113016802785705674
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.93821504646525730396888814431841685612721510315006839695121933622652774008768
Short name T165
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 18 12:49:20 PM PDT 23
Finished Oct 18 12:49:25 PM PDT 23
Peak memory 201176 kb
Host smart-96f8eec8-5193-4200-ae51-4dae95754be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93821504646525730396888814431841685612721510315006839695121933622652774008768 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.93821504646525730396888814431841685612721510315006839695121933622652774008768
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.71063598688800673401532077205593042629697835071841685574720310292217663124553
Short name T631
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 18 12:49:18 PM PDT 23
Finished Oct 18 12:49:23 PM PDT 23
Peak memory 201228 kb
Host smart-3bc54d05-4ee2-4852-abae-9a1278bc2607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71063598688800673401532077205593042629697835071841685574720310292217663124553 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_smoke.71063598688800673401532077205593042629697835071841685574720310292217663124553
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.67837765515590526115459902737529245404362781692719446397662440452238799258060
Short name T292
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.53 seconds
Started Oct 18 12:49:01 PM PDT 23
Finished Oct 18 12:51:16 PM PDT 23
Peak memory 201416 kb
Host smart-95e746c1-3966-4de4-84a9-dd54998a8a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67837765515590526115459902737529245404362781692719446397662440452238799258060 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.67837765515590526115459902737529245404362781692719446397662440452238799258060
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.111757001347198063862291376719838016374702640005905360938950074859862115886991
Short name T275
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Oct 18 12:49:19 PM PDT 23
Finished Oct 18 12:49:24 PM PDT 23
Peak memory 201236 kb
Host smart-3643b517-0ee3-4925-aba3-42776fa69a64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111757001347198063862291376719838016374702640005905360938950074859862115886991 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.11175700134719806386229137671983801637470264000590536093895
0074859862115886991
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.11651524589458107303770745291269033899634429885897701729721757068793768876148
Short name T367
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:17 PM PDT 23
Peak memory 201240 kb
Host smart-ee1e081e-b53d-4c37-acf0-c3c762e72bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11651524589458107303770745291269033899634429885897701729721757068793768876148 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.11651524589458107303770745291269033899634429885897701729721757068793768876148
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.72884487022386085693988472665619815067191545406286880548982544692413519873386
Short name T259
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.58 seconds
Started Oct 18 12:49:02 PM PDT 23
Finished Oct 18 12:49:07 PM PDT 23
Peak memory 201292 kb
Host smart-7600ce7b-c670-4ece-8570-5f9087a2a127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72884487022386085693988472665619815067191545406286880548982544692413519873386 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.72884487022386085693988472665619815067191545406286880548982544692413519873386
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.61678700785381182060521945980285559705271553075379129597714672078929996648080
Short name T144
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.56 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:52:19 PM PDT 23
Peak memory 201440 kb
Host smart-5bb17860-c420-45bb-9c3e-d2431f5a2413
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61678700785381182060521945980285559705271553075379129597714672078929996648080 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.61678700785381182060521945980285559705271553075379129597714672
078929996648080
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.5857825336710452362211379305000759999830182432657816932170586783146281380656
Short name T238
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:49:23 PM PDT 23
Peak memory 201256 kb
Host smart-679024c2-7e40-4387-a2a8-3d18162d8d89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5857825336710452362211379305000759999830182432657816932170586783146281380656 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.5857825336710452362211379305000759999830182432657816932170586
783146281380656
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.75233023695903792146057421836623950228238930488116739978379116251154649084778
Short name T303
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 18 12:49:07 PM PDT 23
Finished Oct 18 12:49:14 PM PDT 23
Peak memory 201120 kb
Host smart-5eb4c906-390b-41ac-9096-960a7f06754f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75233023695903792146057421836623950228238930488116739978379116251154649084778 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.7523302369590379214605742183662395022823893048811673997837911625
1154649084778
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.103795544598515448900648941884481870449837975859729890555292881665839293472728
Short name T546
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 18 12:49:02 PM PDT 23
Finished Oct 18 12:49:07 PM PDT 23
Peak memory 201156 kb
Host smart-b91c678c-e5e3-4f80-9893-22e2ba1e5de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103795544598515448900648941884481870449837975859729890555292881665839293472728 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.103795544598515448900648941884481870449837975859729890555292881665839293472728
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.25880824119223396279457083510798935667505010943343329230485708598552476165336
Short name T175
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 18 12:49:02 PM PDT 23
Finished Oct 18 12:49:07 PM PDT 23
Peak memory 201160 kb
Host smart-b802901a-879f-405d-9e69-483d0a30e640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25880824119223396279457083510798935667505010943343329230485708598552476165336 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.25880824119223396279457083510798935667505010943343329230485708598552476165336
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.27790903741387870882662968902020625451288492886410480810866443289989459415617
Short name T413
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 18 12:49:16 PM PDT 23
Finished Oct 18 12:49:21 PM PDT 23
Peak memory 201188 kb
Host smart-f87cedee-f4da-44eb-9550-efad67193502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27790903741387870882662968902020625451288492886410480810866443289989459415617 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.27790903741387870882662968902020625451288492886410480810866443289989459415617
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.8831358574012423373221967174826038029737546502661787234589832867480058778492
Short name T42
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Oct 18 12:49:14 PM PDT 23
Finished Oct 18 12:49:19 PM PDT 23
Peak memory 201260 kb
Host smart-8759db74-120e-44aa-a5e4-af323dd9b007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8831358574012423373221967174826038029737546502661787234589832867480058778492 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.8831358574012423373221967174826038029737546502661787234589832867480058778492
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.94612231876734437021195787638331078056041227513530725484237922317904884935941
Short name T531
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 18 12:49:19 PM PDT 23
Finished Oct 18 12:49:24 PM PDT 23
Peak memory 201156 kb
Host smart-1fb1cb98-7980-49ea-81ef-dcd77df2f0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94612231876734437021195787638331078056041227513530725484237922317904884935941 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_smoke.94612231876734437021195787638331078056041227513530725484237922317904884935941
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.95958996549780481252022410693106224271733858648599735850829234481888727915234
Short name T343
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.78 seconds
Started Oct 18 12:49:21 PM PDT 23
Finished Oct 18 12:51:36 PM PDT 23
Peak memory 201516 kb
Host smart-0b869150-55a2-404a-af08-0661db7ffdff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95958996549780481252022410693106224271733858648599735850829234481888727915234 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.95958996549780481252022410693106224271733858648599735850829234481888727915234
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.77188199018527769226564614175537161821915088657891328002286155528939430033303
Short name T51
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Oct 18 12:49:25 PM PDT 23
Finished Oct 18 12:49:30 PM PDT 23
Peak memory 201128 kb
Host smart-254ee662-a6c9-430c-b596-ad77440ba68c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77188199018527769226564614175537161821915088657891328002286155528939430033303 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.771881990185277692265646141755371618219150886578913280022861
55528939430033303
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.97285905759898056072148047680625983168239390170704260417118368214220735395115
Short name T611
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.6 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:49:19 PM PDT 23
Peak memory 201428 kb
Host smart-a630ce4e-99e2-4208-8105-9a0a0982dc69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97285905759898056072148047680625983168239390170704260417118368214220735395115 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.97285905759898056072148047680625983168239390170704260417118368214220735395115
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.57874586598620404793285309403757540613523619812341182089534859933007564210323
Short name T433
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Oct 18 12:49:16 PM PDT 23
Finished Oct 18 12:49:21 PM PDT 23
Peak memory 201280 kb
Host smart-7d306061-e5d7-4088-9852-f42ab3b2cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57874586598620404793285309403757540613523619812341182089534859933007564210323 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.57874586598620404793285309403757540613523619812341182089534859933007564210323
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.48608895575974142088917024682954783576431945402849548714609859180635863799009
Short name T318
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.13 seconds
Started Oct 18 12:49:24 PM PDT 23
Finished Oct 18 12:52:27 PM PDT 23
Peak memory 201432 kb
Host smart-b5a5225a-833b-41a2-9f8e-1a8252662d76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48608895575974142088917024682954783576431945402849548714609859180635863799009 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.48608895575974142088917024682954783576431945402849548714609859
180635863799009
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3119413018814953486984341088389138881212364406517453108080406951405478497693
Short name T613
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Oct 18 12:49:10 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201168 kb
Host smart-5cd8ff05-55eb-4f9e-8bc9-bbe4bb593de0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119413018814953486984341088389138881212364406517453108080406951405478497693 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.3119413018814953486984341088389138881212364406517453108080406
951405478497693
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.46468292078623640963995956340848962070737019020611063721710668572374445160581
Short name T36
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 18 12:49:02 PM PDT 23
Finished Oct 18 12:49:09 PM PDT 23
Peak memory 201116 kb
Host smart-921924ac-7ed3-4387-9b25-a9635f77ae72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46468292078623640963995956340848962070737019020611063721710668572374445160581 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.4646829207862364096399595634084896207073701902061106372171066857
2374445160581
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.103556709357904398030066525494661793327453691163056212204960634385162893668024
Short name T525
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Oct 18 12:49:05 PM PDT 23
Finished Oct 18 12:49:10 PM PDT 23
Peak memory 201152 kb
Host smart-9ed18f83-e3db-4557-96d0-6b6e5cfa681e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103556709357904398030066525494661793327453691163056212204960634385162893668024 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.103556709357904398030066525494661793327453691163056212204960634385162893668024
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.12894074866396541500428660050845015245903503818766369221484490035608687992956
Short name T226
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Oct 18 12:49:12 PM PDT 23
Finished Oct 18 12:49:17 PM PDT 23
Peak memory 201140 kb
Host smart-fa1ef475-fddf-4edd-906c-87abe23f1af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12894074866396541500428660050845015245903503818766369221484490035608687992956 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.12894074866396541500428660050845015245903503818766369221484490035608687992956
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.110267871059831776758999716550896104242565684746485713935537477566100623526118
Short name T229
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 18 12:49:17 PM PDT 23
Finished Oct 18 12:49:22 PM PDT 23
Peak memory 201104 kb
Host smart-a9eb91f8-0e2e-4abc-948e-d12e09c7fa17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110267871059831776758999716550896104242565684746485713935537477566100623526118 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.110267871059831776758999716550896104242565684746485713935537477566100623526118
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.105709229258889747613415851959380346769141066667897063271943209312793858757395
Short name T443
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201188 kb
Host smart-252c861a-0add-41e2-8d89-49d2426dd68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105709229258889747613415851959380346769141066667897063271943209312793858757395 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.105709229258889747613415851959380346769141066667897063271943209312793858757395
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.46484931649743425391255006223995065464165403006674039570631468077098403903260
Short name T566
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:13 PM PDT 23
Peak memory 201032 kb
Host smart-6a41dc10-4377-465a-833b-d45a368234c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46484931649743425391255006223995065464165403006674039570631468077098403903260 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_smoke.46484931649743425391255006223995065464165403006674039570631468077098403903260
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.57105116145083764110396106850934335211743324375262328603896152235017604931824
Short name T646
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.8 seconds
Started Oct 18 12:49:20 PM PDT 23
Finished Oct 18 12:51:35 PM PDT 23
Peak memory 201512 kb
Host smart-4441f858-be5b-44c5-bf7b-0388401be211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57105116145083764110396106850934335211743324375262328603896152235017604931824 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.57105116145083764110396106850934335211743324375262328603896152235017604931824
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.71981986631615805662993853839150754476505388047110375083192445426920275721614
Short name T529
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 18 12:49:17 PM PDT 23
Finished Oct 18 12:49:23 PM PDT 23
Peak memory 201104 kb
Host smart-ce4a6f1e-3b43-41af-b9d4-33f8f1a1b0b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71981986631615805662993853839150754476505388047110375083192445426920275721614 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.719819866316158056629938538391507544765053880471103750831924
45426920275721614
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.103451676052198327597012255262192973316993653637893532241904763303877549851039
Short name T363
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 18 12:49:08 PM PDT 23
Finished Oct 18 12:49:12 PM PDT 23
Peak memory 201228 kb
Host smart-709041e2-a207-48d1-9ffb-b09056decd74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103451676052198327597012255262192973316993653637893532241904763303877549851039 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.103451676052198327597012255262192973316993653637893532241904763303877549851039
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.44187408051469342875084785375746613696353658807088074205982653807160004918435
Short name T99
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 18 12:49:30 PM PDT 23
Finished Oct 18 12:49:36 PM PDT 23
Peak memory 201216 kb
Host smart-fa824892-0622-46d8-ae38-4f5ebe7ce5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44187408051469342875084785375746613696353658807088074205982653807160004918435 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.44187408051469342875084785375746613696353658807088074205982653807160004918435
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.100042163057618433745416098343912124051634456784215367139628318531918494685110
Short name T304
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.94 seconds
Started Oct 18 12:49:17 PM PDT 23
Finished Oct 18 12:52:21 PM PDT 23
Peak memory 201344 kb
Host smart-0492dab2-5093-4ade-8a58-e9dbc43d0a7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100042163057618433745416098343912124051634456784215367139628318531918494685110 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.1000421630576184337454160983439121240516344567842153671396283
18531918494685110
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.30407278752535150071959955052807805601027841575266264698148855253293813202348
Short name T197
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:21 PM PDT 23
Peak memory 201196 kb
Host smart-d1381045-0837-4d4b-8ff7-04623e625a74
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30407278752535150071959955052807805601027841575266264698148855253293813202348 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.304072787525351500719599550528078056010278415752662646981488
55253293813202348
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.12176075397590974263000220734866830504611874255222465844986576972047072710118
Short name T131
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 18 12:49:30 PM PDT 23
Finished Oct 18 12:49:37 PM PDT 23
Peak memory 201132 kb
Host smart-8912df98-4094-4b05-9a03-9daaf067a061
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12176075397590974263000220734866830504611874255222465844986576972047072710118 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.1217607539759097426300022073486683050461187425522246584498657697
2047072710118
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.85156607728337631562068987692668343346786796608618733465005163434209567423987
Short name T632
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 18 12:49:13 PM PDT 23
Finished Oct 18 12:49:18 PM PDT 23
Peak memory 201220 kb
Host smart-aeaeacd6-1fd3-4d9e-89f8-fbf594372a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85156607728337631562068987692668343346786796608618733465005163434209567423987 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.85156607728337631562068987692668343346786796608618733465005163434209567423987
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.26136407870662636771776696948431024107610787062932347188916878131793057624823
Short name T111
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 18 12:49:19 PM PDT 23
Finished Oct 18 12:49:24 PM PDT 23
Peak memory 201256 kb
Host smart-276f9575-c9b1-46a0-86ab-6735f24064ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26136407870662636771776696948431024107610787062932347188916878131793057624823 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.26136407870662636771776696948431024107610787062932347188916878131793057624823
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.19312002916725762253414414699645811765643866836910226001897181698037055141558
Short name T528
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 18 12:49:06 PM PDT 23
Finished Oct 18 12:49:10 PM PDT 23
Peak memory 201188 kb
Host smart-7c8bd9ba-2837-4103-8c5b-539467537078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19312002916725762253414414699645811765643866836910226001897181698037055141558 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.19312002916725762253414414699645811765643866836910226001897181698037055141558
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.41848982032264199017529432023234965915794286269192176828507961653098693023724
Short name T66
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.48 seconds
Started Oct 18 12:49:23 PM PDT 23
Finished Oct 18 12:49:28 PM PDT 23
Peak memory 201252 kb
Host smart-b8f1f8fc-ca91-4ad2-94a3-be44f08119f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41848982032264199017529432023234965915794286269192176828507961653098693023724 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.41848982032264199017529432023234965915794286269192176828507961653098693023724
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.104253171364606818370047683486463657569971311500138561331270055350758277233494
Short name T596
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 18 12:49:21 PM PDT 23
Finished Oct 18 12:49:25 PM PDT 23
Peak memory 201096 kb
Host smart-be561ef9-fd78-460b-a9c9-d747697db3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104253171364606818370047683486463657569971311500138561331270055350758277233494 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.sysrst_ctrl_smoke.104253171364606818370047683486463657569971311500138561331270055350758277233494
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.18258595348028560067154219159506019296606708206432668213595316160045019856314
Short name T300
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.93 seconds
Started Oct 18 12:49:10 PM PDT 23
Finished Oct 18 12:51:26 PM PDT 23
Peak memory 201416 kb
Host smart-dc324cc8-88a4-4949-ae27-aaeccd534be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18258595348028560067154219159506019296606708206432668213595316160045019856314 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.18258595348028560067154219159506019296606708206432668213595316160045019856314
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.113284872007395000973463062773819165979634528829632749494530663575376915203572
Short name T50
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Oct 18 12:48:57 PM PDT 23
Finished Oct 18 12:49:02 PM PDT 23
Peak memory 201212 kb
Host smart-8faa2733-98ea-4847-8f64-c240eb2699a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113284872007395000973463062773819165979634528829632749494530663575376915203572 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.11328487200739500097346306277381916597963452882963274949453
0663575376915203572
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.96980717226750843630348814906802401929470512953398240559748845778379898406149
Short name T308
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 18 12:49:09 PM PDT 23
Finished Oct 18 12:49:13 PM PDT 23
Peak memory 201148 kb
Host smart-1d368387-9883-45e7-b92b-16a1112c37be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96980717226750843630348814906802401929470512953398240559748845778379898406149 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.96980717226750843630348814906802401929470512953398240559748845778379898406149
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.91013898015973031045370210549131386567735607226883612311088559141289067123884
Short name T444
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 18 12:49:26 PM PDT 23
Finished Oct 18 12:49:32 PM PDT 23
Peak memory 201280 kb
Host smart-deb270b1-4c3f-485d-9442-6056ee4ee22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91013898015973031045370210549131386567735607226883612311088559141289067123884 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.91013898015973031045370210549131386567735607226883612311088559141289067123884
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.74851195804807262242832928174502787286997494588349788591841315481175472447311
Short name T123
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.42 seconds
Started Oct 18 12:49:17 PM PDT 23
Finished Oct 18 12:52:18 PM PDT 23
Peak memory 201384 kb
Host smart-0e4e78cf-3042-43e2-9696-04913cfe2fcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74851195804807262242832928174502787286997494588349788591841315481175472447311 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.74851195804807262242832928174502787286997494588349788591841315
481175472447311
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.96251082974550413770119921198856268835454233743879304926109397577692284093069
Short name T178
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.47 seconds
Started Oct 18 12:49:35 PM PDT 23
Finished Oct 18 12:49:42 PM PDT 23
Peak memory 201156 kb
Host smart-60de43a5-62e7-4ef7-8050-082447fefc80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96251082974550413770119921198856268835454233743879304926109397577692284093069 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.962510829745504137701199211988562688354542337438793049261093
97577692284093069
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.72544032438987880366348828266023116274873517643926666761758490636320881584544
Short name T23
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Oct 18 12:49:24 PM PDT 23
Finished Oct 18 12:49:30 PM PDT 23
Peak memory 201212 kb
Host smart-081e40cd-147f-4b9e-bcfc-de5731c98555
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72544032438987880366348828266023116274873517643926666761758490636320881584544 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.7254403243898788036634882826602311627487351764392666676175849063
6320881584544
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.39819077893273734940492974970620063102523281957683369771614832122595794716042
Short name T349
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Oct 18 12:49:17 PM PDT 23
Finished Oct 18 12:49:22 PM PDT 23
Peak memory 201208 kb
Host smart-81f7341d-b8a3-422e-951e-152596a6f728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39819077893273734940492974970620063102523281957683369771614832122595794716042 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.39819077893273734940492974970620063102523281957683369771614832122595794716042
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.81848734373894497877541557491555603760415824793648313898501096647399524259753
Short name T593
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.91 seconds
Started Oct 18 12:49:17 PM PDT 23
Finished Oct 18 12:49:23 PM PDT 23
Peak memory 201156 kb
Host smart-2d138f8b-d1c7-4669-af02-46226c188214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81848734373894497877541557491555603760415824793648313898501096647399524259753 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.81848734373894497877541557491555603760415824793648313898501096647399524259753
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.62572711095136593334022245608273832434877893330534646389422237489788605141157
Short name T228
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Oct 18 12:49:15 PM PDT 23
Finished Oct 18 12:49:19 PM PDT 23
Peak memory 201400 kb
Host smart-a0760aea-28d5-4a4b-a6d4-e104ff98f96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62572711095136593334022245608273832434877893330534646389422237489788605141157 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.62572711095136593334022245608273832434877893330534646389422237489788605141157
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.99782390408386137369574975343495534806539056544334788689910886274339535074260
Short name T599
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 18 12:49:11 PM PDT 23
Finished Oct 18 12:49:16 PM PDT 23
Peak memory 201128 kb
Host smart-971965ba-6f70-4d15-8850-1b1afd69dc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99782390408386137369574975343495534806539056544334788689910886274339535074260 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.99782390408386137369574975343495534806539056544334788689910886274339535074260
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.21828211529670358103781473614364490300745730023796581997011543044414932303494
Short name T616
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 18 12:49:18 PM PDT 23
Finished Oct 18 12:49:22 PM PDT 23
Peak memory 201120 kb
Host smart-4884e96d-7243-41a6-b178-ef7db88eebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21828211529670358103781473614364490300745730023796581997011543044414932303494 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sysrst_ctrl_smoke.21828211529670358103781473614364490300745730023796581997011543044414932303494
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.102714177108107124312162789075015793165277909146132943871122287918297507560000
Short name T32
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.78 seconds
Started Oct 18 12:49:20 PM PDT 23
Finished Oct 18 12:51:35 PM PDT 23
Peak memory 201456 kb
Host smart-776c04e5-dd9d-416b-8992-01fa21fe8c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102714177108107124312162789075015793165277909146132943871122287918297507560000 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.102714177108107124312162789075015793165277909146132943871122287918297507560000
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.26604303915337739418625731717467871782579766196466500542269316393830975345555
Short name T48
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 18 12:49:31 PM PDT 23
Finished Oct 18 12:49:36 PM PDT 23
Peak memory 201124 kb
Host smart-b2663d7a-9715-437b-919b-cbcfda77b9a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26604303915337739418625731717467871782579766196466500542269316393830975345555 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.266043039153377394186257317174678717825797661964665005422693
16393830975345555
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.27087965569085389560114981595018364990121171272522724467781955641965204026305
Short name T310
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201244 kb
Host smart-a7274446-e250-4adc-9976-60c18855cc4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27087965569085389560114981595018364990121171272522724467781955641965204026305 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.27087965569085389560114981595018364990121171272522724467781955641965204026305
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.38094029141065354131844917940953084756160960995741889130403466169562589676276
Short name T547
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.38 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:10 PM PDT 23
Peak memory 201312 kb
Host smart-2e7ce93c-fc91-46d9-ab7f-2f0f0f0e81ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38094029141065354131844917940953084756160960995741889130403466169562589676276 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.38094029141065354131844917940953084756160960995741889130403466169562589676276
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.115617154305186726350968908580498129856842983319141981329954930005617277825197
Short name T426
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.34 seconds
Started Oct 18 12:47:09 PM PDT 23
Finished Oct 18 12:50:11 PM PDT 23
Peak memory 201372 kb
Host smart-dfd24975-aaf8-42f4-bbf1-5f3f3d3975ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115617154305186726350968908580498129856842983319141981329954930005617277825197 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.11561715430518672635096890858049812985684298331914198132995493
0005617277825197
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.23790119021287283847310578481459887201537467466299700816038279084515779964583
Short name T215
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:09 PM PDT 23
Peak memory 201172 kb
Host smart-b7545bdb-b952-451a-a2d2-c2b8462d7617
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790119021287283847310578481459887201537467466299700816038279084515779964583 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.2379011902128728384731057848145988720153746746629970081603827
9084515779964583
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.29238025386618612992153915923954551857656124806957910174735920453241968499669
Short name T658
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 18 12:47:02 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201220 kb
Host smart-4fb1f09a-0907-4b6e-b68d-c63ba91de66e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238025386618612992153915923954551857656124806957910174735920453241968499669 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.29238025386618612992153915923954551857656124806957910174735920453241968499669
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.101757333709198523117600093598634135986160468876127944810581075169895492456281
Short name T331
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.73 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:47:16 PM PDT 23
Peak memory 201040 kb
Host smart-11015e0d-8934-46fc-87bf-208dd67046a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101757333709198523117600093598634135986160468876127944810581075169895492456281 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.101757333709198523117600093598634135986160468876127944810581075169895492456281
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.67760605162271935289535215761479129707591282320692532257143985519061472315028
Short name T173
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.92 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:07 PM PDT 23
Peak memory 201264 kb
Host smart-1dc2be32-882c-4b24-9815-8ee5ca0c7a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67760605162271935289535215761479129707591282320692532257143985519061472315028 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.67760605162271935289535215761479129707591282320692532257143985519061472315028
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.50678822103512306934608433806789227494862487220037629437296340052645538924309
Short name T306
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 18 12:47:09 PM PDT 23
Finished Oct 18 12:47:13 PM PDT 23
Peak memory 201096 kb
Host smart-645ebfe3-5df2-42b6-8fe4-abaea8786542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50678822103512306934608433806789227494862487220037629437296340052645538924309 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.50678822103512306934608433806789227494862487220037629437296340052645538924309
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.31279765888946634124107092416457282229061525673372413908197990621280954819202
Short name T115
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:47:10 PM PDT 23
Peak memory 201152 kb
Host smart-901332bc-ded9-4beb-8dff-9447bec2a68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31279765888946634124107092416457282229061525673372413908197990621280954819202 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.31279765888946634124107092416457282229061525673372413908197990621280954819202
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.94713664626583436390198836889524548200839585570659967388417192615879685334670
Short name T162
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 18 12:47:06 PM PDT 23
Finished Oct 18 12:47:11 PM PDT 23
Peak memory 201156 kb
Host smart-ec3c0385-f702-40fd-bea8-046609988d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94713664626583436390198836889524548200839585570659967388417192615879685334670 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sysrst_ctrl_smoke.94713664626583436390198836889524548200839585570659967388417192615879685334670
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.72493187521737246486761038517362242894364431782885932692075468088119860557025
Short name T522
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.8 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:49:19 PM PDT 23
Peak memory 201524 kb
Host smart-70e74d7a-9df5-4a5c-8f26-aaf4f2e1e1fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72493187521737246486761038517362242894364431782885932692075468088119860557025 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.72493187521737246486761038517362242894364431782885932692075468088119860557025
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.67743282627476349086337537808530660296674746870173878067587271078749482542134
Short name T514
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 18 12:47:06 PM PDT 23
Finished Oct 18 12:47:11 PM PDT 23
Peak memory 201200 kb
Host smart-f74b9cbd-e9c7-4d23-a0fe-dbc79e88fcf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67743282627476349086337537808530660296674746870173878067587271078749482542134 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.6774328262747634908633753780853066029667474687017387806758727
1078749482542134
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.7600466486315311274469151012312838447234568301482288956320169017474713003496
Short name T396
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 18 12:47:11 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201204 kb
Host smart-c775ba71-b5e4-45e5-868d-0fb2543d7631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7600466486315311274469151012312838447234568301482288956320169017474713003496 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.7600466486315311274469151012312838447234568301482288956320169017474713003496
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.58863440754975197726668645675062888834625992881487494514887003860432530239097
Short name T118
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:07 PM PDT 23
Peak memory 201312 kb
Host smart-d478bc1f-cdf7-41ac-bd42-d188bd77a52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58863440754975197726668645675062888834625992881487494514887003860432530239097 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.58863440754975197726668645675062888834625992881487494514887003860432530239097
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.128880451572801960161497259344599942943321760628175201021261872233583089288
Short name T172
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.12 seconds
Started Oct 18 12:47:02 PM PDT 23
Finished Oct 18 12:50:05 PM PDT 23
Peak memory 201464 kb
Host smart-9d2414ce-486e-4712-a190-990b979f830a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128880451572801960161497259344599942943321760628175201021261872233583089288 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.128880451572801960161497259344599942943321760628175201021261872233583089288
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.52398215057878487127259278740212774123906372916260101957047965479578577737047
Short name T180
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Oct 18 12:47:07 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201244 kb
Host smart-8f34290f-0544-446b-bbc8-9f2c8e8b207e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52398215057878487127259278740212774123906372916260101957047965479578577737047 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.5239821505787848712725927874021277412390637291626010195704796
5479578577737047
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.36120203989682056070353372803798048777333536201244462155301614576806315113573
Short name T410
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:47:06 PM PDT 23
Finished Oct 18 12:47:12 PM PDT 23
Peak memory 201232 kb
Host smart-03323cf1-e68c-47c9-b14a-39da77abe273
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36120203989682056070353372803798048777333536201244462155301614576806315113573 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.36120203989682056070353372803798048777333536201244462155301614576806315113573
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.48218930039026904873229146922956673656093175339695214387878488226395875884801
Short name T622
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 18 12:47:13 PM PDT 23
Finished Oct 18 12:47:18 PM PDT 23
Peak memory 201136 kb
Host smart-21f4e3df-7176-4f52-be56-44e1777db5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48218930039026904873229146922956673656093175339695214387878488226395875884801 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.48218930039026904873229146922956673656093175339695214387878488226395875884801
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.107077826549373551887897564356422076355488747607369541171343030684284415591081
Short name T494
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Oct 18 12:47:10 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201252 kb
Host smart-c20fcb51-5861-4a05-a41d-b085f884c2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107077826549373551887897564356422076355488747607369541171343030684284415591081 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.107077826549373551887897564356422076355488747607369541171343030684284415591081
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.7821112918732406309764958536827306732694814369494078592434781690964552441461
Short name T570
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 18 12:47:08 PM PDT 23
Finished Oct 18 12:47:13 PM PDT 23
Peak memory 201188 kb
Host smart-7577d61c-3c50-4641-8c51-9ff40bd33496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7821112918732406309764958536827306732694814369494078592434781690964552441461 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.7821112918732406309764958536827306732694814369494078592434781690964552441461
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.72276864795346561728526813657823693432993699652071824608903569318111999708602
Short name T220
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.65 seconds
Started Oct 18 12:47:10 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201216 kb
Host smart-6ae4a6a0-f356-471d-aeb0-b348e825ace1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72276864795346561728526813657823693432993699652071824608903569318111999708602 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.72276864795346561728526813657823693432993699652071824608903569318111999708602
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.48279157880510690855767795736433995117076876163061852000163223885942219473164
Short name T160
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 18 12:47:13 PM PDT 23
Finished Oct 18 12:47:17 PM PDT 23
Peak memory 201156 kb
Host smart-47119ede-5086-4085-82a1-c54bfe05cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48279157880510690855767795736433995117076876163061852000163223885942219473164 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_smoke.48279157880510690855767795736433995117076876163061852000163223885942219473164
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.106710938608970186153511237144653532634388352326967969888077004895071636972221
Short name T121
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.35 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:49:23 PM PDT 23
Peak memory 201408 kb
Host smart-a4d0e15c-3198-45d2-9051-261bb131bd41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106710938608970186153511237144653532634388352326967969888077004895071636972221 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.106710938608970186153511237144653532634388352326967969888077004895071636972221
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.115633875090469544150967582414590924889250439455150781215829100964554492438782
Short name T663
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:09 PM PDT 23
Peak memory 201208 kb
Host smart-4444e1de-d81b-4d37-8c3a-50d03f0a894c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115633875090469544150967582414590924889250439455150781215829100964554492438782 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.115633875090469544150967582414590924889250439455150781215829
100964554492438782
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.8740521868870648662346296673924204754484022356620240742289848986252774567030
Short name T649
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201236 kb
Host smart-42404a9d-effa-4cf3-9e70-a0c670eeedfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8740521868870648662346296673924204754484022356620240742289848986252774567030 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.8740521868870648662346296673924204754484022356620240742289848986252774567030
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.49549585285827452766076607901687544901036661313244575334994831840805069062055
Short name T652
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:47:11 PM PDT 23
Peak memory 201236 kb
Host smart-27dcc14d-1f86-4a70-8dbe-06580a7ef2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49549585285827452766076607901687544901036661313244575334994831840805069062055 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.49549585285827452766076607901687544901036661313244575334994831840805069062055
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.102767927175004841570571686296845325797131951865570728046542704004653856028995
Short name T100
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.51 seconds
Started Oct 18 12:47:15 PM PDT 23
Finished Oct 18 12:50:16 PM PDT 23
Peak memory 201484 kb
Host smart-3424f25d-11ea-4b00-8fc6-58dbe9a5f7a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102767927175004841570571686296845325797131951865570728046542704004653856028995 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.10276792717500484157057168629684532579713195186557072804654270
4004653856028995
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.13290949557478038907942338658541231764326687968431486336520178596076851619136
Short name T364
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.57 seconds
Started Oct 18 12:47:14 PM PDT 23
Finished Oct 18 12:47:22 PM PDT 23
Peak memory 201244 kb
Host smart-9ee02f3f-1966-4a79-93d0-60ea19fd2cd6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13290949557478038907942338658541231764326687968431486336520178596076851619136 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.1329094955747803890794233865854123176432668796843148633652017
8596076851619136
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.85201822098649264351380473361566149350935074003119277739777103880530423524533
Short name T323
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:47:11 PM PDT 23
Peak memory 201216 kb
Host smart-fb4faffe-7f98-42d7-ac08-82a82c687acf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85201822098649264351380473361566149350935074003119277739777103880530423524533 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.85201822098649264351380473361566149350935074003119277739777103880530423524533
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.76961000708583922762524411079913410561982628002326037247469992235417870956480
Short name T452
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 18 12:47:03 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201236 kb
Host smart-dcb88729-871e-4113-b0a9-75d2ef2d19b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76961000708583922762524411079913410561982628002326037247469992235417870956480 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.76961000708583922762524411079913410561982628002326037247469992235417870956480
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.96416294563927347245746080075827725486742639964222287719007050836411128814495
Short name T434
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Oct 18 12:47:06 PM PDT 23
Finished Oct 18 12:47:11 PM PDT 23
Peak memory 201212 kb
Host smart-e36231c3-ca7f-4911-b708-b272a34a9229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96416294563927347245746080075827725486742639964222287719007050836411128814495 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.96416294563927347245746080075827725486742639964222287719007050836411128814495
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.9932725537174087784171387916768300068071803294627094406913349716898550695947
Short name T314
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:06 PM PDT 23
Peak memory 201188 kb
Host smart-b248d1b5-60f1-4894-b333-45d11ef73c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9932725537174087784171387916768300068071803294627094406913349716898550695947 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.9932725537174087784171387916768300068071803294627094406913349716898550695947
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.50968549805157032498220878280567994821642373782007235632626261795427059655533
Short name T213
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 18 12:47:12 PM PDT 23
Finished Oct 18 12:47:17 PM PDT 23
Peak memory 201224 kb
Host smart-ad85668b-6a77-4ba3-a121-fb55e6e082d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50968549805157032498220878280567994821642373782007235632626261795427059655533 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.50968549805157032498220878280567994821642373782007235632626261795427059655533
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.82610482285061166806842813975282749696291188384369819889582098875159742349832
Short name T159
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 18 12:46:59 PM PDT 23
Finished Oct 18 12:47:03 PM PDT 23
Peak memory 201052 kb
Host smart-70c23fd6-b79d-4c8c-a583-47cffddb4234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82610482285061166806842813975282749696291188384369819889582098875159742349832 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_smoke.82610482285061166806842813975282749696291188384369819889582098875159742349832
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.9980293606682318155386572623961783131234647614666992167048936915902019254530
Short name T393
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.47 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:49:19 PM PDT 23
Peak memory 201500 kb
Host smart-112c82b9-34b5-4c74-aa65-93b274ddf2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9980293606682318155386572623961783131234647614666992167048936915902019254530 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.9980293606682318155386572623961783131234647614666992167048936915902019254530
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.66886213436128174216311184803223342290727788584974666671947204764477126511836
Short name T30
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201224 kb
Host smart-12e81fb5-2fe1-42e0-928e-b1e833d30d39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66886213436128174216311184803223342290727788584974666671947204764477126511836 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.6688621343612817421631118480322334229072778858497466667194720
4764477126511836
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.51483302552261726138854316122255735802376107557269905502375505648094583331055
Short name T186
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201240 kb
Host smart-50600540-9fb3-4fe3-b672-e200b975aa64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51483302552261726138854316122255735802376107557269905502375505648094583331055 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.51483302552261726138854316122255735802376107557269905502375505648094583331055
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.91412885190441788358941859848820856926992822791963249367443442501252073866728
Short name T385
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.65 seconds
Started Oct 18 12:47:09 PM PDT 23
Finished Oct 18 12:47:15 PM PDT 23
Peak memory 201284 kb
Host smart-3eccd516-97c2-42bb-b105-86816ffee954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91412885190441788358941859848820856926992822791963249367443442501252073866728 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.91412885190441788358941859848820856926992822791963249367443442501252073866728
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.17114778408342375363236606230109687591743032200760585499605601827126464089986
Short name T490
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.65 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:50:03 PM PDT 23
Peak memory 201428 kb
Host smart-0c8028ef-0200-4e94-837b-1d0ec58efb98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17114778408342375363236606230109687591743032200760585499605601827126464089986 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.171147784083423753632366062301096875917430322007605854996056018
27126464089986
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.19939677036381212939972634240231482418346397816655782167124806962912099979568
Short name T417
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.45 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:12 PM PDT 23
Peak memory 201160 kb
Host smart-79ba8a3a-3ac0-4d7d-8bde-e52a647e2ea9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19939677036381212939972634240231482418346397816655782167124806962912099979568 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.1993967703638121293997263424023148241834639781665578216712480
6962912099979568
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.37467810136431553582399333444934110259110126293603827739318211743747469849672
Short name T297
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.44 seconds
Started Oct 18 12:47:00 PM PDT 23
Finished Oct 18 12:47:07 PM PDT 23
Peak memory 201216 kb
Host smart-f1104be9-f619-4cf5-a217-61b3975d46ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37467810136431553582399333444934110259110126293603827739318211743747469849672 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.37467810136431553582399333444934110259110126293603827739318211743747469849672
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.89446460605326429349192546248795069974836992188121253312299505273128440881677
Short name T568
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.74 seconds
Started Oct 18 12:47:03 PM PDT 23
Finished Oct 18 12:47:08 PM PDT 23
Peak memory 201248 kb
Host smart-5202e8ca-a2c6-48e4-9957-f23040008776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89446460605326429349192546248795069974836992188121253312299505273128440881677 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.89446460605326429349192546248795069974836992188121253312299505273128440881677
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1186221744461787343412289089579992399291506788736271930534932474064045626632
Short name T325
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 18 12:47:08 PM PDT 23
Finished Oct 18 12:47:13 PM PDT 23
Peak memory 201244 kb
Host smart-833d3fc4-a73e-4698-bfc7-1bd286f40b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186221744461787343412289089579992399291506788736271930534932474064045626632 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.1186221744461787343412289089579992399291506788736271930534932474064045626632
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.101362114260482537417177422390418648532448381485582909820152648684741260510612
Short name T342
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 18 12:47:01 PM PDT 23
Finished Oct 18 12:47:05 PM PDT 23
Peak memory 201168 kb
Host smart-3a46bdac-a458-4d83-a302-351d098a2241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101362114260482537417177422390418648532448381485582909820152648684741260510612 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.101362114260482537417177422390418648532448381485582909820152648684741260510612
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.68966440114770925739432942952147321405512004046489474041073546978006638589945
Short name T492
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:47:10 PM PDT 23
Peak memory 201256 kb
Host smart-d7e9bca4-b007-4f28-b6a6-5f513a20f26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68966440114770925739432942952147321405512004046489474041073546978006638589945 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.68966440114770925739432942952147321405512004046489474041073546978006638589945
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.20470343956214729450064944828490869084191956530614135717936857043880515590489
Short name T362
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 18 12:47:08 PM PDT 23
Finished Oct 18 12:47:12 PM PDT 23
Peak memory 201044 kb
Host smart-68ee0659-e7ac-40cd-b67a-b5b4937d9e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20470343956214729450064944828490869084191956530614135717936857043880515590489 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_smoke.20470343956214729450064944828490869084191956530614135717936857043880515590489
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.45182511426801406548985715960014090789809996110105909266158833523006495887032
Short name T22
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.88 seconds
Started Oct 18 12:47:03 PM PDT 23
Finished Oct 18 12:49:20 PM PDT 23
Peak memory 201508 kb
Host smart-15b80e5c-ac80-4659-b8bb-43deb47be4aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45182511426801406548985715960014090789809996110105909266158833523006495887032 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.45182511426801406548985715960014090789809996110105909266158833523006495887032
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1171014616896891153678097259212985500940631917424960183001973320138990105290
Short name T454
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 18 12:47:02 PM PDT 23
Finished Oct 18 12:47:07 PM PDT 23
Peak memory 201028 kb
Host smart-624dc239-459b-4516-9e3f-48e805a4dfb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171014616896891153678097259212985500940631917424960183001973320138990105290 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.11710146168968911536780972592129855009406319174249601830019733
20138990105290
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.96493975496691896109985348728105049777994492124856398799373461103364930416907
Short name T390
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 18 12:47:55 PM PDT 23
Finished Oct 18 12:47:59 PM PDT 23
Peak memory 201232 kb
Host smart-f04e1d25-c1d0-4f03-a409-c25ab87d0d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96493975496691896109985348728105049777994492124856398799373461103364930416907 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.96493975496691896109985348728105049777994492124856398799373461103364930416907
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.51301224442881295589662014211246347125264096832477769225101851941093181755742
Short name T470
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Oct 18 12:47:53 PM PDT 23
Finished Oct 18 12:47:59 PM PDT 23
Peak memory 201276 kb
Host smart-1cc0be5a-d51f-4640-880b-c65b5971d47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51301224442881295589662014211246347125264096832477769225101851941093181755742 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.51301224442881295589662014211246347125264096832477769225101851941093181755742
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.29909074503796315045536582296057454049322505205639630952083338595104487522252
Short name T330
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.32 seconds
Started Oct 18 12:47:56 PM PDT 23
Finished Oct 18 12:50:57 PM PDT 23
Peak memory 201464 kb
Host smart-0b50a140-d931-4baf-8d1b-03ac0032fda4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29909074503796315045536582296057454049322505205639630952083338595104487522252 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.299090745037963150455365822960574540493225052056396309520833385
95104487522252
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.60900256325696448015126805933958847574047189970752533770217365034275516610761
Short name T424
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Oct 18 12:47:54 PM PDT 23
Finished Oct 18 12:48:02 PM PDT 23
Peak memory 201264 kb
Host smart-892da187-83df-41a9-a082-f846883721d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60900256325696448015126805933958847574047189970752533770217365034275516610761 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.6090025632569644801512680593395884757404718997075253377021736
5034275516610761
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.30829688359406385860283975399597173169080320049672448325774247160375117119699
Short name T326
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 18 12:47:54 PM PDT 23
Finished Oct 18 12:48:00 PM PDT 23
Peak memory 201204 kb
Host smart-1052526b-cf95-42c5-bb12-f5cd6b1ce013
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30829688359406385860283975399597173169080320049672448325774247160375117119699 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.30829688359406385860283975399597173169080320049672448325774247160375117119699
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.31233108925961240784185251079788238017860082760536222499938609845288864071749
Short name T556
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 18 12:48:02 PM PDT 23
Finished Oct 18 12:48:07 PM PDT 23
Peak memory 201200 kb
Host smart-097ccdc9-1cf9-4c37-8dbd-405030e2c24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31233108925961240784185251079788238017860082760536222499938609845288864071749 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.31233108925961240784185251079788238017860082760536222499938609845288864071749
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.12177910971473881105407701219808730230359895913101571223659006662201440924312
Short name T200
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Oct 18 12:47:05 PM PDT 23
Finished Oct 18 12:47:11 PM PDT 23
Peak memory 201180 kb
Host smart-69049c1f-e296-4a27-a98b-75b29ba22d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12177910971473881105407701219808730230359895913101571223659006662201440924312 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.12177910971473881105407701219808730230359895913101571223659006662201440924312
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.75686170487658166083198360668043676070948893800360922539938085518821571195439
Short name T225
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 18 12:47:04 PM PDT 23
Finished Oct 18 12:47:09 PM PDT 23
Peak memory 201188 kb
Host smart-1d140512-f92e-44db-9d73-7d823ed0708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75686170487658166083198360668043676070948893800360922539938085518821571195439 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.75686170487658166083198360668043676070948893800360922539938085518821571195439
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.96973568845828887813863975985364385498695069403495565399800709165104759542147
Short name T610
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 18 12:47:58 PM PDT 23
Finished Oct 18 12:48:03 PM PDT 23
Peak memory 201212 kb
Host smart-a8729a67-d6d3-4f1c-9e99-131d141625ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96973568845828887813863975985364385498695069403495565399800709165104759542147 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.96973568845828887813863975985364385498695069403495565399800709165104759542147
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.6910687640720947540841532658032774983146947031004026558542007597344482995158
Short name T251
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 18 12:47:08 PM PDT 23
Finished Oct 18 12:47:12 PM PDT 23
Peak memory 201136 kb
Host smart-9a5677de-f9a2-451b-a5e1-2f7c25b7913b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6910687640720947540841532658032774983146947031004026558542007597344482995158 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sysrst_ctrl_smoke.6910687640720947540841532658032774983146947031004026558542007597344482995158
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.63654946383036254741743266083916908304255373008085590188225414685416796591801
Short name T559
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.63 seconds
Started Oct 18 12:48:00 PM PDT 23
Finished Oct 18 12:50:15 PM PDT 23
Peak memory 201504 kb
Host smart-d22184c9-6e7b-4d9e-81b3-8705e156ecbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63654946383036254741743266083916908304255373008085590188225414685416796591801 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.63654946383036254741743266083916908304255373008085590188225414685416796591801
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.9077534302847197073874571660506548421328355231979694655498704097451543680452
Short name T388
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Oct 18 12:47:55 PM PDT 23
Finished Oct 18 12:48:00 PM PDT 23
Peak memory 201120 kb
Host smart-6d6f4538-cd37-41d9-8f04-185d702df6a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9077534302847197073874571660506548421328355231979694655498704097451543680452 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.90775343028471970738745716605065484213283552319796946554987040
97451543680452
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest
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