Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

99291

1

T18

20

T19

1

T20

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132924	1			T18	2		T19	3		T20	23
values[0x0]	38672	1			T18	26		T19	1		T20	5
values[0x1]	42840	1			T18	34		T19	1		T20	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

126226

1

T18

25

T19

3

T20

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	556	1			T91	3		T92	3		T1	2
valid_sources[0x01]	986	1			T24	3		T29	3		T30	3
valid_sources[0x02]	1715	1			T25	11		T26	11		T28	11
valid_sources[0x03]	1542	1			T18	1		T20	4		T24	6
valid_sources[0x04]	950	1			T25	8		T26	8		T28	8
valid_sources[0x05]	620	1			T1	1		T12	4		T14	12
valid_sources[0x06]	1290	1			T23	1		T24	2		T25	5
valid_sources[0x07]	625	1			T1	3		T12	11		T14	3
valid_sources[0x08]	692	1			T18	5		T24	1		T29	1
valid_sources[0x09]	922	1			T24	4		T29	4		T30	4
valid_sources[0x0a]	1160	1			T24	1		T25	3		T26	3
valid_sources[0x0b]	380	1			T1	2		T12	4		T14	6
valid_sources[0x0c]	1707	1			T24	1		T25	7		T26	7
valid_sources[0x0d]	755	1			T24	8		T29	8		T30	8
valid_sources[0x0e]	5364	1			T18	7		T19	3		T20	11
valid_sources[0x0f]	345	1			T1	3		T12	14		T16	2
valid_sources[0x10]	655	1			T25	3		T26	3		T28	3
valid_sources[0x11]	425	1			T12	21		T14	4		T16	4
valid_sources[0x12]	950	1			T1	1		T12	38		T14	9
valid_sources[0x13]	565	1			T24	2		T29	2		T30	2
valid_sources[0x14]	1102	1			T24	1		T25	9		T26	9
valid_sources[0x15]	865	1			T25	5		T26	5		T28	5
valid_sources[0x16]	590	1			T25	5		T26	5		T28	5
valid_sources[0x17]	450	1			T1	4		T12	1		T14	9
valid_sources[0x18]	760	1			T25	7		T26	7		T28	7
valid_sources[0x19]	1050	1			T25	4		T26	4		T28	4
valid_sources[0x1a]	500	1			T25	2		T26	2		T28	2
valid_sources[0x1b]	280	1			T12	11		T14	1		T74	1
valid_sources[0x1c]	334	1			T24	2		T45	2		T63	2
valid_sources[0x1d]	655	1			T24	7		T25	2		T26	2
valid_sources[0x1e]	1630	1			T24	4		T25	17		T26	17
valid_sources[0x1f]	515	1			T12	3		T14	13		T74	13
valid_sources[0x20]	705	1			T24	1		T29	1		T30	1
valid_sources[0x21]	1176	1			T24	3		T25	2		T26	2
valid_sources[0x22]	612	1			T24	2		T29	2		T30	2
valid_sources[0x23]	540	1			T1	2		T12	31		T14	8
valid_sources[0x24]	760	1			T1	2		T2	6		T12	8
valid_sources[0x25]	1904	1			T24	13		T29	13		T30	13
valid_sources[0x26]	430	1			T12	22		T69	16		T8	12
valid_sources[0x27]	857	1			T24	5		T29	5		T30	5
valid_sources[0x28]	280	1			T12	1		T69	27		T8	7
valid_sources[0x29]	555	1			T2	10		T12	1		T3	10
valid_sources[0x2a]	440	1			T1	1		T12	6		T69	14
valid_sources[0x2b]	515	1			T25	4		T26	4		T28	4
valid_sources[0x2c]	1065	1			T24	4		T29	4		T30	4
valid_sources[0x2d]	1525	1			T25	8		T26	8		T28	8
valid_sources[0x2e]	220	1			T25	1		T26	1		T28	1
valid_sources[0x2f]	1290	1			T18	2		T24	5		T43	2
valid_sources[0x30]	625	1			T24	5		T25	2		T26	2
valid_sources[0x31]	930	1			T25	4		T26	4		T28	4
valid_sources[0x32]	675	1			T1	2		T2	6		T3	6
valid_sources[0x33]	540	1			T25	2		T26	2		T28	2
valid_sources[0x34]	1585	1			T24	8		T25	11		T26	11
valid_sources[0x35]	395	1			T65	10		T66	10		T1	1
valid_sources[0x36]	430	1			T12	3		T69	35		T8	12
valid_sources[0x37]	1049	1			T18	3		T20	2		T23	3
valid_sources[0x38]	770	1			T24	4		T29	4		T30	4
valid_sources[0x39]	665	1			T25	9		T26	9		T28	9
valid_sources[0x3a]	564	1			T24	2		T25	2		T26	2
valid_sources[0x3b]	712	1			T24	11		T29	11		T30	11
valid_sources[0x3c]	950	1			T24	7		T29	7		T30	7
valid_sources[0x3d]	540	1			T24	2		T25	1		T26	1
valid_sources[0x3e]	1140	1			T25	1		T26	1		T28	1
valid_sources[0x3f]	2047	1			T24	12		T25	11		T26	11
valid_sources[0x40]	520	1			T25	3		T26	3		T28	3
valid_sources[0x41]	445	1			T1	1		T12	12		T14	6
valid_sources[0x42]	580	1			T25	1		T26	1		T28	1
valid_sources[0x43]	455	1			T24	1		T29	1		T30	1
valid_sources[0x44]	290	1			T1	4		T12	28		T14	1
valid_sources[0x45]	1300	1			T24	5		T25	14		T26	14
valid_sources[0x46]	820	1			T24	4		T29	4		T30	4
valid_sources[0x47]	815	1			T1	2		T12	22		T14	20
valid_sources[0x48]	405	1			T12	5		T14	1		T74	1
valid_sources[0x49]	1189	1			T24	2		T25	5		T43	2
valid_sources[0x4a]	380	1			T12	16		T14	2		T74	2
valid_sources[0x4b]	430	1			T24	1		T29	1		T30	1
valid_sources[0x4c]	1468	1			T25	13		T26	13		T45	3
valid_sources[0x4d]	620	1			T65	1		T66	1		T1	1
valid_sources[0x4e]	815	1			T24	7		T29	7		T30	7
valid_sources[0x4f]	790	1			T25	10		T26	10		T28	10
valid_sources[0x50]	445	1			T33	6		T90	6		T110	6
valid_sources[0x51]	620	1			T24	1		T25	1		T26	1
valid_sources[0x52]	220	1			T1	1		T12	2		T69	14
valid_sources[0x53]	520	1			T25	5		T26	5		T28	5
valid_sources[0x54]	929	1			T91	7		T92	7		T65	11
valid_sources[0x55]	1285	1			T24	14		T25	6		T26	6
valid_sources[0x56]	940	1			T25	2		T26	2		T28	2
valid_sources[0x57]	1116	1			T24	8		T29	8		T30	8
valid_sources[0x58]	520	1			T1	2		T2	1		T12	15
valid_sources[0x59]	745	1			T25	3		T26	3		T28	3
valid_sources[0x5a]	1565	1			T24	16		T25	5		T26	5
valid_sources[0x5b]	1215	1			T25	16		T26	16		T28	16
valid_sources[0x5c]	1745	1			T25	23		T26	23		T28	23
valid_sources[0x5d]	470	1			T1	8		T12	8		T14	5
valid_sources[0x5e]	1249	1			T18	2		T20	2		T24	8
valid_sources[0x5f]	992	1			T24	2		T29	2		T30	2
valid_sources[0x60]	235	1			T65	1		T66	1		T14	6
valid_sources[0x61]	365	1			T1	1		T12	3		T14	3
valid_sources[0x62]	1550	1			T25	19		T26	19		T28	19
valid_sources[0x63]	175	1			T65	2		T66	2		T12	6
valid_sources[0x64]	1090	1			T24	6		T25	6		T26	6
valid_sources[0x65]	1645	1			T18	4		T24	5		T25	4
valid_sources[0x66]	280	1			T25	1		T26	1		T28	1
valid_sources[0x67]	1260	1			T20	5		T24	3		T25	10
valid_sources[0x68]	647	1			T91	1		T92	1		T12	27
valid_sources[0x69]	422	1			T24	4		T29	4		T30	4
valid_sources[0x6a]	565	1			T65	6		T66	6		T1	6
valid_sources[0x6b]	665	1			T25	2		T26	2		T28	2
valid_sources[0x6c]	290	1			T1	2		T12	12		T69	14
valid_sources[0x6d]	530	1			T25	4		T26	4		T28	4
valid_sources[0x6e]	1274	1			T24	13		T45	6		T63	6
valid_sources[0x6f]	495	1			T25	2		T26	2		T28	2
valid_sources[0x70]	780	1			T24	6		T29	6		T30	6
valid_sources[0x71]	720	1			T1	1		T12	23		T69	25
valid_sources[0x72]	966	1			T23	2		T24	3		T25	4
valid_sources[0x73]	560	1			T25	2		T26	2		T28	2
valid_sources[0x74]	810	1			T24	6		T25	1		T26	1
valid_sources[0x75]	1660	1			T18	11		T24	2		T43	5
valid_sources[0x76]	760	1			T23	3		T25	6		T26	6
valid_sources[0x77]	1380	1			T24	5		T25	1		T26	1
valid_sources[0x78]	1342	1			T24	1		T25	3		T26	3
valid_sources[0x79]	840	1			T25	1		T26	1		T28	1
valid_sources[0x7a]	620	1			T24	1		T29	1		T30	1
valid_sources[0x7b]	871	1			T24	9		T29	9		T30	9
valid_sources[0x7c]	785	1			T25	2		T26	2		T28	2
valid_sources[0x7d]	615	1			T24	1		T29	1		T30	1
valid_sources[0x7e]	860	1			T25	10		T26	10		T28	10
valid_sources[0x7f]	1957	1			T18	6		T19	2		T24	6
valid_sources[0x80]	415	1			T25	2		T26	2		T28	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56449

1

T18

2

T19

1

T20

9

values[0x0]

all_enables

biggest_size

23727

1

T18

12

T20

3

T23

1

values[0x1]

all_enables

biggest_size

19115

1

T18

6

T20

2

T23

1