Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T19,T20,T24
1	0	Covered	T19,T20,T24
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T19,T20,T24
1	0	Covered	T20,T21,T22
1	1	Covered	T19,T20,T24

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	125837	0	0
SrcPulseCheck_M	2147483647	127146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	125837
T24	5488664	27
T25	4047448	15
T26	4047448	15
T27	1632376	0
T28	4047448	15
T29	0	27
T30	1372166	27
T33	0	2
T34	0	27
T35	0	15
T38	0	15
T42	906136	0
T43	1110688	0
T44	932720	0
T45	1130928	0
T46	906136	0
T87	352820	16
T88	352820	16
T89	0	16
T90	141936	0
T93	0	16
T94	0	16
T95	0	16
T96	0	16
T97	0	16
T98	0	16
T99	0	5
T100	0	16
T101	277672	0
T102	226534	0
T103	237938	0
T104	237938	0
T105	277672	0
T106	294458	0
T107	277672	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	127146
T24	5488664	27
T25	4047448	15
T26	4047448	15
T27	1632376	0
T28	4047448	15
T29	0	27
T30	1372166	27
T33	0	2
T34	0	27
T35	0	15
T38	0	15
T42	906136	0
T43	1110688	0
T44	932720	0
T45	1130928	0
T46	906136	0
T87	352820	16
T88	352820	16
T89	0	16
T90	506	0
T93	0	16
T94	0	16
T95	0	16
T96	0	16
T97	0	16
T98	0	16
T99	0	5
T100	0	16
T101	277672	0
T102	226534	0
T103	237938	0
T104	237938	0
T105	277672	0
T106	294458	0
T107	277672	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T19,T24,T25
1	0	Covered	T19,T24,T25
1	1	Covered	T12,T14,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T19,T24,T25
1	0	Covered	T12,T14,T16
1	1	Covered	T19,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1932	0	0
SrcPulseCheck_M	754515696	1962	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1932
T19	884	1
T20	1037	0
T23	817	0
T24	23657	9
T25	17445	5
T26	17445	5
T28	0	5
T29	0	9
T30	0	9
T33	0	1
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T108	0	1
T109	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1962
T19	247808	1
T20	130789	0
T23	203230	0
T24	662426	9
T25	488486	5
T26	488486	5
T28	0	5
T29	0	9
T30	0	9
T33	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T108	0	1
T109	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T19,T24,T25
1	0	Covered	T19,T24,T25
1	1	Covered	T12,T14,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T19,T24,T25
1	0	Covered	T12,T14,T16
1	1	Covered	T19,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1932	0	0
SrcPulseCheck_M	2727417	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1932
T19	247808	1
T20	130789	0
T23	203230	0
T24	662426	9
T25	488486	5
T26	488486	5
T28	0	5
T29	0	9
T30	0	9
T33	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T108	0	1
T109	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1932
T19	884	1
T20	1037	0
T23	817	0
T24	23657	9
T25	17445	5
T26	17445	5
T28	0	5
T29	0	9
T30	0	9
T33	0	1
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T108	0	1
T109	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1197
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1238	0	0
SrcPulseCheck_M	754515696	1268	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1238
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1268
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1238	0	0
SrcPulseCheck_M	2727417	1238	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1238
T20	130789	2
T21	0	2
T22	0	2
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	2
T40	0	2
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1238
T20	1037	2
T21	0	2
T22	0	2
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	2
T40	0	2
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	2
T48	0	2
T49	0	2
T50	0	2
T51	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T12,T14,T16

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T21,T22
1	0	Covered	T12,T14,T16
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	800	0	0
SrcPulseCheck_M	754515696	830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	800
T20	1037	1
T21	0	1
T22	0	1
T23	817	0
T24	23657	0
T25	17445	0
T26	17445	0
T27	817	0
T39	0	1
T40	0	1
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	830
T20	130789	1
T21	0	1
T22	0	1
T23	203230	0
T24	662426	0
T25	488486	0
T26	488486	0
T27	203230	0
T39	0	1
T40	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T47	0	1
T48	0	1
T49	0	1
T50	0	1
T51	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T24,T25
1	0	Covered	T20,T24,T25
1	1	Covered	T25,T26,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T20,T24,T25
1	0	Covered	T25,T26,T28
1	1	Covered	T20,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1510	0	0
SrcPulseCheck_M	754515696	1552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1510
T20	1037	1
T21	0	1
T22	0	1
T23	817	0
T24	23657	8
T25	17445	7
T26	17445	7
T27	817	0
T28	0	7
T29	0	8
T30	0	8
T34	0	8
T41	403	0
T42	403	0
T43	494	0
T44	414	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1552
T20	130789	1
T21	0	1
T22	0	1
T23	203230	0
T24	662426	8
T25	488486	7
T26	488486	7
T27	203230	0
T28	0	7
T29	0	8
T30	0	8
T33	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T43,T26
1	0	Covered	T25,T43,T26
1	1	Covered	T25,T43,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T43,T26
1	0	Covered	T25,T43,T26
1	1	Covered	T25,T43,T26

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	3105	0	0
SrcPulseCheck_M	754515696	3135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	3105
T21	1037	0
T25	17445	20
T26	17445	20
T27	817	0
T28	17445	20
T35	0	20
T42	403	0
T43	494	20
T44	414	0
T45	503	0
T46	403	0
T64	0	20
T101	0	20
T105	0	20
T107	0	20
T111	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	3135
T21	130789	0
T25	488486	20
T26	488486	20
T27	203230	0
T28	488486	20
T35	0	20
T42	112864	0
T43	138342	20
T44	116176	0
T45	140863	0
T46	112864	0
T64	0	20
T101	0	20
T105	0	20
T107	0	20
T111	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T43,T26
1	0	Covered	T25,T43,T26
1	1	Covered	T25,T43,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T43,T26
1	0	Covered	T25,T43,T26
1	1	Covered	T25,T43,T26

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	3105	0	0
SrcPulseCheck_M	2727417	3105	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	3105
T21	130789	0
T25	488486	20
T26	488486	20
T27	203230	0
T28	488486	20
T35	0	20
T42	112864	0
T43	138342	20
T44	116176	0
T45	140863	0
T46	112864	0
T64	0	20
T101	0	20
T105	0	20
T107	0	20
T111	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	3105
T21	1037	0
T25	17445	20
T26	17445	20
T27	817	0
T28	17445	20
T35	0	20
T42	403	0
T43	494	20
T44	414	0
T45	503	0
T46	403	0
T64	0	20
T101	0	20
T105	0	20
T107	0	20
T111	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T43
1	0	Covered	T18,T25,T43
1	1	Covered	T18,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T43
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T25,T43

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5170	0	0
SrcPulseCheck_M	754515696	5200	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5170
T18	523	20
T19	884	0
T20	1037	0
T23	817	0
T24	23657	0
T25	17445	41
T26	17445	41
T28	0	41
T41	403	0
T42	403	0
T43	494	1
T45	0	20
T63	0	20
T64	0	1
T101	0	1
T105	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5200
T18	146706	20
T19	247808	0
T20	130789	0
T23	203230	0
T24	662426	0
T25	488486	41
T26	488486	41
T28	0	41
T41	112864	0
T42	112864	0
T43	138342	1
T45	0	20
T63	0	20
T64	0	1
T101	0	1
T105	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T43
1	0	Covered	T18,T25,T43
1	1	Covered	T18,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T43
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T25,T43

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5170	0	0
SrcPulseCheck_M	2727417	5170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5170
T18	146706	20
T19	247808	0
T20	130789	0
T23	203230	0
T24	662426	0
T25	488486	41
T26	488486	41
T28	0	41
T41	112864	0
T42	112864	0
T43	138342	1
T45	0	20
T63	0	20
T64	0	1
T101	0	1
T105	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5170
T18	523	20
T19	884	0
T20	1037	0
T23	817	0
T24	23657	0
T25	17445	41
T26	17445	41
T28	0	41
T41	403	0
T42	403	0
T43	494	1
T45	0	20
T63	0	20
T64	0	1
T101	0	1
T105	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T19,T24
1	0	Covered	T18,T19,T24
1	1	Covered	T18,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T19,T24
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T19,T24

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5967	0	0
SrcPulseCheck_M	754515696	5997	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5967
T18	523	20
T19	884	1
T20	1037	0
T23	817	0
T24	23657	9
T25	17445	46
T26	17445	46
T28	0	46
T29	0	9
T41	403	0
T42	403	0
T43	494	1
T45	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5997
T18	146706	20
T19	247808	1
T20	130789	0
T23	203230	0
T24	662426	9
T25	488486	46
T26	488486	46
T28	0	46
T29	0	9
T41	112864	0
T42	112864	0
T43	138342	1
T45	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T19,T24
1	0	Covered	T18,T19,T24
1	1	Covered	T18,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T19,T24
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T19,T24

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5967	0	0
SrcPulseCheck_M	2727417	5967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5967
T18	146706	20
T19	247808	1
T20	130789	0
T23	203230	0
T24	662426	9
T25	488486	46
T26	488486	46
T28	0	46
T29	0	9
T41	112864	0
T42	112864	0
T43	138342	1
T45	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5967
T18	523	20
T19	884	1
T20	1037	0
T23	817	0
T24	23657	9
T25	17445	46
T26	17445	46
T28	0	46
T29	0	9
T41	403	0
T42	403	0
T43	494	1
T45	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T26
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T26
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	4925	0	0
SrcPulseCheck_M	754515696	4955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	4925
T18	523	20
T19	884	0
T20	1037	0
T23	817	0
T24	23657	0
T25	17445	40
T26	17445	40
T28	0	40
T35	0	40
T38	0	40
T41	403	0
T42	403	0
T43	494	0
T45	0	20
T63	0	20
T106	0	20
T112	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	4955
T18	146706	20
T19	247808	0
T20	130789	0
T23	203230	0
T24	662426	0
T25	488486	40
T26	488486	40
T28	0	40
T35	0	40
T38	0	40
T41	112864	0
T42	112864	0
T43	138342	0
T45	0	20
T63	0	20
T106	0	20
T112	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T26
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T25,T26

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T18,T25,T26
1	0	Covered	T18,T25,T26
1	1	Covered	T18,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	4925	0	0
SrcPulseCheck_M	2727417	4925	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	4925
T18	146706	20
T19	247808	0
T20	130789	0
T23	203230	0
T24	662426	0
T25	488486	40
T26	488486	40
T28	0	40
T35	0	40
T38	0	40
T41	112864	0
T42	112864	0
T43	138342	0
T45	0	20
T63	0	20
T106	0	20
T112	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	4925
T18	523	20
T19	884	0
T20	1037	0
T23	817	0
T24	23657	0
T25	17445	40
T26	17445	40
T28	0	40
T35	0	40
T38	0	40
T41	403	0
T42	403	0
T43	494	0
T45	0	20
T63	0	20
T106	0	20
T112	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T25,T26
1	0	Covered	T23,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T23,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1246	0	0
SrcPulseCheck_M	754515696	1276	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1246
T23	817	1
T24	23657	0
T25	17445	1
T26	17445	1
T27	817	1
T28	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T37	0	1
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T45	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1276
T23	203230	1
T24	662426	0
T25	488486	1
T26	488486	1
T27	203230	1
T28	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T37	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T25,T26
1	0	Covered	T23,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T23,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1246	0	0
SrcPulseCheck_M	2727417	1246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1246
T23	203230	1
T24	662426	0
T25	488486	1
T26	488486	1
T27	203230	1
T28	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T37	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1246
T23	817	1
T24	23657	0
T25	17445	1
T26	17445	1
T27	817	1
T28	0	1
T31	0	1
T32	0	1
T35	0	1
T36	0	1
T37	0	1
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T45	503	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T24,T25
1	0	Covered	T91,T92,T12
1	1	Covered	T23,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1924	0	0
SrcPulseCheck_M	754515696	1974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1924
T23	817	1
T24	23657	9
T25	17445	6
T26	17445	6
T27	817	1
T28	0	6
T29	0	9
T30	0	9
T31	0	1
T32	0	1
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T45	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1974
T23	203230	1
T24	662426	9
T25	488486	6
T26	488486	6
T27	203230	1
T28	0	6
T29	0	9
T30	0	9
T31	0	1
T32	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T24,T25
1	0	Covered	T91,T92,T12
1	1	Covered	T23,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1924	0	0
SrcPulseCheck_M	2727417	1924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1924
T23	203230	1
T24	662426	9
T25	488486	6
T26	488486	6
T27	203230	1
T28	0	6
T29	0	9
T30	0	9
T31	0	1
T32	0	1
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1924
T23	817	1
T24	23657	9
T25	17445	6
T26	17445	6
T27	817	1
T28	0	6
T29	0	9
T30	0	9
T31	0	1
T32	0	1
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T45	503	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1254	0	0
SrcPulseCheck_M	754515696	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1254
T30	23657	0
T87	627	5
T88	627	5
T89	0	5
T93	0	5
T94	0	5
T95	0	5
T96	0	5
T97	0	5
T98	0	5
T100	0	5
T101	494	0
T102	403	0
T103	423	0
T104	423	0
T105	494	0
T106	523	0
T107	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1289
T30	662426	0
T87	175783	5
T88	175783	5
T89	0	5
T93	0	5
T94	0	5
T95	0	5
T96	0	5
T97	0	5
T98	0	5
T100	0	5
T101	138342	0
T102	112864	0
T103	118546	0
T104	118546	0
T105	138342	0
T106	146706	0
T107	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1259	0	0
SrcPulseCheck_M	2727417	1259	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1259
T30	662426	0
T87	175783	5
T88	175783	5
T89	0	5
T93	0	5
T94	0	5
T95	0	5
T96	0	5
T97	0	5
T98	0	5
T100	0	5
T101	138342	0
T102	112864	0
T103	118546	0
T104	118546	0
T105	138342	0
T106	146706	0
T107	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1259
T30	23657	0
T87	627	5
T88	627	5
T89	0	5
T93	0	5
T94	0	5
T95	0	5
T96	0	5
T97	0	5
T98	0	5
T100	0	5
T101	494	0
T102	403	0
T103	423	0
T104	423	0
T105	494	0
T106	523	0
T107	494	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1192	0	0
SrcPulseCheck_M	754515696	1222	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1192
T30	23657	0
T87	627	3
T88	627	3
T89	0	3
T93	0	3
T94	0	3
T95	0	3
T96	0	3
T97	0	3
T98	0	3
T100	0	3
T101	494	0
T102	403	0
T103	423	0
T104	423	0
T105	494	0
T106	523	0
T107	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1222
T30	662426	0
T87	175783	3
T88	175783	3
T89	0	3
T93	0	3
T94	0	3
T95	0	3
T96	0	3
T97	0	3
T98	0	3
T100	0	3
T101	138342	0
T102	112864	0
T103	118546	0
T104	118546	0
T105	138342	0
T106	146706	0
T107	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T87,T88,T89
1	0	Covered	T87,T88,T89
1	1	Covered	T87,T88,T89

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1192	0	0
SrcPulseCheck_M	2727417	1192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1192
T30	662426	0
T87	175783	3
T88	175783	3
T89	0	3
T93	0	3
T94	0	3
T95	0	3
T96	0	3
T97	0	3
T98	0	3
T100	0	3
T101	138342	0
T102	112864	0
T103	118546	0
T104	118546	0
T105	138342	0
T106	146706	0
T107	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1192
T30	23657	0
T87	627	3
T88	627	3
T89	0	3
T93	0	3
T94	0	3
T95	0	3
T96	0	3
T97	0	3
T98	0	3
T100	0	3
T101	494	0
T102	403	0
T103	423	0
T104	423	0
T105	494	0
T106	523	0
T107	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T90,T91,T92
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T91,T92,T12
1	1	Covered	T90,T91,T92

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1052	0	0
SrcPulseCheck_M	754515696	1102	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1052
T12	0	2
T14	0	13
T16	0	2
T40	1037	0
T90	506	1
T91	7721	11
T92	0	11
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	884	0
T118	17445	0
T119	17445	0
T120	884	0
T121	503	0
T122	503	0
T123	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1102
T2	0	2
T40	130789	0
T65	0	2
T66	0	2
T90	141936	1
T91	215076	11
T92	0	11
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	247808	0
T118	488486	0
T119	488486	0
T120	247808	0
T121	140863	0
T122	140863	0
T123	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T90,T91,T92
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T91,T92,T12
1	1	Covered	T90,T91,T92

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1052	0	0
SrcPulseCheck_M	2727417	1052	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1052
T12	0	2
T14	0	13
T16	0	2
T40	130789	0
T90	141936	1
T91	215076	11
T92	0	11
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	247808	0
T118	488486	0
T119	488486	0
T120	247808	0
T121	140863	0
T122	140863	0
T123	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1052
T12	0	2
T14	0	13
T16	0	2
T40	1037	0
T90	506	1
T91	7721	11
T92	0	11
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	884	0
T118	17445	0
T119	17445	0
T120	884	0
T121	503	0
T122	503	0
T123	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T65
1	0	Covered	T91,T92,T65
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T2
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	982	0	0
SrcPulseCheck_M	754515696	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	982
T8	0	20
T12	0	2
T14	0	9
T16	0	2
T17	0	2
T69	0	66
T70	0	2
T74	0	9
T91	7721	11
T92	7721	11
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1012
T2	0	1
T3	0	1
T12	0	2
T14	0	9
T16	0	2
T17	0	2
T65	0	2
T66	0	2
T91	215076	11
T92	215076	11
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	982	0	0
SrcPulseCheck_M	2727417	982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	982
T8	0	20
T12	0	2
T14	0	9
T16	0	2
T17	0	2
T69	0	66
T70	0	2
T74	0	9
T91	215076	11
T92	215076	11
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	982
T8	0	20
T12	0	2
T14	0	9
T16	0	2
T17	0	2
T69	0	66
T70	0	2
T74	0	9
T91	7721	11
T92	7721	11
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T65
1	0	Covered	T91,T92,T65
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T2
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1127	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1127
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	67
T70	0	2
T74	0	16
T91	7721	11
T92	7721	11
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T2	0	2
T3	0	2
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T65	0	2
T66	0	2
T91	215076	11
T92	215076	11
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1127	0	0
SrcPulseCheck_M	2727417	1127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1127
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	67
T70	0	2
T74	0	16
T91	215076	11
T92	215076	11
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1127
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	67
T70	0	2
T74	0	16
T91	7721	11
T92	7721	11
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T65
1	0	Covered	T91,T92,T65
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T2
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T8	0	20
T12	0	2
T14	0	10
T16	0	2
T17	0	2
T69	0	68
T70	0	2
T74	0	10
T91	7721	11
T92	7721	11
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T2	0	1
T3	0	1
T12	0	2
T14	0	10
T16	0	2
T17	0	2
T65	0	2
T66	0	2
T91	215076	11
T92	215076	11
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T8	0	20
T12	0	2
T14	0	10
T16	0	2
T17	0	2
T69	0	68
T70	0	2
T74	0	10
T91	215076	11
T92	215076	11
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T8	0	20
T12	0	2
T14	0	10
T16	0	2
T17	0	2
T69	0	68
T70	0	2
T74	0	10
T91	7721	11
T92	7721	11
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T90,T91,T92
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T91,T92,T12
1	1	Covered	T90,T91,T92

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1023	0	0
SrcPulseCheck_M	754515696	1053	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1023
T12	0	2
T14	0	11
T16	0	2
T40	1037	0
T90	506	1
T91	7721	9
T92	0	9
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	884	0
T118	17445	0
T119	17445	0
T120	884	0
T121	503	0
T122	503	0
T123	494	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1053
T2	0	1
T40	130789	0
T65	0	2
T66	0	2
T90	141936	1
T91	215076	9
T92	0	9
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	247808	0
T118	488486	0
T119	488486	0
T120	247808	0
T121	140863	0
T122	140863	0
T123	138342	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T90,T91,T92
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T90,T91,T92
1	0	Covered	T91,T92,T12
1	1	Covered	T90,T91,T92

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1023	0	0
SrcPulseCheck_M	2727417	1023	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1023
T12	0	2
T14	0	11
T16	0	2
T40	130789	0
T90	141936	1
T91	215076	9
T92	0	9
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	247808	0
T118	488486	0
T119	488486	0
T120	247808	0
T121	140863	0
T122	140863	0
T123	138342	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1023
T12	0	2
T14	0	11
T16	0	2
T40	1037	0
T90	506	1
T91	7721	9
T92	0	9
T113	0	1
T114	0	1
T115	0	1
T116	0	1
T117	884	0
T118	17445	0
T119	17445	0
T120	884	0
T121	503	0
T122	503	0
T123	494	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T65
1	0	Covered	T91,T92,T65
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T2
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1123	0	0
SrcPulseCheck_M	754515696	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1123
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	67
T70	0	2
T74	0	16
T91	7721	9
T92	7721	9
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1173
T2	0	2
T3	0	2
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T65	0	2
T66	0	2
T91	215076	9
T92	215076	9
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1123	0	0
SrcPulseCheck_M	2727417	1123	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1123
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	67
T70	0	2
T74	0	16
T91	215076	9
T92	215076	9
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1123
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	67
T70	0	2
T74	0	16
T91	7721	9
T92	7721	9
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T65
1	0	Covered	T91,T92,T65
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T2
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1118	0	0
SrcPulseCheck_M	754515696	1168	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1118
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	66
T70	0	2
T74	0	16
T91	7721	9
T92	7721	9
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1168
T2	0	2
T3	0	2
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T65	0	2
T66	0	2
T91	215076	9
T92	215076	9
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1118	0	0
SrcPulseCheck_M	2727417	1118	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1118
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	66
T70	0	2
T74	0	16
T91	215076	9
T92	215076	9
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1118
T8	0	20
T12	0	2
T14	0	16
T16	0	2
T17	0	2
T69	0	66
T70	0	2
T74	0	16
T91	7721	9
T92	7721	9
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T65
1	0	Covered	T91,T92,T65
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T2
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1048	0	0
SrcPulseCheck_M	754515696	1078	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1048
T8	0	20
T12	0	2
T14	0	12
T16	0	2
T17	0	2
T69	0	68
T70	0	2
T74	0	12
T91	7721	9
T92	7721	9
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1078
T2	0	1
T3	0	1
T12	0	2
T14	0	12
T16	0	2
T17	0	2
T65	0	2
T66	0	2
T91	215076	9
T92	215076	9
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92,T12
1	0	Covered	T91,T92,T12
1	1	Covered	T91,T92,T12

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1048	0	0
SrcPulseCheck_M	2727417	1048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1048
T8	0	20
T12	0	2
T14	0	12
T16	0	2
T17	0	2
T69	0	68
T70	0	2
T74	0	12
T91	215076	9
T92	215076	9
T123	138342	0
T124	130789	0
T125	140863	0
T126	134330	0
T127	662426	0
T128	130789	0
T129	203230	0
T130	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1048
T8	0	20
T12	0	2
T14	0	12
T16	0	2
T17	0	2
T69	0	68
T70	0	2
T74	0	12
T91	7721	9
T92	7721	9
T123	494	0
T124	1037	0
T125	503	0
T126	479	0
T127	23657	0
T128	1037	0
T129	817	0
T130	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1777	0	0
SrcPulseCheck_M	754515696	1827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1777
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1827
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1777	0	0
SrcPulseCheck_M	2727417	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1777
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1777
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1597	0	0
SrcPulseCheck_M	754515696	1627	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1597
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1627
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1597	0	0
SrcPulseCheck_M	2727417	1597	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1597
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1597
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1747	0	0
SrcPulseCheck_M	754515696	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1747
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1777
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1747	0	0
SrcPulseCheck_M	2727417	1747	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1747
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1747
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1692	0	0
SrcPulseCheck_M	754515696	1722	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1692
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1722
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1692	0	0
SrcPulseCheck_M	2727417	1692	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1692
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1692
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1968	0	0
SrcPulseCheck_M	754515696	1998	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1968
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1998
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1968	0	0
SrcPulseCheck_M	2727417	1968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1968
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1968
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1763	0	0
SrcPulseCheck_M	754515696	1793	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1763
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1793
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1763	0	0
SrcPulseCheck_M	2727417	1763	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1763
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1763
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1738	0	0
SrcPulseCheck_M	754515696	1768	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1738
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1768
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1738	0	0
SrcPulseCheck_M	2727417	1738	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1738
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1738
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1813	0	0
SrcPulseCheck_M	754515696	1863	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1813
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1863
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1813	0	0
SrcPulseCheck_M	2727417	1813	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1813
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1813
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1773	0	0
SrcPulseCheck_M	754515696	1803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1773
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1803
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1773	0	0
SrcPulseCheck_M	2727417	1773	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1773
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1773
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T33	0	1
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1663	0	0
SrcPulseCheck_M	754515696	1693	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1663
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1693
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1663	0	0
SrcPulseCheck_M	2727417	1663	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1663
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1663
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1603	0	0
SrcPulseCheck_M	754515696	1633	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1603
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1633
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1603	0	0
SrcPulseCheck_M	2727417	1603	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1603
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1603
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1683	0	0
SrcPulseCheck_M	754515696	1733	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1683
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1733
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T91,T92,T12

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T91,T92,T12
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1683	0	0
SrcPulseCheck_M	2727417	1683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1683
T24	662426	9
T25	488486	5
T26	488486	5
T27	203230	0
T28	488486	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0
T99	0	5

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1683
T24	23657	9
T25	17445	5
T26	17445	5
T27	817	0
T28	17445	5
T29	0	9
T30	0	9
T34	0	9
T35	0	5
T38	0	5
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0
T99	0	5

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T26,T28

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T25,T26,T28
1	1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1410	0	0
SrcPulseCheck_M	754515696	1440	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1410
T24	23657	8
T25	17445	7
T26	17445	7
T27	817	0
T28	17445	7
T29	0	8
T30	0	8
T33	0	1
T34	0	8
T35	0	7
T38	0	7
T42	403	0
T43	494	0
T44	414	0
T45	503	0
T46	403	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1440
T24	662426	8
T25	488486	7
T26	488486	7
T27	203230	0
T28	488486	7
T29	0	8
T30	0	8
T33	0	1
T34	0	8
T35	0	7
T38	0	7
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0
T46	112864	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T25,T26
1	0	Covered	T23,T25,T26
1	1	Covered	T23,T27,T31

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T23,T25,T26
1	0	Covered	T23,T27,T31
1	1	Covered	T23,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T18,T19,T20
0	Covered	T18,T19,T20

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	990	0	0
SrcPulseCheck_M	754515696	1022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	990
T23	817	3
T24	23657	0
T25	17445	1
T26	17445	1
T27	817	3
T28	0	1
T31	0	3
T32	0	3
T35	0	1
T36	0	3
T37	0	3
T41	403	0
T42	403	0
T43	494	0
T44	414	0
T45	503	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1022
T23	203230	3
T24	662426	0
T25	488486	1
T26	488486	1
T27	203230	3
T28	0	1
T31	0	3
T32	0	3
T35	0	1
T36	0	3
T37	0	3
T41	112864	0
T42	112864	0
T43	138342	0
T44	116176	0
T45	140863	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc