Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_com_det_ctl_1.wr_en_data

Module Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_det_ctl_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_det_ctl_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_det_ctl_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_0_bat_disable_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_0_interrupt_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_0_ec_rst_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_0_rst_req_0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_1_bat_disable_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_1_interrupt_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_1_ec_rst_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_1_rst_req_1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_2_bat_disable_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_2_interrupt_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_2_ec_rst_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_2_rst_req_2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_3_bat_disable_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_3_interrupt_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_3_ec_rst_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_com_out_ctl_3_rst_req_3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_combo_intr_status_combo0_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_combo_intr_status_combo1_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_combo_intr_status_combo2_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_combo_intr_status_combo3_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_pwrb_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.00	100.00	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_key0_in_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_key1_in_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_bat_disable_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_interrupt_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_ec_rst_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_rst_req_0.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_bat_disable_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_interrupt_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_ec_rst_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_rst_req_1.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_bat_disable_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_interrupt_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_ec_rst_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_rst_req_2.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_bat_disable_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_interrupt_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_ec_rst_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	39	0	0

Line No.	Covered	Statements
33	1	1
34	1	1
39		unreachable

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Unreachable
1	0	Covered	T24,T25,T26

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_rst_req_3.wr_en_data_arb

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	34	2	2	100.00



	LineNo.	Expression
-1-:	34	((we == 1'b1)) ?

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T18,T19,T20

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

Line No.	Covered	Statements
88	1	1
110	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo0_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T26,T28
1	0	Covered	T24,T25,T26

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T25,T26,T28
1	1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

Line No.	Covered	Statements
88	1	1
110	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo1_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T26,T28
1	0	Covered	T24,T25,T26

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T25,T26,T28
1	1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

Line No.	Covered	Statements
88	1	1
110	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo2_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T26,T28
1	0	Covered	T24,T25,T26

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T25,T26,T28
1	1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

Line No.	Covered	Statements
88	1	1
110	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_combo3_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T24,T25,T26

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

Line No.	Covered	Statements
88	1	1
110	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92
1	0	Covered	T23,T25,T26

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T91,T92

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T91,T92

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T23,T25,T26

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

Line No.	Covered	Statements
88	1	1
110	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	9	90.00
Logical	10	9	90.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T91,T92
1	0	Covered	T23,T25,T26

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Not Covered
1	1	Covered	T91,T92

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T91,T92

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T23,T25,T26

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

Line No.	Covered	Statements
88	1	1
110	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T18,T19,T20
0	1	Covered	T25,T26,T28
1	0	Covered	T23,T25,T26

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T18,T19,T20
1	0	Covered	T25,T26,T28
1	1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T25,T26,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T18,T19,T20
1	Covered	T23,T25,T26