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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
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T554 /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.14458642481300152623166168424481365568823051824594583653416809018190715330508 Oct 25 02:15:07 PM PDT 23 Oct 25 02:15:12 PM PDT 23 2619740714 ps
T555 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.66406257875798878598552791836142412803305324465717965507456072768048001260540 Oct 25 02:13:43 PM PDT 23 Oct 25 02:16:45 PM PDT 23 118289458206 ps
T556 /workspace/coverage/default/16.sysrst_ctrl_alert_test.58015594399408261124840565022108812948192836845953778773236117080233676696225 Oct 25 02:13:40 PM PDT 23 Oct 25 02:13:44 PM PDT 23 2015424120 ps
T557 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.71762565043320194188715732530349863800669846200809820139963132826245687096670 Oct 25 02:12:34 PM PDT 23 Oct 25 02:12:39 PM PDT 23 2619740714 ps
T558 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.58332965163654955705222798486159707939499416472292145556444479164193031985531 Oct 25 02:12:15 PM PDT 23 Oct 25 02:12:20 PM PDT 23 2470384766 ps
T559 /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.112442096683000324675815899821377491714443931944519377485309588984479801269670 Oct 25 02:14:06 PM PDT 23 Oct 25 02:14:10 PM PDT 23 2074566504 ps
T560 /workspace/coverage/default/28.sysrst_ctrl_smoke.70612189996159076098576350593565091641148018446183893481057162839974161984250 Oct 25 02:14:14 PM PDT 23 Oct 25 02:14:19 PM PDT 23 2116887594 ps
T561 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.99839464862546863005864614834180585179985606680583731770787605094740064379003 Oct 25 02:13:41 PM PDT 23 Oct 25 02:13:46 PM PDT 23 2619740714 ps
T562 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.18517409114949272434998850003945252887994566220728731886530172918091256618165 Oct 25 02:14:14 PM PDT 23 Oct 25 02:14:19 PM PDT 23 2515402263 ps
T563 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.65812357495233772087179027728421095591670820393730115889471133424085967294388 Oct 25 02:14:08 PM PDT 23 Oct 25 02:17:10 PM PDT 23 118289458206 ps
T564 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.35305195920743236085259037253809834902112836910656975486043724673827321120521 Oct 25 02:12:39 PM PDT 23 Oct 25 02:12:45 PM PDT 23 3138968703 ps
T565 /workspace/coverage/default/44.sysrst_ctrl_alert_test.72562968382855238022254368353322801076570985169242605100563514535365227566506 Oct 25 02:15:55 PM PDT 23 Oct 25 02:15:59 PM PDT 23 2015424120 ps
T566 /workspace/coverage/default/8.sysrst_ctrl_smoke.87929822996563829252361850468922617700662598586050314704022702537027921112209 Oct 25 02:12:14 PM PDT 23 Oct 25 02:12:19 PM PDT 23 2116887594 ps
T567 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.87188647418251716177566543006132963666826001270028381566207061413201323831988 Oct 25 02:14:12 PM PDT 23 Oct 25 02:17:15 PM PDT 23 118289458206 ps
T568 /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.112168207795633029554528347939455898796502197252656948958867985318053932628965 Oct 25 02:15:58 PM PDT 23 Oct 25 02:16:04 PM PDT 23 5189470156 ps
T569 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.73947736489660840049438954951582322410828477774014946580124992997833570184478 Oct 25 02:13:11 PM PDT 23 Oct 25 02:13:16 PM PDT 23 2515402263 ps
T570 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.58971397089644241212172185209742230630878888132580711556321848596607716234398 Oct 25 02:15:58 PM PDT 23 Oct 25 02:16:03 PM PDT 23 2074566504 ps
T571 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.105767662421426746120080067755680909834288698630196049309357232946371525944994 Oct 25 02:13:40 PM PDT 23 Oct 25 02:13:47 PM PDT 23 4089103959 ps
T572 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.88239982112895423777798550813663695033894621917213639064993501737832772181475 Oct 25 02:16:00 PM PDT 23 Oct 25 02:16:07 PM PDT 23 4089103959 ps
T573 /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.98200383444358734768088181810284803108173993151603178153106714651133921666850 Oct 25 02:13:24 PM PDT 23 Oct 25 02:13:29 PM PDT 23 2515402263 ps
T574 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.39891507436438059715038168666416910491809283059267000641676843802251816743767 Oct 25 02:13:59 PM PDT 23 Oct 25 02:14:03 PM PDT 23 2074566504 ps
T575 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.58369302493561073947175491361908534661093054982062097988123930869972720116203 Oct 25 02:15:17 PM PDT 23 Oct 25 02:15:22 PM PDT 23 2470384766 ps
T576 /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.51043930255155754851231165099055164727971053333861905560059428638496753292573 Oct 25 02:14:07 PM PDT 23 Oct 25 02:14:12 PM PDT 23 2619740714 ps
T577 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.114880566458890283860981237185745755774296746095391327040611997316265783218 Oct 25 02:13:19 PM PDT 23 Oct 25 02:13:26 PM PDT 23 4089103959 ps
T578 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.70735834402667129164886153969837044286644217072781090816688388845303758859146 Oct 25 02:12:56 PM PDT 23 Oct 25 02:13:03 PM PDT 23 4425119128 ps
T579 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.102052375941162182731118982305152127735951273623767376519944621772254573012799 Oct 25 02:14:01 PM PDT 23 Oct 25 02:14:08 PM PDT 23 5189470156 ps
T580 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.19798345635069769299856596600512400932723502805269391273725985392189576477719 Oct 25 02:14:10 PM PDT 23 Oct 25 02:14:17 PM PDT 23 4089103959 ps
T581 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.7092228939302550392032946309035062873947203981674839000849452928281109951006 Oct 25 02:14:04 PM PDT 23 Oct 25 02:14:10 PM PDT 23 3138968703 ps
T582 /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.5190654928093293322926107921941399110707460410615326580428048814404071397086 Oct 25 02:14:03 PM PDT 23 Oct 25 02:14:08 PM PDT 23 2074566504 ps
T583 /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.40427323027577279765767824267806037406974208598166248568415300777703698773375 Oct 25 02:14:10 PM PDT 23 Oct 25 02:14:16 PM PDT 23 2470384766 ps
T584 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.89471165311807699874897384855099800017932093394127468582225068772893458007046 Oct 25 02:14:13 PM PDT 23 Oct 25 02:14:18 PM PDT 23 2074566504 ps
T585 /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.55801161153320894533437820480982837751049022730161854235764369134786512045275 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:22 PM PDT 23 2470384766 ps
T586 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.78779096689609194205610179704146990038480228047368199193974018548439303564587 Oct 25 02:13:00 PM PDT 23 Oct 25 02:13:05 PM PDT 23 2470384766 ps
T587 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.29312948939870707751078375616677253233823610084618755715735842136532285757355 Oct 25 02:13:16 PM PDT 23 Oct 25 02:13:21 PM PDT 23 5189470156 ps
T588 /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.63497674273336783460857561358382116873455397343797185424176227038831336335734 Oct 25 02:13:12 PM PDT 23 Oct 25 02:13:20 PM PDT 23 4425119128 ps
T589 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.40662606449081726251080699074874513429142682171744736733672237993668561211946 Oct 25 02:13:16 PM PDT 23 Oct 25 02:13:22 PM PDT 23 2470384766 ps
T590 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.100304273275317505088253543578727241529437411618331618368397055211072121082081 Oct 25 02:14:09 PM PDT 23 Oct 25 02:14:16 PM PDT 23 4089103959 ps
T591 /workspace/coverage/default/46.sysrst_ctrl_alert_test.47126090139353006167086640418304399103789835833527574776353473508083627961669 Oct 25 02:16:06 PM PDT 23 Oct 25 02:16:10 PM PDT 23 2015424120 ps
T592 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.24642358382570246915380477887852188518379067771424229022757210525814524757634 Oct 25 02:14:13 PM PDT 23 Oct 25 02:14:18 PM PDT 23 2619740714 ps
T593 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.17785786736580971680151389148052219015070332397077744383750230299081089690591 Oct 25 02:13:15 PM PDT 23 Oct 25 02:13:20 PM PDT 23 2619740714 ps
T594 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.81891427139305195568041980071675300462295051679221841940859774802676161361037 Oct 25 02:13:40 PM PDT 23 Oct 25 02:13:45 PM PDT 23 2074566504 ps
T595 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.53935489687875799674382801659060619422956118430189852430027964756876565475568 Oct 25 02:15:52 PM PDT 23 Oct 25 02:16:00 PM PDT 23 4425119128 ps
T596 /workspace/coverage/default/2.sysrst_ctrl_stress_all.110085239806920237889640351279924937322523483464583035595384812253775129602553 Oct 25 02:12:53 PM PDT 23 Oct 25 02:15:09 PM PDT 23 87228974549 ps
T597 /workspace/coverage/default/24.sysrst_ctrl_stress_all.88241120116870578960357996054915955042662296465311288350171221049320264130879 Oct 25 02:13:37 PM PDT 23 Oct 25 02:15:51 PM PDT 23 87228974549 ps
T598 /workspace/coverage/default/43.sysrst_ctrl_smoke.78589324771770055076782311826177725490975954699015113372936416358116081121102 Oct 25 02:14:39 PM PDT 23 Oct 25 02:14:44 PM PDT 23 2116887594 ps
T599 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.104480654135994462197367969872841345294101319374008661458429346013500423117229 Oct 25 02:14:09 PM PDT 23 Oct 25 02:14:14 PM PDT 23 2619740714 ps
T600 /workspace/coverage/default/7.sysrst_ctrl_alert_test.55071037980671863752010641482243108681337272409281939578651073117041538589898 Oct 25 02:12:13 PM PDT 23 Oct 25 02:12:17 PM PDT 23 2015424120 ps
T601 /workspace/coverage/default/19.sysrst_ctrl_alert_test.54077299562305102026391153166558347093093271145252008319695787895826175059375 Oct 25 02:14:07 PM PDT 23 Oct 25 02:14:11 PM PDT 23 2015424120 ps
T602 /workspace/coverage/default/32.sysrst_ctrl_smoke.35246156268660910445222472218215499755709452636009852029114986438290824086034 Oct 25 02:14:14 PM PDT 23 Oct 25 02:14:18 PM PDT 23 2116887594 ps
T603 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.88266652445818054348277545365881196778649801881271422636532185260882235255882 Oct 25 02:14:13 PM PDT 23 Oct 25 02:14:19 PM PDT 23 4089103959 ps
T604 /workspace/coverage/default/46.sysrst_ctrl_smoke.79046985072199014984319583639309922679927975693737465936569085699968006122067 Oct 25 02:16:09 PM PDT 23 Oct 25 02:16:14 PM PDT 23 2116887594 ps
T605 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.29721869715712549818233542094218044616620778045355641904035248677501661539933 Oct 25 02:14:25 PM PDT 23 Oct 25 02:14:31 PM PDT 23 5189470156 ps
T606 /workspace/coverage/default/2.sysrst_ctrl_alert_test.92129478243944539830144998427549793188571124313157516224179473407804713646751 Oct 25 02:12:53 PM PDT 23 Oct 25 02:12:57 PM PDT 23 2015424120 ps
T607 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.34554528027823174877943926265080613299411853222772305503974294931371495847971 Oct 25 02:14:00 PM PDT 23 Oct 25 02:14:05 PM PDT 23 2619740714 ps
T608 /workspace/coverage/default/39.sysrst_ctrl_alert_test.62207692934821925921698266363031861768358492668879546697100619328537728405396 Oct 25 02:14:35 PM PDT 23 Oct 25 02:14:39 PM PDT 23 2015424120 ps
T609 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.69231659108081128245743813843245237968458966011626560190662127321292135206274 Oct 25 02:13:24 PM PDT 23 Oct 25 02:13:30 PM PDT 23 5189470156 ps
T610 /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.29246469710341411081584279026516242622797044490247179147491660577752180624565 Oct 25 02:14:06 PM PDT 23 Oct 25 02:14:11 PM PDT 23 2619740714 ps
T611 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.65548491601672975213949021478958807303152782201433988183340831328611407714792 Oct 25 02:12:54 PM PDT 23 Oct 25 02:12:59 PM PDT 23 2515402263 ps
T612 /workspace/coverage/default/47.sysrst_ctrl_alert_test.27055897170813619625474966419423086281219149212318018880053027395041861914997 Oct 25 02:15:14 PM PDT 23 Oct 25 02:15:18 PM PDT 23 2015424120 ps
T613 /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.93200050369717776585021077558604096259841548689012835327823095810276482151882 Oct 25 02:14:12 PM PDT 23 Oct 25 02:14:17 PM PDT 23 2470384766 ps
T614 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.75441821600326246205199231479819188286036306004054319646952817910973494385637 Oct 25 02:14:44 PM PDT 23 Oct 25 02:14:48 PM PDT 23 2074566504 ps
T615 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.42610645421298322308818632297262689387430098882056963625342893788143615250161 Oct 25 02:14:28 PM PDT 23 Oct 25 02:14:33 PM PDT 23 2470384766 ps
T616 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.58399102564664245407935879870083391088831211621333808780421285829693994738652 Oct 25 02:12:56 PM PDT 23 Oct 25 02:13:01 PM PDT 23 2619740714 ps
T617 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.12614040404224745610158598567877012314600252048274713711944151470645709401826 Oct 25 02:15:58 PM PDT 23 Oct 25 02:16:05 PM PDT 23 4089103959 ps
T618 /workspace/coverage/default/25.sysrst_ctrl_stress_all.77672373711812295727937450153219299533865591204590411730801170415410850004556 Oct 25 02:13:44 PM PDT 23 Oct 25 02:15:59 PM PDT 23 87228974549 ps
T619 /workspace/coverage/default/5.sysrst_ctrl_edge_detect.14250425143633846937187335082251952305814467708883162434786458268346656067148 Oct 25 02:12:42 PM PDT 23 Oct 25 02:12:48 PM PDT 23 4089103959 ps
T620 /workspace/coverage/default/4.sysrst_ctrl_combo_detect.86777186098944897046578238912404114781744555209729617647954247685291535246207 Oct 25 02:12:17 PM PDT 23 Oct 25 02:15:18 PM PDT 23 118289458206 ps
T621 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.70466165897222585161916661524080935916304128648257886951412923143373233542446 Oct 25 02:13:46 PM PDT 23 Oct 25 02:13:52 PM PDT 23 3138968703 ps
T622 /workspace/coverage/default/3.sysrst_ctrl_stress_all.102015671119865057131791878655715435554953293073967613950034077322953033415034 Oct 25 02:12:57 PM PDT 23 Oct 25 02:15:14 PM PDT 23 87228974549 ps
T623 /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.13341963417158700258675902767425096754647251098292139328893485130036351692555 Oct 25 02:15:06 PM PDT 23 Oct 25 02:15:12 PM PDT 23 3138968703 ps
T624 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.53526332732015231644073434728534222586618375728502107420587350268552365901945 Oct 25 02:14:01 PM PDT 23 Oct 25 02:14:08 PM PDT 23 5189470156 ps
T625 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.59956001622335732619547746576759982142911328205065791324428667417058314728973 Oct 25 02:15:56 PM PDT 23 Oct 25 02:16:03 PM PDT 23 4089103959 ps
T626 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.13536275003548946411710688659906188844198000341066574620392276515590212097525 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:22 PM PDT 23 2515402263 ps
T627 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.21064577449885376514636226976490530405940607687153487547310525428195916800090 Oct 25 02:15:58 PM PDT 23 Oct 25 02:16:06 PM PDT 23 4425119128 ps
T628 /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.110077511204525397629701167934516464638418803968581886707134650834952233642156 Oct 25 02:12:16 PM PDT 23 Oct 25 02:12:21 PM PDT 23 2515402263 ps
T629 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.63647663848220803336183780502780878403155360352036747632063957654339738122207 Oct 25 02:14:17 PM PDT 23 Oct 25 02:17:19 PM PDT 23 118289458206 ps
T630 /workspace/coverage/default/44.sysrst_ctrl_stress_all.4406679252609749045531421848812502817781335640984659755202055078217725344296 Oct 25 02:15:46 PM PDT 23 Oct 25 02:18:01 PM PDT 23 87228974549 ps
T631 /workspace/coverage/default/7.sysrst_ctrl_stress_all.35094412924559085985166614807830039772579937878920293213919079889621283048471 Oct 25 02:12:15 PM PDT 23 Oct 25 02:14:30 PM PDT 23 87228974549 ps
T632 /workspace/coverage/default/2.sysrst_ctrl_smoke.36053394836426357142127106645910444902335957583994704308459848328930617581047 Oct 25 02:12:17 PM PDT 23 Oct 25 02:12:22 PM PDT 23 2116887594 ps
T633 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.72586766471670866220812067410184679284106642300857284493199365916567807773784 Oct 25 02:13:44 PM PDT 23 Oct 25 02:13:50 PM PDT 23 3138968703 ps
T634 /workspace/coverage/default/5.sysrst_ctrl_stress_all.94878115215251574504183568779403612923035901664923417965481213519029008408733 Oct 25 02:12:52 PM PDT 23 Oct 25 02:15:07 PM PDT 23 87228974549 ps
T635 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3747930584003982370343371924971310429162931311441530051746828669902770735222 Oct 25 02:15:16 PM PDT 23 Oct 25 02:15:21 PM PDT 23 2515402263 ps
T636 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.106906862211579860849233383663402039884003097866221053429715517680248591891950 Oct 25 02:14:29 PM PDT 23 Oct 25 02:17:32 PM PDT 23 118289458206 ps
T637 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.27097561475050219603225508113390252631893733893814885843670119485603408401979 Oct 25 02:15:59 PM PDT 23 Oct 25 02:19:02 PM PDT 23 118289458206 ps
T638 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.33199036062777364845557210883063609475688807663835147324834663380304386416972 Oct 25 02:13:43 PM PDT 23 Oct 25 02:13:51 PM PDT 23 4425119128 ps
T639 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.7171032069312686260637904654334796594901074615897593719613272591979712744803 Oct 25 02:13:12 PM PDT 23 Oct 25 02:13:17 PM PDT 23 2470384766 ps
T640 /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.106437328965265483270991331552140234460218654969247322903595601885387848293385 Oct 25 02:14:11 PM PDT 23 Oct 25 02:14:19 PM PDT 23 4425119128 ps
T641 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.57320637141523540332366647197227662988970468145105611221222659768852135565725 Oct 25 02:12:20 PM PDT 23 Oct 25 02:15:23 PM PDT 23 118289458206 ps
T642 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.35274697078171625221474444448842258411316149865195914056202044426825103010554 Oct 25 02:12:18 PM PDT 23 Oct 25 02:12:23 PM PDT 23 2515402263 ps
T643 /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.59391337731421082265451062232780394497820560978240653730868477096836056146125 Oct 25 02:13:00 PM PDT 23 Oct 25 02:13:06 PM PDT 23 3138968703 ps
T644 /workspace/coverage/default/33.sysrst_ctrl_smoke.17896360441009382968791902349443423119511005253860481268656630310032774277711 Oct 25 02:14:12 PM PDT 23 Oct 25 02:14:17 PM PDT 23 2116887594 ps
T645 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.95065882844863540165627188321325360735223111792788860497370575437698340933371 Oct 25 02:15:54 PM PDT 23 Oct 25 02:15:59 PM PDT 23 2470384766 ps
T646 /workspace/coverage/default/10.sysrst_ctrl_stress_all.74339310607069123250289130690682723244664403568207051914643148620093228206302 Oct 25 02:13:23 PM PDT 23 Oct 25 02:15:38 PM PDT 23 87228974549 ps
T647 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.10596141660776142758243639775775063774295346747252549428233907754507797794367 Oct 25 02:12:55 PM PDT 23 Oct 25 02:15:59 PM PDT 23 118289458206 ps
T648 /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.84770202335914626801036547683736476255103617169865314219210099055435720583690 Oct 25 02:14:07 PM PDT 23 Oct 25 02:14:13 PM PDT 23 2470384766 ps
T649 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.71117876042774730324489481548276092242505259955425005411300696221156437815079 Oct 25 02:15:59 PM PDT 23 Oct 25 02:16:04 PM PDT 23 2470384766 ps
T650 /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.101070859025280831636811557537332227534728285169774656084545373224627167988313 Oct 25 02:14:06 PM PDT 23 Oct 25 02:14:10 PM PDT 23 2074566504 ps
T651 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.101594081484410311715615082117991347401633049930009279674358422494326552167418 Oct 25 02:14:07 PM PDT 23 Oct 25 02:14:13 PM PDT 23 3138968703 ps
T652 /workspace/coverage/default/0.sysrst_ctrl_smoke.5311803202427177348291046256207111049495646271767197837970641382312243246958 Oct 25 02:12:18 PM PDT 23 Oct 25 02:12:22 PM PDT 23 2116887594 ps
T653 /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.352902090775314577066522272311495693413288309334532170558603717910765680680 Oct 25 02:12:19 PM PDT 23 Oct 25 02:12:26 PM PDT 23 2515402263 ps
T654 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.72508207684003376645372438713037575514535303606458598301580113267356662310086 Oct 25 02:12:55 PM PDT 23 Oct 25 02:13:03 PM PDT 23 4425119128 ps
T655 /workspace/coverage/default/20.sysrst_ctrl_alert_test.112005950323892643662180541477738650642458817403897346032258476582833115859836 Oct 25 02:13:41 PM PDT 23 Oct 25 02:13:45 PM PDT 23 2015424120 ps
T656 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3968185779370005639428442341190988990604193345719199808629522077909076429786 Oct 25 02:16:03 PM PDT 23 Oct 25 02:16:11 PM PDT 23 4425119128 ps
T657 /workspace/coverage/default/8.sysrst_ctrl_alert_test.3536875811643174936007217683187925993147231124249371124198368054855927267939 Oct 25 02:13:10 PM PDT 23 Oct 25 02:13:15 PM PDT 23 2015424120 ps
T658 /workspace/coverage/default/17.sysrst_ctrl_stress_all.13896079656968551921085177533503543443210943754263146474955055408643161451459 Oct 25 02:13:43 PM PDT 23 Oct 25 02:16:00 PM PDT 23 87228974549 ps
T659 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.115256525101140993906150101597093837058398503163587431656647790098484557791639 Oct 25 02:14:04 PM PDT 23 Oct 25 02:17:06 PM PDT 23 118289458206 ps
T660 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.21388889464414878120405937829343291714072557860798524587367149378168851194630 Oct 25 02:13:43 PM PDT 23 Oct 25 02:13:50 PM PDT 23 4089103959 ps
T661 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.91968368127852393525274411930750920003554282602224223769568395706996347481002 Oct 25 02:14:28 PM PDT 23 Oct 25 02:14:33 PM PDT 23 2515402263 ps
T662 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.73045402254474281784066427254679877440466672227220858492629439599833532999536 Oct 25 02:13:18 PM PDT 23 Oct 25 02:13:24 PM PDT 23 3138968703 ps
T663 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.65144698058162115530949629075135956968007322445244217883308389868262385531788 Oct 25 02:14:05 PM PDT 23 Oct 25 02:14:11 PM PDT 23 3138968703 ps
T664 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.44339948488364680448836057468681270101122077638764254662355399669294706929213 Oct 25 02:12:39 PM PDT 23 Oct 25 02:12:44 PM PDT 23 2074566504 ps
T665 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.66586779684167869006547681235026576059345468818011562442987604846285405603012 Oct 25 02:14:00 PM PDT 23 Oct 25 02:14:07 PM PDT 23 4089103959 ps
T666 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.94060345203570482233532426700439692350875001415033404160529857341320868272620 Oct 25 02:14:27 PM PDT 23 Oct 25 02:14:34 PM PDT 23 4089103959 ps
T667 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.83239415074083530547711818144958206569447548333305796478441249657423494464608 Oct 25 02:15:27 PM PDT 23 Oct 25 02:15:31 PM PDT 23 2074566504 ps
T668 /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.10011241385935531709257816885099078924037681357344496661851659472560389843218 Oct 25 02:14:35 PM PDT 23 Oct 25 02:14:42 PM PDT 23 4425119128 ps
T669 /workspace/coverage/default/28.sysrst_ctrl_stress_all.11988824869744819194695517268085072438245338900928780029364571705523290677226 Oct 25 02:14:14 PM PDT 23 Oct 25 02:16:29 PM PDT 23 87228974549 ps
T670 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.74635887776255367519749855049798494508446736058133945985662662470871906391312 Oct 25 02:12:52 PM PDT 23 Oct 25 02:12:59 PM PDT 23 4089103959 ps
T140 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.42433278774585205942529303954546423654745165646010893903235235291517670335602 Oct 25 02:11:36 PM PDT 23 Oct 25 02:11:41 PM PDT 23 2023227629 ps
T141 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.8693639598073729708984052564052449928084307787763192525323966054276134532699 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2023227629 ps
T65 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.66760718259559902079745785329782044233466085908803950612470780178864551653414 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:23 PM PDT 23 6030981281 ps
T152 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.103643429228113052940221273861087606338345993952749082432635562624071137987664 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:40 PM PDT 23 2023227629 ps
T66 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.78177072184490564311941019956904809929970250921912475364065762270449201755267 Oct 25 02:10:35 PM PDT 23 Oct 25 02:10:46 PM PDT 23 6030981281 ps
T67 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.9754452159902022103623475487204165288897900280871543843874945969049313513368 Oct 25 02:11:40 PM PDT 23 Oct 25 02:11:44 PM PDT 23 2023227629 ps
T68 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.74358112900849545739405877922622994197856118449098817770499484517208709487468 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:17 PM PDT 23 2023227629 ps
T1 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.84020025081455426462489011795280898317804349195911209886372364779508910614096 Oct 25 02:11:31 PM PDT 23 Oct 25 02:11:37 PM PDT 23 2186637036 ps
T11 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.115441897453809221171740685868578335413758505036333930035653063977501844085381 Oct 25 02:12:08 PM PDT 23 Oct 25 02:12:12 PM PDT 23 2023227629 ps
T2 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4871166201356072220510407390411300026892553488793848165757659295276645605281 Oct 25 02:11:18 PM PDT 23 Oct 25 02:11:23 PM PDT 23 2142012393 ps
T12 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2277783164054700140947636730299271766684159847491710142940946015297564235012 Oct 25 02:11:10 PM PDT 23 Oct 25 02:11:20 PM PDT 23 2890827831 ps
T3 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.90168801277037489975987142613499880247054423265536589118595740499894681483357 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2142012393 ps
T13 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.103738600623660508971881257053861959137823863287477323518972322518656752704544 Oct 25 02:11:41 PM PDT 23 Oct 25 02:11:45 PM PDT 23 2023227629 ps
T14 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.57373861091558473675551693920177528326676620282440040061253702504042443871579 Oct 25 02:11:39 PM PDT 23 Oct 25 02:12:04 PM PDT 23 9477310853 ps
T15 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.74421972116128865418826086832770454301492371943243521724274981838034216549450 Oct 25 02:12:04 PM PDT 23 Oct 25 02:12:09 PM PDT 23 2023227629 ps
T16 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.80027832227993776919326715892729487386320234160702519823478995061698888401953 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2074977215 ps
T17 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.80611706255772286770554501841864258825127211936176414679265567903046339150319 Oct 25 02:10:30 PM PDT 23 Oct 25 02:10:35 PM PDT 23 2074977215 ps
T74 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.43026785756441969007200017934699222655289557330481270330094401652856666479602 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:37 PM PDT 23 9477310853 ps
T69 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.92398586426871494727041710911175222240733156014897785141910122360905368682922 Oct 25 02:10:50 PM PDT 23 Oct 25 02:12:44 PM PDT 23 41047879715 ps
T4 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.7379428968481939546938157394439162245178174885207021373717856460505314751162 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2142012393 ps
T83 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.12856714905528068984120272014592727016416040762365731087043509876111396528754 Oct 25 02:12:05 PM PDT 23 Oct 25 02:12:09 PM PDT 23 2023227629 ps
T5 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4586806287965782067701286761448866054946869429779496043724118152855960812640 Oct 25 02:11:40 PM PDT 23 Oct 25 02:11:45 PM PDT 23 2142012393 ps
T70 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.58528824484462336477069323549305593420097831923193598559571471076487589892958 Oct 25 02:11:11 PM PDT 23 Oct 25 02:11:16 PM PDT 23 2074977215 ps
T6 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1780110881736453741308148339327707372229087920770897826282760486119302495317 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:19 PM PDT 23 2186637036 ps
T7 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.22890633846063519056725334533994956369959133468351460982561863291776491739854 Oct 25 02:11:11 PM PDT 23 Oct 25 02:11:16 PM PDT 23 2142012393 ps
T8 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.88668570899247426537647599500951137740692440405934241259359388464027034699849 Oct 25 02:11:36 PM PDT 23 Oct 25 02:12:45 PM PDT 23 42510939439 ps
T671 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.48549353449659578494282878056903108053560508563382145330853869766777866301827 Oct 25 02:11:30 PM PDT 23 Oct 25 02:11:34 PM PDT 23 2023227629 ps
T9 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.35004498542704960889227937099665774024008151530650827120025400135854708418034 Oct 25 02:10:51 PM PDT 23 Oct 25 02:12:01 PM PDT 23 42510939439 ps
T10 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.71269968192030098965192483132131187692600460859961221324635630893851425861524 Oct 25 02:10:49 PM PDT 23 Oct 25 02:10:53 PM PDT 23 2142012393 ps
T84 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.59110860971192543451330345103356061242656692568697741324352496155172372788940 Oct 25 02:10:28 PM PDT 23 Oct 25 02:10:54 PM PDT 23 9477310853 ps
T52 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.65571712098346020657284961323014422110338929285873102920322590910275311609211 Oct 25 02:12:08 PM PDT 23 Oct 25 02:13:17 PM PDT 23 42510939439 ps
T672 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.104991757911022068906276138600585505264552590020454481822903234613105738074376 Oct 25 02:11:32 PM PDT 23 Oct 25 02:11:37 PM PDT 23 2142012393 ps
T53 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.27101142897606825813634827150248702367673137131408537637031550937203903196090 Oct 25 02:11:17 PM PDT 23 Oct 25 02:12:26 PM PDT 23 42510939439 ps
T71 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.57097535509227563176097229149476740525304198186644119724913234670328930208286 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:19 PM PDT 23 2074977215 ps
T54 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.96370056575102817812759827864034098692010309749632668586708287586619193408780 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:20 PM PDT 23 2186637036 ps
T85 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.33030759682376264022127298656486105083456673768947955809384308467819590105912 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:39 PM PDT 23 9477310853 ps
T72 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.28711232567122977126347950886211679047351746792185781063600598065890439572578 Oct 25 02:10:29 PM PDT 23 Oct 25 02:12:23 PM PDT 23 41047879715 ps
T73 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.74527197034597393727365505984432729556340700718724500210731389563727712912058 Oct 25 02:12:05 PM PDT 23 Oct 25 02:12:10 PM PDT 23 2074977215 ps
T673 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.39370780774085359378517872749504519905934084068184665336745219493848106715361 Oct 25 02:11:17 PM PDT 23 Oct 25 02:11:22 PM PDT 23 2023227629 ps
T55 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.42398988014342284594889852698457148524902364225861387510347468742469525176138 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:19 PM PDT 23 2186637036 ps
T56 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.75499786113966567145084909877681702456176341071376817839706267038726267566154 Oct 25 02:10:32 PM PDT 23 Oct 25 02:10:38 PM PDT 23 2186637036 ps
T57 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.108990192667930032070853103985982323208860787128496267015005324207843913752158 Oct 25 02:11:13 PM PDT 23 Oct 25 02:12:22 PM PDT 23 42510939439 ps
T58 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.40873000345029365443789926039673465848209780375234613234958786881739721642319 Oct 25 02:11:15 PM PDT 23 Oct 25 02:11:22 PM PDT 23 2186637036 ps
T674 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.65006879250327574614112308398868677831907315406112074511415139571999405200026 Oct 25 02:11:18 PM PDT 23 Oct 25 02:11:23 PM PDT 23 2142012393 ps
T675 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.18873047332200312465557421654589382195445208813122872014062147587333238678130 Oct 25 02:11:09 PM PDT 23 Oct 25 02:11:14 PM PDT 23 2023227629 ps
T676 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.49112098999220710437045954311512653014667351014128801435811295723354752434389 Oct 25 02:11:36 PM PDT 23 Oct 25 02:11:40 PM PDT 23 2023227629 ps
T59 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.9575148406751657246558395652064941444474544983961313623671651754884127315701 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2186637036 ps
T677 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.98086425300676560399326154494309456075730154213301994638131952123178506332576 Oct 25 02:11:31 PM PDT 23 Oct 25 02:12:41 PM PDT 23 42510939439 ps
T86 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.90655169461642509056677515401407751935080189203664959148290217268647842830873 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2074977215 ps
T678 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.24943335574810339274513193453429146291320673631049502370628205997332371817091 Oct 25 02:11:30 PM PDT 23 Oct 25 02:11:35 PM PDT 23 2023227629 ps
T679 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.91863588842140197790343104477757939937252372982269818645433226898993078818138 Oct 25 02:12:03 PM PDT 23 Oct 25 02:12:07 PM PDT 23 2023227629 ps
T680 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.85412012481475019554030221706456461622239817943206704258519691152595068021724 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2074977215 ps
T681 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.21733586294439163291018867501793702615706741896081499146968818025166873895158 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:39 PM PDT 23 2023227629 ps
T682 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.27563664287125741788423668851548398629309248625644649018749927493026744282683 Oct 25 02:12:16 PM PDT 23 Oct 25 02:13:25 PM PDT 23 42510939439 ps
T75 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.53611332063301410663825009467758340431164124864335727007231784544211872563891 Oct 25 02:10:48 PM PDT 23 Oct 25 02:10:57 PM PDT 23 2890827831 ps
T683 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.82263962280217506655397944358689235475954865945181722309376108868951071175099 Oct 25 02:11:39 PM PDT 23 Oct 25 02:12:04 PM PDT 23 9477310853 ps
T82 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.46300620513487937101741045591165276379863506396221106306113233954099979755835 Oct 25 02:11:15 PM PDT 23 Oct 25 02:11:26 PM PDT 23 6030981281 ps
T684 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.7858150573788463798601789067870991970675897796709268043115786515074581456328 Oct 25 02:11:15 PM PDT 23 Oct 25 02:11:42 PM PDT 23 9477310853 ps
T685 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.66602277740933649894109794515814636395466623099243943990093447402988874552325 Oct 25 02:11:17 PM PDT 23 Oct 25 02:11:43 PM PDT 23 9477310853 ps
T76 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.114934187653436170457358756715591978628364720425252288633227915535569420372728 Oct 25 02:11:11 PM PDT 23 Oct 25 02:13:05 PM PDT 23 41047879715 ps
T686 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.71071716679994717750533885454469412992793129607373763937302663167780298751335 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:20 PM PDT 23 2023227629 ps
T687 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.101300930079656009578771819932358535651872137398424448987685094065105309877910 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2074977215 ps
T77 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.86832606550093505687649735375397132447191969358686584622257904896572134049665 Oct 25 02:11:34 PM PDT 23 Oct 25 02:13:27 PM PDT 23 41047879715 ps
T78 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.36346762741665491255284586624697628453811360118387315179514868039832898454034 Oct 25 02:11:12 PM PDT 23 Oct 25 02:13:05 PM PDT 23 41047879715 ps
T688 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.97019316049110643925622752001261703830284518649926391690945939683683276474797 Oct 25 02:11:34 PM PDT 23 Oct 25 02:11:38 PM PDT 23 2023227629 ps
T689 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.81312991545153371755515234954494377393726273209486201780032479662728883888123 Oct 25 02:11:27 PM PDT 23 Oct 25 02:11:52 PM PDT 23 9477310853 ps
T690 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.54240328180398210959011986556269222689310801893531378152167921557735826540737 Oct 25 02:11:11 PM PDT 23 Oct 25 02:11:16 PM PDT 23 2074977215 ps
T691 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.89774734188804471170263482123577585019324268850071314884498423053458685248682 Oct 25 02:11:11 PM PDT 23 Oct 25 02:11:36 PM PDT 23 9477310853 ps
T60 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.23817285424051058731533462784273067230810290149152209563690686492737726007629 Oct 25 02:11:11 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2186637036 ps
T61 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.70227440958060819360456032002451365498436094933679130308740741727412106008956 Oct 25 02:11:24 PM PDT 23 Oct 25 02:11:30 PM PDT 23 2186637036 ps
T692 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.84613548877708338891562673610559128693305509221259646369896542473334502836995 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:17 PM PDT 23 2074977215 ps
T62 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.114763444826879141437733871457166459396762346938397665010336632184661212003663 Oct 25 02:11:31 PM PDT 23 Oct 25 02:11:37 PM PDT 23 2186637036 ps
T693 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.68834993644611684053710618487707688101525865229641840587583579960498792439286 Oct 25 02:11:09 PM PDT 23 Oct 25 02:11:19 PM PDT 23 6030981281 ps
T79 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.104304723752656382646009503210407867538564299501129386065570219095134143120837 Oct 25 02:10:31 PM PDT 23 Oct 25 02:10:40 PM PDT 23 2890827831 ps
T694 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.63155470209603946712405273505149564899471125810658286533136459113016081348546 Oct 25 02:11:10 PM PDT 23 Oct 25 02:11:15 PM PDT 23 2142012393 ps
T695 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.39589366949438827064297043542197164467586229762963213962809526785089227278976 Oct 25 02:11:15 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2142012393 ps
T696 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.98563119168391164586942439130693481656332287843020369098135727719681561150474 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:38 PM PDT 23 9477310853 ps
T697 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.37759218373574077728986031458912135895970747006634771176171558234041441018596 Oct 25 02:11:17 PM PDT 23 Oct 25 02:12:27 PM PDT 23 42510939439 ps
T698 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.83009557660349312741365626238681475697527013964111343438063968156594687449359 Oct 25 02:11:36 PM PDT 23 Oct 25 02:11:42 PM PDT 23 2186637036 ps
T699 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.21031350896268256666893582473199501216310822070157496949997942587740633501167 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2074977215 ps
T700 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.29035468815030284815952061090841365540308291051495452952933107200612833397549 Oct 25 02:12:13 PM PDT 23 Oct 25 02:12:17 PM PDT 23 2142012393 ps
T701 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.65328783944276275968334006911759363078723224099807367209023714349379979493056 Oct 25 02:10:50 PM PDT 23 Oct 25 02:10:55 PM PDT 23 2142012393 ps
T702 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.101948023362562892228675302538278132922668704284692316152337656716096669837829 Oct 25 02:10:26 PM PDT 23 Oct 25 02:10:32 PM PDT 23 2186637036 ps
T703 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.99179187715457280147643602638407564126184117689428460407617944825114765161943 Oct 25 02:11:09 PM PDT 23 Oct 25 02:11:13 PM PDT 23 2074977215 ps
T704 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.32525932635343005303574962473031819573194479949531144118893525347977923412858 Oct 25 02:10:32 PM PDT 23 Oct 25 02:10:37 PM PDT 23 2023227629 ps
T705 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.11395700745136132636956473696863755523353318018118901083208322502750629272749 Oct 25 02:11:32 PM PDT 23 Oct 25 02:11:36 PM PDT 23 2023227629 ps
T706 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.16816227533668532266771613629217308534026759943745466452142719478436981594093 Oct 25 02:12:05 PM PDT 23 Oct 25 02:12:09 PM PDT 23 2023227629 ps
T707 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.32108578856863006230707301142081901584882654371544093070329277161409964112808 Oct 25 02:11:11 PM PDT 23 Oct 25 02:12:21 PM PDT 23 42510939439 ps
T708 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.26219050489019350339536297362425804492937649927430428635789791149942802648327 Oct 25 02:11:15 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2074977215 ps
T709 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.16114078703819892822258815931331339153012588479112315695098709318339116632818 Oct 25 02:11:57 PM PDT 23 Oct 25 02:12:01 PM PDT 23 2023227629 ps
T710 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.49571848950098679778218361706125639142573670903909830253352180350508959915747 Oct 25 02:10:33 PM PDT 23 Oct 25 02:10:37 PM PDT 23 2023227629 ps
T711 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.105148904943794640847641841294177366538763601879908504424297184619315140326359 Oct 25 02:11:17 PM PDT 23 Oct 25 02:12:26 PM PDT 23 42510939439 ps
T712 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.18874525183918408785071380579379203644972462605976473001091557773732973832402 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2023227629 ps
T713 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.29860306834787243784735636536366469713599326600678278010217656780408700101182 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:23 PM PDT 23 2186637036 ps
T714 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.88395682051061973583835067954445690489521890065374964038416097468362476458285 Oct 25 02:11:19 PM PDT 23 Oct 25 02:11:24 PM PDT 23 2142012393 ps
T715 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.111506638324368127121881952570809179400633418480671930571658300161619519229426 Oct 25 02:10:51 PM PDT 23 Oct 25 02:12:00 PM PDT 23 42510939439 ps
T716 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.110740943554425720165071947525288768585723621600488134840203257914508870055991 Oct 25 02:11:50 PM PDT 23 Oct 25 02:11:54 PM PDT 23 2023227629 ps
T717 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.12815729610332109104350581746363648188169944334670268386920831679552646144283 Oct 25 02:11:37 PM PDT 23 Oct 25 02:11:41 PM PDT 23 2023227629 ps
T718 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.109502204787864534859014391658189758107739835089954569921276042750336217253550 Oct 25 02:12:18 PM PDT 23 Oct 25 02:12:22 PM PDT 23 2023227629 ps
T719 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.98341828183191689359636397761746768326236529752139462635327135482196935236336 Oct 25 02:11:40 PM PDT 23 Oct 25 02:11:44 PM PDT 23 2023227629 ps
T720 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.34271772728551045989626816813910135425892274359193143518837706914899156131917 Oct 25 02:12:05 PM PDT 23 Oct 25 02:12:09 PM PDT 23 2023227629 ps
T721 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.59914005225493113659496522153272146861455574413511175642103749504329919065938 Oct 25 02:11:47 PM PDT 23 Oct 25 02:11:51 PM PDT 23 2023227629 ps
T722 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1227895161672913398732149982721135495215719532052214499216964690902114698295 Oct 25 02:10:51 PM PDT 23 Oct 25 02:11:16 PM PDT 23 9477310853 ps
T723 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.21884858044644039669266365837906446650043951613267821875472824527916657777845 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:37 PM PDT 23 9477310853 ps
T724 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.35614090749293369290974644189159214262252008544438956950009533281507628855248 Oct 25 02:11:30 PM PDT 23 Oct 25 02:11:35 PM PDT 23 2142012393 ps
T725 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.107344968621135673879160494269785605892397399772771652643203764674171022721099 Oct 25 02:11:14 PM PDT 23 Oct 25 02:12:24 PM PDT 23 42510939439 ps
T726 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.82102087562161149433059540830468464961863862873836878881664343502656035018891 Oct 25 02:11:11 PM PDT 23 Oct 25 02:12:20 PM PDT 23 42510939439 ps
T727 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.76911392215275578346169414548971812219318271806374162450888765874005556414409 Oct 25 02:11:33 PM PDT 23 Oct 25 02:11:58 PM PDT 23 9477310853 ps
T728 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.77783666353724504563784181028559604674233054585773166544303538071940451139576 Oct 25 02:11:40 PM PDT 23 Oct 25 02:11:44 PM PDT 23 2023227629 ps
T729 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.95944117701824811715688948634465103425614993035233554056833236556132080049345 Oct 25 02:11:31 PM PDT 23 Oct 25 02:11:36 PM PDT 23 2142012393 ps
T730 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.63214442732908573749859924665113988193233827584526380233424118868261252724697 Oct 25 02:11:34 PM PDT 23 Oct 25 02:11:38 PM PDT 23 2023227629 ps
T731 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.114021780502122043015303389021345818432906919856862725241873070780164831317461 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:16 PM PDT 23 2142012393 ps
T732 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.110293454248145807960440246823682577387028846318325012475376896174280302028930 Oct 25 02:11:37 PM PDT 23 Oct 25 02:11:41 PM PDT 23 2023227629 ps
T733 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.26741814833718964783945020405562196178805561214797443034326227599223601961950 Oct 25 02:11:34 PM PDT 23 Oct 25 02:11:38 PM PDT 23 2023227629 ps
T734 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.9201270768429468403979362207576585563870329204583300195835573808031551720526 Oct 25 02:11:12 PM PDT 23 Oct 25 02:12:22 PM PDT 23 42510939439 ps
T735 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.105401129897572277450153942264361353495125119838255448349693944856879256640786 Oct 25 02:11:38 PM PDT 23 Oct 25 02:11:43 PM PDT 23 2023227629 ps
T736 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.16846377662544893990130107507925394161395240866926884307040446627567734198172 Oct 25 02:11:33 PM PDT 23 Oct 25 02:11:58 PM PDT 23 9477310853 ps
T737 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.67889714351089602094106792213970326476184183192481325736824056770656586729797 Oct 25 02:12:18 PM PDT 23 Oct 25 02:12:22 PM PDT 23 2074977215 ps
T738 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.6483525411008804151577726469771396174976597878160435338370057172027114702070 Oct 25 02:12:08 PM PDT 23 Oct 25 02:12:12 PM PDT 23 2074977215 ps
T739 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.29788661629879172384751537260317385106417605853003797386028573059574521265798 Oct 25 02:11:31 PM PDT 23 Oct 25 02:11:38 PM PDT 23 2186637036 ps
T740 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.21044274359377401169065490267556528937065652809898650273656724658393514422558 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:40 PM PDT 23 2074977215 ps
T741 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.113433482635611611535841509983087284065616682553103567712352263502066510623298 Oct 25 02:11:29 PM PDT 23 Oct 25 02:12:39 PM PDT 23 42510939439 ps
T742 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.73414930248467537204055629243916515764477407788954262697333365674859712318145 Oct 25 02:11:14 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2142012393 ps
T743 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.114110656624589917559404220875882459058963292447272064774288619215613250551794 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:16 PM PDT 23 2023227629 ps
T744 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.16086417955776950002629852236046253633242495733927804439289529635470292529065 Oct 25 02:11:36 PM PDT 23 Oct 25 02:12:01 PM PDT 23 9477310853 ps
T745 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.58655574772777325152643082004222376713602781604736826276143809656678519373005 Oct 25 02:11:31 PM PDT 23 Oct 25 02:11:35 PM PDT 23 2023227629 ps
T80 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.25755229624763633373140761809383272395088929126057515989567089641319669954810 Oct 25 02:11:17 PM PDT 23 Oct 25 02:11:26 PM PDT 23 2890827831 ps
T746 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.47035184027634014022842462944287408217881444344209132969130583015028629087344 Oct 25 02:12:03 PM PDT 23 Oct 25 02:12:08 PM PDT 23 2142012393 ps
T747 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.24071956259236090370270843843300191846694390761713551602057938085935418600199 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:20 PM PDT 23 2023227629 ps
T81 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.38501314403411749904816231018835383370724117370856393563955828199534075844907 Oct 25 02:11:16 PM PDT 23 Oct 25 02:11:25 PM PDT 23 2890827831 ps
T748 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.67391209079213592315686126671465314836696168803995982231202401416436940831168 Oct 25 02:12:19 PM PDT 23 Oct 25 02:12:23 PM PDT 23 2023227629 ps
T749 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.82338690659435505766919538722219065841228659669075039704770170441218330225491 Oct 25 02:11:18 PM PDT 23 Oct 25 02:11:22 PM PDT 23 2023227629 ps
T750 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3500975202293622557209738651616592402943940004130965600971535304147074568355 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2142012393 ps
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