Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T751 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.11825811034558328969542701315014752398015486938278809084255769119809558026811 Oct 25 02:11:17 PM PDT 23 Oct 25 02:12:27 PM PDT 23 42510939439 ps
T752 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.12858777963314641449132152809850254866026896015131750699944595064953525750488 Oct 25 02:11:11 PM PDT 23 Oct 25 02:11:15 PM PDT 23 2023227629 ps
T753 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.90051226939099403131534103784038090781629930210426376665449576440880013340422 Oct 25 02:12:03 PM PDT 23 Oct 25 02:12:09 PM PDT 23 2186637036 ps
T754 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.108291488115568379838485868863070482047997356621168835416133373934391724865714 Oct 25 02:10:49 PM PDT 23 Oct 25 02:10:56 PM PDT 23 2186637036 ps
T755 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.44421784955903488391157301399313108430104703590324353586295318438228306255031 Oct 25 02:12:04 PM PDT 23 Oct 25 02:12:29 PM PDT 23 9477310853 ps
T756 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.87390188174320445243607187232252294404982744294790870430638841541254142688837 Oct 25 02:11:35 PM PDT 23 Oct 25 02:11:41 PM PDT 23 2186637036 ps
T757 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.58388738614474390291310398614899088290515319244937771606776501101130727913226 Oct 25 02:11:11 PM PDT 23 Oct 25 02:12:20 PM PDT 23 42510939439 ps
T758 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.99078407206657645699893453683379074045515136109637618352759424618102625449917 Oct 25 02:11:18 PM PDT 23 Oct 25 02:11:23 PM PDT 23 2023227629 ps
T759 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.104486298564239499036278750704326672001605545535297109920862254090853794334497 Oct 25 02:11:29 PM PDT 23 Oct 25 02:11:34 PM PDT 23 2074977215 ps
T760 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.93057653235894098023053099477145421602922982927344479100004463097745482040139 Oct 25 02:11:13 PM PDT 23 Oct 25 02:12:23 PM PDT 23 42510939439 ps
T761 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.114395611019253158010825942969057108841092137423066364667924002374315059600877 Oct 25 02:11:15 PM PDT 23 Oct 25 02:11:22 PM PDT 23 2186637036 ps
T762 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.96192705550789381117766717754557613686854581578892627398232633531798821993461 Oct 25 02:11:13 PM PDT 23 Oct 25 02:12:23 PM PDT 23 42510939439 ps
T763 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.105455719934511133547010562611254454208003633787204346617779920573934922419881 Oct 25 02:11:32 PM PDT 23 Oct 25 02:11:36 PM PDT 23 2023227629 ps
T764 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.66586588877792171535713244545122056002145707615410437909191890172856520911495 Oct 25 02:11:38 PM PDT 23 Oct 25 02:12:03 PM PDT 23 9477310853 ps
T765 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.73190727390202884763317752121480178123020307126787956218118342422183447227289 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:18 PM PDT 23 2023227629 ps
T766 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.33378428219057426431134550614484023390988209488705681882540863907424003243340 Oct 25 02:12:07 PM PDT 23 Oct 25 02:12:11 PM PDT 23 2023227629 ps
T767 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.62777595428419789394771445019961377092965506525988581550391115951800713905656 Oct 25 02:11:15 PM PDT 23 Oct 25 02:11:21 PM PDT 23 2074977215 ps
T768 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.54783381000226408448465303199963406561516141792512703285147102270509101352963 Oct 25 02:11:12 PM PDT 23 Oct 25 02:11:23 PM PDT 23 6030981281 ps
T769 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.50650753199753131421116730033986345791746826468821478815944885144762365360128 Oct 25 02:11:09 PM PDT 23 Oct 25 02:12:18 PM PDT 23 42510939439 ps
T770 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.62281849938659042246601689198387540455047144534483309756298868539458479102367 Oct 25 02:11:11 PM PDT 23 Oct 25 02:11:17 PM PDT 23 2186637036 ps
T771 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.61871069450334874225219507514427093916916259554703930878525881834692217223831 Oct 25 02:11:37 PM PDT 23 Oct 25 02:11:44 PM PDT 23 2186637036 ps
T772 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.75606403283614216670060090254780296731017329718535976061092166048397796842467 Oct 25 02:11:28 PM PDT 23 Oct 25 02:11:54 PM PDT 23 9477310853 ps
T773 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.113907223073768884267326798105740341459832820656658688230933107100586819708792 Oct 25 02:11:37 PM PDT 23 Oct 25 02:11:41 PM PDT 23 2023227629 ps
T774 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.42565445166970288760154492350438318287823582703191717602407198043149275679256 Oct 25 02:11:38 PM PDT 23 Oct 25 02:11:42 PM PDT 23 2023227629 ps
T775 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.50586446204426181823969313673677120204437630496438769824153226303725343363365 Oct 25 02:11:35 PM PDT 23 Oct 25 02:12:00 PM PDT 23 9477310853 ps
T776 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.80440712586284321767053451382391020208291888488963573949529181258151529256526 Oct 25 02:10:29 PM PDT 23 Oct 25 02:10:33 PM PDT 23 2074977215 ps
T777 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.106030723327122671818515206135447732506199165757857752526822152953680718681456 Oct 25 02:11:18 PM PDT 23 Oct 25 02:11:22 PM PDT 23 2023227629 ps
T778 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.61430521863652258567277866689739673306404729120346219671617855459441221395945 Oct 25 02:11:13 PM PDT 23 Oct 25 02:11:38 PM PDT 23 9477310853 ps
T779 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.72048987750863328706864093369009909265454603992384142136498549319691721225587 Oct 25 02:11:36 PM PDT 23 Oct 25 02:11:41 PM PDT 23 2023227629 ps
T780 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.48472221299821410261281491306625754048710469765175269852881749166104099315268 Oct 25 02:11:33 PM PDT 23 Oct 25 02:11:37 PM PDT 23 2023227629 ps
T781 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.31946267454721436222611071555133037171213627592576131219374703918020439894098 Oct 25 02:11:34 PM PDT 23 Oct 25 02:11:39 PM PDT 23 2074977215 ps
T782 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.42894629981620366620201898149799021001681755614883159184543423299462510104396 Oct 25 02:11:30 PM PDT 23 Oct 25 02:11:35 PM PDT 23 2142012393 ps

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.6264284259332881186354395799839148518014187136238524312850322724012417237029
Short name T26
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.79 seconds
Started Oct 25 02:13:47 PM PDT 23
Finished Oct 25 02:16:02 PM PDT 23
Peak memory 201504 kb
Host smart-750d91ca-65c6-43d1-9963-1e2916e00a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6264284259332881186354395799839148518014187136238524312850322724012417237029 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.6264284259332881186354395799839148518014187136238524312850322724012417237029
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.29934012627649501667193100061083254950858898706596157278287881305887060294593
Short name T91
Test name
Test status
Simulation time 38606274248 ps
CPU time 59.19 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201228 kb
Host smart-79b660f2-562a-4d33-be33-caf1e8306203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29934012627649501667193100061083254950858898706596157278287881305887060294593 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.29934012627649501667193100061083254950858898706596157278287881305887060294593
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.46334066483814238199805863863239573843180948481094882046321160177584267864096
Short name T21
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201184 kb
Host smart-0d72311b-0d67-4a6d-b00f-962f9b3461c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46334066483814238199805863863239573843180948481094882046321160177584267864096 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.463340664838142381998058638632395738431809484810948820463211
60177584267864096
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.7407886086668982170404844017720545641447195618017233389852145756640430099630
Short name T36
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 25 02:12:13 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201296 kb
Host smart-6355f404-c428-4f26-835d-f10b2476e45f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7407886086668982170404844017720545641447195618017233389852145756640430099630 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.7407886086668982170404844017720545641447195618017233389852145756640430099630
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.88668570899247426537647599500951137740692440405934241259359388464027034699849
Short name T8
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.88 seconds
Started Oct 25 02:11:36 PM PDT 23
Finished Oct 25 02:12:45 PM PDT 23
Peak memory 201340 kb
Host smart-46ad789b-5d47-43d1-aa98-d1c229ccdf56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88668570899247426537647599500951137740692440405934241259359388464027034699849 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.88668570899247426537647599500951137740692440405934241259359388
464027034699849
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.13671933414729953557606994040873399510461190347856897785616986001373756915356
Short name T88
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 25 02:13:24 PM PDT 23
Finished Oct 25 02:13:30 PM PDT 23
Peak memory 201160 kb
Host smart-26ac962f-957f-4cc1-8c4b-64dca95454f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13671933414729953557606994040873399510461190347856897785616986001373756915356 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.13671933414729953557606994040873399510461190347856897785616986001373756915356
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.79294393587480604678743935360879024682917009786650648317670080457345668208597
Short name T29
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.79 seconds
Started Oct 25 02:13:17 PM PDT 23
Finished Oct 25 02:16:20 PM PDT 23
Peak memory 201536 kb
Host smart-e0221b68-62b3-4fe0-a203-abc2d1a5bf97
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79294393587480604678743935360879024682917009786650648317670080457345668208597 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.79294393587480604678743935360879024682917009786650648317670080
457345668208597
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.84020025081455426462489011795280898317804349195911209886372364779508910614096
Short name T1
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.69 seconds
Started Oct 25 02:11:31 PM PDT 23
Finished Oct 25 02:11:37 PM PDT 23
Peak memory 201256 kb
Host smart-766319e1-fddd-4dd7-b2cd-7650bbfc3ced
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84020025081455426462489011795280898317804349195911209886372364779508910614096 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.84020025081455426462489011795280898317804349195911209886372364779508910614096
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.79787401547961823805431370958083099833127164461359849289937329465466319104024
Short name T172
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:19 PM PDT 23
Peak memory 201284 kb
Host smart-59efb728-94c9-46dc-8ea5-372f203ba218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79787401547961823805431370958083099833127164461359849289937329465466319104024 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.79787401547961823805431370958083099833127164461359849289937329465466319104024
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.57373861091558473675551693920177528326676620282440040061253702504042443871579
Short name T14
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.64 seconds
Started Oct 25 02:11:39 PM PDT 23
Finished Oct 25 02:12:04 PM PDT 23
Peak memory 201216 kb
Host smart-70089aae-141c-4040-a53c-1a7e40244aaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57373861091558473675551693920177528326676620282440040061253702504042443871579
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.57373861091558473675551693920177528326676620
282440040061253702504042443871579
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.56378569758093050380176823691979625371419859781542926814971094071656629259459
Short name T194
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201160 kb
Host smart-f67cb6ad-be61-422e-ae1a-d3e389c94694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56378569758093050380176823691979625371419859781542926814971094071656629259459 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.56378569758093050380176823691979625371419859781542926814971094071656629259459
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.49919120702018169495608269677611716958791235707821804315915653955292217091753
Short name T138
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.63 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 221604 kb
Host smart-ca393810-e57b-46ed-a1b8-f4cfd4ad7e03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49919120702018169495608269677611716958791235707821804315915653955292217091753 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.49919120702018169495608269677611716958791235707821804315915653955292217091753
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.115441897453809221171740685868578335413758505036333930035653063977501844085381
Short name T11
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 25 02:12:08 PM PDT 23
Finished Oct 25 02:12:12 PM PDT 23
Peak memory 201008 kb
Host smart-bdfa04b9-3633-4abd-9b4d-7017124e7539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115441897453809221171740685868578335413758505036333930035653063977501844085381 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.115441897453809221171740685868578335413758505036333930035653063977501844085381
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.92398586426871494727041710911175222240733156014897785141910122360905368682922
Short name T69
Test name
Test status
Simulation time 41047879715 ps
CPU time 113 seconds
Started Oct 25 02:10:50 PM PDT 23
Finished Oct 25 02:12:44 PM PDT 23
Peak memory 201204 kb
Host smart-6daaf981-d8a7-44df-ac25-4d246d6e287c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92398586426871494727041710911175222240733156014897785141910122360905368682922 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.92398586426871494727041710911175222240733156014897785141910122360905368682922
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.22366276327868118841347433350825106122118143639232345646558268693293191716349
Short name T175
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.24 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201168 kb
Host smart-b5c034c4-b20e-48ef-b0ac-0fd21c170919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22366276327868118841347433350825106122118143639232345646558268693293191716349 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.22366276327868118841347433350825106122118143639232345646558268693293191716349
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.9007447403221347753328199053693908986749223423833917355280108410018668527685
Short name T164
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.28 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:27 PM PDT 23
Peak memory 201248 kb
Host smart-001cedc5-a809-4427-8714-1953be0164cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9007447403221347753328199053693908986749223423833917355280108410018668527685 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.9007447403221347753328199053693908986749223423833917355280108
410018668527685
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.38501314403411749904816231018835383370724117370856393563955828199534075844907
Short name T81
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.75 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:25 PM PDT 23
Peak memory 201068 kb
Host smart-604893a5-2fb9-4e04-bb99-86803eda7fa1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38501314403411749904816231018835383370724117370856393563955828199534075844907 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.38501314403411749904816231018835383370724117370856393563955828199534075844907
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.114934187653436170457358756715591978628364720425252288633227915535569420372728
Short name T76
Test name
Test status
Simulation time 41047879715 ps
CPU time 113.89 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:13:05 PM PDT 23
Peak memory 201228 kb
Host smart-2dfb9cfc-374c-41be-ab0a-2241d6f94f43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114934187653436170457358756715591978628364720425252288633227915535569420372728 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.1149341876534361704573587567155919786283647204252522886332279155
35569420372728
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.54783381000226408448465303199963406561516141792512703285147102270509101352963
Short name T768
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.1 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:23 PM PDT 23
Peak memory 201132 kb
Host smart-3fb0a43b-fcb7-4254-a6e1-52536a190cd5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54783381000226408448465303199963406561516141792512703285147102270509101352963 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.54783381000226408448465303199963406561516141792512703285147102270509101352963
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.88395682051061973583835067954445690489521890065374964038416097468362476458285
Short name T714
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.34 seconds
Started Oct 25 02:11:19 PM PDT 23
Finished Oct 25 02:11:24 PM PDT 23
Peak memory 201080 kb
Host smart-c25cc63b-911e-4a09-bae2-11cf051f100e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8839568205106197358383506795444569048952189
0065374964038416097468362476458285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.8839
5682051061973583835067954445690489521890065374964038416097468362476458285
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.57097535509227563176097229149476740525304198186644119724913234670328930208286
Short name T71
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.08 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:19 PM PDT 23
Peak memory 200952 kb
Host smart-721a054f-8fee-4b66-aeef-4862ae029d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57097535509227563176097229149476740525304198186644119724913234670328930208286 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.57097535509227563176097229149476740525304198186644119724913234670328930208286
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.18874525183918408785071380579379203644972462605976473001091557773732973832402
Short name T712
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 200996 kb
Host smart-accf03df-aea6-4b9f-9848-67385f9091c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874525183918408785071380579379203644972462605976473001091557773732973832402 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.18874525183918408785071380579379203644972462605976473001091557773732973832402
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.89774734188804471170263482123577585019324268850071314884498423053458685248682
Short name T691
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.46 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:11:36 PM PDT 23
Peak memory 201044 kb
Host smart-afc91b0b-b4e2-4768-9da5-8e7d9acdfe51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89774734188804471170263482123577585019324268850071314884498423053458685248682
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.897747341888044711702634821235775850193242688
50071314884498423053458685248682
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.23817285424051058731533462784273067230810290149152209563690686492737726007629
Short name T60
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.8 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 201284 kb
Host smart-86168ea6-a470-49d5-bbf1-e871a506d632
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23817285424051058731533462784273067230810290149152209563690686492737726007629 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.23817285424051058731533462784273067230810290149152209563690686492737726007629
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.9201270768429468403979362207576585563870329204583300195835573808031551720526
Short name T734
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.82 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201320 kb
Host smart-4fcb4371-a597-4e82-868c-d610825df2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9201270768429468403979362207576585563870329204583300195835573808031551720526 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.9201270768429468403979362207576585563870329204583300195835573808031551720526
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.25755229624763633373140761809383272395088929126057515989567089641319669954810
Short name T80
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.56 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:11:26 PM PDT 23
Peak memory 201288 kb
Host smart-24dec352-da83-469f-8670-2b3d4d1d6ec7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25755229624763633373140761809383272395088929126057515989567089641319669954810 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.25755229624763633373140761809383272395088929126057515989567089641319669954810
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.86832606550093505687649735375397132447191969358686584622257904896572134049665
Short name T77
Test name
Test status
Simulation time 41047879715 ps
CPU time 113.04 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:13:27 PM PDT 23
Peak memory 201256 kb
Host smart-fb2f4f4d-86ff-4b71-9ac3-f72dad82fc2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86832606550093505687649735375397132447191969358686584622257904896572134049665 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.86832606550093505687649735375397132447191969358686584622257904896572134049665
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.46300620513487937101741045591165276379863506396221106306113233954099979755835
Short name T82
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.12 seconds
Started Oct 25 02:11:15 PM PDT 23
Finished Oct 25 02:11:26 PM PDT 23
Peak memory 201184 kb
Host smart-b62263d8-7945-45f3-9edd-ab2577426550
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46300620513487937101741045591165276379863506396221106306113233954099979755835 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.46300620513487937101741045591165276379863506396221106306113233954099979755835
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.104991757911022068906276138600585505264552590020454481822903234613105738074376
Short name T672
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.22 seconds
Started Oct 25 02:11:32 PM PDT 23
Finished Oct 25 02:11:37 PM PDT 23
Peak memory 201008 kb
Host smart-297596e9-b7a4-4165-8f34-0dd926c76791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049917579110220689062761386005855052645525
90020454481822903234613105738074376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.104
991757911022068906276138600585505264552590020454481822903234613105738074376
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.62777595428419789394771445019961377092965506525988581550391115951800713905656
Short name T767
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.18 seconds
Started Oct 25 02:11:15 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 200916 kb
Host smart-88508000-4f5e-43c0-85b7-34667a05eacc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62777595428419789394771445019961377092965506525988581550391115951800713905656 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.62777595428419789394771445019961377092965506525988581550391115951800713905656
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.71071716679994717750533885454469412992793129607373763937302663167780298751335
Short name T686
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:20 PM PDT 23
Peak memory 201028 kb
Host smart-66963b7a-2e51-4873-8e8a-cd6f40fd613c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71071716679994717750533885454469412992793129607373763937302663167780298751335 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.71071716679994717750533885454469412992793129607373763937302663167780298751335
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.75606403283614216670060090254780296731017329718535976061092166048397796842467
Short name T772
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.58 seconds
Started Oct 25 02:11:28 PM PDT 23
Finished Oct 25 02:11:54 PM PDT 23
Peak memory 201212 kb
Host smart-f42f3bbb-ab01-457c-94f7-41c4913f7ada
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75606403283614216670060090254780296731017329718535976061092166048397796842467
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.756064032836142166700600902547802967310173297
18535976061092166048397796842467
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.96370056575102817812759827864034098692010309749632668586708287586619193408780
Short name T54
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.76 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:20 PM PDT 23
Peak memory 201240 kb
Host smart-de853f1f-9e26-4fd3-b0aa-fb390b075366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96370056575102817812759827864034098692010309749632668586708287586619193408780 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.96370056575102817812759827864034098692010309749632668586708287586619193408780
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.27101142897606825813634827150248702367673137131408537637031550937203903196090
Short name T53
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.84 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 201316 kb
Host smart-c51716a4-0388-43da-9fe5-d6d9de157266
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27101142897606825813634827150248702367673137131408537637031550937203903196090 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.271011428976068258136348271502487023676731371314085376370315509
37203903196090
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.65006879250327574614112308398868677831907315406112074511415139571999405200026
Short name T674
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.15 seconds
Started Oct 25 02:11:18 PM PDT 23
Finished Oct 25 02:11:23 PM PDT 23
Peak memory 201152 kb
Host smart-a708c881-c771-4c23-8528-6b789dbd4bce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6500687925032757461411230839886867783190731
5406112074511415139571999405200026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.650
06879250327574614112308398868677831907315406112074511415139571999405200026
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.85412012481475019554030221706456461622239817943206704258519691152595068021724
Short name T680
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 201064 kb
Host smart-ef28db2e-1c26-4fd2-9c3b-ca8eb24e3bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85412012481475019554030221706456461622239817943206704258519691152595068021724 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.85412012481475019554030221706456461622239817943206704258519691152595068021724
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.73190727390202884763317752121480178123020307126787956218118342422183447227289
Short name T765
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 201012 kb
Host smart-ab6f58f0-0e1c-4c4b-8e5e-e7d5b8fea236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73190727390202884763317752121480178123020307126787956218118342422183447227289 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.73190727390202884763317752121480178123020307126787956218118342422183447227289
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.76911392215275578346169414548971812219318271806374162450888765874005556414409
Short name T727
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.81 seconds
Started Oct 25 02:11:33 PM PDT 23
Finished Oct 25 02:11:58 PM PDT 23
Peak memory 201124 kb
Host smart-84f62596-49f0-4f20-906f-c17856bdfaba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76911392215275578346169414548971812219318271806374162450888765874005556414409
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.76911392215275578346169414548971812219318271
806374162450888765874005556414409
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.42398988014342284594889852698457148524902364225861387510347468742469525176138
Short name T55
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.62 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:19 PM PDT 23
Peak memory 201236 kb
Host smart-45247a0f-a475-4f36-a3d6-73ff0686beea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42398988014342284594889852698457148524902364225861387510347468742469525176138 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.42398988014342284594889852698457148524902364225861387510347468742469525176138
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.108990192667930032070853103985982323208860787128496267015005324207843913752158
Short name T57
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.12 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201332 kb
Host smart-f462b512-d263-4d19-a831-ba09db1f6049
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108990192667930032070853103985982323208860787128496267015005324207843913752158 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.1089901926679300320708531039859823232088607871284962670150053
24207843913752158
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4871166201356072220510407390411300026892553488793848165757659295276645605281
Short name T2
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Oct 25 02:11:18 PM PDT 23
Finished Oct 25 02:11:23 PM PDT 23
Peak memory 201172 kb
Host smart-54560f4f-5b31-46c2-84f2-5244e1cc4d76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4871166201356072220510407390411300026892553
488793848165757659295276645605281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4871
166201356072220510407390411300026892553488793848165757659295276645605281
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.90655169461642509056677515401407751935080189203664959148290217268647842830873
Short name T86
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.05 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 201168 kb
Host smart-09ef5922-1e0f-4cc2-90c0-c63e02e791a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90655169461642509056677515401407751935080189203664959148290217268647842830873 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.90655169461642509056677515401407751935080189203664959148290217268647842830873
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.99078407206657645699893453683379074045515136109637618352759424618102625449917
Short name T758
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 25 02:11:18 PM PDT 23
Finished Oct 25 02:11:23 PM PDT 23
Peak memory 201064 kb
Host smart-2dbdc751-52ab-49a0-86b5-d7810714231b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99078407206657645699893453683379074045515136109637618352759424618102625449917 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.99078407206657645699893453683379074045515136109637618352759424618102625449917
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.16846377662544893990130107507925394161395240866926884307040446627567734198172
Short name T736
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.11 seconds
Started Oct 25 02:11:33 PM PDT 23
Finished Oct 25 02:11:58 PM PDT 23
Peak memory 201124 kb
Host smart-cf7bce77-8f7c-450b-8369-9d468918c40c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16846377662544893990130107507925394161395240866926884307040446627567734198172
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.16846377662544893990130107507925394161395240
866926884307040446627567734198172
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.58388738614474390291310398614899088290515319244937771606776501101130727913226
Short name T757
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.2 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201172 kb
Host smart-672742af-f4e4-4418-bd93-67e50a4441b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58388738614474390291310398614899088290515319244937771606776501101130727913226 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.58388738614474390291310398614899088290515319244937771606776501
101130727913226
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.35614090749293369290974644189159214262252008544438956950009533281507628855248
Short name T724
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.22 seconds
Started Oct 25 02:11:30 PM PDT 23
Finished Oct 25 02:11:35 PM PDT 23
Peak memory 201172 kb
Host smart-a57c326c-b9b4-455b-a7cf-c45fc424da71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561409074929336929097464418915921426225200
8544438956950009533281507628855248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.356
14090749293369290974644189159214262252008544438956950009533281507628855248
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.80027832227993776919326715892729487386320234160702519823478995061698888401953
Short name T16
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.08 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 201064 kb
Host smart-566a72a2-e7a9-46e6-bd13-70559d06dfb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80027832227993776919326715892729487386320234160702519823478995061698888401953 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.80027832227993776919326715892729487386320234160702519823478995061698888401953
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.48472221299821410261281491306625754048710469765175269852881749166104099315268
Short name T780
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 25 02:11:33 PM PDT 23
Finished Oct 25 02:11:37 PM PDT 23
Peak memory 201008 kb
Host smart-c5ccbdab-b072-4ad8-8290-b2e345c1d7a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48472221299821410261281491306625754048710469765175269852881749166104099315268 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.48472221299821410261281491306625754048710469765175269852881749166104099315268
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.50586446204426181823969313673677120204437630496438769824153226303725343363365
Short name T775
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.3 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:12:00 PM PDT 23
Peak memory 201296 kb
Host smart-cab07e89-e0bc-40bd-bdc9-588fab818a7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50586446204426181823969313673677120204437630496438769824153226303725343363365
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.50586446204426181823969313673677120204437630
496438769824153226303725343363365
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.61871069450334874225219507514427093916916259554703930878525881834692217223831
Short name T771
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.79 seconds
Started Oct 25 02:11:37 PM PDT 23
Finished Oct 25 02:11:44 PM PDT 23
Peak memory 201088 kb
Host smart-6342f7bf-19d2-44ce-8474-8932af6b23bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61871069450334874225219507514427093916916259554703930878525881834692217223831 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.61871069450334874225219507514427093916916259554703930878525881834692217223831
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.11825811034558328969542701315014752398015486938278809084255769119809558026811
Short name T751
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.23 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:12:27 PM PDT 23
Peak memory 201304 kb
Host smart-cf42087e-45d0-42ca-b9ba-9a1cbff4388e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11825811034558328969542701315014752398015486938278809084255769119809558026811 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.11825811034558328969542701315014752398015486938278809084255769
119809558026811
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.95944117701824811715688948634465103425614993035233554056833236556132080049345
Short name T729
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Oct 25 02:11:31 PM PDT 23
Finished Oct 25 02:11:36 PM PDT 23
Peak memory 201152 kb
Host smart-bfd6628c-0e46-49e2-a96f-6f62e7415426
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9594411770182481171568894863446510342561499
3035233554056833236556132080049345 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.959
44117701824811715688948634465103425614993035233554056833236556132080049345
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.21044274359377401169065490267556528937065652809898650273656724658393514422558
Short name T740
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:40 PM PDT 23
Peak memory 201000 kb
Host smart-333ceb6c-6078-408d-b1e3-f7839488fd1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21044274359377401169065490267556528937065652809898650273656724658393514422558 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.21044274359377401169065490267556528937065652809898650273656724658393514422558
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.49112098999220710437045954311512653014667351014128801435811295723354752434389
Short name T676
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 25 02:11:36 PM PDT 23
Finished Oct 25 02:11:40 PM PDT 23
Peak memory 201008 kb
Host smart-ae97917b-f04d-48fd-9768-de07ca2b12da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49112098999220710437045954311512653014667351014128801435811295723354752434389 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.49112098999220710437045954311512653014667351014128801435811295723354752434389
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.16086417955776950002629852236046253633242495733927804439289529635470292529065
Short name T744
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.66 seconds
Started Oct 25 02:11:36 PM PDT 23
Finished Oct 25 02:12:01 PM PDT 23
Peak memory 201320 kb
Host smart-c3019ca4-714b-480b-9994-53e652517faa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16086417955776950002629852236046253633242495733927804439289529635470292529065
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.16086417955776950002629852236046253633242495
733927804439289529635470292529065
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.83009557660349312741365626238681475697527013964111343438063968156594687449359
Short name T698
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.73 seconds
Started Oct 25 02:11:36 PM PDT 23
Finished Oct 25 02:11:42 PM PDT 23
Peak memory 201236 kb
Host smart-83762830-6319-43f7-96db-1fe1e3ea7820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83009557660349312741365626238681475697527013964111343438063968156594687449359 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.83009557660349312741365626238681475697527013964111343438063968156594687449359
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.113433482635611611535841509983087284065616682553103567712352263502066510623298
Short name T741
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.02 seconds
Started Oct 25 02:11:29 PM PDT 23
Finished Oct 25 02:12:39 PM PDT 23
Peak memory 201300 kb
Host smart-71e6291f-a676-4fdd-ae7f-bf49e68414f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113433482635611611535841509983087284065616682553103567712352263502066510623298 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.1134334826356116115358415099830872840656166825531035677123522
63502066510623298
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.47035184027634014022842462944287408217881444344209132969130583015028629087344
Short name T746
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.22 seconds
Started Oct 25 02:12:03 PM PDT 23
Finished Oct 25 02:12:08 PM PDT 23
Peak memory 201036 kb
Host smart-d1df9102-7ede-4e2d-8a9b-319bdaed0cc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4703518402763401402284246294428740821788144
4344209132969130583015028629087344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.470
35184027634014022842462944287408217881444344209132969130583015028629087344
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.6483525411008804151577726469771396174976597878160435338370057172027114702070
Short name T738
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Oct 25 02:12:08 PM PDT 23
Finished Oct 25 02:12:12 PM PDT 23
Peak memory 201032 kb
Host smart-83314240-79b5-419e-a5e9-9a3fd93cd829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6483525411008804151577726469771396174976597878160435338370057172027114702070 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.6483525411008804151577726469771396174976597878160435338370057172027114702070
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.97019316049110643925622752001261703830284518649926391690945939683683276474797
Short name T688
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:11:38 PM PDT 23
Peak memory 201012 kb
Host smart-959f5e51-a953-4f34-aad2-c34343c3b1c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97019316049110643925622752001261703830284518649926391690945939683683276474797 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.97019316049110643925622752001261703830284518649926391690945939683683276474797
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.114763444826879141437733871457166459396762346938397665010336632184661212003663
Short name T62
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.74 seconds
Started Oct 25 02:11:31 PM PDT 23
Finished Oct 25 02:11:37 PM PDT 23
Peak memory 201276 kb
Host smart-e53b6457-e647-4e10-941f-a381d7825b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114763444826879141437733871457166459396762346938397665010336632184661212003663 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.114763444826879141437733871457166459396762346938397665010336632184661212003663
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4586806287965782067701286761448866054946869429779496043724118152855960812640
Short name T5
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.17 seconds
Started Oct 25 02:11:40 PM PDT 23
Finished Oct 25 02:11:45 PM PDT 23
Peak memory 200964 kb
Host smart-33db4e47-1828-4b48-bce4-67da0fdc37ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4586806287965782067701286761448866054946869
429779496043724118152855960812640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.4586
806287965782067701286761448866054946869429779496043724118152855960812640
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.74527197034597393727365505984432729556340700718724500210731389563727712912058
Short name T73
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.13 seconds
Started Oct 25 02:12:05 PM PDT 23
Finished Oct 25 02:12:10 PM PDT 23
Peak memory 201016 kb
Host smart-e3545d45-f5e1-4563-8d05-43f15a79c0d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74527197034597393727365505984432729556340700718724500210731389563727712912058 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.74527197034597393727365505984432729556340700718724500210731389563727712912058
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.82263962280217506655397944358689235475954865945181722309376108868951071175099
Short name T683
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.71 seconds
Started Oct 25 02:11:39 PM PDT 23
Finished Oct 25 02:12:04 PM PDT 23
Peak memory 201216 kb
Host smart-33aa4f29-f02e-4567-b660-4d9b47e9c005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82263962280217506655397944358689235475954865945181722309376108868951071175099
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.82263962280217506655397944358689235475954865
945181722309376108868951071175099
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.87390188174320445243607187232252294404982744294790870430638841541254142688837
Short name T756
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.78 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:41 PM PDT 23
Peak memory 201288 kb
Host smart-9713b947-8517-4844-9d55-6843e7275803
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87390188174320445243607187232252294404982744294790870430638841541254142688837 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.87390188174320445243607187232252294404982744294790870430638841541254142688837
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.98086425300676560399326154494309456075730154213301994638131952123178506332576
Short name T677
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.23 seconds
Started Oct 25 02:11:31 PM PDT 23
Finished Oct 25 02:12:41 PM PDT 23
Peak memory 201208 kb
Host smart-ae36e920-f56f-4bc5-9a52-657a6a9022f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98086425300676560399326154494309456075730154213301994638131952123178506332576 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.98086425300676560399326154494309456075730154213301994638131952
123178506332576
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.29035468815030284815952061090841365540308291051495452952933107200612833397549
Short name T700
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.24 seconds
Started Oct 25 02:12:13 PM PDT 23
Finished Oct 25 02:12:17 PM PDT 23
Peak memory 201044 kb
Host smart-ab78bb0d-8d13-4f48-a73b-3c4338acb784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903546881503028481595206109084136554030829
1051495452952933107200612833397549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.290
35468815030284815952061090841365540308291051495452952933107200612833397549
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.67889714351089602094106792213970326476184183192481325736824056770656586729797
Short name T737
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.05 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201028 kb
Host smart-ed8cf4be-ce66-4d94-b96d-2ec8a0dc9f22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67889714351089602094106792213970326476184183192481325736824056770656586729797 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.67889714351089602094106792213970326476184183192481325736824056770656586729797
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.16816227533668532266771613629217308534026759943745466452142719478436981594093
Short name T706
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 25 02:12:05 PM PDT 23
Finished Oct 25 02:12:09 PM PDT 23
Peak memory 201032 kb
Host smart-2edb61f2-6561-4d97-8668-23a6334185f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16816227533668532266771613629217308534026759943745466452142719478436981594093 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.16816227533668532266771613629217308534026759943745466452142719478436981594093
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.44421784955903488391157301399313108430104703590324353586295318438228306255031
Short name T755
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.1 seconds
Started Oct 25 02:12:04 PM PDT 23
Finished Oct 25 02:12:29 PM PDT 23
Peak memory 201112 kb
Host smart-b8f24c4e-fd36-40f7-8b4e-466273dd4e78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44421784955903488391157301399313108430104703590324353586295318438228306255031
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.44421784955903488391157301399313108430104703
590324353586295318438228306255031
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.90051226939099403131534103784038090781629930210426376665449576440880013340422
Short name T753
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.63 seconds
Started Oct 25 02:12:03 PM PDT 23
Finished Oct 25 02:12:09 PM PDT 23
Peak memory 201232 kb
Host smart-73fd7438-726b-4ebb-a666-fb147f81ad09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90051226939099403131534103784038090781629930210426376665449576440880013340422 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.90051226939099403131534103784038090781629930210426376665449576440880013340422
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.65571712098346020657284961323014422110338929285873102920322590910275311609211
Short name T52
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.72 seconds
Started Oct 25 02:12:08 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201316 kb
Host smart-af105ba5-6d59-4b79-a46f-d4db525daf34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65571712098346020657284961323014422110338929285873102920322590910275311609211 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.65571712098346020657284961323014422110338929285873102920322590
910275311609211
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.39589366949438827064297043542197164467586229762963213962809526785089227278976
Short name T695
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.25 seconds
Started Oct 25 02:11:15 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 200956 kb
Host smart-f99d5f59-2df7-46e9-b20c-e64d55e0a0bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958936694943882706429704354219716446758622
9762963213962809526785089227278976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.395
89366949438827064297043542197164467586229762963213962809526785089227278976
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.101300930079656009578771819932358535651872137398424448987685094065105309877910
Short name T687
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.01 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 201124 kb
Host smart-e3daeee7-4502-499d-b194-6bca60725354
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101300930079656009578771819932358535651872137398424448987685094065105309877910 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.101300930079656009578771819932358535651872137398424448987685094065105309877910
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.67391209079213592315686126671465314836696168803995982231202401416436940831168
Short name T748
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:23 PM PDT 23
Peak memory 200988 kb
Host smart-6cccf169-184e-4464-9033-ecc52ac35fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67391209079213592315686126671465314836696168803995982231202401416436940831168 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.67391209079213592315686126671465314836696168803995982231202401416436940831168
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.66602277740933649894109794515814636395466623099243943990093447402988874552325
Short name T685
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.92 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:11:43 PM PDT 23
Peak memory 201196 kb
Host smart-c366e94b-9ce0-47de-b368-acf10e7e6fcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66602277740933649894109794515814636395466623099243943990093447402988874552325
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.66602277740933649894109794515814636395466623
099243943990093447402988874552325
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.29788661629879172384751537260317385106417605853003797386028573059574521265798
Short name T739
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.65 seconds
Started Oct 25 02:11:31 PM PDT 23
Finished Oct 25 02:11:38 PM PDT 23
Peak memory 201256 kb
Host smart-c1c0ad28-e6d4-4246-af06-260930580d99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29788661629879172384751537260317385106417605853003797386028573059574521265798 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.29788661629879172384751537260317385106417605853003797386028573059574521265798
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.27563664287125741788423668851548398629309248625644649018749927493026744282683
Short name T682
Test name
Test status
Simulation time 42510939439 ps
CPU time 69 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:13:25 PM PDT 23
Peak memory 201308 kb
Host smart-bb249145-6cf8-4e5c-9393-2757b1d47071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27563664287125741788423668851548398629309248625644649018749927493026744282683 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.27563664287125741788423668851548398629309248625644649018749927
493026744282683
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.7379428968481939546938157394439162245178174885207021373717856460505314751162
Short name T4
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.22 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 200884 kb
Host smart-32904ffe-d412-4a3b-8ed2-a11b7abc864d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7379428968481939546938157394439162245178174
885207021373717856460505314751162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.7379
428968481939546938157394439162245178174885207021373717856460505314751162
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.31946267454721436222611071555133037171213627592576131219374703918020439894098
Short name T781
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:11:39 PM PDT 23
Peak memory 201156 kb
Host smart-933bf832-6dcb-47ff-93d9-7e00df1adf2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31946267454721436222611071555133037171213627592576131219374703918020439894098 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.31946267454721436222611071555133037171213627592576131219374703918020439894098
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.106030723327122671818515206135447732506199165757857752526822152953680718681456
Short name T777
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.8 seconds
Started Oct 25 02:11:18 PM PDT 23
Finished Oct 25 02:11:22 PM PDT 23
Peak memory 200944 kb
Host smart-5fb70208-92e9-4d86-8e23-89f97ce11160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106030723327122671818515206135447732506199165757857752526822152953680718681456 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.106030723327122671818515206135447732506199165757857752526822152953680718681456
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.43026785756441969007200017934699222655289557330481270330094401652856666479602
Short name T74
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.83 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:37 PM PDT 23
Peak memory 201280 kb
Host smart-ef03baef-68d9-4f49-8c88-b4c263a19606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43026785756441969007200017934699222655289557330481270330094401652856666479602
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.43026785756441969007200017934699222655289557
330481270330094401652856666479602
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.70227440958060819360456032002451365498436094933679130308740741727412106008956
Short name T61
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.7 seconds
Started Oct 25 02:11:24 PM PDT 23
Finished Oct 25 02:11:30 PM PDT 23
Peak memory 201220 kb
Host smart-30124d9d-ee29-4e19-98d9-8be49f88033c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70227440958060819360456032002451365498436094933679130308740741727412106008956 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.70227440958060819360456032002451365498436094933679130308740741727412106008956
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.105148904943794640847641841294177366538763601879908504424297184619315140326359
Short name T711
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.77 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 201392 kb
Host smart-733d3b93-2e63-4d1b-b972-1d2e78a917ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105148904943794640847641841294177366538763601879908504424297184619315140326359 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.1051489049437946408476418412941773665387636018799085044242971
84619315140326359
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.42894629981620366620201898149799021001681755614883159184543423299462510104396
Short name T782
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.23 seconds
Started Oct 25 02:11:30 PM PDT 23
Finished Oct 25 02:11:35 PM PDT 23
Peak memory 201000 kb
Host smart-c60fa250-1920-4401-9ed9-39fc1ee0cade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289462998162036662020189814979902100168175
5614883159184543423299462510104396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.428
94629981620366620201898149799021001681755614883159184543423299462510104396
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.104486298564239499036278750704326672001605545535297109920862254090853794334497
Short name T759
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.15 seconds
Started Oct 25 02:11:29 PM PDT 23
Finished Oct 25 02:11:34 PM PDT 23
Peak memory 201128 kb
Host smart-c59c996d-3f93-46b2-8826-0e3fa7a6845e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104486298564239499036278750704326672001605545535297109920862254090853794334497 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.104486298564239499036278750704326672001605545535297109920862254090853794334497
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.58655574772777325152643082004222376713602781604736826276143809656678519373005
Short name T745
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 25 02:11:31 PM PDT 23
Finished Oct 25 02:11:35 PM PDT 23
Peak memory 200960 kb
Host smart-b62a0386-8be9-4c47-b0b2-36156e307ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58655574772777325152643082004222376713602781604736826276143809656678519373005 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.58655574772777325152643082004222376713602781604736826276143809656678519373005
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.66586588877792171535713244545122056002145707615410437909191890172856520911495
Short name T764
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.87 seconds
Started Oct 25 02:11:38 PM PDT 23
Finished Oct 25 02:12:03 PM PDT 23
Peak memory 201060 kb
Host smart-689d5b1f-1e9e-4ddb-9cdc-b3bdfb5b1c57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66586588877792171535713244545122056002145707615410437909191890172856520911495
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.66586588877792171535713244545122056002145707
615410437909191890172856520911495
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.29860306834787243784735636536366469713599326600678278010217656780408700101182
Short name T713
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.8 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:23 PM PDT 23
Peak memory 201020 kb
Host smart-4748cdc6-b1f4-46fe-ad36-01921a39678e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860306834787243784735636536366469713599326600678278010217656780408700101182 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.29860306834787243784735636536366469713599326600678278010217656780408700101182
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.96192705550789381117766717754557613686854581578892627398232633531798821993461
Short name T762
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.29 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:12:23 PM PDT 23
Peak memory 201332 kb
Host smart-5965921c-f03a-4bab-b335-74b2798c8ff0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96192705550789381117766717754557613686854581578892627398232633531798821993461 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.96192705550789381117766717754557613686854581578892627398232633
531798821993461
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.53611332063301410663825009467758340431164124864335727007231784544211872563891
Short name T75
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.55 seconds
Started Oct 25 02:10:48 PM PDT 23
Finished Oct 25 02:10:57 PM PDT 23
Peak memory 201132 kb
Host smart-dce05124-d67e-4c53-be4a-0434862e5ac1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53611332063301410663825009467758340431164124864335727007231784544211872563891 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.53611332063301410663825009467758340431164124864335727007231784544211872563891
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.28711232567122977126347950886211679047351746792185781063600598065890439572578
Short name T72
Test name
Test status
Simulation time 41047879715 ps
CPU time 113.64 seconds
Started Oct 25 02:10:29 PM PDT 23
Finished Oct 25 02:12:23 PM PDT 23
Peak memory 201248 kb
Host smart-add5b95d-ad45-45e7-864f-f937870bb593
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28711232567122977126347950886211679047351746792185781063600598065890439572578 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.28711232567122977126347950886211679047351746792185781063600598065890439572578
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.78177072184490564311941019956904809929970250921912475364065762270449201755267
Short name T66
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.13 seconds
Started Oct 25 02:10:35 PM PDT 23
Finished Oct 25 02:10:46 PM PDT 23
Peak memory 201164 kb
Host smart-955d49b3-3f66-42fe-9ddb-eae92c5cbcea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78177072184490564311941019956904809929970250921912475364065762270449201755267 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.78177072184490564311941019956904809929970250921912475364065762270449201755267
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.71269968192030098965192483132131187692600460859961221324635630893851425861524
Short name T10
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Oct 25 02:10:49 PM PDT 23
Finished Oct 25 02:10:53 PM PDT 23
Peak memory 201120 kb
Host smart-261fefe2-909e-4bec-908a-847b3520961a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7126996819203009896519248313213118769260046
0859961221324635630893851425861524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.7126
9968192030098965192483132131187692600460859961221324635630893851425861524
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.80440712586284321767053451382391020208291888488963573949529181258151529256526
Short name T776
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.04 seconds
Started Oct 25 02:10:29 PM PDT 23
Finished Oct 25 02:10:33 PM PDT 23
Peak memory 201000 kb
Host smart-c17bd98d-8ac4-4704-95c2-01e3a0f3a232
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80440712586284321767053451382391020208291888488963573949529181258151529256526 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.80440712586284321767053451382391020208291888488963573949529181258151529256526
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.49571848950098679778218361706125639142573670903909830253352180350508959915747
Short name T710
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 25 02:10:33 PM PDT 23
Finished Oct 25 02:10:37 PM PDT 23
Peak memory 200980 kb
Host smart-0f12e065-4125-4411-9c02-9dbbfd929b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49571848950098679778218361706125639142573670903909830253352180350508959915747 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.49571848950098679778218361706125639142573670903909830253352180350508959915747
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.59110860971192543451330345103356061242656692568697741324352496155172372788940
Short name T84
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.74 seconds
Started Oct 25 02:10:28 PM PDT 23
Finished Oct 25 02:10:54 PM PDT 23
Peak memory 201236 kb
Host smart-7ed2cbd2-b853-4bfb-bda3-d5cf1cd99964
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59110860971192543451330345103356061242656692568697741324352496155172372788940
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.591108609711925434513303451033560612426566925
68697741324352496155172372788940
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.75499786113966567145084909877681702456176341071376817839706267038726267566154
Short name T56
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.66 seconds
Started Oct 25 02:10:32 PM PDT 23
Finished Oct 25 02:10:38 PM PDT 23
Peak memory 201332 kb
Host smart-37a88040-6d75-4158-b335-58df38a0d0a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75499786113966567145084909877681702456176341071376817839706267038726267566154 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.75499786113966567145084909877681702456176341071376817839706267038726267566154
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.111506638324368127121881952570809179400633418480671930571658300161619519229426
Short name T715
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.5 seconds
Started Oct 25 02:10:51 PM PDT 23
Finished Oct 25 02:12:00 PM PDT 23
Peak memory 201152 kb
Host smart-9e187aa6-893a-4f95-a6a1-1001fb72afc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111506638324368127121881952570809179400633418480671930571658300161619519229426 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.11150663832436812712188195257080917940063341848067193057165830
0161619519229426
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.39370780774085359378517872749504519905934084068184665336745219493848106715361
Short name T673
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.83 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:11:22 PM PDT 23
Peak memory 200860 kb
Host smart-ba2b4b6d-f2ca-49b3-b948-859e01a18fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39370780774085359378517872749504519905934084068184665336745219493848106715361 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.39370780774085359378517872749504519905934084068184665336745219493848106715361
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.42565445166970288760154492350438318287823582703191717602407198043149275679256
Short name T774
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 25 02:11:38 PM PDT 23
Finished Oct 25 02:11:42 PM PDT 23
Peak memory 200808 kb
Host smart-025087d7-7859-4f41-817e-6ca47c2d10d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42565445166970288760154492350438318287823582703191717602407198043149275679256 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.42565445166970288760154492350438318287823582703191717602407198043149275679256
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.82338690659435505766919538722219065841228659669075039704770170441218330225491
Short name T749
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Oct 25 02:11:18 PM PDT 23
Finished Oct 25 02:11:22 PM PDT 23
Peak memory 200872 kb
Host smart-8934afef-1b80-4db4-a4ad-ec3569f64b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82338690659435505766919538722219065841228659669075039704770170441218330225491 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.82338690659435505766919538722219065841228659669075039704770170441218330225491
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.48549353449659578494282878056903108053560508563382145330853869766777866301827
Short name T671
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 25 02:11:30 PM PDT 23
Finished Oct 25 02:11:34 PM PDT 23
Peak memory 201020 kb
Host smart-0f3bbdc5-3cc2-4b4c-8e27-b82663ad2cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48549353449659578494282878056903108053560508563382145330853869766777866301827 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.48549353449659578494282878056903108053560508563382145330853869766777866301827
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.72048987750863328706864093369009909265454603992384142136498549319691721225587
Short name T779
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Oct 25 02:11:36 PM PDT 23
Finished Oct 25 02:11:41 PM PDT 23
Peak memory 200812 kb
Host smart-cbbd5ad5-1bbd-486e-af84-102f29c739fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72048987750863328706864093369009909265454603992384142136498549319691721225587 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.72048987750863328706864093369009909265454603992384142136498549319691721225587
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.24943335574810339274513193453429146291320673631049502370628205997332371817091
Short name T678
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 25 02:11:30 PM PDT 23
Finished Oct 25 02:11:35 PM PDT 23
Peak memory 200988 kb
Host smart-ffbceb49-ba5b-41f4-b722-68829539fef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24943335574810339274513193453429146291320673631049502370628205997332371817091 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.24943335574810339274513193453429146291320673631049502370628205997332371817091
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.103643429228113052940221273861087606338345993952749082432635562624071137987664
Short name T152
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:40 PM PDT 23
Peak memory 201032 kb
Host smart-f1a14f3b-059c-43c6-ac5e-3fc4052e7b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103643429228113052940221273861087606338345993952749082432635562624071137987664 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.103643429228113052940221273861087606338345993952749082432635562624071137987664
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.21733586294439163291018867501793702615706741896081499146968818025166873895158
Short name T681
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Oct 25 02:11:35 PM PDT 23
Finished Oct 25 02:11:39 PM PDT 23
Peak memory 200960 kb
Host smart-01dd2b92-7333-4afe-9595-76e45ab9c934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21733586294439163291018867501793702615706741896081499146968818025166873895158 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.21733586294439163291018867501793702615706741896081499146968818025166873895158
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.26741814833718964783945020405562196178805561214797443034326227599223601961950
Short name T733
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:11:38 PM PDT 23
Peak memory 200880 kb
Host smart-244675e8-3e30-4b3b-b1b3-10cab8089254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26741814833718964783945020405562196178805561214797443034326227599223601961950 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.26741814833718964783945020405562196178805561214797443034326227599223601961950
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.113907223073768884267326798105740341459832820656658688230933107100586819708792
Short name T773
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 25 02:11:37 PM PDT 23
Finished Oct 25 02:11:41 PM PDT 23
Peak memory 201064 kb
Host smart-4565100d-4cc7-4ccd-8745-71bfe3fe7e9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113907223073768884267326798105740341459832820656658688230933107100586819708792 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.113907223073768884267326798105740341459832820656658688230933107100586819708792
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.104304723752656382646009503210407867538564299501129386065570219095134143120837
Short name T79
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.57 seconds
Started Oct 25 02:10:31 PM PDT 23
Finished Oct 25 02:10:40 PM PDT 23
Peak memory 201232 kb
Host smart-606eb1f7-560f-4e44-8229-32b3ee38d442
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104304723752656382646009503210407867538564299501129386065570219095134143120837 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.1043047237526563826460095032104078675385642995011293860655702190
95134143120837
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.68834993644611684053710618487707688101525865229641840587583579960498792439286
Short name T693
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.03 seconds
Started Oct 25 02:11:09 PM PDT 23
Finished Oct 25 02:11:19 PM PDT 23
Peak memory 201180 kb
Host smart-658951fb-dc1c-40dc-aef1-4cd81b4478dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68834993644611684053710618487707688101525865229641840587583579960498792439286 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.68834993644611684053710618487707688101525865229641840587583579960498792439286
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.65328783944276275968334006911759363078723224099807367209023714349379979493056
Short name T701
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Oct 25 02:10:50 PM PDT 23
Finished Oct 25 02:10:55 PM PDT 23
Peak memory 201120 kb
Host smart-5bd234b6-92d3-4009-b6d2-5eaa6eb329f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6532878394427627596833400691175936307872322
4099807367209023714349379979493056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.6532
8783944276275968334006911759363078723224099807367209023714349379979493056
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.80611706255772286770554501841864258825127211936176414679265567903046339150319
Short name T17
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.12 seconds
Started Oct 25 02:10:30 PM PDT 23
Finished Oct 25 02:10:35 PM PDT 23
Peak memory 200884 kb
Host smart-e3824618-fbec-4428-b9f9-7f807f51bc16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80611706255772286770554501841864258825127211936176414679265567903046339150319 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.80611706255772286770554501841864258825127211936176414679265567903046339150319
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.32525932635343005303574962473031819573194479949531144118893525347977923412858
Short name T704
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 25 02:10:32 PM PDT 23
Finished Oct 25 02:10:37 PM PDT 23
Peak memory 200988 kb
Host smart-f990a560-ebd3-49ce-9b30-b5ae01ef459a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32525932635343005303574962473031819573194479949531144118893525347977923412858 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.32525932635343005303574962473031819573194479949531144118893525347977923412858
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1227895161672913398732149982721135495215719532052214499216964690902114698295
Short name T722
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.8 seconds
Started Oct 25 02:10:51 PM PDT 23
Finished Oct 25 02:11:16 PM PDT 23
Peak memory 201160 kb
Host smart-1a1d72ea-f7ef-4414-aeb8-182b036a3ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227895161672913398732149982721135495215719532052214499216964690902114698295 -
assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.1227895161672913398732149982721135495215719532
052214499216964690902114698295
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.101948023362562892228675302538278132922668704284692316152337656716096669837829
Short name T702
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.57 seconds
Started Oct 25 02:10:26 PM PDT 23
Finished Oct 25 02:10:32 PM PDT 23
Peak memory 201060 kb
Host smart-76d734a7-a3d0-476e-b56d-37560a168cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101948023362562892228675302538278132922668704284692316152337656716096669837829 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.101948023362562892228675302538278132922668704284692316152337656716096669837829
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.35004498542704960889227937099665774024008151530650827120025400135854708418034
Short name T9
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.18 seconds
Started Oct 25 02:10:51 PM PDT 23
Finished Oct 25 02:12:01 PM PDT 23
Peak memory 201316 kb
Host smart-f95fb48b-61ae-45dd-ae70-dec7811c27fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004498542704960889227937099665774024008151530650827120025400135854708418034 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.350044985427049608892279370996657740240081515306508271200254001
35854708418034
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.105401129897572277450153942264361353495125119838255448349693944856879256640786
Short name T735
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.66 seconds
Started Oct 25 02:11:38 PM PDT 23
Finished Oct 25 02:11:43 PM PDT 23
Peak memory 200968 kb
Host smart-dbe10071-4387-4e49-801b-deccfa86e0ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105401129897572277450153942264361353495125119838255448349693944856879256640786 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.105401129897572277450153942264361353495125119838255448349693944856879256640786
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.105455719934511133547010562611254454208003633787204346617779920573934922419881
Short name T763
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Oct 25 02:11:32 PM PDT 23
Finished Oct 25 02:11:36 PM PDT 23
Peak memory 200968 kb
Host smart-f75239d1-6220-4c4f-a433-0b14c44cd518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105455719934511133547010562611254454208003633787204346617779920573934922419881 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.105455719934511133547010562611254454208003633787204346617779920573934922419881
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.110740943554425720165071947525288768585723621600488134840203257914508870055991
Short name T716
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 25 02:11:50 PM PDT 23
Finished Oct 25 02:11:54 PM PDT 23
Peak memory 201020 kb
Host smart-c17c66b6-622e-4eef-bed6-9a460e717129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110740943554425720165071947525288768585723621600488134840203257914508870055991 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.110740943554425720165071947525288768585723621600488134840203257914508870055991
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.12815729610332109104350581746363648188169944334670268386920831679552646144283
Short name T717
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 25 02:11:37 PM PDT 23
Finished Oct 25 02:11:41 PM PDT 23
Peak memory 201020 kb
Host smart-3f39863d-9d53-4f3b-bc9e-bf2c75acdff3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815729610332109104350581746363648188169944334670268386920831679552646144283 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.12815729610332109104350581746363648188169944334670268386920831679552646144283
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.42433278774585205942529303954546423654745165646010893903235235291517670335602
Short name T140
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 25 02:11:36 PM PDT 23
Finished Oct 25 02:11:41 PM PDT 23
Peak memory 201020 kb
Host smart-fa640690-940e-47d0-a9ca-ae728d477d68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42433278774585205942529303954546423654745165646010893903235235291517670335602 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.42433278774585205942529303954546423654745165646010893903235235291517670335602
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.110293454248145807960440246823682577387028846318325012475376896174280302028930
Short name T732
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.8 seconds
Started Oct 25 02:11:37 PM PDT 23
Finished Oct 25 02:11:41 PM PDT 23
Peak memory 201020 kb
Host smart-27a87cd3-d9aa-4611-beda-11f2f4632acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110293454248145807960440246823682577387028846318325012475376896174280302028930 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.110293454248145807960440246823682577387028846318325012475376896174280302028930
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.16114078703819892822258815931331339153012588479112315695098709318339116632818
Short name T709
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 25 02:11:57 PM PDT 23
Finished Oct 25 02:12:01 PM PDT 23
Peak memory 200976 kb
Host smart-0a411e46-b8a1-47de-81a0-69992b41bf2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114078703819892822258815931331339153012588479112315695098709318339116632818 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.16114078703819892822258815931331339153012588479112315695098709318339116632818
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.11395700745136132636956473696863755523353318018118901083208322502750629272749
Short name T705
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Oct 25 02:11:32 PM PDT 23
Finished Oct 25 02:11:36 PM PDT 23
Peak memory 200960 kb
Host smart-90366b16-c3b1-4ad7-ba4b-b174596754cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11395700745136132636956473696863755523353318018118901083208322502750629272749 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.11395700745136132636956473696863755523353318018118901083208322502750629272749
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.91863588842140197790343104477757939937252372982269818645433226898993078818138
Short name T679
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.85 seconds
Started Oct 25 02:12:03 PM PDT 23
Finished Oct 25 02:12:07 PM PDT 23
Peak memory 200908 kb
Host smart-ab6c1ebe-e4b8-4c1c-865f-6ca2163a7b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91863588842140197790343104477757939937252372982269818645433226898993078818138 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.91863588842140197790343104477757939937252372982269818645433226898993078818138
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.63214442732908573749859924665113988193233827584526380233424118868261252724697
Short name T730
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Oct 25 02:11:34 PM PDT 23
Finished Oct 25 02:11:38 PM PDT 23
Peak memory 200956 kb
Host smart-038227a4-a3f5-412f-b4e3-e63c4ff59b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63214442732908573749859924665113988193233827584526380233424118868261252724697 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.63214442732908573749859924665113988193233827584526380233424118868261252724697
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2277783164054700140947636730299271766684159847491710142940946015297564235012
Short name T12
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.56 seconds
Started Oct 25 02:11:10 PM PDT 23
Finished Oct 25 02:11:20 PM PDT 23
Peak memory 201124 kb
Host smart-b0a6af13-fc07-4a74-b927-4d4f33a38026
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277783164054700140947636730299271766684159847491710142940946015297564235012 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.2277783164054700140947636730299271766684159847491710142940946015297564235012
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.36346762741665491255284586624697628453811360118387315179514868039832898454034
Short name T78
Test name
Test status
Simulation time 41047879715 ps
CPU time 112.57 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:13:05 PM PDT 23
Peak memory 201268 kb
Host smart-105e2e8b-b174-4b6c-b7f4-2d3479daf3dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36346762741665491255284586624697628453811360118387315179514868039832898454034 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.36346762741665491255284586624697628453811360118387315179514868039832898454034
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.66760718259559902079745785329782044233466085908803950612470780178864551653414
Short name T65
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.03 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:23 PM PDT 23
Peak memory 201176 kb
Host smart-a51fb4fd-6758-4609-9277-4a0f5f2ec1b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66760718259559902079745785329782044233466085908803950612470780178864551653414 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.66760718259559902079745785329782044233466085908803950612470780178864551653414
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.63155470209603946712405273505149564899471125810658286533136459113016081348546
Short name T694
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.36 seconds
Started Oct 25 02:11:10 PM PDT 23
Finished Oct 25 02:11:15 PM PDT 23
Peak memory 201140 kb
Host smart-21a0f809-c13e-451c-86cf-2b83c026fbc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6315547020960394671240527350514956489947112
5810658286533136459113016081348546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.6315
5470209603946712405273505149564899471125810658286533136459113016081348546
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.99179187715457280147643602638407564126184117689428460407617944825114765161943
Short name T703
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.05 seconds
Started Oct 25 02:11:09 PM PDT 23
Finished Oct 25 02:11:13 PM PDT 23
Peak memory 201064 kb
Host smart-952e0185-37a8-4718-91d6-ecac82a0a952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99179187715457280147643602638407564126184117689428460407617944825114765161943 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.99179187715457280147643602638407564126184117689428460407617944825114765161943
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.114110656624589917559404220875882459058963292447272064774288619215613250551794
Short name T743
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:16 PM PDT 23
Peak memory 201028 kb
Host smart-e09b0b7e-12c0-4fab-883e-a766344d3e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114110656624589917559404220875882459058963292447272064774288619215613250551794 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.114110656624589917559404220875882459058963292447272064774288619215613250551794
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.21884858044644039669266365837906446650043951613267821875472824527916657777845
Short name T723
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.61 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:37 PM PDT 23
Peak memory 201164 kb
Host smart-f4e20224-1e76-4b30-a3f8-05b91de10405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884858044644039669266365837906446650043951613267821875472824527916657777845
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.218848580446440396692663658379064466500439516
13267821875472824527916657777845
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.108291488115568379838485868863070482047997356621168835416133373934391724865714
Short name T754
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.7 seconds
Started Oct 25 02:10:49 PM PDT 23
Finished Oct 25 02:10:56 PM PDT 23
Peak memory 201236 kb
Host smart-73424fa7-43ab-4370-ac22-3cd143b3a8c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108291488115568379838485868863070482047997356621168835416133373934391724865714 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.108291488115568379838485868863070482047997356621168835416133373934391724865714
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.50650753199753131421116730033986345791746826468821478815944885144762365360128
Short name T769
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.3 seconds
Started Oct 25 02:11:09 PM PDT 23
Finished Oct 25 02:12:18 PM PDT 23
Peak memory 201144 kb
Host smart-6ebf2cc4-f87d-4186-a95a-e1a458d49c6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50650753199753131421116730033986345791746826468821478815944885144762365360128 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.506507531997531314211167300339863457917468264688214788159448851
44762365360128
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.33378428219057426431134550614484023390988209488705681882540863907424003243340
Short name T766
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.67 seconds
Started Oct 25 02:12:07 PM PDT 23
Finished Oct 25 02:12:11 PM PDT 23
Peak memory 200948 kb
Host smart-322bac56-fff4-4ab3-9b24-827d7836a3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33378428219057426431134550614484023390988209488705681882540863907424003243340 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.33378428219057426431134550614484023390988209488705681882540863907424003243340
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.12856714905528068984120272014592727016416040762365731087043509876111396528754
Short name T83
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Oct 25 02:12:05 PM PDT 23
Finished Oct 25 02:12:09 PM PDT 23
Peak memory 200888 kb
Host smart-c2e22c46-92d9-4bba-98fb-ad02534d9fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856714905528068984120272014592727016416040762365731087043509876111396528754 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.12856714905528068984120272014592727016416040762365731087043509876111396528754
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.9754452159902022103623475487204165288897900280871543843874945969049313513368
Short name T67
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 25 02:11:40 PM PDT 23
Finished Oct 25 02:11:44 PM PDT 23
Peak memory 200900 kb
Host smart-403a79df-50f2-4748-ad3c-14ab9791dafe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9754452159902022103623475487204165288897900280871543843874945969049313513368 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.9754452159902022103623475487204165288897900280871543843874945969049313513368
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.77783666353724504563784181028559604674233054585773166544303538071940451139576
Short name T728
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 25 02:11:40 PM PDT 23
Finished Oct 25 02:11:44 PM PDT 23
Peak memory 200888 kb
Host smart-4a0f7b6d-e2c4-413a-b63c-90bd8acd4534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77783666353724504563784181028559604674233054585773166544303538071940451139576 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.77783666353724504563784181028559604674233054585773166544303538071940451139576
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.34271772728551045989626816813910135425892274359193143518837706914899156131917
Short name T720
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Oct 25 02:12:05 PM PDT 23
Finished Oct 25 02:12:09 PM PDT 23
Peak memory 201008 kb
Host smart-3ea9c98e-0d97-4eb2-9b19-ae992703768a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34271772728551045989626816813910135425892274359193143518837706914899156131917 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.34271772728551045989626816813910135425892274359193143518837706914899156131917
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.98341828183191689359636397761746768326236529752139462635327135482196935236336
Short name T719
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.78 seconds
Started Oct 25 02:11:40 PM PDT 23
Finished Oct 25 02:11:44 PM PDT 23
Peak memory 200888 kb
Host smart-ffcdef73-2649-4e87-b2e0-498b7d240dc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98341828183191689359636397761746768326236529752139462635327135482196935236336 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.98341828183191689359636397761746768326236529752139462635327135482196935236336
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.103738600623660508971881257053861959137823863287477323518972322518656752704544
Short name T13
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Oct 25 02:11:41 PM PDT 23
Finished Oct 25 02:11:45 PM PDT 23
Peak memory 200888 kb
Host smart-de3693cd-6aab-49ae-99e8-fe123a048ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103738600623660508971881257053861959137823863287477323518972322518656752704544 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.103738600623660508971881257053861959137823863287477323518972322518656752704544
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.59914005225493113659496522153272146861455574413511175642103749504329919065938
Short name T721
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 25 02:11:47 PM PDT 23
Finished Oct 25 02:11:51 PM PDT 23
Peak memory 200988 kb
Host smart-c5ae05ea-552f-43e3-beb4-2d1093ff8d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59914005225493113659496522153272146861455574413511175642103749504329919065938 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.59914005225493113659496522153272146861455574413511175642103749504329919065938
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.74421972116128865418826086832770454301492371943243521724274981838034216549450
Short name T15
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Oct 25 02:12:04 PM PDT 23
Finished Oct 25 02:12:09 PM PDT 23
Peak memory 200980 kb
Host smart-5c081a4a-dbb0-4dd6-8e5e-667479a9cbdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74421972116128865418826086832770454301492371943243521724274981838034216549450 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.74421972116128865418826086832770454301492371943243521724274981838034216549450
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.109502204787864534859014391658189758107739835089954569921276042750336217253550
Short name T718
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 200860 kb
Host smart-0e9ecb44-1fcf-403b-9b48-373790d0e5c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109502204787864534859014391658189758107739835089954569921276042750336217253550 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.109502204787864534859014391658189758107739835089954569921276042750336217253550
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.114021780502122043015303389021345818432906919856862725241873070780164831317461
Short name T731
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.17 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:16 PM PDT 23
Peak memory 200980 kb
Host smart-3899ed35-aaf3-482d-8689-b48546bd7a8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140217805021220430153033890213458184329069
19856862725241873070780164831317461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.114
021780502122043015303389021345818432906919856862725241873070780164831317461
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.84613548877708338891562673610559128693305509221259646369896542473334502836995
Short name T692
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.09 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:17 PM PDT 23
Peak memory 200952 kb
Host smart-80b0d944-ab18-4ea9-820d-238084d688d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84613548877708338891562673610559128693305509221259646369896542473334502836995 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.84613548877708338891562673610559128693305509221259646369896542473334502836995
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.18873047332200312465557421654589382195445208813122872014062147587333238678130
Short name T675
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Oct 25 02:11:09 PM PDT 23
Finished Oct 25 02:11:14 PM PDT 23
Peak memory 201008 kb
Host smart-80802fe6-7ff0-4da2-946f-32be27ba215b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18873047332200312465557421654589382195445208813122872014062147587333238678130 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.18873047332200312465557421654589382195445208813122872014062147587333238678130
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.7858150573788463798601789067870991970675897796709268043115786515074581456328
Short name T684
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.44 seconds
Started Oct 25 02:11:15 PM PDT 23
Finished Oct 25 02:11:42 PM PDT 23
Peak memory 201228 kb
Host smart-d1ef2897-9a41-45c5-80ea-258c48fc83db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7858150573788463798601789067870991970675897796709268043115786515074581456328 -
assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.7858150573788463798601789067870991970675897796
709268043115786515074581456328
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.9575148406751657246558395652064941444474544983961313623671651754884127315701
Short name T59
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.82 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 201324 kb
Host smart-4f2cfe85-8a4c-44ca-adbe-6b66a8ea6359
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9575148406751657246558395652064941444474544983961313623671651754884127315701 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.9575148406751657246558395652064941444474544983961313623671651754884127315701
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.93057653235894098023053099477145421602922982927344479100004463097745482040139
Short name T760
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.11 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:12:23 PM PDT 23
Peak memory 201380 kb
Host smart-566c509b-75c4-43c6-bfe0-52ac28b7ca4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93057653235894098023053099477145421602922982927344479100004463097745482040139 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.930576532358940980230530994771454216029229829273444791000044630
97745482040139
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.73414930248467537204055629243916515764477407788954262697333365674859712318145
Short name T742
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 201060 kb
Host smart-591e0d0d-9eb9-4672-92e8-cfbf353bbd6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7341493024846753720405562924391651576447740
7788954262697333365674859712318145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.7341
4930248467537204055629243916515764477407788954262697333365674859712318145
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.26219050489019350339536297362425804492937649927430428635789791149942802648327
Short name T708
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.14 seconds
Started Oct 25 02:11:15 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 200824 kb
Host smart-df3ebc91-75b2-4e75-a276-ce6303084de6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26219050489019350339536297362425804492937649927430428635789791149942802648327 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.26219050489019350339536297362425804492937649927430428635789791149942802648327
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.8693639598073729708984052564052449928084307787763192525323966054276134532699
Short name T141
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 201060 kb
Host smart-2dc6df69-2c2c-4f8d-abf9-07d064b29328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8693639598073729708984052564052449928084307787763192525323966054276134532699 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.8693639598073729708984052564052449928084307787763192525323966054276134532699
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.33030759682376264022127298656486105083456673768947955809384308467819590105912
Short name T85
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.87 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:39 PM PDT 23
Peak memory 201168 kb
Host smart-53883b13-efc5-46e4-bf61-b206d178088b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030759682376264022127298656486105083456673768947955809384308467819590105912
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.330307596823762640221272986564861050834566737
68947955809384308467819590105912
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.40873000345029365443789926039673465848209780375234613234958786881739721642319
Short name T58
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.81 seconds
Started Oct 25 02:11:15 PM PDT 23
Finished Oct 25 02:11:22 PM PDT 23
Peak memory 201332 kb
Host smart-3b0193db-96bb-4653-b2ca-d1890ebfd675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873000345029365443789926039673465848209780375234613234958786881739721642319 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.40873000345029365443789926039673465848209780375234613234958786881739721642319
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.37759218373574077728986031458912135895970747006634771176171558234041441018596
Short name T697
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.68 seconds
Started Oct 25 02:11:17 PM PDT 23
Finished Oct 25 02:12:27 PM PDT 23
Peak memory 201324 kb
Host smart-690c21fe-40d8-42ab-88af-68f764d2d6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37759218373574077728986031458912135895970747006634771176171558234041441018596 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.377592183735740777289860314589121358959707470066347711761715582
34041441018596
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3500975202293622557209738651616592402943940004130965600971535304147074568355
Short name T750
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.14 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 201084 kb
Host smart-65b30865-5f54-4f22-9e8d-1d4123da7171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500975202293622557209738651616592402943940
004130965600971535304147074568355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.35009
75202293622557209738651616592402943940004130965600971535304147074568355
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.54240328180398210959011986556269222689310801893531378152167921557735826540737
Short name T690
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.12 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:11:16 PM PDT 23
Peak memory 201048 kb
Host smart-ed4b924f-5334-4e8f-b26d-c60699941c03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54240328180398210959011986556269222689310801893531378152167921557735826540737 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.54240328180398210959011986556269222689310801893531378152167921557735826540737
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.12858777963314641449132152809850254866026896015131750699944595064953525750488
Short name T752
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:11:15 PM PDT 23
Peak memory 200876 kb
Host smart-61e1c0e8-9ad8-4a8e-baa8-fb6f9479e7cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12858777963314641449132152809850254866026896015131750699944595064953525750488 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.12858777963314641449132152809850254866026896015131750699944595064953525750488
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.61430521863652258567277866689739673306404729120346219671617855459441221395945
Short name T778
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.5 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:38 PM PDT 23
Peak memory 201200 kb
Host smart-b62b70f3-e18a-4524-9218-3dc75c77c505
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61430521863652258567277866689739673306404729120346219671617855459441221395945
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.614305218636522585672778666897396733064047291
20346219671617855459441221395945
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1780110881736453741308148339327707372229087920770897826282760486119302495317
Short name T6
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.78 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:19 PM PDT 23
Peak memory 201232 kb
Host smart-e2e84750-6e34-4690-b14f-f1ee2f5a2f74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780110881736453741308148339327707372229087920770897826282760486119302495317 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.1780110881736453741308148339327707372229087920770897826282760486119302495317
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.32108578856863006230707301142081901584882654371544093070329277161409964112808
Short name T707
Test name
Test status
Simulation time 42510939439 ps
CPU time 69 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:12:21 PM PDT 23
Peak memory 201412 kb
Host smart-c191fdba-422e-431d-91c2-58fc696b7859
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32108578856863006230707301142081901584882654371544093070329277161409964112808 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.321085788568630062307073011420819015848826543715440930703292771
61409964112808
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.22890633846063519056725334533994956369959133468351460982561863291776491739854
Short name T7
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.19 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:11:16 PM PDT 23
Peak memory 200984 kb
Host smart-d8f18bd3-3f21-4add-b214-dc67b1f9806f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289063384606351905672533453399495636995913
3468351460982561863291776491739854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2289
0633846063519056725334533994956369959133468351460982561863291776491739854
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.58528824484462336477069323549305593420097831923193598559571471076487589892958
Short name T70
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.16 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:11:16 PM PDT 23
Peak memory 201000 kb
Host smart-ddce4d49-8fa0-4a50-99fa-dfd1f2b7d460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58528824484462336477069323549305593420097831923193598559571471076487589892958 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.58528824484462336477069323549305593420097831923193598559571471076487589892958
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.74358112900849545739405877922622994197856118449098817770499484517208709487468
Short name T68
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.76 seconds
Started Oct 25 02:11:13 PM PDT 23
Finished Oct 25 02:11:17 PM PDT 23
Peak memory 201012 kb
Host smart-cefce112-fab0-47c0-b6d3-13ee501e36a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74358112900849545739405877922622994197856118449098817770499484517208709487468 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.74358112900849545739405877922622994197856118449098817770499484517208709487468
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.98563119168391164586942439130693481656332287843020369098135727719681561150474
Short name T696
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.17 seconds
Started Oct 25 02:11:12 PM PDT 23
Finished Oct 25 02:11:38 PM PDT 23
Peak memory 201280 kb
Host smart-e91cac28-98b3-4cb5-bbe6-9c10e454507b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98563119168391164586942439130693481656332287843020369098135727719681561150474
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.985631191683911645869424391306934816563322878
43020369098135727719681561150474
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.62281849938659042246601689198387540455047144534483309756298868539458479102367
Short name T770
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.68 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:11:17 PM PDT 23
Peak memory 201284 kb
Host smart-1a719236-4f40-40bb-b0c3-0c1f405d1576
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62281849938659042246601689198387540455047144534483309756298868539458479102367 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.62281849938659042246601689198387540455047144534483309756298868539458479102367
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.82102087562161149433059540830468464961863862873836878881664343502656035018891
Short name T726
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.6 seconds
Started Oct 25 02:11:11 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201152 kb
Host smart-e220ea0e-1249-42c2-8056-0e24a0d0e8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82102087562161149433059540830468464961863862873836878881664343502656035018891 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.821020875621611494330595408304684649618638628738368788816643435
02656035018891
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.90168801277037489975987142613499880247054423265536589118595740499894681483357
Short name T3
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:21 PM PDT 23
Peak memory 201152 kb
Host smart-eadfd0cc-5560-4132-a3a0-88832bc01d9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9016880127703748997598714261349988024705442
3265536589118595740499894681483357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.9016
8801277037489975987142613499880247054423265536589118595740499894681483357
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.21031350896268256666893582473199501216310822070157496949997942587740633501167
Short name T699
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.01 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:11:18 PM PDT 23
Peak memory 200932 kb
Host smart-26fe0c3e-0f5a-4ebf-b2bb-5f93cbf907b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21031350896268256666893582473199501216310822070157496949997942587740633501167 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.21031350896268256666893582473199501216310822070157496949997942587740633501167
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.24071956259236090370270843843300191846694390761713551602057938085935418600199
Short name T747
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Oct 25 02:11:16 PM PDT 23
Finished Oct 25 02:11:20 PM PDT 23
Peak memory 200988 kb
Host smart-84fb3ebf-ae1d-488e-a89c-c0426ce124f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071956259236090370270843843300191846694390761713551602057938085935418600199 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.24071956259236090370270843843300191846694390761713551602057938085935418600199
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.81312991545153371755515234954494377393726273209486201780032479662728883888123
Short name T689
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.01 seconds
Started Oct 25 02:11:27 PM PDT 23
Finished Oct 25 02:11:52 PM PDT 23
Peak memory 201096 kb
Host smart-b6c8ad90-fa2e-4102-8746-dc87798f9379
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81312991545153371755515234954494377393726273209486201780032479662728883888123
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.813129915451533717555152349544943773937262732
09486201780032479662728883888123
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.114395611019253158010825942969057108841092137423066364667924002374315059600877
Short name T761
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.74 seconds
Started Oct 25 02:11:15 PM PDT 23
Finished Oct 25 02:11:22 PM PDT 23
Peak memory 201260 kb
Host smart-ae2b9d5c-2248-4960-a806-e9fcf6244b52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114395611019253158010825942969057108841092137423066364667924002374315059600877 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.114395611019253158010825942969057108841092137423066364667924002374315059600877
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.107344968621135673879160494269785605892397399772771652643203764674171022721099
Short name T725
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.4 seconds
Started Oct 25 02:11:14 PM PDT 23
Finished Oct 25 02:12:24 PM PDT 23
Peak memory 201244 kb
Host smart-b66a2b7d-d639-477c-91ce-b4d76e5b5679
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107344968621135673879160494269785605892397399772771652643203764674171022721099 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.10734496862113567387916049426978560589239739977277165264320376
4674171022721099
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.20774701772667446734583240952680609915338786910392862079004461953843737215967
Short name T418
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201284 kb
Host smart-6b8b3287-d312-4aba-b695-325ec10baad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20774701772667446734583240952680609915338786910392862079004461953843737215967 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.20774701772667446734583240952680609915338786910392862079004461953843737215967
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.57320637141523540332366647197227662988970468145105611221222659768852135565725
Short name T641
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.25 seconds
Started Oct 25 02:12:20 PM PDT 23
Finished Oct 25 02:15:23 PM PDT 23
Peak memory 201360 kb
Host smart-ba05642e-5839-4498-87c9-f78f957da2c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57320637141523540332366647197227662988970468145105611221222659768852135565725 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.573206371415235403323666471972276629889704681451056112212226597
68852135565725
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.15017608869708630474162802752122284993490303282601591273338973235392911464497
Short name T114
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.46 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201304 kb
Host smart-3be6f850-7bba-4791-8682-bb16ec0062e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15017608869708630474162802752122284993490303282601591273338973235392911464497 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.15017608869708630474162802752122284993490303282601591
273338973235392911464497
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.67605030845147086613878873569453143509843472427169009040325133365969296642299
Short name T145
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.3 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:24 PM PDT 23
Peak memory 201248 kb
Host smart-2ec554fe-d9ee-4191-a5fa-8caec3274841
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67605030845147086613878873569453143509843472427169009040325133365969296642299 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.6760503084514708661387887356945314350984347242716900904032513
3365969296642299
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.71762565043320194188715732530349863800669846200809820139963132826245687096670
Short name T557
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Oct 25 02:12:34 PM PDT 23
Finished Oct 25 02:12:39 PM PDT 23
Peak memory 201256 kb
Host smart-0c7efefa-2e7c-466e-93f9-1546b04267e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71762565043320194188715732530349863800669846200809820139963132826245687096670 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.71762565043320194188715732530349863800669846200809820139963132826245687096670
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.58332965163654955705222798486159707939499416472292145556444479164193031985531
Short name T558
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 25 02:12:15 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201276 kb
Host smart-e298fe08-1661-40c8-949f-1e4e073dd771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58332965163654955705222798486159707939499416472292145556444479164193031985531 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.58332965163654955705222798486159707939499416472292145556444479164193031985531
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.35274697078171625221474444448842258411316149865195914056202044426825103010554
Short name T642
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:23 PM PDT 23
Peak memory 201108 kb
Host smart-779c92d9-7cd7-448c-807f-eedac388939a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35274697078171625221474444448842258411316149865195914056202044426825103010554 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.35274697078171625221474444448842258411316149865195914056202044426825103010554
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.5311803202427177348291046256207111049495646271767197837970641382312243246958
Short name T652
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201152 kb
Host smart-4197af0b-ec0e-49a2-9eee-cb752bf6a18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5311803202427177348291046256207111049495646271767197837970641382312243246958 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sysrst_ctrl_smoke.5311803202427177348291046256207111049495646271767197837970641382312243246958
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.60883673439051408628577145265855007285595865429342419314735046523959962755994
Short name T411
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.96 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201564 kb
Host smart-f57e993f-b02d-456d-a2e4-1e9c8236f754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60883673439051408628577145265855007285595865429342419314735046523959962755994 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.60883673439051408628577145265855007285595865429342419314735046523959962755994
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.14308660718653590982737462672303864461643731204368645892472510286015197184111
Short name T260
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:19 PM PDT 23
Peak memory 201208 kb
Host smart-a064f33a-d8d2-4663-8211-ac7a69c189cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308660718653590982737462672303864461643731204368645892472510286015197184111 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.1430866071865359098273746267230386446164373120436864589247251
0286015197184111
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.93709254321787743761946164764452702794722279719090072864946466558312242816547
Short name T461
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:12:44 PM PDT 23
Peak memory 201180 kb
Host smart-4fe28088-cbe7-4a55-841d-04ffeab794c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93709254321787743761946164764452702794722279719090072864946466558312242816547 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.93709254321787743761946164764452702794722279719090072864946466558312242816547
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.32500258356257785231317462922076294414513608977007368367855561821342195931131
Short name T373
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:24 PM PDT 23
Peak memory 201316 kb
Host smart-b1424251-4aa7-43f1-afe3-b1f61355880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32500258356257785231317462922076294414513608977007368367855561821342195931131 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.32500258356257785231317462922076294414513608977007368367855561821342195931131
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.104872690659713995486311178300041477945539097359289902891303940164876935842419
Short name T354
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.05 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:15:18 PM PDT 23
Peak memory 201392 kb
Host smart-705b0205-6c37-4f0d-8693-5fc99811883d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104872690659713995486311178300041477945539097359289902891303940164876935842419 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.10487269065971399548631117830004147794553909735928990289130394
0164876935842419
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.107776786067991756604127006650310111118845699052962167051510542407317171598633
Short name T33
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.25 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201164 kb
Host smart-7bd84307-4e45-4f3b-815e-a734248e13e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107776786067991756604127006650310111118845699052962167051510542407317171598633 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.107776786067991756604127006650310111118845699052962167051510542407317171598633
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.96210620198081216718465001431544001362822446379522249670446894393259654873225
Short name T116
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.43 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201252 kb
Host smart-cce2b621-3f56-4bdb-a012-2f151f971912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96210620198081216718465001431544001362822446379522249670446894393259654873225 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.96210620198081216718465001431544001362822446379522249
670446894393259654873225
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.28227316103575016100457819531724278398788521382934610644613723264291353058266
Short name T246
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 25 02:12:18 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 201264 kb
Host smart-6e60c96d-b8b5-49e4-9e74-804a209ec06f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28227316103575016100457819531724278398788521382934610644613723264291353058266 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.2822731610357501610045781953172427839878852138293461064461372
3264291353058266
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.90800159671191925438668284088592661836414184281455318177470150624352529712488
Short name T342
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Oct 25 02:12:15 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201144 kb
Host smart-ad14cdc4-d5ac-4dfe-a065-1bbf1bd6dcf0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90800159671191925438668284088592661836414184281455318177470150624352529712488 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.90800159671191925438668284088592661836414184281455318177470150624352529712488
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.54669666596256660958882557296802168255580090662752573395976580848785901954012
Short name T92
Test name
Test status
Simulation time 38606274248 ps
CPU time 59.73 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201224 kb
Host smart-228299fe-7e1b-47da-a509-626f1f0c107d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54669666596256660958882557296802168255580090662752573395976580848785901954012 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.54669666596256660958882557296802168255580090662752573395976580848785901954012
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.80185957530209135793877698428202446704881273189802469590339112741296720403214
Short name T106
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 25 02:12:15 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201332 kb
Host smart-55741fe0-fb9c-4d51-8dba-ddf7bcf5a95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80185957530209135793877698428202446704881273189802469590339112741296720403214 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.80185957530209135793877698428202446704881273189802469590339112741296720403214
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.94540366872822070606760151058404709732127813315289143533218358256487953837086
Short name T123
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.73 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201316 kb
Host smart-4dfca5eb-1221-44be-b91d-8dcd55f5e4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94540366872822070606760151058404709732127813315289143533218358256487953837086 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.94540366872822070606760151058404709732127813315289143533218358256487953837086
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.10952090410186142975545592042442076925013393795563587743827532537879350741243
Short name T501
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201236 kb
Host smart-1a610467-bb29-471e-bf4c-64acee9fefbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10952090410186142975545592042442076925013393795563587743827532537879350741243 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.10952090410186142975545592042442076925013393795563587743827532537879350741243
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.26586800100896641310118843565705133505997656492958644460176691589818778116275
Short name T470
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:19 PM PDT 23
Peak memory 201244 kb
Host smart-e554eca5-1d95-49af-9446-a696e65e175f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26586800100896641310118843565705133505997656492958644460176691589818778116275 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.26586800100896641310118843565705133505997656492958644460176691589818778116275
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.83895862283580756989181315741854711469301658988751543932171384454743596357268
Short name T142
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.92 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:13:22 PM PDT 23
Peak memory 221476 kb
Host smart-6ab80f7b-2780-468e-9f49-ae849d7a4ada
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83895862283580756989181315741854711469301658988751543932171384454743596357268 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.83895862283580756989181315741854711469301658988751543932171384454743596357268
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.27505738343719368094073854093169147767863238962745708168934778730599939851858
Short name T269
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:20 PM PDT 23
Peak memory 201024 kb
Host smart-12aa8706-64c5-4671-9281-8341da1daecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27505738343719368094073854093169147767863238962745708168934778730599939851858 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_smoke.27505738343719368094073854093169147767863238962745708168934778730599939851858
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.114653079602897613500574387823609636931296176239404610303166701877419349041086
Short name T446
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.49 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:14:55 PM PDT 23
Peak memory 201460 kb
Host smart-29a85a90-6c27-4990-b2db-9260762cbafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114653079602897613500574387823609636931296176239404610303166701877419349041086 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.114653079602897613500574387823609636931296176239404610303166701877419349041086
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.65402268225267849796070203197559292734158417090276700904510051681192924126464
Short name T317
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201292 kb
Host smart-ad87c4fa-ee3d-4efc-a59f-0ba2f71dfbde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65402268225267849796070203197559292734158417090276700904510051681192924126464 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.6540226822526784979607020319755929273415841709027670090451005
1681192924126464
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.93018655103205790129181852548897489488436375529952124706150321768803944444510
Short name T155
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 25 02:13:25 PM PDT 23
Finished Oct 25 02:13:29 PM PDT 23
Peak memory 201200 kb
Host smart-7e63b67e-0c55-4363-b838-2f324781e895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93018655103205790129181852548897489488436375529952124706150321768803944444510 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.93018655103205790129181852548897489488436375529952124706150321768803944444510
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.61720794376706062902566499641092137477477539837709536467875052079457346205797
Short name T432
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 25 02:13:23 PM PDT 23
Finished Oct 25 02:13:29 PM PDT 23
Peak memory 200920 kb
Host smart-670b8b22-bed5-4621-b188-6c9c0e830a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61720794376706062902566499641092137477477539837709536467875052079457346205797 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.61720794376706062902566499641092137477477539837709536467875052079457346205797
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.101996393470037774935736601461122195124958977420663374765824905587220835577674
Short name T151
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.47 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:16:15 PM PDT 23
Peak memory 201432 kb
Host smart-42766380-3a07-4f43-b9a8-e445237ecde1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101996393470037774935736601461122195124958977420663374765824905587220835577674 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.1019963934700377749357366014611221951249589774206633747658249
05587220835577674
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.62582885245002526032473410142375274581391570343940115097073152818197823408683
Short name T445
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Oct 25 02:13:15 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 201236 kb
Host smart-cd841dee-65fa-4e71-8e1a-6bea0b8fe805
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62582885245002526032473410142375274581391570343940115097073152818197823408683 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.625828852450025260324734101423752745813915703439401150970731
52818197823408683
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.12942818480572581690188326453807955919133042162926356185222969090280648154612
Short name T379
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:26 PM PDT 23
Peak memory 201208 kb
Host smart-cac24ae9-0ca0-494a-932a-9ddc7200f425
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12942818480572581690188326453807955919133042162926356185222969090280648154612 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.1294281848057258169018832645380795591913304216292635618522296909
0280648154612
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.5782570707276828894526424483224257687896136478747137013995443857662177339614
Short name T176
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 25 02:13:18 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 201124 kb
Host smart-df0d3cd3-4ed8-4d2a-8751-909a5827a536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5782570707276828894526424483224257687896136478747137013995443857662177339614 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.5782570707276828894526424483224257687896136478747137013995443857662177339614
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.40662606449081726251080699074874513429142682171744736733672237993668561211946
Short name T589
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:22 PM PDT 23
Peak memory 201300 kb
Host smart-445c6d13-24a9-4fad-840d-01355f49d367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40662606449081726251080699074874513429142682171744736733672237993668561211946 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.40662606449081726251080699074874513429142682171744736733672237993668561211946
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.104165309430586517586938101551741451981012134232369772169372510750059594996660
Short name T482
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:13:18 PM PDT 23
Finished Oct 25 02:13:22 PM PDT 23
Peak memory 201088 kb
Host smart-48ecdcb8-e60a-4d15-93b0-62933c11b000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104165309430586517586938101551741451981012134232369772169372510750059594996660 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.104165309430586517586938101551741451981012134232369772169372510750059594996660
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.4866999162556856221496731443405392703361862278202575634820497120960108842850
Short name T389
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:13:19 PM PDT 23
Peak memory 201096 kb
Host smart-e4cc8f78-9a52-452c-92a0-4811287a02f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4866999162556856221496731443405392703361862278202575634820497120960108842850 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.4866999162556856221496731443405392703361862278202575634820497120960108842850
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.69266575110567928779277280059252163422891325451758171752117567172274198700854
Short name T156
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 201056 kb
Host smart-3173cce8-ec44-4e01-b529-e5e832059bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69266575110567928779277280059252163422891325451758171752117567172274198700854 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_smoke.69266575110567928779277280059252163422891325451758171752117567172274198700854
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.74339310607069123250289130690682723244664403568207051914643148620093228206302
Short name T646
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.78 seconds
Started Oct 25 02:13:23 PM PDT 23
Finished Oct 25 02:15:38 PM PDT 23
Peak memory 201060 kb
Host smart-39c5168d-351a-4d15-89ab-94353199b603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74339310607069123250289130690682723244664403568207051914643148620093228206302 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.74339310607069123250289130690682723244664403568207051914643148620093228206302
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.29312948939870707751078375616677253233823610084618755715735842136532285757355
Short name T587
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:21 PM PDT 23
Peak memory 201212 kb
Host smart-c3b894ef-cbe0-4e51-9894-8b24dcea118c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29312948939870707751078375616677253233823610084618755715735842136532285757355 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.293129489398707077510783756166772532338236100846187557157358
42136532285757355
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1828482716136554786622487421905480209862839183933243595693138833523450853337
Short name T490
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.6 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201248 kb
Host smart-b7ebdbf3-89db-43b1-8986-8712eb89ee44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828482716136554786622487421905480209862839183933243595693138833523450853337 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.1828482716136554786622487421905480209862839183933243595693138833523450853337
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.15481785889760963701211313918563817555951643528118376716296176190935327189505
Short name T258
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.45 seconds
Started Oct 25 02:13:23 PM PDT 23
Finished Oct 25 02:16:24 PM PDT 23
Peak memory 201332 kb
Host smart-863b2ba5-efdc-4f7b-9970-1749002ec473
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481785889760963701211313918563817555951643528118376716296176190935327189505 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.15481785889760963701211313918563817555951643528118376716296176
190935327189505
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.87727867733444742179321326772631512214564672008061145418095745775846572760283
Short name T462
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 25 02:13:20 PM PDT 23
Finished Oct 25 02:13:27 PM PDT 23
Peak memory 201156 kb
Host smart-c5462411-ce82-4902-ac2e-fc0ae7f3de79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87727867733444742179321326772631512214564672008061145418095745775846572760283 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.8772786773344474217932132677263151221456467200806114541809574577
5846572760283
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.17785786736580971680151389148052219015070332397077744383750230299081089690591
Short name T593
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 25 02:13:15 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201240 kb
Host smart-47218a6e-9184-4d65-9cb4-9c0c642f061f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17785786736580971680151389148052219015070332397077744383750230299081089690591 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.17785786736580971680151389148052219015070332397077744383750230299081089690591
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.8790095793742618701262855174397876575662891740323808550821887751907707476768
Short name T526
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.69 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:21 PM PDT 23
Peak memory 201184 kb
Host smart-ef51c0e8-19f7-4385-a4d8-acc3004ad77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8790095793742618701262855174397876575662891740323808550821887751907707476768 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.8790095793742618701262855174397876575662891740323808550821887751907707476768
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.24547045594478998106291194719228347184022912779300198141859127997902920254815
Short name T405
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 25 02:13:20 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201108 kb
Host smart-97098f4d-093c-4d0f-9ee4-7b830e429572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24547045594478998106291194719228347184022912779300198141859127997902920254815 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.24547045594478998106291194719228347184022912779300198141859127997902920254815
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.96402211872165262977970468839925225099272755912817028070040345958587834691318
Short name T244
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 25 02:13:24 PM PDT 23
Finished Oct 25 02:13:29 PM PDT 23
Peak memory 201100 kb
Host smart-c949ca75-24ff-4e12-a496-a9d2eb564087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96402211872165262977970468839925225099272755912817028070040345958587834691318 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.96402211872165262977970468839925225099272755912817028070040345958587834691318
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.95604664426876685197308083045828949110613305507691318272818194288720011687071
Short name T458
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.73 seconds
Started Oct 25 02:13:22 PM PDT 23
Finished Oct 25 02:13:27 PM PDT 23
Peak memory 201148 kb
Host smart-325d82ff-6f9a-4790-a7ed-a5a8a4a6b356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95604664426876685197308083045828949110613305507691318272818194288720011687071 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_smoke.95604664426876685197308083045828949110613305507691318272818194288720011687071
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.112377766142837268839077138707479014429871207472221393503271131836063886834860
Short name T494
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.77 seconds
Started Oct 25 02:13:25 PM PDT 23
Finished Oct 25 02:15:39 PM PDT 23
Peak memory 201468 kb
Host smart-8ba7595c-50e5-4035-9fd7-260afe6e5dfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112377766142837268839077138707479014429871207472221393503271131836063886834860 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.112377766142837268839077138707479014429871207472221393503271131836063886834860
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.69231659108081128245743813843245237968458966011626560190662127321292135206274
Short name T609
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 25 02:13:24 PM PDT 23
Finished Oct 25 02:13:30 PM PDT 23
Peak memory 201180 kb
Host smart-3881552c-5b85-4500-9296-73745a0fa0ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69231659108081128245743813843245237968458966011626560190662127321292135206274 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.692316591080811282457438138432452379684589660116265601906621
27321292135206274
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.91588369618910318210176655991214389912748384787084028856757077385740184520012
Short name T236
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201080 kb
Host smart-73da7864-8eff-4761-a708-f4ed294c2eef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91588369618910318210176655991214389912748384787084028856757077385740184520012 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.91588369618910318210176655991214389912748384787084028856757077385740184520012
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.73045402254474281784066427254679877440466672227220858492629439599833532999536
Short name T662
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 25 02:13:18 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201200 kb
Host smart-6e91deb0-b6c0-4dbe-96fb-6a3fee9e5b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73045402254474281784066427254679877440466672227220858492629439599833532999536 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.73045402254474281784066427254679877440466672227220858492629439599833532999536
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.62657175233126492342968111675144519737589511617198326730885013682847550879244
Short name T223
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.05 seconds
Started Oct 25 02:13:09 PM PDT 23
Finished Oct 25 02:16:11 PM PDT 23
Peak memory 201468 kb
Host smart-d22033f3-a496-4fa9-8d38-24019f9c6fbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62657175233126492342968111675144519737589511617198326730885013682847550879244 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.62657175233126492342968111675144519737589511617198326730885013
682847550879244
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.63497674273336783460857561358382116873455397343797185424176227038831336335734
Short name T588
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201228 kb
Host smart-9d6c1b30-719e-4dda-a59c-59dd3932f182
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63497674273336783460857561358382116873455397343797185424176227038831336335734 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.634976742733367834608575613583821168734553973437971854241762
27038831336335734
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.57448950253634403100204168111094311448905450914272345581244250899947486433806
Short name T316
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.56 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201280 kb
Host smart-8b1100f1-b72c-445d-8b1e-206e771bfd5b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57448950253634403100204168111094311448905450914272345581244250899947486433806 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.5744895025363440310020416811109431144890545091427234558124425089
9947486433806
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.69210662349492513698464797484703709491243991959996746598878115678511165437265
Short name T18
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 25 02:13:15 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201152 kb
Host smart-ba392118-e08f-4484-b3e9-96477488b774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69210662349492513698464797484703709491243991959996746598878115678511165437265 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.69210662349492513698464797484703709491243991959996746598878115678511165437265
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.61526030334339397812516340301329536774600549565900583557868403008418566365338
Short name T111
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:16 PM PDT 23
Peak memory 201268 kb
Host smart-4fe8fee1-2ea6-4e19-9b86-9138e9e1cae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61526030334339397812516340301329536774600549565900583557868403008418566365338 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.61526030334339397812516340301329536774600549565900583557868403008418566365338
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.97275573835095483157821277060698561972429321784071486478699819762952254507487
Short name T183
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Oct 25 02:13:25 PM PDT 23
Finished Oct 25 02:13:30 PM PDT 23
Peak memory 201152 kb
Host smart-93526399-8dd0-4a79-b665-d557d9a50ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97275573835095483157821277060698561972429321784071486478699819762952254507487 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.97275573835095483157821277060698561972429321784071486478699819762952254507487
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.36822894239109443873561317889965190611633461845425374918378364341161587619732
Short name T369
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201292 kb
Host smart-928a90f6-1866-48cc-a87f-691436ee7346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36822894239109443873561317889965190611633461845425374918378364341161587619732 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.36822894239109443873561317889965190611633461845425374918378364341161587619732
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.50651919557964254485284066105798473900450901768094886410051980802718173956229
Short name T425
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 25 02:13:25 PM PDT 23
Finished Oct 25 02:13:29 PM PDT 23
Peak memory 201132 kb
Host smart-af955e3d-5ae3-4ecb-892b-44669745cc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50651919557964254485284066105798473900450901768094886410051980802718173956229 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sysrst_ctrl_smoke.50651919557964254485284066105798473900450901768094886410051980802718173956229
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.40333396897421399482523938392097364151408668377609806941599266951262256304462
Short name T28
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.29 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:15:27 PM PDT 23
Peak memory 201492 kb
Host smart-c4eb062f-adb6-4e27-ba37-e03c61ab1e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333396897421399482523938392097364151408668377609806941599266951262256304462 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.40333396897421399482523938392097364151408668377609806941599266951262256304462
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.89127627889128760871364220575535804813758316241548447751854527445413938131106
Short name T417
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201268 kb
Host smart-1ecf3f97-bc92-4a4b-a226-5607194a0847
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89127627889128760871364220575535804813758316241548447751854527445413938131106 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.891276278891287608713642205755358048137583162415484477518545
27445413938131106
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.49165908523925814260529030701600291028510650526006533414017176633071120748801
Short name T364
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Oct 25 02:13:20 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201240 kb
Host smart-96f11e06-6da3-4f14-a777-b644b9401581
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49165908523925814260529030701600291028510650526006533414017176633071120748801 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.49165908523925814260529030701600291028510650526006533414017176633071120748801
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.3325657159456648784918026537094172123875768192165274397270840216229627423231
Short name T290
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 25 02:13:17 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 201332 kb
Host smart-56200827-df13-4eb0-8a02-12e211ffdaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325657159456648784918026537094172123875768192165274397270840216229627423231 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.3325657159456648784918026537094172123875768192165274397270840216229627423231
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.64052337513623981835790125271470054366280548349994619857332002149548751789032
Short name T34
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.9 seconds
Started Oct 25 02:13:15 PM PDT 23
Finished Oct 25 02:16:18 PM PDT 23
Peak memory 201452 kb
Host smart-0f5e12db-885d-447d-88b6-a3092706c5b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64052337513623981835790125271470054366280548349994619857332002149548751789032 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.64052337513623981835790125271470054366280548349994619857332002
149548751789032
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.48812900048865201544540250530049301802185404087017465830253522439057836572096
Short name T221
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:21 PM PDT 23
Peak memory 201252 kb
Host smart-982562b8-7b8a-443c-8faa-0173cc302c31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48812900048865201544540250530049301802185404087017465830253522439057836572096 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.488129000488652015445402505300493018021854040870174658302535
22439057836572096
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.53927507976489217802715903570171970493680227243461336162883248511621276477585
Short name T201
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 201240 kb
Host smart-1e196aaa-f46a-4030-9d72-a52bfedeba42
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53927507976489217802715903570171970493680227243461336162883248511621276477585 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.5392750797648921780271590357017197049368022724346133616288324851
1621276477585
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.68178174167673665760488972783820524104966574341899257079746049967066345033332
Short name T263
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201104 kb
Host smart-d1b5e3b1-5347-4821-9bfa-cfe4f931d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68178174167673665760488972783820524104966574341899257079746049967066345033332 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.68178174167673665760488972783820524104966574341899257079746049967066345033332
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.23313944050541113709276420868328020763018964929472251614231014679773930548678
Short name T173
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201260 kb
Host smart-bea7c995-c0a7-4185-8361-ec1c9d95ef10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23313944050541113709276420868328020763018964929472251614231014679773930548678 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.23313944050541113709276420868328020763018964929472251614231014679773930548678
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.6945643692437897094428098573484964559327727261326161908635456412923969150326
Short name T154
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 201096 kb
Host smart-0547f5c0-78b6-4685-a96e-5d54e13ecf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6945643692437897094428098573484964559327727261326161908635456412923969150326 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.6945643692437897094428098573484964559327727261326161908635456412923969150326
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.54304690918168469900820495726256254281988156187746021517645568822020387849367
Short name T45
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:16 PM PDT 23
Peak memory 201332 kb
Host smart-34059d5e-2f8a-4c6d-8ba5-9ea311198b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54304690918168469900820495726256254281988156187746021517645568822020387849367 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.54304690918168469900820495726256254281988156187746021517645568822020387849367
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.39972297109343423023415118787372379920304465503979967359369219824745589699116
Short name T321
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.75 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201148 kb
Host smart-4f730bb9-7b38-4328-bdf7-859ca0841ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39972297109343423023415118787372379920304465503979967359369219824745589699116 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sysrst_ctrl_smoke.39972297109343423023415118787372379920304465503979967359369219824745589699116
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.102827882196011522448622984863323433183979444507476982995267732862597538379805
Short name T132
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.84 seconds
Started Oct 25 02:13:15 PM PDT 23
Finished Oct 25 02:15:31 PM PDT 23
Peak memory 201524 kb
Host smart-9d95c98e-8605-43ce-8127-61a6bc4718ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102827882196011522448622984863323433183979444507476982995267732862597538379805 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.102827882196011522448622984863323433183979444507476982995267732862597538379805
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.37257135803918036628195361445522721460285805424032115653812936042270485025020
Short name T409
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 25 02:13:22 PM PDT 23
Finished Oct 25 02:13:28 PM PDT 23
Peak memory 201220 kb
Host smart-f2deef7e-81d3-4574-aae3-3466966efb25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37257135803918036628195361445522721460285805424032115653812936042270485025020 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.372571358039180366281953614455227214602858054240321156538129
36042270485025020
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.66925039186123870343275331112736484461059722871046541951256828179801070677915
Short name T41
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201260 kb
Host smart-42c5e671-c1b9-4043-afd0-c5757a6cac27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66925039186123870343275331112736484461059722871046541951256828179801070677915 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.66925039186123870343275331112736484461059722871046541951256828179801070677915
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.36425977006112656410163908672500558677841345887525524536757814918800038133040
Short name T420
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Oct 25 02:13:18 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201200 kb
Host smart-8669caec-539a-4160-9c5e-51e1263b044f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36425977006112656410163908672500558677841345887525524536757814918800038133040 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.36425977006112656410163908672500558677841345887525524536757814918800038133040
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.113257127853103076961224212127464491052956086213453974208454725714223141764262
Short name T108
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.31 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:23 PM PDT 23
Peak memory 201176 kb
Host smart-6dabec22-1b26-4a57-9ad2-c772f653f211
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113257127853103076961224212127464491052956086213453974208454725714223141764262 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.11325712785310307696122421212746449105295608621345397420845
4725714223141764262
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.71851774072861539306079862150286016643341102819033750816992646839477130859484
Short name T295
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 25 02:13:21 PM PDT 23
Finished Oct 25 02:13:28 PM PDT 23
Peak memory 201192 kb
Host smart-8e8c2d75-0f6c-491a-9f3c-8db376a98c6a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71851774072861539306079862150286016643341102819033750816992646839477130859484 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.7185177407286153930607986215028601664334110281903375081699264683
9477130859484
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.46181328150366994288525789410351884626715544319557881182658869651086535034412
Short name T239
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 25 02:13:20 PM PDT 23
Finished Oct 25 02:13:25 PM PDT 23
Peak memory 201248 kb
Host smart-3f678e96-00bc-493f-8f9b-9d3780f97961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46181328150366994288525789410351884626715544319557881182658869651086535034412 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.46181328150366994288525789410351884626715544319557881182658869651086535034412
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.46511401125197712860827007885887512533693335841961984849606811031884317891006
Short name T457
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.72 seconds
Started Oct 25 02:13:22 PM PDT 23
Finished Oct 25 02:13:27 PM PDT 23
Peak memory 201276 kb
Host smart-452379c5-81a7-470c-8626-7b2d5dce21f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46511401125197712860827007885887512533693335841961984849606811031884317891006 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.46511401125197712860827007885887512533693335841961984849606811031884317891006
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.66083627909096202807883429777746579990603543856586896041364084467805456016750
Short name T518
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201240 kb
Host smart-a8b5304a-f3aa-4ad9-8cec-b91ed6ae7c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66083627909096202807883429777746579990603543856586896041364084467805456016750 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.66083627909096202807883429777746579990603543856586896041364084467805456016750
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.92777334423057362589737635150181154386791421614477138805511097650269388550296
Short name T280
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 25 02:13:21 PM PDT 23
Finished Oct 25 02:13:26 PM PDT 23
Peak memory 201248 kb
Host smart-49d206e1-dd6b-4b97-9528-4f075b206f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92777334423057362589737635150181154386791421614477138805511097650269388550296 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.92777334423057362589737635150181154386791421614477138805511097650269388550296
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.103837193547120155724684463853530264005106303339235513146925365166645567230526
Short name T276
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201120 kb
Host smart-ba3c8332-85b5-4de6-ad17-c5cb6755009f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103837193547120155724684463853530264005106303339235513146925365166645567230526 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.sysrst_ctrl_smoke.103837193547120155724684463853530264005106303339235513146925365166645567230526
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.32360706638009272491921446158049091565875943005038439710995796106288241645443
Short name T206
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.82 seconds
Started Oct 25 02:13:20 PM PDT 23
Finished Oct 25 02:15:36 PM PDT 23
Peak memory 201428 kb
Host smart-b9351442-4400-4ca9-8442-472e85dea26f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32360706638009272491921446158049091565875943005038439710995796106288241645443 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.32360706638009272491921446158049091565875943005038439710995796106288241645443
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.25663717313105690782400590971846818440248795466993698287221488320228428592099
Short name T50
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Oct 25 02:13:22 PM PDT 23
Finished Oct 25 02:13:27 PM PDT 23
Peak memory 201220 kb
Host smart-24dd4b80-a3cc-49b7-91f6-89845b55492d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25663717313105690782400590971846818440248795466993698287221488320228428592099 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.256637173131056907824005909718468184402487954669936982872214
88320228428592099
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.101802801134955450338347560078937576702847011983526133568478637446807647726599
Short name T252
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 25 02:13:10 PM PDT 23
Finished Oct 25 02:13:14 PM PDT 23
Peak memory 201024 kb
Host smart-c9e32f38-624d-4c51-83d0-c86fde6b11cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101802801134955450338347560078937576702847011983526133568478637446807647726599 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.101802801134955450338347560078937576702847011983526133568478637446807647726599
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.54697455895565447820725468310132578697318202132952198710548133114102005250782
Short name T397
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.39 seconds
Started Oct 25 02:13:18 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201348 kb
Host smart-81cd6f2c-f5b1-41c5-a591-ab31c40f1601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54697455895565447820725468310132578697318202132952198710548133114102005250782 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.54697455895565447820725468310132578697318202132952198710548133114102005250782
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.83722184434008266199603873266609936591583803727718376190590717103022354132407
Short name T30
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.61 seconds
Started Oct 25 02:13:25 PM PDT 23
Finished Oct 25 02:16:26 PM PDT 23
Peak memory 201336 kb
Host smart-dd52d5a5-8857-4bfe-aef2-2b300bfeb2c0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83722184434008266199603873266609936591583803727718376190590717103022354132407 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.83722184434008266199603873266609936591583803727718376190590717
103022354132407
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.74041987171313460855383287462023323858020539582595256820010982906451538099200
Short name T455
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 25 02:13:20 PM PDT 23
Finished Oct 25 02:13:28 PM PDT 23
Peak memory 201188 kb
Host smart-20924b2a-f9f0-4402-8354-7220661646ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74041987171313460855383287462023323858020539582595256820010982906451538099200 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.740419871713134608553832874620233238580205395825952568200109
82906451538099200
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.19922226813198723592726254143532789944914559230504601929899322049951663790574
Short name T134
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.2 seconds
Started Oct 25 02:13:25 PM PDT 23
Finished Oct 25 02:13:31 PM PDT 23
Peak memory 201180 kb
Host smart-ceb4824b-8daf-415b-b10b-e096f5b1b093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19922226813198723592726254143532789944914559230504601929899322049951663790574 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.1992222681319872359272625414353278994491455923050460192989932204
9951663790574
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.21650183819155935234843496186402480102291986639864196493919508139954658634716
Short name T306
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 25 02:13:21 PM PDT 23
Finished Oct 25 02:13:26 PM PDT 23
Peak memory 201204 kb
Host smart-a64e5d45-a133-4bdb-b99f-1eee82bd4358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21650183819155935234843496186402480102291986639864196493919508139954658634716 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.21650183819155935234843496186402480102291986639864196493919508139954658634716
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.28548881990677151964967375307935966221253307119798161554378558146799728056764
Short name T529
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.7 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201260 kb
Host smart-9e214608-1b7e-4de6-81ba-8cca5e44ac47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28548881990677151964967375307935966221253307119798161554378558146799728056764 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.28548881990677151964967375307935966221253307119798161554378558146799728056764
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.61812070940604669311333538341957472393868080587899199740203217357698223655181
Short name T238
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 25 02:13:24 PM PDT 23
Finished Oct 25 02:13:28 PM PDT 23
Peak memory 201060 kb
Host smart-4d74608e-a326-4c73-adda-0587e88d4831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61812070940604669311333538341957472393868080587899199740203217357698223655181 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.61812070940604669311333538341957472393868080587899199740203217357698223655181
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.98200383444358734768088181810284803108173993151603178153106714651133921666850
Short name T573
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.49 seconds
Started Oct 25 02:13:24 PM PDT 23
Finished Oct 25 02:13:29 PM PDT 23
Peak memory 201100 kb
Host smart-a58473ac-eafd-48ef-a8c8-4bb2a230fd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98200383444358734768088181810284803108173993151603178153106714651133921666850 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.98200383444358734768088181810284803108173993151603178153106714651133921666850
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.109957266679737070135810259077774988386505813368814537421270961430486194269940
Short name T158
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 25 02:13:20 PM PDT 23
Finished Oct 25 02:13:24 PM PDT 23
Peak memory 201092 kb
Host smart-ba3049e5-8ebb-4fe3-86e7-a297871823d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109957266679737070135810259077774988386505813368814537421270961430486194269940 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.sysrst_ctrl_smoke.109957266679737070135810259077774988386505813368814537421270961430486194269940
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.18211528831254867238590005902901941942152837946360394756452900964284551588006
Short name T487
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.93 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:15:35 PM PDT 23
Peak memory 201524 kb
Host smart-d26774b7-4953-4c15-9d7d-8b0aacc35019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18211528831254867238590005902901941942152837946360394756452900964284551588006 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.18211528831254867238590005902901941942152837946360394756452900964284551588006
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.40473836693432911324054405551796324389595841563892479770670609071703226922666
Short name T241
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 25 02:13:25 PM PDT 23
Finished Oct 25 02:13:30 PM PDT 23
Peak memory 201208 kb
Host smart-79dc9a08-97aa-4158-8036-12e3841e27da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40473836693432911324054405551796324389595841563892479770670609071703226922666 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.404738366934329113240544055517963243895958415638924797706706
09071703226922666
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.58015594399408261124840565022108812948192836845953778773236117080233676696225
Short name T556
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:13:44 PM PDT 23
Peak memory 201240 kb
Host smart-3facdeb9-1b94-4758-8e49-1a3dfd895e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58015594399408261124840565022108812948192836845953778773236117080233676696225 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.58015594399408261124840565022108812948192836845953778773236117080233676696225
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.57256641674626478315116381248077227306470275009490950949745292477128957335990
Short name T366
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:19 PM PDT 23
Peak memory 201148 kb
Host smart-4c4d0261-2e93-420c-8e8f-fa481c545b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57256641674626478315116381248077227306470275009490950949745292477128957335990 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.57256641674626478315116381248077227306470275009490950949745292477128957335990
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.38749212835391415256212225820301002846460883003727958053939561581596803412565
Short name T468
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.2 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:16:12 PM PDT 23
Peak memory 201300 kb
Host smart-fb1108ee-acd4-4078-9d40-83f649b5471e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749212835391415256212225820301002846460883003727958053939561581596803412565 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.38749212835391415256212225820301002846460883003727958053939561
581596803412565
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.5244812256900749493949591765045896789035650545413630970625881447680966524574
Short name T19
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 25 02:13:10 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201288 kb
Host smart-077ff923-05b0-4e1c-ab5b-11730f3bdf27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5244812256900749493949591765045896789035650545413630970625881447680966524574 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.5244812256900749493949591765045896789035650545413630970625881
447680966524574
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.27298885879669543146095085353952160205176899581272309145659406988681933701267
Short name T37
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201248 kb
Host smart-e0c2eec5-20e5-4709-ba29-c6b01df6fa3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27298885879669543146095085353952160205176899581272309145659406988681933701267 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.2729888587966954314609508535395216020517689958127230914565940698
8681933701267
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.91612291467092994232310985710872068273669673698055851869746227714855995191430
Short name T334
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 25 02:13:09 PM PDT 23
Finished Oct 25 02:13:15 PM PDT 23
Peak memory 201264 kb
Host smart-a67c91ed-81c2-4276-9839-b235cf2bac37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91612291467092994232310985710872068273669673698055851869746227714855995191430 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.91612291467092994232310985710872068273669673698055851869746227714855995191430
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.22568535164753818135494809601964011906055249710641489803287807417860364320645
Short name T43
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201316 kb
Host smart-fecec968-d7c9-4eae-b707-81f45ccb2c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22568535164753818135494809601964011906055249710641489803287807417860364320645 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.22568535164753818135494809601964011906055249710641489803287807417860364320645
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.91087800268952765395009069430823804995043615871391590322117415824161454890651
Short name T159
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.7 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:16 PM PDT 23
Peak memory 201188 kb
Host smart-1d76f34a-8841-4359-9ddd-973a39530133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91087800268952765395009069430823804995043615871391590322117415824161454890651 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.91087800268952765395009069430823804995043615871391590322117415824161454890651
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.93618038901309175005141209678416950828469605421604321574316422563129963055638
Short name T242
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.69 seconds
Started Oct 25 02:13:10 PM PDT 23
Finished Oct 25 02:13:15 PM PDT 23
Peak memory 201244 kb
Host smart-3377edd9-a0f1-476a-903c-4050229aca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93618038901309175005141209678416950828469605421604321574316422563129963055638 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.93618038901309175005141209678416950828469605421604321574316422563129963055638
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.45830633571530625191760008234284675061434144155415166118900406360454906795856
Short name T465
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:15 PM PDT 23
Peak memory 201024 kb
Host smart-1ff39b1d-ea45-425d-8986-47d1c8e01ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45830633571530625191760008234284675061434144155415166118900406360454906795856 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_smoke.45830633571530625191760008234284675061434144155415166118900406360454906795856
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.34615639512118778233970767139078721724259011669150749959385436880105000320024
Short name T435
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.71 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:15:26 PM PDT 23
Peak memory 201576 kb
Host smart-358e9cf5-d6a5-4205-8e80-9e71bdb86def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34615639512118778233970767139078721724259011669150749959385436880105000320024 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.34615639512118778233970767139078721724259011669150749959385436880105000320024
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.114506443786698596583686682777460637894809635316885646174884221492508801612599
Short name T485
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201092 kb
Host smart-1e56cc46-ec3e-479b-82be-074b4fc3db43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114506443786698596583686682777460637894809635316885646174884221492508801612599 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.11450644378669859658368668277746063789480963531688564617488
4221492508801612599
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.9787579833020068153334454516481242573863032794290448558039797836989791691501
Short name T502
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:45 PM PDT 23
Peak memory 201236 kb
Host smart-3a862578-a185-4bc4-8657-6a77686a7f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9787579833020068153334454516481242573863032794290448558039797836989791691501 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.9787579833020068153334454516481242573863032794290448558039797836989791691501
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.82159397949756361659043225846131792352488050631683766623246622411471191698812
Short name T303
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Oct 25 02:13:37 PM PDT 23
Finished Oct 25 02:13:43 PM PDT 23
Peak memory 201288 kb
Host smart-8f293ab7-46c3-4396-b12a-6faf3902d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82159397949756361659043225846131792352488050631683766623246622411471191698812 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.82159397949756361659043225846131792352488050631683766623246622411471191698812
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.110821503973248249649940393488738220645104570679083724392615511350702959610851
Short name T189
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.25 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:16:45 PM PDT 23
Peak memory 201388 kb
Host smart-01b39820-ebad-4667-9bc4-046c2c008337
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110821503973248249649940393488738220645104570679083724392615511350702959610851 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.1108215039732482496499403934887382206451045706790837243926155
11350702959610851
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.25864210574314852934330914151981468472428962990591688149675388713762077806214
Short name T228
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201276 kb
Host smart-874c2795-ba5f-487f-87f9-c72cbff11615
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25864210574314852934330914151981468472428962990591688149675388713762077806214 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.258642105743148529343309141519814684724289629905916881496753
88713762077806214
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.27046660060702319972009490708974932702965499507757919529423357937368485630249
Short name T284
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201224 kb
Host smart-1c2aef6e-0c80-4d8e-8c9c-d8807b148fac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27046660060702319972009490708974932702965499507757919529423357937368485630249 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.2704666006070231997200949070897493270296549950775791952942335793
7368485630249
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.32155262678750397925705490192701315162816317070039427535865409143237604502439
Short name T302
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201228 kb
Host smart-6bcd9376-59c8-4107-995f-07ae8c52dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32155262678750397925705490192701315162816317070039427535865409143237604502439 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.32155262678750397925705490192701315162816317070039427535865409143237604502439
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.24739655384668385649053540905488518968079409492416293422938689890609641266351
Short name T224
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201196 kb
Host smart-3cf90ec2-1c53-4c3e-b795-e8391ebbe6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24739655384668385649053540905488518968079409492416293422938689890609641266351 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.24739655384668385649053540905488518968079409492416293422938689890609641266351
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.81891427139305195568041980071675300462295051679221841940859774802676161361037
Short name T594
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:13:45 PM PDT 23
Peak memory 201036 kb
Host smart-0bd82fc4-2f1a-4c63-8134-13ea5813819d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81891427139305195568041980071675300462295051679221841940859774802676161361037 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.81891427139305195568041980071675300462295051679221841940859774802676161361037
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.49679479763557607600746192393196981407514008661457722333535194899046945120349
Short name T506
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.65 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:49 PM PDT 23
Peak memory 201308 kb
Host smart-34334769-e41e-4fae-b261-64dd4f5d2da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49679479763557607600746192393196981407514008661457722333535194899046945120349 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.49679479763557607600746192393196981407514008661457722333535194899046945120349
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.23623419562664512237652161530604192925886546051674652030688229671721893601081
Short name T325
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:13:45 PM PDT 23
Peak memory 201144 kb
Host smart-7a34029b-d1d4-496a-9b5a-54faaf264c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23623419562664512237652161530604192925886546051674652030688229671721893601081 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_smoke.23623419562664512237652161530604192925886546051674652030688229671721893601081
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.13896079656968551921085177533503543443210943754263146474955055408643161451459
Short name T658
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.18 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:16:00 PM PDT 23
Peak memory 201552 kb
Host smart-0fa8feb4-04ff-4a6a-9720-be7f2cc76445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13896079656968551921085177533503543443210943754263146474955055408643161451459 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.13896079656968551921085177533503543443210943754263146474955055408643161451459
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.34554600510137914223582516982838353313747312931177305183300894132476430537273
Short name T124
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201256 kb
Host smart-c0ec36ed-0987-4956-b67d-0b708a17e975
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34554600510137914223582516982838353313747312931177305183300894132476430537273 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.345546005101379142235825169828383533137473129311773051833008
94132476430537273
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.25386400561006246598418221973061325593866637912178117939313465476993924112038
Short name T437
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:46 PM PDT 23
Peak memory 201212 kb
Host smart-9fc75110-262d-478a-959a-2e43a4a87773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25386400561006246598418221973061325593866637912178117939313465476993924112038 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.25386400561006246598418221973061325593866637912178117939313465476993924112038
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.80399562313711883262996356694378620244931963830286968206849214151684950507300
Short name T272
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.39 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201260 kb
Host smart-6eb10efa-0d76-418c-9dc9-11c6988e1c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80399562313711883262996356694378620244931963830286968206849214151684950507300 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.80399562313711883262996356694378620244931963830286968206849214151684950507300
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.56465192240783842071195888629753800256680488122731452667984720060715837109888
Short name T357
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.35 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:17:05 PM PDT 23
Peak memory 201556 kb
Host smart-518ca4b7-9efd-473e-8930-ad9702e33427
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56465192240783842071195888629753800256680488122731452667984720060715837109888 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.56465192240783842071195888629753800256680488122731452667984720
060715837109888
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.40140728721948112441586820820192691718612011813922123354517364382454449596871
Short name T434
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.29 seconds
Started Oct 25 02:13:56 PM PDT 23
Finished Oct 25 02:14:03 PM PDT 23
Peak memory 201308 kb
Host smart-91ec4124-1cf3-4226-bf4f-cfd7c519e347
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40140728721948112441586820820192691718612011813922123354517364382454449596871 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.401407287219481124415868208201926917186120118139221233545173
64382454449596871
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.29980340752924583064166670737454870523670949458242522726175315594509902066240
Short name T32
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.2 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201176 kb
Host smart-fafd6818-c30b-4e10-9be3-7fed1014e4b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29980340752924583064166670737454870523670949458242522726175315594509902066240 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.2998034075292458306416667073745487052367094945824252272617531559
4509902066240
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.81564463630425638347055366233489317171786158124098453042465689317666747345986
Short name T503
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.76 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:46 PM PDT 23
Peak memory 201228 kb
Host smart-5f7634bf-71ea-46a2-9af4-33d690eeb18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81564463630425638347055366233489317171786158124098453042465689317666747345986 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.81564463630425638347055366233489317171786158124098453042465689317666747345986
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.104251401904575544678710667863523736854993920347317218673564367944978656892220
Short name T101
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201236 kb
Host smart-a9100262-3229-4be8-a433-52eecb5e446d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104251401904575544678710667863523736854993920347317218673564367944978656892220 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.104251401904575544678710667863523736854993920347317218673564367944978656892220
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.14337126530891569014599196006638550322142376647630498284028940014021176781763
Short name T235
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201216 kb
Host smart-397f25d1-98b7-437e-9b2b-ea033abd78d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14337126530891569014599196006638550322142376647630498284028940014021176781763 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.14337126530891569014599196006638550322142376647630498284028940014021176781763
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.33830960587247138981365411425422859807462648793476242739203968532914256533349
Short name T254
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.5 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:13:45 PM PDT 23
Peak memory 201096 kb
Host smart-a5b51cdd-f4eb-421b-a01c-73383657d180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33830960587247138981365411425422859807462648793476242739203968532914256533349 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.33830960587247138981365411425422859807462648793476242739203968532914256533349
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.36381062904745032589951915511920694471257846666226870368156716697847524259245
Short name T454
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Oct 25 02:13:45 PM PDT 23
Finished Oct 25 02:13:50 PM PDT 23
Peak memory 201152 kb
Host smart-1c8abe24-acde-4777-a52b-555f7d45188b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36381062904745032589951915511920694471257846666226870368156716697847524259245 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sysrst_ctrl_smoke.36381062904745032589951915511920694471257846666226870368156716697847524259245
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.96893620362894652049287144109926774849209793546711346769117247357486759519325
Short name T35
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.47 seconds
Started Oct 25 02:13:46 PM PDT 23
Finished Oct 25 02:16:01 PM PDT 23
Peak memory 201620 kb
Host smart-b104da6e-f679-4a92-93d3-cc874462e8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96893620362894652049287144109926774849209793546711346769117247357486759519325 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.96893620362894652049287144109926774849209793546711346769117247357486759519325
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.46563583197352968433866914013603432481427574334524882924348961548378182381279
Short name T496
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Oct 25 02:13:57 PM PDT 23
Finished Oct 25 02:14:02 PM PDT 23
Peak memory 201016 kb
Host smart-6d1ea02e-7eb7-4cdb-837e-8a362a567676
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46563583197352968433866914013603432481427574334524882924348961548378182381279 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.465635831973529684338669140136034324814275743345248829243489
61548378182381279
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.54077299562305102026391153166558347093093271145252008319695787895826175059375
Short name T601
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201300 kb
Host smart-d2f23de0-9d70-45a9-b4ce-a0fec5b04a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54077299562305102026391153166558347093093271145252008319695787895826175059375 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.54077299562305102026391153166558347093093271145252008319695787895826175059375
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.65144698058162115530949629075135956968007322445244217883308389868262385531788
Short name T663
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.62 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201200 kb
Host smart-37a58462-a4db-4e0a-85c3-6317a5157df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65144698058162115530949629075135956968007322445244217883308389868262385531788 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.65144698058162115530949629075135956968007322445244217883308389868262385531788
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.47639556676216341480849455560808343025795753084174220660914332157443730867121
Short name T190
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.4 seconds
Started Oct 25 02:13:57 PM PDT 23
Finished Oct 25 02:16:59 PM PDT 23
Peak memory 201432 kb
Host smart-2f97ba20-15c9-42b7-8bef-751d88ac6bb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47639556676216341480849455560808343025795753084174220660914332157443730867121 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.47639556676216341480849455560808343025795753084174220660914332
157443730867121
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.47030917687530993616269449068240383395164144500768191378953191457050589779203
Short name T423
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.49 seconds
Started Oct 25 02:13:46 PM PDT 23
Finished Oct 25 02:13:54 PM PDT 23
Peak memory 201044 kb
Host smart-5924ea2b-d409-417b-befb-19622236c8c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47030917687530993616269449068240383395164144500768191378953191457050589779203 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.470309176875309936162694490682403833951641445007681913789531
91457050589779203
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.66586779684167869006547681235026576059345468818011562442987604846285405603012
Short name T665
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 25 02:14:00 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201212 kb
Host smart-4da48d24-2fc2-429e-aae4-30c7d7c40e1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66586779684167869006547681235026576059345468818011562442987604846285405603012 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.6658677968416786900654768123502657605934546881801156244298760484
6285405603012
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.84256192339589716823798636779352839756562019573944390524243828623197266432522
Short name T399
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:14:14 PM PDT 23
Peak memory 201256 kb
Host smart-00028a8b-c93f-44c7-a029-c0c7cc1ea21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84256192339589716823798636779352839756562019573944390524243828623197266432522 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.84256192339589716823798636779352839756562019573944390524243828623197266432522
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.21401324164703850370728421669710596223085905752974321783866172774362835185979
Short name T456
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 25 02:13:58 PM PDT 23
Finished Oct 25 02:14:04 PM PDT 23
Peak memory 201140 kb
Host smart-ca6068e9-ae33-4739-989a-724d16dc0f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21401324164703850370728421669710596223085905752974321783866172774362835185979 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.21401324164703850370728421669710596223085905752974321783866172774362835185979
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.5190654928093293322926107921941399110707460410615326580428048814404071397086
Short name T582
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 25 02:14:03 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201080 kb
Host smart-ec7b9474-7fa6-43d9-ab89-bddafc2a2ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5190654928093293322926107921941399110707460410615326580428048814404071397086 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.5190654928093293322926107921941399110707460410615326580428048814404071397086
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.2134415598579431183978350768211272831587286231235136138726694837056866543418
Short name T186
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.68 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201224 kb
Host smart-6df182ca-fab2-4b01-9598-47e6d715ee7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134415598579431183978350768211272831587286231235136138726694837056866543418 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.2134415598579431183978350768211272831587286231235136138726694837056866543418
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.88789654097625110090407747064008487581157395831637406822642282247185458062451
Short name T419
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 25 02:13:45 PM PDT 23
Finished Oct 25 02:13:49 PM PDT 23
Peak memory 201280 kb
Host smart-5b6fb883-0b25-4978-a2b2-6d46e8ab90a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88789654097625110090407747064008487581157395831637406822642282247185458062451 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sysrst_ctrl_smoke.88789654097625110090407747064008487581157395831637406822642282247185458062451
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.36745542125660060120784327229150726134931161184865907479822463942594419300925
Short name T226
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.49 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:16:18 PM PDT 23
Peak memory 201536 kb
Host smart-8cc5c2d7-dd5a-40c1-afe4-4192966cbc36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36745542125660060120784327229150726134931161184865907479822463942594419300925 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.36745542125660060120784327229150726134931161184865907479822463942594419300925
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.32233588652696077139563305050678404502003358858965511510695687974481801489435
Short name T391
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:49 PM PDT 23
Peak memory 201228 kb
Host smart-d5714ca4-4d60-4b19-afad-16823a260817
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32233588652696077139563305050678404502003358858965511510695687974481801489435 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.322335886526960771395633050506784045020033588589655115106956
87974481801489435
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.92129478243944539830144998427549793188571124313157516224179473407804713646751
Short name T606
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 25 02:12:53 PM PDT 23
Finished Oct 25 02:12:57 PM PDT 23
Peak memory 201092 kb
Host smart-829102a4-d844-446c-9c9d-5107eeff7320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92129478243944539830144998427549793188571124313157516224179473407804713646751 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.92129478243944539830144998427549793188571124313157516224179473407804713646751
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.35305195920743236085259037253809834902112836910656975486043724673827321120521
Short name T564
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:12:45 PM PDT 23
Peak memory 201316 kb
Host smart-ca1e6377-76cf-4e60-8d6c-0cedef1ff07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35305195920743236085259037253809834902112836910656975486043724673827321120521 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.35305195920743236085259037253809834902112836910656975486043724673827321120521
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.10596141660776142758243639775775063774295346747252549428233907754507797794367
Short name T647
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.92 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:15:59 PM PDT 23
Peak memory 201480 kb
Host smart-2d7ab5c3-4f95-4f0b-a50a-d0d2d6cbc728
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596141660776142758243639775775063774295346747252549428233907754507797794367 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.105961416607761427582436397757750637742953467472525494282339077
54507797794367
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.50598556361686467794360384415546370792515462317940951235518145177484073852316
Short name T126
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.24 seconds
Started Oct 25 02:12:37 PM PDT 23
Finished Oct 25 02:12:42 PM PDT 23
Peak memory 201308 kb
Host smart-da5169b0-abef-4687-b622-848450e11cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50598556361686467794360384415546370792515462317940951235518145177484073852316 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.50598556361686467794360384415546370792515462317940951235518145177484073852316
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.30624061726894942271672358439980514362096900249958489381259982944991843225850
Short name T115
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.47 seconds
Started Oct 25 02:12:37 PM PDT 23
Finished Oct 25 02:12:42 PM PDT 23
Peak memory 201348 kb
Host smart-694455de-e237-41d9-8735-9ffec3b96b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30624061726894942271672358439980514362096900249958489381259982944991843225850 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.30624061726894942271672358439980514362096900249958489
381259982944991843225850
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.79358197342099275085294033267308659936984729310402235307145080900024016480632
Short name T504
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Oct 25 02:12:38 PM PDT 23
Finished Oct 25 02:12:47 PM PDT 23
Peak memory 201264 kb
Host smart-24f7f1a2-a11d-4440-8cfb-6e8b17ce37da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79358197342099275085294033267308659936984729310402235307145080900024016480632 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.7935819734209927508529403326730865993698472931040223530714508
0900024016480632
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.8725507695002847829823860584879096833081659527087136046440114882592381727370
Short name T484
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.37 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:12:47 PM PDT 23
Peak memory 201192 kb
Host smart-420e946b-a920-4376-b2ac-ec0e925d6f35
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8725507695002847829823860584879096833081659527087136046440114882592381727370 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.8725507695002847829823860584879096833081659527087136046440114882592381727370
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.63462412049689955602470956899172960824137558252504683335595207809193561286933
Short name T414
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 25 02:12:40 PM PDT 23
Finished Oct 25 02:12:45 PM PDT 23
Peak memory 201120 kb
Host smart-4b202e13-ad9e-4e9f-b2f4-e000871fb49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63462412049689955602470956899172960824137558252504683335595207809193561286933 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.63462412049689955602470956899172960824137558252504683335595207809193561286933
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.16146509256465823197349144205392571710122005150439140742631243187746232305920
Short name T171
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:12:45 PM PDT 23
Peak memory 201152 kb
Host smart-00ccc979-fe57-4223-8fc6-e83c8d138a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16146509256465823197349144205392571710122005150439140742631243187746232305920 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.16146509256465823197349144205392571710122005150439140742631243187746232305920
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.82122788212606555918310136932132998504578518435110443409341414674057471817265
Short name T532
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:12:44 PM PDT 23
Peak memory 201088 kb
Host smart-d559505f-44d0-4296-aab8-3c8401800688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82122788212606555918310136932132998504578518435110443409341414674057471817265 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.82122788212606555918310136932132998504578518435110443409341414674057471817265
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.103185518585643069266595761695543937244826967952418527484644766879692063449885
Short name T233
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 25 02:12:24 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 201204 kb
Host smart-65ab442f-ac4b-4a43-9682-a8251a7af5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103185518585643069266595761695543937244826967952418527484644766879692063449885 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.103185518585643069266595761695543937244826967952418527484644766879692063449885
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.52482432733992411979893373392900899375767958775081195912211531458090683005252
Short name T137
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.23 seconds
Started Oct 25 02:12:52 PM PDT 23
Finished Oct 25 02:13:57 PM PDT 23
Peak memory 221600 kb
Host smart-6d789409-40da-4e8e-9141-926fbfa4e870
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52482432733992411979893373392900899375767958775081195912211531458090683005252 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.52482432733992411979893373392900899375767958775081195912211531458090683005252
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.36053394836426357142127106645910444902335957583994704308459848328930617581047
Short name T632
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201152 kb
Host smart-ea550876-4ba6-44f6-b81a-c67f6cd54f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36053394836426357142127106645910444902335957583994704308459848328930617581047 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_smoke.36053394836426357142127106645910444902335957583994704308459848328930617581047
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.110085239806920237889640351279924937322523483464583035595384812253775129602553
Short name T596
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.44 seconds
Started Oct 25 02:12:53 PM PDT 23
Finished Oct 25 02:15:09 PM PDT 23
Peak memory 201508 kb
Host smart-0fb163ec-19fa-47d1-8720-2db9dff72dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110085239806920237889640351279924937322523483464583035595384812253775129602553 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.110085239806920237889640351279924937322523483464583035595384812253775129602553
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.51050112225694734018488192439572084589331897779690190552889858957629979159628
Short name T253
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Oct 25 02:12:25 PM PDT 23
Finished Oct 25 02:12:30 PM PDT 23
Peak memory 201192 kb
Host smart-c5eecba1-02d2-4520-93ff-028eaf4078a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51050112225694734018488192439572084589331897779690190552889858957629979159628 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.5105011222569473401848819243957208458933189777969019055288985
8957629979159628
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.112005950323892643662180541477738650642458817403897346032258476582833115859836
Short name T655
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:45 PM PDT 23
Peak memory 201200 kb
Host smart-ee272435-6184-4cc4-a30c-320fd35d5b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112005950323892643662180541477738650642458817403897346032258476582833115859836 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.112005950323892643662180541477738650642458817403897346032258476582833115859836
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.115589501446825498674740068065843733865007976921808818944416935827431434974593
Short name T96
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201212 kb
Host smart-7089b399-1b74-455b-8f7e-cc97b7e5b7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115589501446825498674740068065843733865007976921808818944416935827431434974593 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.115589501446825498674740068065843733865007976921808818944416935827431434974593
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.39971271575117582687058071726585505374386944930946137145403034894967634626362
Short name T127
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.41 seconds
Started Oct 25 02:13:36 PM PDT 23
Finished Oct 25 02:16:38 PM PDT 23
Peak memory 201392 kb
Host smart-079a86d1-9f4a-4b5c-a5fc-47d8e94542e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39971271575117582687058071726585505374386944930946137145403034894967634626362 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.39971271575117582687058071726585505374386944930946137145403034
894967634626362
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.78851062077483893963040470634116575235629756478313457982952655802229231050656
Short name T535
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:51 PM PDT 23
Peak memory 201172 kb
Host smart-5ff954cd-a17a-49c3-ae45-9457bfe06884
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78851062077483893963040470634116575235629756478313457982952655802229231050656 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.788510620774838939630404706341165752356297564783134579829526
55802229231050656
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.8122736082347550417960350331690985127803843545011122426520993595038568564797
Short name T135
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201224 kb
Host smart-67440a18-2da5-4712-b217-2b0dd8822fd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8122736082347550417960350331690985127803843545011122426520993595038568564797 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.8122736082347550417960350331690985127803843545011122426520993595038568564797
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.104480654135994462197367969872841345294101319374008661458429346013500423117229
Short name T599
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Oct 25 02:14:09 PM PDT 23
Finished Oct 25 02:14:14 PM PDT 23
Peak memory 201228 kb
Host smart-b4ff914b-6c27-45f4-baec-c8d58ee7fa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104480654135994462197367969872841345294101319374008661458429346013500423117229 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.104480654135994462197367969872841345294101319374008661458429346013500423117229
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.100491754577856683110006479397348039575595223312458677039323518942593441262922
Short name T181
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.97 seconds
Started Oct 25 02:14:00 PM PDT 23
Finished Oct 25 02:14:05 PM PDT 23
Peak memory 201196 kb
Host smart-285c601d-32c9-40b1-a26b-6858f94228c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100491754577856683110006479397348039575595223312458677039323518942593441262922 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.100491754577856683110006479397348039575595223312458677039323518942593441262922
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.63498542941555043561082763641017461553546486113419162352619136756503502576717
Short name T44
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201184 kb
Host smart-2f1ad097-0cad-4979-83d2-627a21a381e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63498542941555043561082763641017461553546486113419162352619136756503502576717 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.63498542941555043561082763641017461553546486113419162352619136756503502576717
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.55729123597244758924233046659518071059579348991939109794043064691521710570308
Short name T328
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:14:13 PM PDT 23
Peak memory 201148 kb
Host smart-4d21fab4-5016-423c-830c-9411cedf7061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55729123597244758924233046659518071059579348991939109794043064691521710570308 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.55729123597244758924233046659518071059579348991939109794043064691521710570308
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.40312327653889826535208767656507450367737879365781236691200438049492973927508
Short name T515
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.75 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201080 kb
Host smart-33b10f77-6892-4e0b-b175-6bfe18afc1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40312327653889826535208767656507450367737879365781236691200438049492973927508 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_smoke.40312327653889826535208767656507450367737879365781236691200438049492973927508
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.15111554454236847041272873157458823653978836721685581351946580364727527830074
Short name T265
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.9 seconds
Started Oct 25 02:13:37 PM PDT 23
Finished Oct 25 02:15:52 PM PDT 23
Peak memory 201428 kb
Host smart-ab801fc1-f6f0-4e9a-bc50-40526bd94c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15111554454236847041272873157458823653978836721685581351946580364727527830074 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.15111554454236847041272873157458823653978836721685581351946580364727527830074
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.20471121020192234303476754163283549718952190476668222463495525828945969859981
Short name T463
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201060 kb
Host smart-2b975ce2-d4ad-4825-8ab9-52fb70a91d29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20471121020192234303476754163283549718952190476668222463495525828945969859981 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.204711210201922343034767541632835497189521904766682224634955
25828945969859981
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.92750743117540852360444717916535298972950284312661094845559628857604216517717
Short name T102
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201260 kb
Host smart-3a667f7c-3401-478b-be8a-813abfd5fb43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92750743117540852360444717916535298972950284312661094845559628857604216517717 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.92750743117540852360444717916535298972950284312661094845559628857604216517717
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.28150165772627812024315230114475064657845989437666946234818479560547868649350
Short name T313
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 25 02:13:45 PM PDT 23
Finished Oct 25 02:13:51 PM PDT 23
Peak memory 201412 kb
Host smart-4973b994-52f9-4519-9cd1-b872a8a082b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28150165772627812024315230114475064657845989437666946234818479560547868649350 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.28150165772627812024315230114475064657845989437666946234818479560547868649350
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.66406257875798878598552791836142412803305324465717965507456072768048001260540
Short name T555
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.93 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:16:45 PM PDT 23
Peak memory 201480 kb
Host smart-02774b5d-ac07-4b38-abec-62c45c0f87a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66406257875798878598552791836142412803305324465717965507456072768048001260540 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.66406257875798878598552791836142412803305324465717965507456072
768048001260540
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.42061725881711094718736166784885187497528711032421433931811781141793746270387
Short name T517
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.3 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201276 kb
Host smart-bc3e3997-5de0-4bc4-8a65-39cdf179fae1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42061725881711094718736166784885187497528711032421433931811781141793746270387 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.420617258817110947187361667848851874975287110324214339318117
81141793746270387
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.88793444016949307225802416183815926038956519917912215446606422898573013972835
Short name T509
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:49 PM PDT 23
Peak memory 201176 kb
Host smart-ba0eae26-772f-4aad-b3b0-08af9b10484e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88793444016949307225802416183815926038956519917912215446606422898573013972835 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.8879344401694930722580241618381592603895651991791221544660642289
8573013972835
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.93410431984954457877349735261319896017865851077981931561453652601512973513985
Short name T163
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Oct 25 02:13:39 PM PDT 23
Finished Oct 25 02:13:44 PM PDT 23
Peak memory 201152 kb
Host smart-b1354410-80d6-4f87-95a1-1cba15553a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93410431984954457877349735261319896017865851077981931561453652601512973513985 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.93410431984954457877349735261319896017865851077981931561453652601512973513985
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.49330547098576876999423743216030826972730762154963623659148466548186387823746
Short name T514
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 25 02:13:37 PM PDT 23
Finished Oct 25 02:13:42 PM PDT 23
Peak memory 201288 kb
Host smart-bed93186-df7a-48bc-ac28-4886668e6d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49330547098576876999423743216030826972730762154963623659148466548186387823746 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.49330547098576876999423743216030826972730762154963623659148466548186387823746
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.78603755884689609686341603297589391523193992440839733500886967030471879618338
Short name T153
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201204 kb
Host smart-82d578fc-de0b-483e-82e1-0214fd43fbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78603755884689609686341603297589391523193992440839733500886967030471879618338 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.78603755884689609686341603297589391523193992440839733500886967030471879618338
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.73038321308387581815843704165276409177206819473182829994289415833163316224169
Short name T232
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.51 seconds
Started Oct 25 02:13:39 PM PDT 23
Finished Oct 25 02:13:44 PM PDT 23
Peak memory 201240 kb
Host smart-61a8080d-e199-4271-ba0f-d7131c1299a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73038321308387581815843704165276409177206819473182829994289415833163316224169 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.73038321308387581815843704165276409177206819473182829994289415833163316224169
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.70702417848037800374479060177650820476107287977939885520912205420475954226095
Short name T309
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201076 kb
Host smart-c489e317-ec5a-49a7-b392-05af295d5cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70702417848037800374479060177650820476107287977939885520912205420475954226095 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_smoke.70702417848037800374479060177650820476107287977939885520912205420475954226095
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.66698528495291999022512065696069658610898925999703011785257100614330224064262
Short name T227
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.29 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:15:56 PM PDT 23
Peak memory 201508 kb
Host smart-91572714-b49b-405b-bc56-02b76435718d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66698528495291999022512065696069658610898925999703011785257100614330224064262 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.66698528495291999022512065696069658610898925999703011785257100614330224064262
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.48268353501197674597652010786639316360148765911335756509343469116930679770153
Short name T531
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201176 kb
Host smart-06f9fb82-5110-4b37-8aa4-9fdf7b1c4ca7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48268353501197674597652010786639316360148765911335756509343469116930679770153 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.482683535011976745976520107866393163601487659113357565093434
69116930679770153
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.105345487744182857545180353271354630110501318755441925050569258978883806181729
Short name T215
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 25 02:13:58 PM PDT 23
Finished Oct 25 02:14:02 PM PDT 23
Peak memory 201240 kb
Host smart-cc88ff9e-acd8-4278-a598-c16f5efeb246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105345487744182857545180353271354630110501318755441925050569258978883806181729 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.105345487744182857545180353271354630110501318755441925050569258978883806181729
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.70466165897222585161916661524080935916304128648257886951412923143373233542446
Short name T621
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Oct 25 02:13:46 PM PDT 23
Finished Oct 25 02:13:52 PM PDT 23
Peak memory 201064 kb
Host smart-33ab39ad-7c3a-4bb9-9f09-7576d0a19f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70466165897222585161916661524080935916304128648257886951412923143373233542446 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.70466165897222585161916661524080935916304128648257886951412923143373233542446
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.54100966026932213051168886831469149311831129979349456140200649888311548794793
Short name T312
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.45 seconds
Started Oct 25 02:13:57 PM PDT 23
Finished Oct 25 02:16:57 PM PDT 23
Peak memory 201468 kb
Host smart-665b9b68-907a-481f-b7fa-6a4480b4b8dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54100966026932213051168886831469149311831129979349456140200649888311548794793 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.54100966026932213051168886831469149311831129979349456140200649
888311548794793
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.58760303137990700389927783919165380522904408690317079293678452382051454044325
Short name T415
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.31 seconds
Started Oct 25 02:13:59 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201272 kb
Host smart-9b96109d-41ea-447e-b025-0b2077d53d30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58760303137990700389927783919165380522904408690317079293678452382051454044325 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.587603031379907003899277839191653805229044086903170792936784
52382051454044325
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.79191535128525498668685055125886320823528709804355310780129245463305998582068
Short name T447
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 25 02:14:03 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201244 kb
Host smart-afd843f7-8cf9-413c-b8e7-3428e8288c07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79191535128525498668685055125886320823528709804355310780129245463305998582068 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.7919153512852549866868505512588632082352870980435531078012924546
3305998582068
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.69724006792802783486258566214250967030514231802090265368641573234542548714462
Short name T351
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:49 PM PDT 23
Peak memory 201120 kb
Host smart-4ce4b947-03b0-41b3-a04b-f378fa10abac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69724006792802783486258566214250967030514231802090265368641573234542548714462 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.69724006792802783486258566214250967030514231802090265368641573234542548714462
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.105658006557752242008195394219004250409703873115652811043829966684431762047736
Short name T216
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201280 kb
Host smart-d02f9531-9180-4fa8-ac45-c8ffe25aa132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105658006557752242008195394219004250409703873115652811043829966684431762047736 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.105658006557752242008195394219004250409703873115652811043829966684431762047736
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.110136652965255004436757035670069588072934203248320443028122369935773133090220
Short name T174
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201208 kb
Host smart-73d73c35-fa7f-4d45-9863-b27718ce598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110136652965255004436757035670069588072934203248320443028122369935773133090220 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.110136652965255004436757035670069588072934203248320443028122369935773133090220
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.15861102480462473160113135601529838058587995099299498421578995608638789372117
Short name T278
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201292 kb
Host smart-5f1de182-a87d-484c-8df5-8d2555683e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15861102480462473160113135601529838058587995099299498421578995608638789372117 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.15861102480462473160113135601529838058587995099299498421578995608638789372117
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.112832536652945527663005716365657311342086782910049831219601095500789631285409
Short name T298
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201156 kb
Host smart-e39f22c4-5084-4961-8f24-82b244c82888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112832536652945527663005716365657311342086782910049831219601095500789631285409 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 22.sysrst_ctrl_smoke.112832536652945527663005716365657311342086782910049831219601095500789631285409
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.35768326939798380373273034085184502214282753985081815419259068803267439211826
Short name T495
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 25 02:13:46 PM PDT 23
Finished Oct 25 02:13:51 PM PDT 23
Peak memory 201212 kb
Host smart-ad18cae3-4d15-4402-a002-1d55377ddb10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35768326939798380373273034085184502214282753985081815419259068803267439211826 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.357683269397983803732730340851845022142827539850818154192590
68803267439211826
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.83531100219355113647542877330261315158531407991852582319711674336882851888838
Short name T42
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.75 seconds
Started Oct 25 02:13:58 PM PDT 23
Finished Oct 25 02:14:03 PM PDT 23
Peak memory 201240 kb
Host smart-b9384ba3-fd03-4fcc-bf92-64f39220ef61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83531100219355113647542877330261315158531407991852582319711674336882851888838 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.83531100219355113647542877330261315158531407991852582319711674336882851888838
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.7092228939302550392032946309035062873947203981674839000849452928281109951006
Short name T581
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201392 kb
Host smart-32ff5419-1394-43c4-bfde-e41d4f17c91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7092228939302550392032946309035062873947203981674839000849452928281109951006 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.7092228939302550392032946309035062873947203981674839000849452928281109951006
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.41152517647595354421207440299028138291704656190300652648852797446398553002415
Short name T473
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.16 seconds
Started Oct 25 02:14:03 PM PDT 23
Finished Oct 25 02:17:05 PM PDT 23
Peak memory 201500 kb
Host smart-28887da7-7352-4ee9-bcd3-bce5e3e751ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41152517647595354421207440299028138291704656190300652648852797446398553002415 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.41152517647595354421207440299028138291704656190300652648852797
446398553002415
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.100712960473874885096240891731955650789502316114184078977696308599603594593607
Short name T331
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.44 seconds
Started Oct 25 02:14:00 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201248 kb
Host smart-ed72c265-1fcc-42a7-aabd-f149d33d89b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100712960473874885096240891731955650789502316114184078977696308599603594593607 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.10071296047387488509624089173195565078950231611418407897769
6308599603594593607
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.114040696694471759703922583000378993955475149361496325433050247986095669036556
Short name T209
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201220 kb
Host smart-14cd6f72-f4fd-4bd6-a54a-f79ce2630a8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114040696694471759703922583000378993955475149361496325433050247986095669036556 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.114040696694471759703922583000378993955475149361496325433050247
986095669036556
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.29246469710341411081584279026516242622797044490247179147491660577752180624565
Short name T610
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201244 kb
Host smart-8a74781d-de44-440d-995f-965bf98e1591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29246469710341411081584279026516242622797044490247179147491660577752180624565 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.29246469710341411081584279026516242622797044490247179147491660577752180624565
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.96856670616537513863643796857827705497480480343637577027145383746897603158282
Short name T343
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201300 kb
Host smart-a6b18922-6a6f-4531-b4f7-c44262fbd132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96856670616537513863643796857827705497480480343637577027145383746897603158282 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.96856670616537513863643796857827705497480480343637577027145383746897603158282
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.39891507436438059715038168666416910491809283059267000641676843802251816743767
Short name T574
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:13:59 PM PDT 23
Finished Oct 25 02:14:03 PM PDT 23
Peak memory 201132 kb
Host smart-238730c2-fb43-48eb-bb10-79c69772db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39891507436438059715038168666416910491809283059267000641676843802251816743767 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.39891507436438059715038168666416910491809283059267000641676843802251816743767
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.19108299465337878019532164661825102312973266805212445646623123825902667390027
Short name T541
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201152 kb
Host smart-cbb748a5-6cf2-46ec-83e8-0e7d77739840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19108299465337878019532164661825102312973266805212445646623123825902667390027 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.19108299465337878019532164661825102312973266805212445646623123825902667390027
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.104989527902496602512295949424400931708362414414623636705401487558084222296668
Short name T326
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.74 seconds
Started Oct 25 02:13:57 PM PDT 23
Finished Oct 25 02:14:01 PM PDT 23
Peak memory 200960 kb
Host smart-ac634885-700a-47ca-a48e-ecbd1bdbe4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104989527902496602512295949424400931708362414414623636705401487558084222296668 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 23.sysrst_ctrl_smoke.104989527902496602512295949424400931708362414414623636705401487558084222296668
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.88238948679204177183584487995752426499041205108546125977452665018332920397143
Short name T507
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.65 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:16:20 PM PDT 23
Peak memory 201432 kb
Host smart-07cbf18a-b2a8-42eb-ad8b-2d145e915430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88238948679204177183584487995752426499041205108546125977452665018332920397143 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.88238948679204177183584487995752426499041205108546125977452665018332920397143
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.25726865541109162922096194317904084447344652563216548101206692480585446570092
Short name T251
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201144 kb
Host smart-cce3d257-2efc-4250-9472-717ff84fff86
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25726865541109162922096194317904084447344652563216548101206692480585446570092 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.257268655411091629220961943179040844473446525632165481012066
92480585446570092
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3565637391248002306808809940659633673092289122972395498732638770915843330362
Short name T274
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Oct 25 02:13:39 PM PDT 23
Finished Oct 25 02:13:44 PM PDT 23
Peak memory 201232 kb
Host smart-5082a473-25ef-46f7-810f-b981dc6b9ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565637391248002306808809940659633673092289122972395498732638770915843330362 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.3565637391248002306808809940659633673092289122972395498732638770915843330362
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.89327245159581695513769457192490278123241897740831545192243247125139945520207
Short name T384
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201164 kb
Host smart-ef75b347-2b3e-4d71-ac6a-b7bd2c5b5011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89327245159581695513769457192490278123241897740831545192243247125139945520207 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.89327245159581695513769457192490278123241897740831545192243247125139945520207
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.10739049611984456558739877834853857182022872373068258960385955698149910785222
Short name T451
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.04 seconds
Started Oct 25 02:13:58 PM PDT 23
Finished Oct 25 02:17:02 PM PDT 23
Peak memory 201516 kb
Host smart-0b0816e7-9c46-489f-949b-7034052ad51b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10739049611984456558739877834853857182022872373068258960385955698149910785222 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.10739049611984456558739877834853857182022872373068258960385955
698149910785222
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.91636608670160021160159378178094380055540037799896416691479977047010539178994
Short name T350
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.45 seconds
Started Oct 25 02:13:39 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201300 kb
Host smart-fef3227c-ce0a-4c90-9931-61e463e7acb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91636608670160021160159378178094380055540037799896416691479977047010539178994 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.916366086701600211601593781780943800555400377998964166914799
77047010539178994
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.105767662421426746120080067755680909834288698630196049309357232946371525944994
Short name T571
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 25 02:13:40 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201252 kb
Host smart-1748823b-05a4-48fc-a607-5d3e44feadff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105767662421426746120080067755680909834288698630196049309357232946371525944994 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.105767662421426746120080067755680909834288698630196049309357232
946371525944994
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.38038594031078787316801756129984714486389689116261178154192216076168010879964
Short name T388
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201104 kb
Host smart-8eb9662b-ba68-46f2-8000-4156a916ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38038594031078787316801756129984714486389689116261178154192216076168010879964 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.38038594031078787316801756129984714486389689116261178154192216076168010879964
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.10778508946835787864100104849965845503337580831056518473561041562107264155961
Short name T345
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.88 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201364 kb
Host smart-2d6ec4ec-1a1a-4ea2-b4c8-a7454e22e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10778508946835787864100104849965845503337580831056518473561041562107264155961 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.10778508946835787864100104849965845503337580831056518473561041562107264155961
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.110060272887485874326451003804293884472671783164209952771814076534818784285938
Short name T537
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 25 02:13:38 PM PDT 23
Finished Oct 25 02:13:44 PM PDT 23
Peak memory 201200 kb
Host smart-b0dd4bc1-76e9-4b90-90d9-4ccd17f68363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110060272887485874326451003804293884472671783164209952771814076534818784285938 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.110060272887485874326451003804293884472671783164209952771814076534818784285938
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.47605913213981575223561114572332521555110586993397103642470912243177675215560
Short name T525
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201268 kb
Host smart-ad22ea1d-eb69-430c-8296-4a9da49b3c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47605913213981575223561114572332521555110586993397103642470912243177675215560 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.47605913213981575223561114572332521555110586993397103642470912243177675215560
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.1742119929240677911668906553298902232230829687929254898800951173785804341279
Short name T184
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 25 02:14:03 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201180 kb
Host smart-ef8089ff-0417-4024-b865-544e6315518a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742119929240677911668906553298902232230829687929254898800951173785804341279 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sysrst_ctrl_smoke.1742119929240677911668906553298902232230829687929254898800951173785804341279
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.88241120116870578960357996054915955042662296465311288350171221049320264130879
Short name T597
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.92 seconds
Started Oct 25 02:13:37 PM PDT 23
Finished Oct 25 02:15:51 PM PDT 23
Peak memory 201528 kb
Host smart-1962610c-0bfb-491c-ab5b-0cc887179a7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88241120116870578960357996054915955042662296465311288350171221049320264130879 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.88241120116870578960357996054915955042662296465311288350171221049320264130879
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.88745644868855404076445728068960895491739896600517910854206497397335335132966
Short name T148
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:46 PM PDT 23
Peak memory 201268 kb
Host smart-0d463956-b61a-40ff-ad26-086976edd237
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88745644868855404076445728068960895491739896600517910854206497397335335132966 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.887456448688554040764457280689608954917398966005179108542064
97397335335132966
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.50216987634615882077773098433137491384411949281929329385465786517761287672560
Short name T374
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Oct 25 02:13:58 PM PDT 23
Finished Oct 25 02:14:02 PM PDT 23
Peak memory 201160 kb
Host smart-6c377c64-d9ac-42ba-9ea6-060f2779ffb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50216987634615882077773098433137491384411949281929329385465786517761287672560 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.50216987634615882077773098433137491384411949281929329385465786517761287672560
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.72586766471670866220812067410184679284106642300857284493199365916567807773784
Short name T633
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:13:50 PM PDT 23
Peak memory 201064 kb
Host smart-9abc8f73-a34f-40c4-af4d-062d59f0f3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72586766471670866220812067410184679284106642300857284493199365916567807773784 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.72586766471670866220812067410184679284106642300857284493199365916567807773784
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.67973229971659727275904861343892173058865243149010879298669504137945165106720
Short name T281
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.67 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:16:43 PM PDT 23
Peak memory 201468 kb
Host smart-c501f64b-59ec-47c2-9e36-d51ec4406bd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67973229971659727275904861343892173058865243149010879298669504137945165106720 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.67973229971659727275904861343892173058865243149010879298669504
137945165106720
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.33199036062777364845557210883063609475688807663835147324834663380304386416972
Short name T638
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:51 PM PDT 23
Peak memory 201264 kb
Host smart-aab8f0c9-4424-4df7-a372-d257194dc110
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33199036062777364845557210883063609475688807663835147324834663380304386416972 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.331990360627773648455572108830636094756888076638351473248346
63380304386416972
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.21388889464414878120405937829343291714072557860798524587367149378168851194630
Short name T660
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:50 PM PDT 23
Peak memory 201192 kb
Host smart-fa4f69e8-9c80-4d28-a048-019fe0912d37
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21388889464414878120405937829343291714072557860798524587367149378168851194630 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.2138888946441487812040593782934329171407255786079852458736714937
8168851194630
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.99839464862546863005864614834180585179985606680583731770787605094740064379003
Short name T561
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:46 PM PDT 23
Peak memory 201284 kb
Host smart-fd916f3d-afa8-4848-93a9-d1211cf5e4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99839464862546863005864614834180585179985606680583731770787605094740064379003 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.99839464862546863005864614834180585179985606680583731770787605094740064379003
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.449363075124799406559842702937139407801436377220500867516920715020440836020
Short name T508
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201176 kb
Host smart-a026e88b-bdba-4fbf-b99e-c4df97fe3a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449363075124799406559842702937139407801436377220500867516920715020440836020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.449363075124799406559842702937139407801436377220500867516920715020440836020
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.88482152709287733953087583626120941086890739530561415885184131976319926542761
Short name T191
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 25 02:13:43 PM PDT 23
Finished Oct 25 02:13:47 PM PDT 23
Peak memory 201200 kb
Host smart-0edcb50a-5191-4b26-b3c4-dd6c2ef885b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88482152709287733953087583626120941086890739530561415885184131976319926542761 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.88482152709287733953087583626120941086890739530561415885184131976319926542761
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.43286529700976183670662241154711006370865438121817578457490032899685620581734
Short name T179
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 25 02:13:38 PM PDT 23
Finished Oct 25 02:13:44 PM PDT 23
Peak memory 201228 kb
Host smart-01c5d3e3-36e6-40f4-9b72-86fee546b443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43286529700976183670662241154711006370865438121817578457490032899685620581734 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.43286529700976183670662241154711006370865438121817578457490032899685620581734
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.23980150148466808890111039233724321121588429956122854547494747108932509536210
Short name T536
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 25 02:13:41 PM PDT 23
Finished Oct 25 02:13:46 PM PDT 23
Peak memory 201128 kb
Host smart-b9c1c145-f878-4557-a049-ac0d24b41a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23980150148466808890111039233724321121588429956122854547494747108932509536210 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_smoke.23980150148466808890111039233724321121588429956122854547494747108932509536210
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.77672373711812295727937450153219299533865591204590411730801170415410850004556
Short name T618
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.41 seconds
Started Oct 25 02:13:44 PM PDT 23
Finished Oct 25 02:15:59 PM PDT 23
Peak memory 201264 kb
Host smart-acf01f36-9d44-47cd-b6dd-20c2ac9c60b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77672373711812295727937450153219299533865591204590411730801170415410850004556 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.77672373711812295727937450153219299533865591204590411730801170415410850004556
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.25122484430386784150069225427524001645622054609700813899693932134425826147178
Short name T282
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.8 seconds
Started Oct 25 02:13:42 PM PDT 23
Finished Oct 25 02:13:48 PM PDT 23
Peak memory 201132 kb
Host smart-f22d8027-d55e-411c-a672-d17abfd05bba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25122484430386784150069225427524001645622054609700813899693932134425826147178 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.251224844303867841500692254275240016456220546097008138996939
32134425826147178
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.78271582970179334157359532829639539055734414969576792662906582858238703592222
Short name T277
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:14:14 PM PDT 23
Peak memory 201232 kb
Host smart-29023efb-f7aa-43b6-b4a6-0a35cf452757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78271582970179334157359532829639539055734414969576792662906582858238703592222 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.78271582970179334157359532829639539055734414969576792662906582858238703592222
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.9058717772700437895409641613370631617551869813550518193924698355394892749064
Short name T497
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.51 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201328 kb
Host smart-55c96bd1-b1b8-4b8b-9b1e-151ca909989c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9058717772700437895409641613370631617551869813550518193924698355394892749064 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.9058717772700437895409641613370631617551869813550518193924698355394892749064
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.115256525101140993906150101597093837058398503163587431656647790098484557791639
Short name T659
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.77 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:17:06 PM PDT 23
Peak memory 201388 kb
Host smart-b1a34321-2de0-472d-9288-4e2bd3194de8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115256525101140993906150101597093837058398503163587431656647790098484557791639 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.1152565251011409939061501015970938370583985031635874316566477
90098484557791639
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.107649944983164176738913983773305187684330680718066730798261111493558723893861
Short name T448
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201224 kb
Host smart-1f43ef5e-eaff-44a3-98a9-b23aaa30b53c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107649944983164176738913983773305187684330680718066730798261111493558723893861 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.10764994498316417673891398377330518768433068071806673079826
1111493558723893861
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.55625249527273282885037402229705932435697353146962612400748753120599493963955
Short name T406
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:12 PM PDT 23
Peak memory 201136 kb
Host smart-fb8c9dc6-deb1-44fd-b1cf-f5e5f386b5a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55625249527273282885037402229705932435697353146962612400748753120599493963955 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.5562524952727328288503740222970593243569735314696261240074875312
0599493963955
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1940895756630804687033116158120644022899126197208281932354644863068745534419
Short name T474
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201308 kb
Host smart-4b2364c2-7fee-45b5-98db-b4dc7af93ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940895756630804687033116158120644022899126197208281932354644863068745534419 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1940895756630804687033116158120644022899126197208281932354644863068745534419
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.108537245149360400291134791980367828221830300091703094783584398693019918245749
Short name T195
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201124 kb
Host smart-9fe5d3d3-1057-4d73-942a-3c9750fec122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108537245149360400291134791980367828221830300091703094783584398693019918245749 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.108537245149360400291134791980367828221830300091703094783584398693019918245749
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.35595611493027080825788934902105066034816657451788383068959218983806701244311
Short name T198
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201072 kb
Host smart-601f7603-4cde-4c21-ac74-52ae907ea068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35595611493027080825788934902105066034816657451788383068959218983806701244311 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.35595611493027080825788934902105066034816657451788383068959218983806701244311
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.99745183365417178812465224140357677400476324807744993257698070957784289082524
Short name T444
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:14:15 PM PDT 23
Peak memory 201200 kb
Host smart-aef3c8f6-7bf4-4c06-80e3-085d3e6bb082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99745183365417178812465224140357677400476324807744993257698070957784289082524 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.99745183365417178812465224140357677400476324807744993257698070957784289082524
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.107777723296396683575353240013401295674866795928278167479063180309076286133732
Short name T361
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 25 02:14:03 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201180 kb
Host smart-b850c5ee-0159-4e38-a5f0-b824fd1b2741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107777723296396683575353240013401295674866795928278167479063180309076286133732 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 26.sysrst_ctrl_smoke.107777723296396683575353240013401295674866795928278167479063180309076286133732
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.22022263156221027577643374290131221178224794628507993546919273368066097657910
Short name T199
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.74 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:16:25 PM PDT 23
Peak memory 201512 kb
Host smart-206d2264-1fff-4644-98ad-68b6972bb490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22022263156221027577643374290131221178224794628507993546919273368066097657910 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.22022263156221027577643374290131221178224794628507993546919273368066097657910
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.53526332732015231644073434728534222586618375728502107420587350268552365901945
Short name T624
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201140 kb
Host smart-11deae7d-dbe3-4a79-897c-aabb3b0966f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53526332732015231644073434728534222586618375728502107420587350268552365901945 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.535263327320152316440734347285342225866183757285021074205873
50268552365901945
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.14415862134663168305681612853714832350518196501578928467143788967960249649835
Short name T177
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:14:12 PM PDT 23
Peak memory 201240 kb
Host smart-c38e7f75-4b68-4b01-94e3-7085a83144f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14415862134663168305681612853714832350518196501578928467143788967960249649835 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.14415862134663168305681612853714832350518196501578928467143788967960249649835
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.101594081484410311715615082117991347401633049930009279674358422494326552167418
Short name T651
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.39 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:13 PM PDT 23
Peak memory 201316 kb
Host smart-b7969d10-adb6-4324-b492-66b9a90ef2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101594081484410311715615082117991347401633049930009279674358422494326552167418 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.101594081484410311715615082117991347401633049930009279674358422494326552167418
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.41627762106699942295787340514638740199078797552308063074828427812168517387203
Short name T185
Test name
Test status
Simulation time 118289458206 ps
CPU time 179.87 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:17:09 PM PDT 23
Peak memory 201472 kb
Host smart-255d2b4f-ca66-4b44-875e-714b3c001ef7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41627762106699942295787340514638740199078797552308063074828427812168517387203 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.41627762106699942295787340514638740199078797552308063074828427
812168517387203
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.86650565580422077963357874447756630109927013835914973996901335679033807646674
Short name T230
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:15 PM PDT 23
Peak memory 201260 kb
Host smart-351d3555-a1cd-44fb-9909-92c3482e8322
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86650565580422077963357874447756630109927013835914973996901335679033807646674 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.866505655804220779633578744477566301099270138359149739969013
35679033807646674
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.15265596118452356764694038117761698007912775957167819223101013750568591285451
Short name T136
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:14:15 PM PDT 23
Peak memory 201220 kb
Host smart-336d54e6-a61b-4e08-a15c-03ee06dbd540
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15265596118452356764694038117761698007912775957167819223101013750568591285451 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.1526559611845235676469403811776169800791277595716781922310101375
0568591285451
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.31732800567211948598081755614627350802690657218526234515301375508678044507578
Short name T267
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201280 kb
Host smart-bcf46e77-6b38-4962-8a74-adbc171318a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31732800567211948598081755614627350802690657218526234515301375508678044507578 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.31732800567211948598081755614627350802690657218526234515301375508678044507578
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.12505841592549878230384500816684729389742885397810172452617256909036779574590
Short name T237
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201176 kb
Host smart-17f9b179-fc70-43c6-81cd-ef1700e7e063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12505841592549878230384500816684729389742885397810172452617256909036779574590 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.12505841592549878230384500816684729389742885397810172452617256909036779574590
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.95744132388733449681509225371052235708236228514700006703997647391431757219869
Short name T330
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201032 kb
Host smart-8a0e7fe9-1c3b-432c-b703-e27aca17b785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95744132388733449681509225371052235708236228514700006703997647391431757219869 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.95744132388733449681509225371052235708236228514700006703997647391431757219869
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.53600601899410681014509469809383481427461729154413601171249845960943366962540
Short name T335
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201268 kb
Host smart-3dba66f9-1cfe-4b0e-bec9-70fb1cee361b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53600601899410681014509469809383481427461729154413601171249845960943366962540 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.53600601899410681014509469809383481427461729154413601171249845960943366962540
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.57246181147792045110601689665507270119670680474047234718014028327567030965817
Short name T103
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.86 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201152 kb
Host smart-9aab4e0c-46a7-4f64-ae86-d6bf1d6920a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57246181147792045110601689665507270119670680474047234718014028327567030965817 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sysrst_ctrl_smoke.57246181147792045110601689665507270119670680474047234718014028327567030965817
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.15414291240814813542716709870219735788238965500026651738093675216584811708481
Short name T493
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.67 seconds
Started Oct 25 02:14:09 PM PDT 23
Finished Oct 25 02:16:24 PM PDT 23
Peak memory 201512 kb
Host smart-383e26ea-ecf3-4ef6-ac76-9b923b677b2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15414291240814813542716709870219735788238965500026651738093675216584811708481 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.15414291240814813542716709870219735788238965500026651738093675216584811708481
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.992950453528882978328193477757256419830810069565575862591856755752018004382
Short name T480
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 25 02:14:11 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201312 kb
Host smart-5c3ade52-77f4-4628-a396-42a6f9a43cb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992950453528882978328193477757256419830810069565575862591856755752018004382 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.99295045352888297832819347775725641983081006956557586259185675
5752018004382
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.55707829420941544887379279783191035938308816551216195204459758413404498899728
Short name T367
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 25 02:14:35 PM PDT 23
Finished Oct 25 02:14:39 PM PDT 23
Peak memory 201232 kb
Host smart-27c24b05-6fe3-4a95-9f3a-ee037b881538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55707829420941544887379279783191035938308816551216195204459758413404498899728 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.55707829420941544887379279783191035938308816551216195204459758413404498899728
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.31215648860704898229620587324222866101061939231463535695020099048750066744472
Short name T486
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Oct 25 02:14:16 PM PDT 23
Finished Oct 25 02:14:22 PM PDT 23
Peak memory 201184 kb
Host smart-7754fde7-a8d9-4dd2-a052-4be62b13b0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31215648860704898229620587324222866101061939231463535695020099048750066744472 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.31215648860704898229620587324222866101061939231463535695020099048750066744472
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.87188647418251716177566543006132963666826001270028381566207061413201323831988
Short name T567
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.22 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:17:15 PM PDT 23
Peak memory 201360 kb
Host smart-35829f5b-7311-4c86-973b-5055c1a401c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87188647418251716177566543006132963666826001270028381566207061413201323831988 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.87188647418251716177566543006132963666826001270028381566207061
413201323831988
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.106437328965265483270991331552140234460218654969247322903595601885387848293385
Short name T640
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Oct 25 02:14:11 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201140 kb
Host smart-c9e87b2e-4e40-4f2a-b653-aaadc99203af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106437328965265483270991331552140234460218654969247322903595601885387848293385 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.10643732896526548327099133155214023446021865496924732290359
5601885387848293385
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.107406955211194444726140228573355904575656909641850338391010812181154820620937
Short name T352
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 25 02:14:15 PM PDT 23
Finished Oct 25 02:14:21 PM PDT 23
Peak memory 201220 kb
Host smart-dc7c5964-78c2-453e-9211-7e8327528ed8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107406955211194444726140228573355904575656909641850338391010812181154820620937 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.107406955211194444726140228573355904575656909641850338391010812
181154820620937
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.35954685703875763416978934696166866173207721415924202352967911132459356899897
Short name T165
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.6 seconds
Started Oct 25 02:14:13 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201240 kb
Host smart-f372d9ff-0339-4cc9-b8eb-b3d31ec8a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35954685703875763416978934696166866173207721415924202352967911132459356899897 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.35954685703875763416978934696166866173207721415924202352967911132459356899897
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.93200050369717776585021077558604096259841548689012835327823095810276482151882
Short name T613
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:14:17 PM PDT 23
Peak memory 201368 kb
Host smart-3a8903be-0878-4f0a-a19a-b2efe0a7ddd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93200050369717776585021077558604096259841548689012835327823095810276482151882 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.93200050369717776585021077558604096259841548689012835327823095810276482151882
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.81725718810619496222288051781936645236652403474655243418140694354616472922609
Short name T436
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:14:16 PM PDT 23
Finished Oct 25 02:14:21 PM PDT 23
Peak memory 201092 kb
Host smart-5bea9cdb-c688-4741-9529-7851fbd69d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81725718810619496222288051781936645236652403474655243418140694354616472922609 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.81725718810619496222288051781936645236652403474655243418140694354616472922609
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.18517409114949272434998850003945252887994566220728731886530172918091256618165
Short name T562
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 25 02:14:14 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201240 kb
Host smart-e1cd86f8-e9fb-4509-ba44-26aa5de916b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18517409114949272434998850003945252887994566220728731886530172918091256618165 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.18517409114949272434998850003945252887994566220728731886530172918091256618165
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.70612189996159076098576350593565091641148018446183893481057162839974161984250
Short name T560
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 25 02:14:14 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201192 kb
Host smart-af0e855e-ab08-41c4-b640-65fedc9e9548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70612189996159076098576350593565091641148018446183893481057162839974161984250 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_smoke.70612189996159076098576350593565091641148018446183893481057162839974161984250
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.11988824869744819194695517268085072438245338900928780029364571705523290677226
Short name T669
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.38 seconds
Started Oct 25 02:14:14 PM PDT 23
Finished Oct 25 02:16:29 PM PDT 23
Peak memory 201524 kb
Host smart-6a033466-72e5-4fb1-9398-e36b858ac712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11988824869744819194695517268085072438245338900928780029364571705523290677226 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.11988824869744819194695517268085072438245338900928780029364571705523290677226
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.3514337041014698786486907096925383909036390187040767594812430789153156170560
Short name T543
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:14:17 PM PDT 23
Peak memory 201104 kb
Host smart-72e46ac4-d681-4f4f-b6b1-bcf90ccd84e4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514337041014698786486907096925383909036390187040767594812430789153156170560 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.3514337041014698786486907096925383909036390187040767594812430
789153156170560
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.113244382700252924355816562414090904273144773697676856053956858359997266950310
Short name T386
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201280 kb
Host smart-48e03a0a-400e-4eac-9310-134cccc29835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113244382700252924355816562414090904273144773697676856053956858359997266950310 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.113244382700252924355816562414090904273144773697676856053956858359997266950310
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.88082520027911048432383652672750814094268543672586984658803780846893370997322
Short name T249
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 25 02:14:29 PM PDT 23
Finished Oct 25 02:14:35 PM PDT 23
Peak memory 201284 kb
Host smart-c4fbd59b-2c99-400d-a695-86049c36409d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88082520027911048432383652672750814094268543672586984658803780846893370997322 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.88082520027911048432383652672750814094268543672586984658803780846893370997322
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.86307060310797077439177964877424282334149181866031886544826451874143592323598
Short name T169
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.72 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:17:14 PM PDT 23
Peak memory 201468 kb
Host smart-81c0a18c-8435-44b5-9ba1-782bec3e9f71
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86307060310797077439177964877424282334149181866031886544826451874143592323598 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.86307060310797077439177964877424282334149181866031886544826451
874143592323598
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.99092585778824256567143063493800968252767532369619426051763764986781893143993
Short name T117
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Oct 25 02:14:03 PM PDT 23
Finished Oct 25 02:14:12 PM PDT 23
Peak memory 201300 kb
Host smart-e1113b70-3812-4e2f-ad51-54f9737c8e8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99092585778824256567143063493800968252767532369619426051763764986781893143993 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.990925857788242565671430634938009682527675323696194260517637
64986781893143993
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.50249024530884350661797381383017296606009120468433583066804491660132133076433
Short name T31
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201216 kb
Host smart-6146904c-f4e3-47ec-9bf4-36fbf7fdb36b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50249024530884350661797381383017296606009120468433583066804491660132133076433 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.5024902453088435066179738138301729660600912046843358306680449166
0132133076433
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.24642358382570246915380477887852188518379067771424229022757210525814524757634
Short name T592
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 25 02:14:13 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201244 kb
Host smart-aeb57949-eec0-432d-8c7e-66d31d40541c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24642358382570246915380477887852188518379067771424229022757210525814524757634 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.24642358382570246915380477887852188518379067771424229022757210525814524757634
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.80960233628437536320071913429947757734050718991883131478650158606131783210431
Short name T349
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Oct 25 02:14:15 PM PDT 23
Finished Oct 25 02:14:20 PM PDT 23
Peak memory 201292 kb
Host smart-625c9c09-6ced-47f2-98f6-e5b5eebd058c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80960233628437536320071913429947757734050718991883131478650158606131783210431 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.80960233628437536320071913429947757734050718991883131478650158606131783210431
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.84803547404874557249175851741804214591387933673466072895280873277722539440315
Short name T553
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:14:35 PM PDT 23
Finished Oct 25 02:14:39 PM PDT 23
Peak memory 201160 kb
Host smart-cdb617df-b8e4-4eda-840e-73fe8ba9be70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84803547404874557249175851741804214591387933673466072895280873277722539440315 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.84803547404874557249175851741804214591387933673466072895280873277722539440315
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1539843848519371152857386520008958818106745665734477751162669614335465088022
Short name T301
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Oct 25 02:14:33 PM PDT 23
Finished Oct 25 02:14:38 PM PDT 23
Peak memory 201204 kb
Host smart-1b1dd996-f3e8-4039-8012-bba3151c95af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539843848519371152857386520008958818106745665734477751162669614335465088022 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1539843848519371152857386520008958818106745665734477751162669614335465088022
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.106842902000180892037772953100079619417235787885366414158679840140816752421978
Short name T240
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 25 02:14:14 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201164 kb
Host smart-da1e0ebf-afad-4f74-813c-da1df948c305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106842902000180892037772953100079619417235787885366414158679840140816752421978 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 29.sysrst_ctrl_smoke.106842902000180892037772953100079619417235787885366414158679840140816752421978
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.85362802829290609535437814468933271030211476841744468416915640984548897716102
Short name T433
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.98 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:16:20 PM PDT 23
Peak memory 201520 kb
Host smart-8be0aec4-df82-4d20-8622-9eff65ea67fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85362802829290609535437814468933271030211476841744468416915640984548897716102 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.85362802829290609535437814468933271030211476841744468416915640984548897716102
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.109573808098436485940451032377863670617107918393110809877257022485293001847995
Short name T128
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201088 kb
Host smart-de101af3-f902-4248-b1e4-2c1fd9994708
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109573808098436485940451032377863670617107918393110809877257022485293001847995 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.10957380809843648594045103237786367061710791839311080987725
7022485293001847995
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.32396506557382972544256508214355334479741813298631493452393253480005471601403
Short name T160
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 25 02:12:33 PM PDT 23
Finished Oct 25 02:12:37 PM PDT 23
Peak memory 201172 kb
Host smart-cfc56be8-e13c-40f3-9d9a-0817d5dbc31b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396506557382972544256508214355334479741813298631493452393253480005471601403 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.32396506557382972544256508214355334479741813298631493452393253480005471601403
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.59391337731421082265451062232780394497820560978240653730868477096836056146125
Short name T643
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.39 seconds
Started Oct 25 02:13:00 PM PDT 23
Finished Oct 25 02:13:06 PM PDT 23
Peak memory 201184 kb
Host smart-30b84389-fd87-4272-bab8-3352b52204d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59391337731421082265451062232780394497820560978240653730868477096836056146125 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.59391337731421082265451062232780394497820560978240653730868477096836056146125
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.80823460640484731644284951839280883916125138871679138897805626722937375833838
Short name T477
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.36 seconds
Started Oct 25 02:13:16 PM PDT 23
Finished Oct 25 02:16:19 PM PDT 23
Peak memory 201496 kb
Host smart-449ec27a-5004-43fc-a150-44a8a9a843d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80823460640484731644284951839280883916125138871679138897805626722937375833838 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.808234606404847316442849518392808839161251388716791388978056267
22937375833838
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.22566618503977326334778760823475877762301106045779221274196030605386259959333
Short name T546
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.31 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:13:00 PM PDT 23
Peak memory 201140 kb
Host smart-543da2cb-0468-4a55-974c-85eede05484f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22566618503977326334778760823475877762301106045779221274196030605386259959333 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.22566618503977326334778760823475877762301106045779221274196030605386259959333
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.78718224954424540976551157860355804958053808530764801605819034597214377631015
Short name T113
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.4 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:13:04 PM PDT 23
Peak memory 201332 kb
Host smart-678fbf0c-1585-4efb-bae0-c07a1483bddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78718224954424540976551157860355804958053808530764801605819034597214377631015 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.78718224954424540976551157860355804958053808530764801
605819034597214377631015
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.70735834402667129164886153969837044286644217072781090816688388845303758859146
Short name T578
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 25 02:12:56 PM PDT 23
Finished Oct 25 02:13:03 PM PDT 23
Peak memory 201164 kb
Host smart-92004ab3-4c05-4bc0-bcc8-04b8cb780eaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70735834402667129164886153969837044286644217072781090816688388845303758859146 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.7073583440266712916488615396983704428664421707278109081668838
8845303758859146
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.45626943125877768548726649191849401951325700385532105630055932038416756673855
Short name T214
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201160 kb
Host smart-4d0d131d-48c0-46e3-8e50-1b406f860779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45626943125877768548726649191849401951325700385532105630055932038416756673855 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.45626943125877768548726649191849401951325700385532105630055932038416756673855
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.101550629959532758155821065970119576856361092338978593385495217793919683002298
Short name T322
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Oct 25 02:13:00 PM PDT 23
Finished Oct 25 02:13:06 PM PDT 23
Peak memory 201124 kb
Host smart-71aa1001-cea0-464e-8979-dcf75f6229da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101550629959532758155821065970119576856361092338978593385495217793919683002298 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.101550629959532758155821065970119576856361092338978593385495217793919683002298
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.78779096689609194205610179704146990038480228047368199193974018548439303564587
Short name T586
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Oct 25 02:13:00 PM PDT 23
Finished Oct 25 02:13:05 PM PDT 23
Peak memory 201268 kb
Host smart-17c50b10-8ac2-403d-ba73-8a62faca2d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78779096689609194205610179704146990038480228047368199193974018548439303564587 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.78779096689609194205610179704146990038480228047368199193974018548439303564587
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.51737856929526255915654296366200404421686629016446352545491890993249791135657
Short name T193
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:13:03 PM PDT 23
Peak memory 201180 kb
Host smart-38f7b042-2e87-4f7c-a056-e8680f88df24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51737856929526255915654296366200404421686629016446352545491890993249791135657 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.51737856929526255915654296366200404421686629016446352545491890993249791135657
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.65548491601672975213949021478958807303152782201433988183340831328611407714792
Short name T611
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:12:59 PM PDT 23
Peak memory 201272 kb
Host smart-8454a93c-e3b4-414c-b312-94df76383b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65548491601672975213949021478958807303152782201433988183340831328611407714792 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.65548491601672975213949021478958807303152782201433988183340831328611407714792
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.102198715273754382832732594136295451998044359251515990206582545866338372131008
Short name T139
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.79 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:14:17 PM PDT 23
Peak memory 221608 kb
Host smart-b5093979-0899-42e8-9f3d-f35a53f0e0e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102198715273754382832732594136295451998044359251515990206582545866338372131008 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.102198715273754382832732594136295451998044359251515990206582545866338372131008
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.113733141120355991301507993425942653628797034285085965786994392777753179666368
Short name T464
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:13:04 PM PDT 23
Peak memory 201264 kb
Host smart-a27aac26-d43b-4a6e-a368-e52c6b4008aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113733141120355991301507993425942653628797034285085965786994392777753179666368 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.sysrst_ctrl_smoke.113733141120355991301507993425942653628797034285085965786994392777753179666368
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.102015671119865057131791878655715435554953293073967613950034077322953033415034
Short name T622
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.55 seconds
Started Oct 25 02:12:57 PM PDT 23
Finished Oct 25 02:15:14 PM PDT 23
Peak memory 201488 kb
Host smart-100e8449-b1b3-486b-bb48-c7a03e68f780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102015671119865057131791878655715435554953293073967613950034077322953033415034 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.102015671119865057131791878655715435554953293073967613950034077322953033415034
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.76665931358035576678425951847604205577666184482746064480184514311253515733726
Short name T353
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:13:01 PM PDT 23
Finished Oct 25 02:13:06 PM PDT 23
Peak memory 201100 kb
Host smart-32c65c2a-e5e7-4755-91e1-0eb3187f73aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76665931358035576678425951847604205577666184482746064480184514311253515733726 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.7666593135803557667842595184760420557766618448274606448018451
4311253515733726
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.53721020269428120006146663852400859691379886237458673898160751564296041797737
Short name T398
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201116 kb
Host smart-7e120484-50ba-45db-832f-071301bbc5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53721020269428120006146663852400859691379886237458673898160751564296041797737 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.53721020269428120006146663852400859691379886237458673898160751564296041797737
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.91071333714286151774741014227974367345864856822700622849813482106971599479883
Short name T100
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201372 kb
Host smart-1a4c2360-2f4c-48cf-9804-a9e2dde9785a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91071333714286151774741014227974367345864856822700622849813482106971599479883 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.91071333714286151774741014227974367345864856822700622849813482106971599479883
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.65812357495233772087179027728421095591670820393730115889471133424085967294388
Short name T563
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.51 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:17:10 PM PDT 23
Peak memory 201540 kb
Host smart-ee27b895-f622-4467-9871-5d49c09aebd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65812357495233772087179027728421095591670820393730115889471133424085967294388 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.65812357495233772087179027728421095591670820393730115889471133
424085967294388
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.66755594618343275425293222659400848910048875480489746192350645762074468778473
Short name T305
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201340 kb
Host smart-40b6075d-3d69-41fc-90c9-ac2bc284188f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66755594618343275425293222659400848910048875480489746192350645762074468778473 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.667555946183432754252932226594008489100488754804897461923506
45762074468778473
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.19798345635069769299856596600512400932723502805269391273725985392189576477719
Short name T580
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:14:17 PM PDT 23
Peak memory 201188 kb
Host smart-fdfba51d-843d-4fc6-8636-a90ad63a3081
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19798345635069769299856596600512400932723502805269391273725985392189576477719 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.1979834563506976929985659660051240093272350280526939127372598539
2189576477719
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.27157712978290307027857483719020818340811412023071643161151856085257337938790
Short name T161
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201240 kb
Host smart-a75b6675-73ee-4ade-bdcd-22b325a63f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27157712978290307027857483719020818340811412023071643161151856085257337938790 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.27157712978290307027857483719020818340811412023071643161151856085257337938790
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.56348482291777950606871999785900614894547381347951874057123345463033965311597
Short name T105
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.85 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201276 kb
Host smart-6208f29d-7bb2-4ef2-9f3b-19855151c81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56348482291777950606871999785900614894547381347951874057123345463033965311597 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.56348482291777950606871999785900614894547381347951874057123345463033965311597
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.112013313107847321240558375854276029766086108323830159592831024535709787435511
Short name T416
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201336 kb
Host smart-b5bc072a-835c-4588-8a82-db9d952c90d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112013313107847321240558375854276029766086108323830159592831024535709787435511 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.112013313107847321240558375854276029766086108323830159592831024535709787435511
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.52667687510020439647791162509217125532966158947064148827127954935585798154396
Short name T297
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201272 kb
Host smart-aaabbc82-dded-433b-928a-73d7a0e6c53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52667687510020439647791162509217125532966158947064148827127954935585798154396 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.52667687510020439647791162509217125532966158947064148827127954935585798154396
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.24935146010794147810284622998139469140705622995065947162690501909881613015771
Short name T401
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.75 seconds
Started Oct 25 02:14:00 PM PDT 23
Finished Oct 25 02:14:04 PM PDT 23
Peak memory 201148 kb
Host smart-d9290f44-02f2-4288-a483-47ff7d8fadda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24935146010794147810284622998139469140705622995065947162690501909881613015771 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sysrst_ctrl_smoke.24935146010794147810284622998139469140705622995065947162690501909881613015771
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.3825166317602229094301488919004183575570547837420374944886416159441737721090
Short name T510
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.46 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:16:20 PM PDT 23
Peak memory 201532 kb
Host smart-53f0c7e3-c0d8-474e-82b5-413866430d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825166317602229094301488919004183575570547837420374944886416159441737721090 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.3825166317602229094301488919004183575570547837420374944886416159441737721090
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.102052375941162182731118982305152127735951273623767376519944621772254573012799
Short name T579
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201248 kb
Host smart-a826dafe-6c90-4c61-acec-73dd856cc1c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102052375941162182731118982305152127735951273623767376519944621772254573012799 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.10205237594116218273111898230515212773595127362376737651994
4621772254573012799
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.91080794088081792898429497943232181142538565174332095395598659181703359175061
Short name T294
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:14:30 PM PDT 23
Finished Oct 25 02:14:34 PM PDT 23
Peak memory 201284 kb
Host smart-f6e5b71e-4829-4ea6-b430-bbd746fcb84a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91080794088081792898429497943232181142538565174332095395598659181703359175061 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.91080794088081792898429497943232181142538565174332095395598659181703359175061
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.75999772515450972731483657081496151285309736686924586954919485366287813125393
Short name T97
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 25 02:14:09 PM PDT 23
Finished Oct 25 02:14:15 PM PDT 23
Peak memory 201252 kb
Host smart-30689d9b-b62d-4b83-b7f7-e2663f941ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75999772515450972731483657081496151285309736686924586954919485366287813125393 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.75999772515450972731483657081496151285309736686924586954919485366287813125393
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.63647663848220803336183780502780878403155360352036747632063957654339738122207
Short name T629
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.79 seconds
Started Oct 25 02:14:17 PM PDT 23
Finished Oct 25 02:17:19 PM PDT 23
Peak memory 201344 kb
Host smart-706d9fef-f026-4c17-bfbb-66e118e0993b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63647663848220803336183780502780878403155360352036747632063957654339738122207 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.63647663848220803336183780502780878403155360352036747632063957
654339738122207
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.77102642859654140656258138704986916654936347788742103696261460542404194612399
Short name T231
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Oct 25 02:14:11 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201220 kb
Host smart-46f94a78-4a46-4819-9b1f-d3e604163e88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77102642859654140656258138704986916654936347788742103696261460542404194612399 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.771026428596541406562581387049869166549363477887421036962614
60542404194612399
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.79064440235066447448143100476212356700160298991411879233646170901192786256781
Short name T133
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:12 PM PDT 23
Peak memory 201232 kb
Host smart-eb6633b9-99d0-490e-9c65-daef0fd38d6e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79064440235066447448143100476212356700160298991411879233646170901192786256781 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.7906444023506644744814310047621235670016029899141187923364617090
1192786256781
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.51043930255155754851231165099055164727971053333861905560059428638496753292573
Short name T576
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.6 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:12 PM PDT 23
Peak memory 201232 kb
Host smart-961c0fcf-7eba-4b26-8aff-f14c46983790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51043930255155754851231165099055164727971053333861905560059428638496753292573 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.51043930255155754851231165099055164727971053333861905560059428638496753292573
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.42817719220410459179602409222648987952511708556078998497485668593756273584661
Short name T289
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:11 PM PDT 23
Peak memory 201180 kb
Host smart-7f46c5ab-71fd-4817-b75a-7fb0117e4e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42817719220410459179602409222648987952511708556078998497485668593756273584661 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.42817719220410459179602409222648987952511708556078998497485668593756273584661
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.112083779819187925496199413833045696841976753930076525164509137302515655353095
Short name T220
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:14:12 PM PDT 23
Peak memory 201196 kb
Host smart-d5c2acad-93c5-49c8-9ea4-98eec10b1590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112083779819187925496199413833045696841976753930076525164509137302515655353095 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.112083779819187925496199413833045696841976753930076525164509137302515655353095
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.46480982673165770216800189558952385282304862880417069137755283219945277468594
Short name T275
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201196 kb
Host smart-2b5fe152-366d-4dbf-9f45-6a4ce2def411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46480982673165770216800189558952385282304862880417069137755283219945277468594 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.46480982673165770216800189558952385282304862880417069137755283219945277468594
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.32390894024909365244046779144151107534715513186006875949874960708493033342841
Short name T323
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.88 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 200980 kb
Host smart-cceefeac-6963-4d16-a5f6-f14b4807ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32390894024909365244046779144151107534715513186006875949874960708493033342841 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_smoke.32390894024909365244046779144151107534715513186006875949874960708493033342841
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.84277032146874223829909264909383300426698427172712808807590165700634769855047
Short name T268
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.17 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:16:26 PM PDT 23
Peak memory 201400 kb
Host smart-93e12af4-eb49-4904-b583-16554f290991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84277032146874223829909264909383300426698427172712808807590165700634769855047 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.84277032146874223829909264909383300426698427172712808807590165700634769855047
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.44293820029840839530369594194410349475687683328208844101530586711156639471490
Short name T39
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201312 kb
Host smart-48d4818d-e3f2-4792-9583-f1360000763c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44293820029840839530369594194410349475687683328208844101530586711156639471490 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.442938200298408395303695941944103494756876833282088441015305
86711156639471490
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.254710612608517384011588315388043341328631577026346223395603896224205062214
Short name T332
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201332 kb
Host smart-6d1e39a0-f2f8-48cb-a72a-d9fe667a1522
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254710612608517384011588315388043341328631577026346223395603896224205062214 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.254710612608517384011588315388043341328631577026346223395603896224205062214
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.83610682413525237384198279873342986510017821434959757219909787806148617889017
Short name T549
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.39 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:34 PM PDT 23
Peak memory 201304 kb
Host smart-d68b55a3-8031-4c03-afcc-6c62dc8e98af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83610682413525237384198279873342986510017821434959757219909787806148617889017 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.83610682413525237384198279873342986510017821434959757219909787806148617889017
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.106906862211579860849233383663402039884003097866221053429715517680248591891950
Short name T636
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.78 seconds
Started Oct 25 02:14:29 PM PDT 23
Finished Oct 25 02:17:32 PM PDT 23
Peak memory 201464 kb
Host smart-cd514e3d-8617-4017-b970-57e6af07cb28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106906862211579860849233383663402039884003097866221053429715517680248591891950 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.1069068622115798608492333836634020398840030978662210534297155
17680248591891950
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.51280309234425786521304075366702431710865258716207385277955885826691058878099
Short name T338
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.27 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:36 PM PDT 23
Peak memory 201172 kb
Host smart-d51d6583-dbd0-42a4-a94f-473494bbe136
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51280309234425786521304075366702431710865258716207385277955885826691058878099 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.512803092344257865213040753667024317108652587162073852779558
85826691058878099
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.113384053907107871926476513210306594675121832752439747354609690463962617048018
Short name T23
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.17 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:13 PM PDT 23
Peak memory 201200 kb
Host smart-06c0dde3-c3a3-44a6-83ce-7412f842d10a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113384053907107871926476513210306594675121832752439747354609690463962617048018 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.113384053907107871926476513210306594675121832752439747354609690
463962617048018
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.8855896043706333846216642135703384431360056791434782728529962056638068861644
Short name T287
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Oct 25 02:14:14 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201240 kb
Host smart-3505e54b-f425-4363-bac6-4efbbce0cc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8855896043706333846216642135703384431360056791434782728529962056638068861644 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.8855896043706333846216642135703384431360056791434782728529962056638068861644
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.40427323027577279765767824267806037406974208598166248568415300777703698773375
Short name T583
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201252 kb
Host smart-ff2ab243-cbc3-44e0-af9d-38aed06661ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40427323027577279765767824267806037406974208598166248568415300777703698773375 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.40427323027577279765767824267806037406974208598166248568415300777703698773375
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.43076837463358123906877716327423327293359266394760212706580732656614878687370
Short name T359
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:14:15 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201220 kb
Host smart-251e0525-6f0c-4779-91b1-9b634bf81fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43076837463358123906877716327423327293359266394760212706580732656614878687370 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.43076837463358123906877716327423327293359266394760212706580732656614878687370
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.51456251546491292639903294048844621512725089045243298816782884020461730657594
Short name T63
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201228 kb
Host smart-403d4cfe-7846-47d4-a44a-9be692fc28f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51456251546491292639903294048844621512725089045243298816782884020461730657594 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.51456251546491292639903294048844621512725089045243298816782884020461730657594
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.35246156268660910445222472218215499755709452636009852029114986438290824086034
Short name T602
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 25 02:14:14 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201172 kb
Host smart-bb41fb5a-6db9-407c-a032-b28bc48104f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35246156268660910445222472218215499755709452636009852029114986438290824086034 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sysrst_ctrl_smoke.35246156268660910445222472218215499755709452636009852029114986438290824086034
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.68632089900320976208513322451698099192361737948236469177713021745230929826122
Short name T273
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.01 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:16:40 PM PDT 23
Peak memory 201528 kb
Host smart-299dc55b-f9f1-401d-875d-c18d4b344ffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68632089900320976208513322451698099192361737948236469177713021745230929826122 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.68632089900320976208513322451698099192361737948236469177713021745230929826122
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.42223686875266220327030933504758963615504103510450594644565980942932916696087
Short name T511
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201220 kb
Host smart-f0b96b80-c29d-4c50-b1e8-49c631126f26
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223686875266220327030933504758963615504103510450594644565980942932916696087 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.422236868752662203270309335047589636155041035104505946445659
80942932916696087
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.95002354303497768047028448248353595382113822156617965112843478185041092684376
Short name T550
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Oct 25 02:14:05 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201260 kb
Host smart-c23ef9c2-4580-4f41-b326-9c368e699fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95002354303497768047028448248353595382113822156617965112843478185041092684376 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.95002354303497768047028448248353595382113822156617965112843478185041092684376
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.62979957067909119540768983980872105573735340726962364801552754424885400294223
Short name T498
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201284 kb
Host smart-741e906b-9809-4e50-bd49-1112411f9e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62979957067909119540768983980872105573735340726962364801552754424885400294223 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.62979957067909119540768983980872105573735340726962364801552754424885400294223
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.61764925516077424866523160097953488137542786725955869779594992802633977848388
Short name T202
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.67 seconds
Started Oct 25 02:14:09 PM PDT 23
Finished Oct 25 02:17:11 PM PDT 23
Peak memory 201456 kb
Host smart-9df11b7f-f64c-4145-9450-4f843d117c90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61764925516077424866523160097953488137542786725955869779594992802633977848388 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.61764925516077424866523160097953488137542786725955869779594992
802633977848388
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.46720816717715867811605957772197126406930752753527105554507330505162872739698
Short name T212
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.31 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:14 PM PDT 23
Peak memory 201132 kb
Host smart-cb27e767-c719-4f8d-bee0-09e0efb88589
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46720816717715867811605957772197126406930752753527105554507330505162872739698 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.467208167177158678116059577721971264069307527535271055545073
30505162872739698
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.109900849681885384031069183042051610794423959307954254223385446501253684853808
Short name T210
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.36 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201160 kb
Host smart-88db17b7-7398-4e2f-9c65-9809e218df01
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109900849681885384031069183042051610794423959307954254223385446501253684853808 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.109900849681885384031069183042051610794423959307954254223385446
501253684853808
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.107376477275124443517527250584966817264257481545273829659530667915364925025562
Short name T283
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201068 kb
Host smart-69c6ca6e-fd60-489e-b651-c62a735b5e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107376477275124443517527250584966817264257481545273829659530667915364925025562 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.107376477275124443517527250584966817264257481545273829659530667915364925025562
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.35149109130578744001663603730560598545126688058569444877614633484639464246067
Short name T264
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.73 seconds
Started Oct 25 02:14:25 PM PDT 23
Finished Oct 25 02:14:30 PM PDT 23
Peak memory 201296 kb
Host smart-1d58d557-e465-43b1-a2e5-221207967c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35149109130578744001663603730560598545126688058569444877614633484639464246067 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.35149109130578744001663603730560598545126688058569444877614633484639464246067
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.89471165311807699874897384855099800017932093394127468582225068772893458007046
Short name T584
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Oct 25 02:14:13 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201212 kb
Host smart-63632738-6e0d-4eed-872e-9ed4982f8981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89471165311807699874897384855099800017932093394127468582225068772893458007046 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.89471165311807699874897384855099800017932093394127468582225068772893458007046
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.75351831454153457759882636496724785328072280402874893573775322818239611062761
Short name T218
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201236 kb
Host smart-ea4fb4c5-49f7-4d07-a01a-3e5f29ed3d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75351831454153457759882636496724785328072280402874893573775322818239611062761 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.75351831454153457759882636496724785328072280402874893573775322818239611062761
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.17896360441009382968791902349443423119511005253860481268656630310032774277711
Short name T644
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:14:17 PM PDT 23
Peak memory 201148 kb
Host smart-76fe4437-8ba7-4f6a-a17d-b7bc52310d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17896360441009382968791902349443423119511005253860481268656630310032774277711 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_smoke.17896360441009382968791902349443423119511005253860481268656630310032774277711
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.64901761850526781642593775510955993581768153969917114317866480462108614875711
Short name T467
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.78 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:16:22 PM PDT 23
Peak memory 201516 kb
Host smart-a62771ab-1c2e-470e-ae9b-90052476075e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64901761850526781642593775510955993581768153969917114317866480462108614875711 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.64901761850526781642593775510955993581768153969917114317866480462108614875711
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.20028383597260061685971827362337423333639125619373736606449131108769527079518
Short name T394
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:09 PM PDT 23
Peak memory 201256 kb
Host smart-81ba192b-6491-4b0f-8cc7-93e8af9edfac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20028383597260061685971827362337423333639125619373736606449131108769527079518 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.200283835972600616859718273623374233336391256193737366064491
31108769527079518
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.88358734907960218640992972190910740199884472230052708859755407522846088402301
Short name T341
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:14:11 PM PDT 23
Finished Oct 25 02:14:15 PM PDT 23
Peak memory 201228 kb
Host smart-8b171c41-6ddb-4936-9a26-98a62130b06d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88358734907960218640992972190910740199884472230052708859755407522846088402301 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.88358734907960218640992972190910740199884472230052708859755407522846088402301
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.100595399045823699820049219782590182194131996131490997166404622246656357401474
Short name T430
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:13 PM PDT 23
Peak memory 201348 kb
Host smart-4bbe1b7f-a891-4450-a1e2-1d08af9b9ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100595399045823699820049219782590182194131996131490997166404622246656357401474 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.100595399045823699820049219782590182194131996131490997166404622246656357401474
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.86119180803266781284206916416199948042211677006617055592160465299296420918774
Short name T266
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.86 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:17:12 PM PDT 23
Peak memory 201560 kb
Host smart-a0a520b3-9167-49f8-89bc-206e0cb30e64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86119180803266781284206916416199948042211677006617055592160465299296420918774 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.86119180803266781284206916416199948042211677006617055592160465
299296420918774
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.41667676884126326345027797707493841745468285429183361575123727929579433641572
Short name T293
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:15 PM PDT 23
Peak memory 201288 kb
Host smart-3d9eb52e-03c6-4959-aa00-52027edd8da2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667676884126326345027797707493841745468285429183361575123727929579433641572 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.416676768841263263450277977074938417454682854291833615751237
27929579433641572
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.100304273275317505088253543578727241529437411618331618368397055211072121082081
Short name T590
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Oct 25 02:14:09 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201228 kb
Host smart-9167ac78-3436-473e-bb69-ae3ddd9e7210
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100304273275317505088253543578727241529437411618331618368397055211072121082081 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.100304273275317505088253543578727241529437411618331618368397055
211072121082081
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.14043172257213021034431114503711106392164843813585744286749860673072711806429
Short name T256
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:14:13 PM PDT 23
Peak memory 201276 kb
Host smart-83b231ca-0e63-48ec-b38e-056c14a3fb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14043172257213021034431114503711106392164843813585744286749860673072711806429 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.14043172257213021034431114503711106392164843813585744286749860673072711806429
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.84770202335914626801036547683736476255103617169865314219210099055435720583690
Short name T648
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:13 PM PDT 23
Peak memory 201264 kb
Host smart-25ffb121-c68f-4d44-a315-54425b2c9970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84770202335914626801036547683736476255103617169865314219210099055435720583690 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.84770202335914626801036547683736476255103617169865314219210099055435720583690
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.101070859025280831636811557537332227534728285169774656084545373224627167988313
Short name T650
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201108 kb
Host smart-52f2ae2f-7aa4-4273-ad78-607dfeece5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101070859025280831636811557537332227534728285169774656084545373224627167988313 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.101070859025280831636811557537332227534728285169774656084545373224627167988313
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.88020852170355328708521255539879534508981506196044835502618216646094500147218
Short name T170
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Oct 25 02:14:09 PM PDT 23
Finished Oct 25 02:14:14 PM PDT 23
Peak memory 201228 kb
Host smart-a9766ff6-42eb-4f90-b0da-e57839c9faa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88020852170355328708521255539879534508981506196044835502618216646094500147218 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.88020852170355328708521255539879534508981506196044835502618216646094500147218
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.55859509957351383307240775139620949840102377663220476387358949162081414652578
Short name T299
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 25 02:14:04 PM PDT 23
Finished Oct 25 02:14:08 PM PDT 23
Peak memory 201188 kb
Host smart-05c28732-af61-44f9-8ae1-92ad3d77e60b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55859509957351383307240775139620949840102377663220476387358949162081414652578 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sysrst_ctrl_smoke.55859509957351383307240775139620949840102377663220476387358949162081414652578
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.34545952073421137786500494591099763133017704168437642707398617923923574444864
Short name T442
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.99 seconds
Started Oct 25 02:14:08 PM PDT 23
Finished Oct 25 02:16:24 PM PDT 23
Peak memory 201564 kb
Host smart-bc52f906-f3c4-474f-9bc3-8bad8c3e8a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34545952073421137786500494591099763133017704168437642707398617923923574444864 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.34545952073421137786500494591099763133017704168437642707398617923923574444864
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.14152254169296970124630270323271576694197848679777346439243395120143594645787
Short name T248
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:14:12 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201312 kb
Host smart-9d0d8c6b-9061-4d9b-8860-ef58c1247957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14152254169296970124630270323271576694197848679777346439243395120143594645787 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.141522541692969701246302703232715766941978486797773464392433
95120143594645787
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.56225205732718237758763660692936508346658678796387897263930316393899150721063
Short name T46
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:14:13 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201232 kb
Host smart-3ce4de8a-70bb-4187-898e-cffbe2d646b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56225205732718237758763660692936508346658678796387897263930316393899150721063 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.56225205732718237758763660692936508346658678796387897263930316393899150721063
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.72028993206093910353871451905074096034081261248174930477602486813867616512096
Short name T270
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.51 seconds
Started Oct 25 02:14:10 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201268 kb
Host smart-6cfa48af-20e1-4b43-8689-1c832eebdc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72028993206093910353871451905074096034081261248174930477602486813867616512096 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.72028993206093910353871451905074096034081261248174930477602486813867616512096
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.27216124235880797020052618908818094978493797804101640852613395549853141370109
Short name T520
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.02 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:17:32 PM PDT 23
Peak memory 201464 kb
Host smart-afd5261e-4597-4c36-8525-6b9da2274d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27216124235880797020052618908818094978493797804101640852613395549853141370109 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.27216124235880797020052618908818094978493797804101640852613395
549853141370109
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.109005899214611527685210716136239238115808788906536606929731838895515755532586
Short name T120
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 25 02:14:16 PM PDT 23
Finished Oct 25 02:14:24 PM PDT 23
Peak memory 201136 kb
Host smart-1bb8ba53-4a0e-4371-aaa2-0422a84e8a48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109005899214611527685210716136239238115808788906536606929731838895515755532586 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.10900589921461152768521071613623923811580878890653660692973
1838895515755532586
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.26315020297798473588519541556139708896319470655201237728773933027083793212832
Short name T371
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 25 02:14:11 PM PDT 23
Finished Oct 25 02:14:18 PM PDT 23
Peak memory 201312 kb
Host smart-1bbdb944-aad2-48aa-bc7d-714e7969a314
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26315020297798473588519541556139708896319470655201237728773933027083793212832 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.2631502029779847358851954155613970889631947065520123772877393302
7083793212832
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.35551993556802857748189815035168794971479006626292610521902064352016316840927
Short name T356
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 25 02:14:07 PM PDT 23
Finished Oct 25 02:14:12 PM PDT 23
Peak memory 201228 kb
Host smart-1459e786-d1bd-4350-9870-7c0418ac0aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35551993556802857748189815035168794971479006626292610521902064352016316840927 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.35551993556802857748189815035168794971479006626292610521902064352016316840927
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.20347284491378130227147848062936480848571627121522205391071499455524045860568
Short name T347
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 25 02:14:11 PM PDT 23
Finished Oct 25 02:14:17 PM PDT 23
Peak memory 201356 kb
Host smart-506943c1-4d0d-4cb4-af5b-21da4521a169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20347284491378130227147848062936480848571627121522205391071499455524045860568 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.20347284491378130227147848062936480848571627121522205391071499455524045860568
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.112442096683000324675815899821377491714443931944519377485309588984479801269670
Short name T559
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.86 seconds
Started Oct 25 02:14:06 PM PDT 23
Finished Oct 25 02:14:10 PM PDT 23
Peak memory 201200 kb
Host smart-2605efb6-5f53-45ad-96df-1d7ece897de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112442096683000324675815899821377491714443931944519377485309588984479801269670 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.112442096683000324675815899821377491714443931944519377485309588984479801269670
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.17867458841927278431400292533240573209921009415966778166384785032913579150946
Short name T122
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 25 02:14:34 PM PDT 23
Finished Oct 25 02:14:39 PM PDT 23
Peak memory 201080 kb
Host smart-5d61cdc9-007d-4170-a124-0e3cf31e45c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17867458841927278431400292533240573209921009415966778166384785032913579150946 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.17867458841927278431400292533240573209921009415966778166384785032913579150946
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.28270680222002183034344377504978496762704472293301748000432179523136338005050
Short name T319
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Oct 25 02:14:15 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201192 kb
Host smart-77943254-5e9f-41f6-a7ba-5a5760ab2471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28270680222002183034344377504978496762704472293301748000432179523136338005050 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_smoke.28270680222002183034344377504978496762704472293301748000432179523136338005050
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.16847039815623872483881717025759927950850570743898946672912843475850941936406
Short name T131
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.53 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:16:41 PM PDT 23
Peak memory 201540 kb
Host smart-fe4702d9-4a0a-4d1b-83ff-4634e5cdf2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847039815623872483881717025759927950850570743898946672912843475850941936406 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.16847039815623872483881717025759927950850570743898946672912843475850941936406
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.93454933060322257271495697792021207732860143803181417943849863776316512644699
Short name T47
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:14:11 PM PDT 23
Finished Oct 25 02:14:16 PM PDT 23
Peak memory 201108 kb
Host smart-56a1d9b8-7df5-4ceb-aa95-df33b33a56a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93454933060322257271495697792021207732860143803181417943849863776316512644699 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.934549330603222572714956977920212077328601438031814179438498
63776316512644699
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.69956045748853895739465741648529612988661995723440756650320451000869910678659
Short name T519
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Oct 25 02:14:02 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201232 kb
Host smart-f9a77be7-59c9-4ee6-bb11-a673eda027d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69956045748853895739465741648529612988661995723440756650320451000869910678659 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.69956045748853895739465741648529612988661995723440756650320451000869910678659
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.71973977849302143239286840283252749269188447420359568899316033294049405538130
Short name T208
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201284 kb
Host smart-0f7e9572-30e2-407a-a5a5-2457ca05481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71973977849302143239286840283252749269188447420359568899316033294049405538130 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.71973977849302143239286840283252749269188447420359568899316033294049405538130
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.77389637048966884855459244691486690708189226141274644124457794652756335596380
Short name T339
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.79 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:17:30 PM PDT 23
Peak memory 201448 kb
Host smart-27d70075-845e-4fce-bc1f-fbda2874230f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77389637048966884855459244691486690708189226141274644124457794652756335596380 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.77389637048966884855459244691486690708189226141274644124457794
652756335596380
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.82102054002874216327007626036579373514138791366330962723344802527593019376673
Short name T540
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.28 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:36 PM PDT 23
Peak memory 201288 kb
Host smart-124ea26d-040c-43e5-b5dc-c3fe8c06866d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82102054002874216327007626036579373514138791366330962723344802527593019376673 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.821020540028742163270076260365793735141387913663309627233448
02527593019376673
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.88266652445818054348277545365881196778649801881271422636532185260882235255882
Short name T603
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 25 02:14:13 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201224 kb
Host smart-857375a0-7f6c-4842-b056-f7c66eca15cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88266652445818054348277545365881196778649801881271422636532185260882235255882 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.8826665244581805434827754536588119677864980188127142263653218526
0882235255882
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.34554528027823174877943926265080613299411853222772305503974294931371495847971
Short name T607
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 25 02:14:00 PM PDT 23
Finished Oct 25 02:14:05 PM PDT 23
Peak memory 201224 kb
Host smart-3a3dd4c4-76c3-48dd-838d-d8f5141f6a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34554528027823174877943926265080613299411853222772305503974294931371495847971 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.34554528027823174877943926265080613299411853222772305503974294931371495847971
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.20161396665482194068284482989426808339802332794479017427162744367653085945429
Short name T355
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Oct 25 02:14:14 PM PDT 23
Finished Oct 25 02:14:19 PM PDT 23
Peak memory 201292 kb
Host smart-4cbe8413-b28a-474f-981c-b420883e385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20161396665482194068284482989426808339802332794479017427162744367653085945429 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.20161396665482194068284482989426808339802332794479017427162744367653085945429
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.94479375456481877615472305307608267394622873511812665424905187229398983539965
Short name T393
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201280 kb
Host smart-4fc6e1d0-b0a5-41f7-84a7-7166c416db48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94479375456481877615472305307608267394622873511812665424905187229398983539965 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.94479375456481877615472305307608267394622873511812665424905187229398983539965
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.36712615739755976196154011590489977642225224915667547208427588162912209499158
Short name T407
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.5 seconds
Started Oct 25 02:14:01 PM PDT 23
Finished Oct 25 02:14:07 PM PDT 23
Peak memory 201228 kb
Host smart-fb747d86-2e4e-481b-bde9-5c301a00bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36712615739755976196154011590489977642225224915667547208427588162912209499158 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.36712615739755976196154011590489977642225224915667547208427588162912209499158
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.8780028913284070123347381528979281558138757111971997283267817329207376284571
Short name T104
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201096 kb
Host smart-15097ee6-1bd8-4705-9875-42c6191c5a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8780028913284070123347381528979281558138757111971997283267817329207376284571 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sysrst_ctrl_smoke.8780028913284070123347381528979281558138757111971997283267817329207376284571
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.91336507839928550977097190856842632487311892001370109525799851865022587760775
Short name T453
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.87 seconds
Started Oct 25 02:14:34 PM PDT 23
Finished Oct 25 02:16:49 PM PDT 23
Peak memory 201476 kb
Host smart-6a1a175d-d591-42a4-afa4-b8eb7153a218
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91336507839928550977097190856842632487311892001370109525799851865022587760775 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.91336507839928550977097190856842632487311892001370109525799851865022587760775
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.22845775481965736023985797733917555760988950379332594292047742934211754401841
Short name T344
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201260 kb
Host smart-1eb538a9-7b6f-4edd-a2d1-2ae4f507bce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22845775481965736023985797733917555760988950379332594292047742934211754401841 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.22845775481965736023985797733917555760988950379332594292047742934211754401841
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.83567230763708936932024296736820422740458509713716717852013649579564882588047
Short name T93
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.38 seconds
Started Oct 25 02:14:31 PM PDT 23
Finished Oct 25 02:14:37 PM PDT 23
Peak memory 201268 kb
Host smart-4b917793-35a7-4ab2-b729-ca2e7d708de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83567230763708936932024296736820422740458509713716717852013649579564882588047 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.83567230763708936932024296736820422740458509713716717852013649579564882588047
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.81473124557729993608565857096769481613589038849847098339409659414742948899634
Short name T24
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.27 seconds
Started Oct 25 02:14:29 PM PDT 23
Finished Oct 25 02:17:31 PM PDT 23
Peak memory 201468 kb
Host smart-9828e2d9-9225-49fc-a032-bc76790d3f7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81473124557729993608565857096769481613589038849847098339409659414742948899634 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.81473124557729993608565857096769481613589038849847098339409659
414742948899634
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.65089952687244807427021421833386958817117651370850000087152904397940244249143
Short name T310
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 25 02:14:25 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201124 kb
Host smart-7d7f19d9-270b-41a6-bab3-0b2a68378430
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65089952687244807427021421833386958817117651370850000087152904397940244249143 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.650899526872448074270214218333869588171176513708500000871529
04397940244249143
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.12390450388412819151004265470430933632226968962760374398683883597629912781054
Short name T422
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201240 kb
Host smart-fa606e27-0d98-4b03-875b-ba4f281cef9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12390450388412819151004265470430933632226968962760374398683883597629912781054 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.1239045038841281915100426547043093363222696896276037439868388359
7629912781054
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.18200105643726004122923221615925391615402480835576050212995952618482734861125
Short name T378
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.57 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201252 kb
Host smart-c1a1ec80-9ebe-43c8-bbb1-9dd7200c1194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18200105643726004122923221615925391615402480835576050212995952618482734861125 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.18200105643726004122923221615925391615402480835576050212995952618482734861125
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.49990807618710621243720405384075948967284736058914376236072031837436393578824
Short name T307
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.72 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201124 kb
Host smart-36eba682-c263-487f-9b8f-7399ab1d9a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49990807618710621243720405384075948967284736058914376236072031837436393578824 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.49990807618710621243720405384075948967284736058914376236072031837436393578824
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.25426108872797676380646974758045224273311587085000714637663263046068971945158
Short name T538
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:14:31 PM PDT 23
Finished Oct 25 02:14:36 PM PDT 23
Peak memory 201188 kb
Host smart-4ea60885-e71a-4d55-b42e-26c7e8f23b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25426108872797676380646974758045224273311587085000714637663263046068971945158 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.25426108872797676380646974758045224273311587085000714637663263046068971945158
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.89036270406616349160041194605083163304248777252913021276353178800096627186592
Short name T247
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.65 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201272 kb
Host smart-21b2b5d1-f3d4-40bd-a8c7-67a7e416656d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89036270406616349160041194605083163304248777252913021276353178800096627186592 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.89036270406616349160041194605083163304248777252913021276353178800096627186592
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.92111875329176230172058183272328663560632949818304960536304227749737700236568
Short name T255
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.75 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201176 kb
Host smart-ec82baaa-a335-4e0c-ad0f-a9d922a5c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92111875329176230172058183272328663560632949818304960536304227749737700236568 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_smoke.92111875329176230172058183272328663560632949818304960536304227749737700236568
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.93939922035759919771703254309176582140811201837302063061405219569109945940526
Short name T25
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.05 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:16:45 PM PDT 23
Peak memory 201512 kb
Host smart-9bc70b2f-1665-40ae-81f9-240a387d3aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93939922035759919771703254309176582140811201837302063061405219569109945940526 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.93939922035759919771703254309176582140811201837302063061405219569109945940526
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.113964948010964585832765063155273760094447104694667062233179025614650027391286
Short name T318
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201160 kb
Host smart-bd3869b2-0c16-4436-bcde-83200c5e3c7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113964948010964585832765063155273760094447104694667062233179025614650027391286 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.11396494801096458583276506315527376009444710469466706223317
9025614650027391286
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.2826123329933098098576113511411490117281110776596670951021856738824442725972
Short name T443
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Oct 25 02:14:31 PM PDT 23
Finished Oct 25 02:14:35 PM PDT 23
Peak memory 201232 kb
Host smart-0749a26a-db91-44fe-ac3e-f006015b2210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826123329933098098576113511411490117281110776596670951021856738824442725972 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.2826123329933098098576113511411490117281110776596670951021856738824442725972
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.12846314841823416702260488455616464102991460820129143588335146020421796725820
Short name T213
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 25 02:14:40 PM PDT 23
Finished Oct 25 02:14:46 PM PDT 23
Peak memory 201060 kb
Host smart-933c8c2b-5b5a-4e2c-ad88-79a796c8a718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12846314841823416702260488455616464102991460820129143588335146020421796725820 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.12846314841823416702260488455616464102991460820129143588335146020421796725820
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.45253990559475060413441909724513781417350794346290365997829780714389725233557
Short name T291
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.39 seconds
Started Oct 25 02:14:29 PM PDT 23
Finished Oct 25 02:17:31 PM PDT 23
Peak memory 201464 kb
Host smart-0d27a02f-8cd0-4333-b682-b5812c15c8e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45253990559475060413441909724513781417350794346290365997829780714389725233557 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.45253990559475060413441909724513781417350794346290365997829780
714389725233557
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.90509863460427039143857611239591863615288984270259275359722598911811251765344
Short name T522
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.29 seconds
Started Oct 25 02:14:30 PM PDT 23
Finished Oct 25 02:14:38 PM PDT 23
Peak memory 201240 kb
Host smart-b4bee904-0789-462c-b5f6-dee15934ff1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90509863460427039143857611239591863615288984270259275359722598911811251765344 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.905098634604270391438576112395918636152889842702592753597225
98911811251765344
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.29669712030631866935196902492751386618185321587048153531768154937172747439920
Short name T324
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:34 PM PDT 23
Peak memory 201216 kb
Host smart-156364fd-294f-45ec-b3d8-78420bce12fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29669712030631866935196902492751386618185321587048153531768154937172747439920 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.2966971203063186693519690249275138661818532158704815353176815493
7172747439920
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.64732713126682179721486612164543061593300763926241678750041915114565068092296
Short name T431
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 25 02:14:40 PM PDT 23
Finished Oct 25 02:14:45 PM PDT 23
Peak memory 201120 kb
Host smart-e3ec205b-0ebc-41a9-a908-b0b4461b9605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64732713126682179721486612164543061593300763926241678750041915114565068092296 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.64732713126682179721486612164543061593300763926241678750041915114565068092296
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.26656719494017282231710122162357105451284483130534034432963521925825142840722
Short name T187
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201108 kb
Host smart-60007520-30a4-4b11-902b-9c34f83a4c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26656719494017282231710122162357105451284483130534034432963521925825142840722 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.26656719494017282231710122162357105451284483130534034432963521925825142840722
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.103721422052471284379392720036375733051349241190509505043877121265145720396944
Short name T292
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:14:29 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201200 kb
Host smart-bee38c54-7ae3-4934-9f3d-d8365b308737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103721422052471284379392720036375733051349241190509505043877121265145720396944 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.103721422052471284379392720036375733051349241190509505043877121265145720396944
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.91968368127852393525274411930750920003554282602224223769568395706996347481002
Short name T661
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201228 kb
Host smart-310b505e-5d13-4850-ae1d-9663a1cafffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91968368127852393525274411930750920003554282602224223769568395706996347481002 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.91968368127852393525274411930750920003554282602224223769568395706996347481002
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.18014141829460311376121675949770702940342752648777399553753450594805375483425
Short name T365
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201200 kb
Host smart-31b37038-f382-41b2-943a-293a56d2da22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18014141829460311376121675949770702940342752648777399553753450594805375483425 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_smoke.18014141829460311376121675949770702940342752648777399553753450594805375483425
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.96708025839845101128238131279498019016053974763683190969312091125457872386760
Short name T118
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.51 seconds
Started Oct 25 02:14:35 PM PDT 23
Finished Oct 25 02:16:50 PM PDT 23
Peak memory 201476 kb
Host smart-331984ec-c8c2-4282-aff5-84c100327da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96708025839845101128238131279498019016053974763683190969312091125457872386760 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.96708025839845101128238131279498019016053974763683190969312091125457872386760
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.29721869715712549818233542094218044616620778045355641904035248677501661539933
Short name T605
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 25 02:14:25 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201108 kb
Host smart-7551528d-4624-451f-9bf8-e5197d2723e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29721869715712549818233542094218044616620778045355641904035248677501661539933 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.297218697157125498182335420942180446166207780453556419040352
48677501661539933
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.62207692934821925921698266363031861768358492668879546697100619328537728405396
Short name T608
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Oct 25 02:14:35 PM PDT 23
Finished Oct 25 02:14:39 PM PDT 23
Peak memory 201076 kb
Host smart-0e63e6e6-775c-4865-b03b-3f2192e5b18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62207692934821925921698266363031861768358492668879546697100619328537728405396 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.62207692934821925921698266363031861768358492668879546697100619328537728405396
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.67769547485321606565798809018657952888794267316148090799467831289354054605266
Short name T95
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.4 seconds
Started Oct 25 02:14:29 PM PDT 23
Finished Oct 25 02:14:35 PM PDT 23
Peak memory 201316 kb
Host smart-4808d831-f8ff-4ccd-9877-6bc83210e062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67769547485321606565798809018657952888794267316148090799467831289354054605266 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.67769547485321606565798809018657952888794267316148090799467831289354054605266
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.83011910768003827309641102711018951981188343286582380668982543857052568514859
Short name T428
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.82 seconds
Started Oct 25 02:14:35 PM PDT 23
Finished Oct 25 02:17:36 PM PDT 23
Peak memory 201288 kb
Host smart-6abe5553-b927-4f72-a060-d349740a40e7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83011910768003827309641102711018951981188343286582380668982543857052568514859 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.83011910768003827309641102711018951981188343286582380668982543
857052568514859
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.78051510106247090996436641161012936227993767147653341202631782968443018768594
Short name T257
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Oct 25 02:14:30 PM PDT 23
Finished Oct 25 02:14:37 PM PDT 23
Peak memory 201260 kb
Host smart-8b42781e-e6d0-4d2a-b603-fa073d4705b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78051510106247090996436641161012936227993767147653341202631782968443018768594 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.780515101062470909964366411610129362279937671476533412026317
82968443018768594
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.94060345203570482233532426700439692350875001415033404160529857341320868272620
Short name T666
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.22 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:34 PM PDT 23
Peak memory 201100 kb
Host smart-433f3dba-3702-4cc0-8985-ff6c98b716bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94060345203570482233532426700439692350875001415033404160529857341320868272620 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.9406034520357048223353242670043969235087500141503340416052985734
1320868272620
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.62808315182422700838128178258490892685958891801993657000767749387657416591286
Short name T533
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.58 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201268 kb
Host smart-54510914-6960-4b52-9beb-2fd5d016ec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62808315182422700838128178258490892685958891801993657000767749387657416591286 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.62808315182422700838128178258490892685958891801993657000767749387657416591286
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.55249848395432450166614166831478847927123621078854024740125112425832558277784
Short name T460
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.72 seconds
Started Oct 25 02:14:30 PM PDT 23
Finished Oct 25 02:14:35 PM PDT 23
Peak memory 201200 kb
Host smart-5978fb33-7cab-4e3d-9707-7b43954a9b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55249848395432450166614166831478847927123621078854024740125112425832558277784 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.55249848395432450166614166831478847927123621078854024740125112425832558277784
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.71539868951339566193221677598683993722343696282725837936130147716345469731629
Short name T390
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:14:32 PM PDT 23
Finished Oct 25 02:14:36 PM PDT 23
Peak memory 201160 kb
Host smart-404de048-ff92-41e8-81e8-46cbfb704e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71539868951339566193221677598683993722343696282725837936130147716345469731629 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.71539868951339566193221677598683993722343696282725837936130147716345469731629
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.35759987513775675162733742431897596085615630948062629224544524685328446943336
Short name T125
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201216 kb
Host smart-2127f4d3-088b-451b-a7ac-dbc9fe433d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35759987513775675162733742431897596085615630948062629224544524685328446943336 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.35759987513775675162733742431897596085615630948062629224544524685328446943336
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.37658603272495829718367171514421460705082542767278460002555639554809185766048
Short name T147
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.74 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201168 kb
Host smart-3c6927df-5e11-44e6-a795-edc19b0b3536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37658603272495829718367171514421460705082542767278460002555639554809185766048 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sysrst_ctrl_smoke.37658603272495829718367171514421460705082542767278460002555639554809185766048
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.114741005611726884255375431364688300938994933735059433385772865689520510623036
Short name T337
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.96 seconds
Started Oct 25 02:14:45 PM PDT 23
Finished Oct 25 02:17:01 PM PDT 23
Peak memory 201544 kb
Host smart-9278c528-fb55-4ce0-b7db-6710d2c55af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114741005611726884255375431364688300938994933735059433385772865689520510623036 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.114741005611726884255375431364688300938994933735059433385772865689520510623036
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.46998662709985806563286821274474154756251984212499796843929501797526091327519
Short name T229
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:14:47 PM PDT 23
Finished Oct 25 02:14:52 PM PDT 23
Peak memory 201220 kb
Host smart-d4af2730-0856-47aa-9f14-0d8382b76fbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46998662709985806563286821274474154756251984212499796843929501797526091327519 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.469986627099858065632868212744741547562519842124997968439295
01797526091327519
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.1153184330288413084069192418285410550797852408446976652896439186121339533950
Short name T304
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Oct 25 02:12:38 PM PDT 23
Finished Oct 25 02:12:43 PM PDT 23
Peak memory 201332 kb
Host smart-93669adc-0487-48e8-ae5c-3cce38dbca6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153184330288413084069192418285410550797852408446976652896439186121339533950 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.1153184330288413084069192418285410550797852408446976652896439186121339533950
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.115757889024227950704112021286200884085768899239066516762823933649539878538735
Short name T441
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Oct 25 02:12:34 PM PDT 23
Finished Oct 25 02:12:40 PM PDT 23
Peak memory 201152 kb
Host smart-0b377768-3556-4ee9-8148-e05efe571549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115757889024227950704112021286200884085768899239066516762823933649539878538735 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.115757889024227950704112021286200884085768899239066516762823933649539878538735
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.86777186098944897046578238912404114781744555209729617647954247685291535246207
Short name T620
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.25 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:15:18 PM PDT 23
Peak memory 201524 kb
Host smart-96478a3f-0991-4c1b-9da7-43d1227bf94e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86777186098944897046578238912404114781744555209729617647954247685291535246207 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.867771860989448970465782389124041147817445552097296176479542476
85291535246207
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.62052348377405348254972955322767980083990863520873240825472111906426097382107
Short name T110
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.24 seconds
Started Oct 25 02:12:35 PM PDT 23
Finished Oct 25 02:12:40 PM PDT 23
Peak memory 201268 kb
Host smart-4022cc4d-47a8-4c79-9305-5b67ac672002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62052348377405348254972955322767980083990863520873240825472111906426097382107 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.62052348377405348254972955322767980083990863520873240825472111906426097382107
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.35034080737463831911218171679510425192596252962315129557321691474409740585397
Short name T90
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.46 seconds
Started Oct 25 02:13:00 PM PDT 23
Finished Oct 25 02:13:05 PM PDT 23
Peak memory 201124 kb
Host smart-89a8cde3-cac9-4f83-8252-2ac4d3de4b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35034080737463831911218171679510425192596252962315129557321691474409740585397 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.35034080737463831911218171679510425192596252962315129
557321691474409740585397
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.42459038531419592213841277999746567851994121136745342211169769050653402167792
Short name T528
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.27 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:25 PM PDT 23
Peak memory 201244 kb
Host smart-12497ca6-3c09-4f98-b1cf-27e18d3070e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42459038531419592213841277999746567851994121136745342211169769050653402167792 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.4245903853141959221384127799974656785199412113674534221116976
9050653402167792
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.74635887776255367519749855049798494508446736058133945985662662470871906391312
Short name T670
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 25 02:12:52 PM PDT 23
Finished Oct 25 02:12:59 PM PDT 23
Peak memory 201220 kb
Host smart-2b03659b-a2d6-40f7-b361-468a837b1131
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74635887776255367519749855049798494508446736058133945985662662470871906391312 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.74635887776255367519749855049798494508446736058133945985662662470871906391312
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.77142617686809330358935774004437733498541441544899384657112854317588298015971
Short name T505
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.76 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201140 kb
Host smart-5c29c263-155f-468e-8daf-c4b14fa26624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77142617686809330358935774004437733498541441544899384657112854317588298015971 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.77142617686809330358935774004437733498541441544899384657112854317588298015971
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.11045864963467922227130650755716446191121856307277351394593009017104054231062
Short name T400
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201164 kb
Host smart-7c375d80-f805-4c14-8e73-35f35e59c286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11045864963467922227130650755716446191121856307277351394593009017104054231062 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.11045864963467922227130650755716446191121856307277351394593009017104054231062
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.114453931790671151766808556159960982390810516678752719311617597393512210329699
Short name T261
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.82 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:21 PM PDT 23
Peak memory 201196 kb
Host smart-c8b2b95b-cd4a-41cd-87ad-3fc0055a9cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114453931790671151766808556159960982390810516678752719311617597393512210329699 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.114453931790671151766808556159960982390810516678752719311617597393512210329699
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.13536275003548946411710688659906188844198000341066574620392276515590212097525
Short name T626
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201252 kb
Host smart-9f39928a-3a89-4f88-98ab-a3270a8bc62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13536275003548946411710688659906188844198000341066574620392276515590212097525 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.13536275003548946411710688659906188844198000341066574620392276515590212097525
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.40751377412919189850470618405680364136326484061474198993823486564864628674719
Short name T143
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.9 seconds
Started Oct 25 02:12:24 PM PDT 23
Finished Oct 25 02:13:29 PM PDT 23
Peak memory 221576 kb
Host smart-c06ff5e4-e3bb-4a42-b0f0-0bf7f12a0787
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40751377412919189850470618405680364136326484061474198993823486564864628674719 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.40751377412919189850470618405680364136326484061474198993823486564864628674719
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.33781883812112917782528705815366006619909640127307911177007444981743897943052
Short name T410
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:21 PM PDT 23
Peak memory 201020 kb
Host smart-729a74ed-28e9-40c8-b582-5a076256fa25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33781883812112917782528705815366006619909640127307911177007444981743897943052 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_smoke.33781883812112917782528705815366006619909640127307911177007444981743897943052
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.5985890940176551498849574531557043721888855162440799742402818986978928338859
Short name T271
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.5 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:14:54 PM PDT 23
Peak memory 201488 kb
Host smart-2f9efafd-9145-4b22-9be6-2e95ac0500da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5985890940176551498849574531557043721888855162440799742402818986978928338859 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.5985890940176551498849574531557043721888855162440799742402818986978928338859
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.20910898482095375291852366910659164337649812574250187972482654193225508189655
Short name T40
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:19 PM PDT 23
Peak memory 201156 kb
Host smart-1cd68d08-fb88-43b9-9ff7-76589a72794a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20910898482095375291852366910659164337649812574250187972482654193225508189655 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.2091089848209537529185236691065916433764981257425018797248265
4193225508189655
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.31934829182566643140283191191925935654317169242032780188540537430095217486779
Short name T413
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:15:16 PM PDT 23
Finished Oct 25 02:15:20 PM PDT 23
Peak memory 201180 kb
Host smart-4fa10ed9-a574-48e8-b4a7-ec16f116dabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31934829182566643140283191191925935654317169242032780188540537430095217486779 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.31934829182566643140283191191925935654317169242032780188540537430095217486779
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.18112502745039700330331036476670946915219756584046433925095285298143187280207
Short name T94
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Oct 25 02:15:13 PM PDT 23
Finished Oct 25 02:15:19 PM PDT 23
Peak memory 201212 kb
Host smart-4b2af022-7478-4c54-8123-2a70b16ccda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18112502745039700330331036476670946915219756584046433925095285298143187280207 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.18112502745039700330331036476670946915219756584046433925095285298143187280207
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.30609759650479897753611337469515909285997014650073708001096268410873324145777
Short name T144
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.53 seconds
Started Oct 25 02:14:52 PM PDT 23
Finished Oct 25 02:17:53 PM PDT 23
Peak memory 201536 kb
Host smart-d26660c8-5fe7-41ab-a8f5-b9ee174bea36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30609759650479897753611337469515909285997014650073708001096268410873324145777 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.30609759650479897753611337469515909285997014650073708001096268
410873324145777
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.43337749037555597425066646920283254308928585579264663540386285592937299387828
Short name T408
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Oct 25 02:14:55 PM PDT 23
Finished Oct 25 02:15:03 PM PDT 23
Peak memory 201256 kb
Host smart-63284f1b-6046-4a35-b384-de7e23349808
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43337749037555597425066646920283254308928585579264663540386285592937299387828 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.433377490375555974250666469202832543089285855792646635403862
85592937299387828
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.94756903599307982136256585176356842363428722839197708898113975721012801276318
Short name T333
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 25 02:15:13 PM PDT 23
Finished Oct 25 02:15:20 PM PDT 23
Peak memory 201200 kb
Host smart-affe50ed-2048-44a2-8eac-ff19b5719006
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94756903599307982136256585176356842363428722839197708898113975721012801276318 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.9475690359930798213625658517635684236342872283919770889811397572
1012801276318
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.107929620108379693848380528171225645645028060161126205888165593333529798467114
Short name T492
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.73 seconds
Started Oct 25 02:15:08 PM PDT 23
Finished Oct 25 02:15:13 PM PDT 23
Peak memory 201116 kb
Host smart-32942967-1614-42d2-a0c0-3746bdee1623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107929620108379693848380528171225645645028060161126205888165593333529798467114 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.107929620108379693848380528171225645645028060161126205888165593333529798467114
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.80991954536451531294944916832030837117842945946760421327291293137966749628964
Short name T166
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.88 seconds
Started Oct 25 02:14:57 PM PDT 23
Finished Oct 25 02:15:02 PM PDT 23
Peak memory 201260 kb
Host smart-18fc6e23-99a7-445d-a0d9-40b2ca274b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80991954536451531294944916832030837117842945946760421327291293137966749628964 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.80991954536451531294944916832030837117842945946760421327291293137966749628964
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.106704400038082976707280781561672851569632138580031552320114508070403275152543
Short name T245
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:15:09 PM PDT 23
Finished Oct 25 02:15:13 PM PDT 23
Peak memory 201044 kb
Host smart-10ddb729-012a-49fa-92d2-ac0c0b7ec515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106704400038082976707280781561672851569632138580031552320114508070403275152543 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.106704400038082976707280781561672851569632138580031552320114508070403275152543
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.33253570171101236872109483742358765583127496020882683687315955778066943330798
Short name T225
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 25 02:15:05 PM PDT 23
Finished Oct 25 02:15:11 PM PDT 23
Peak memory 201272 kb
Host smart-9837dc2a-f61d-4c44-9420-4f24ad2fb39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33253570171101236872109483742358765583127496020882683687315955778066943330798 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.33253570171101236872109483742358765583127496020882683687315955778066943330798
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.84573511018794109371717313266642765488294149641863272559918182414248419402864
Short name T547
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 25 02:15:00 PM PDT 23
Finished Oct 25 02:15:04 PM PDT 23
Peak memory 201044 kb
Host smart-dd225371-1e5f-4f0f-8100-d0119edb114f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84573511018794109371717313266642765488294149641863272559918182414248419402864 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sysrst_ctrl_smoke.84573511018794109371717313266642765488294149641863272559918182414248419402864
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.93654192985716538828459808896164996003249977343227582834421640461900642251818
Short name T376
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.57 seconds
Started Oct 25 02:15:14 PM PDT 23
Finished Oct 25 02:17:29 PM PDT 23
Peak memory 201476 kb
Host smart-13b32ea5-6406-4d78-bce1-82ed0ca2849a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93654192985716538828459808896164996003249977343227582834421640461900642251818 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.93654192985716538828459808896164996003249977343227582834421640461900642251818
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.16434458557612325789118661887328060421168556736534269681575552974290272062492
Short name T259
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 25 02:14:45 PM PDT 23
Finished Oct 25 02:14:50 PM PDT 23
Peak memory 201136 kb
Host smart-063a82a9-ec5d-475d-8db9-b7075747a45a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16434458557612325789118661887328060421168556736534269681575552974290272062492 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.164344585576123257891186618873280604211685567365342696815755
52974290272062492
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.107486333959825868035126087023031930345596104851134036699605143079563624164941
Short name T204
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:15:55 PM PDT 23
Finished Oct 25 02:15:59 PM PDT 23
Peak memory 201160 kb
Host smart-608a25d6-a524-4793-a8df-b35cb7710b50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107486333959825868035126087023031930345596104851134036699605143079563624164941 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.107486333959825868035126087023031930345596104851134036699605143079563624164941
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.37497161774147342398097404701280116643632383311305944580534217035814732839731
Short name T385
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.42 seconds
Started Oct 25 02:15:17 PM PDT 23
Finished Oct 25 02:15:24 PM PDT 23
Peak memory 201280 kb
Host smart-3c820fc1-5e5e-4b3a-b224-717182a7d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37497161774147342398097404701280116643632383311305944580534217035814732839731 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.37497161774147342398097404701280116643632383311305944580534217035814732839731
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.34350873742378774608500482992701714863427857039329093802775052588450654982421
Short name T513
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.97 seconds
Started Oct 25 02:15:28 PM PDT 23
Finished Oct 25 02:18:30 PM PDT 23
Peak memory 201464 kb
Host smart-f769ab67-a346-4850-8057-e5f241036048
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34350873742378774608500482992701714863427857039329093802775052588450654982421 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.34350873742378774608500482992701714863427857039329093802775052
588450654982421
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.38357675532867075881320287759612475243030495244984950125735120257306026363964
Short name T203
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 25 02:15:29 PM PDT 23
Finished Oct 25 02:15:37 PM PDT 23
Peak memory 201164 kb
Host smart-6076ae9b-2a26-422c-8b9c-1393ff78c066
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38357675532867075881320287759612475243030495244984950125735120257306026363964 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.383576755328670758813202877596124752430304952449849501257351
20257306026363964
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.59956001622335732619547746576759982142911328205065791324428667417058314728973
Short name T625
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Oct 25 02:15:56 PM PDT 23
Finished Oct 25 02:16:03 PM PDT 23
Peak memory 201100 kb
Host smart-9989d21f-3721-4712-b650-78f2ca45c337
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59956001622335732619547746576759982142911328205065791324428667417058314728973 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.5995600162233573261954774657675998214291132820506579132442866741
7058314728973
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.21635022857706814470309337099217872333065633875993611319650521291768635592563
Short name T262
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Oct 25 02:15:50 PM PDT 23
Finished Oct 25 02:15:55 PM PDT 23
Peak memory 201332 kb
Host smart-81ef7ce6-2fdc-497b-967d-3f3c8b63f998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21635022857706814470309337099217872333065633875993611319650521291768635592563 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.21635022857706814470309337099217872333065633875993611319650521291768635592563
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.95065882844863540165627188321325360735223111792788860497370575437698340933371
Short name T645
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 25 02:15:54 PM PDT 23
Finished Oct 25 02:15:59 PM PDT 23
Peak memory 201212 kb
Host smart-41ec5001-2dd9-4ebf-bac8-827348255fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95065882844863540165627188321325360735223111792788860497370575437698340933371 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.95065882844863540165627188321325360735223111792788860497370575437698340933371
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.30564925317973164760924387159871066558657224261620922915023511921088206495202
Short name T530
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.7 seconds
Started Oct 25 02:15:28 PM PDT 23
Finished Oct 25 02:15:33 PM PDT 23
Peak memory 201244 kb
Host smart-f4708915-6034-45e1-8832-24028e1c2747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30564925317973164760924387159871066558657224261620922915023511921088206495202 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.30564925317973164760924387159871066558657224261620922915023511921088206495202
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3747930584003982370343371924971310429162931311441530051746828669902770735222
Short name T635
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Oct 25 02:15:16 PM PDT 23
Finished Oct 25 02:15:21 PM PDT 23
Peak memory 201236 kb
Host smart-1bc251fe-62b2-4ba6-b66b-22f2f8369f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747930584003982370343371924971310429162931311441530051746828669902770735222 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3747930584003982370343371924971310429162931311441530051746828669902770735222
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.30244147155901998891305456502763847905414736713200476580479833178951958951858
Short name T146
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 25 02:15:08 PM PDT 23
Finished Oct 25 02:15:12 PM PDT 23
Peak memory 201176 kb
Host smart-a74acce0-9604-4411-86eb-10e90421eec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30244147155901998891305456502763847905414736713200476580479833178951958951858 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_smoke.30244147155901998891305456502763847905414736713200476580479833178951958951858
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.113922642790085256036734482322054834653072745449892953658441742910786033888488
Short name T539
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.9 seconds
Started Oct 25 02:15:55 PM PDT 23
Finished Oct 25 02:18:11 PM PDT 23
Peak memory 201524 kb
Host smart-7204e98e-67b5-46c0-a91e-33c197dca54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113922642790085256036734482322054834653072745449892953658441742910786033888488 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.113922642790085256036734482322054834653072745449892953658441742910786033888488
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.82201287167294541487211202223503442980881357740572328497068520485485004930025
Short name T475
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.67 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:39 PM PDT 23
Peak memory 201192 kb
Host smart-8b3b358e-6c60-4461-80d5-bcd09ec5ab23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82201287167294541487211202223503442980881357740572328497068520485485004930025 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.822012871672945414872112022235034429808813577405723284970685
20485485004930025
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.76288452826330808445910083445595654652093094153379003506508030407037054466129
Short name T466
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Oct 25 02:14:45 PM PDT 23
Finished Oct 25 02:14:49 PM PDT 23
Peak memory 201164 kb
Host smart-a9c99c43-cfba-4d68-aeec-939d61f19118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76288452826330808445910083445595654652093094153379003506508030407037054466129 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.76288452826330808445910083445595654652093094153379003506508030407037054466129
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.63941858807676361612799452155850418825898054627015435501640392162017491644221
Short name T196
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Oct 25 02:15:33 PM PDT 23
Finished Oct 25 02:15:39 PM PDT 23
Peak memory 201376 kb
Host smart-55aa53d5-d479-4951-b9c4-a81be9877339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63941858807676361612799452155850418825898054627015435501640392162017491644221 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.63941858807676361612799452155850418825898054627015435501640392162017491644221
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.66741658341384625776830104239962860397239464574206490291634582982390761816540
Short name T149
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.21 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:17:30 PM PDT 23
Peak memory 201304 kb
Host smart-c411f292-81b5-41cd-8f3d-0f0eb0c339f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66741658341384625776830104239962860397239464574206490291634582982390761816540 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.66741658341384625776830104239962860397239464574206490291634582
982390761816540
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.90222359290072802984373901302335612325918066870339839500899691974802637067721
Short name T358
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Oct 25 02:15:29 PM PDT 23
Finished Oct 25 02:15:37 PM PDT 23
Peak memory 201324 kb
Host smart-d12f4fac-e38a-4a88-99d0-760f254a8a69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90222359290072802984373901302335612325918066870339839500899691974802637067721 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.902223592900728029843739013023356123259180668703398395008996
91974802637067721
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.18328160478946506387620851188521387890761862370370845085899232588492900498599
Short name T200
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.18 seconds
Started Oct 25 02:14:29 PM PDT 23
Finished Oct 25 02:14:35 PM PDT 23
Peak memory 201216 kb
Host smart-86fd5049-4b49-4ff5-9679-8841020b687b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18328160478946506387620851188521387890761862370370845085899232588492900498599 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.1832816047894650638762085118852138789076186237037084508589923258
8492900498599
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.85060009847622946599984730246808210747148400074440537849769138879303137465721
Short name T314
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:34 PM PDT 23
Peak memory 201248 kb
Host smart-bacc6726-6aa8-4236-b18d-816b7d3b6649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85060009847622946599984730246808210747148400074440537849769138879303137465721 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.85060009847622946599984730246808210747148400074440537849769138879303137465721
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.34223622047849191735850586902563627810002717577434867379822447309310317574015
Short name T308
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.69 seconds
Started Oct 25 02:14:26 PM PDT 23
Finished Oct 25 02:14:31 PM PDT 23
Peak memory 201136 kb
Host smart-b2751ac8-d976-4dad-97c3-d61fbae850a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34223622047849191735850586902563627810002717577434867379822447309310317574015 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.34223622047849191735850586902563627810002717577434867379822447309310317574015
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.58971397089644241212172185209742230630878888132580711556321848596607716234398
Short name T570
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Oct 25 02:15:58 PM PDT 23
Finished Oct 25 02:16:03 PM PDT 23
Peak memory 201304 kb
Host smart-f48e9ca8-ac2d-488d-a095-35e58e499606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58971397089644241212172185209742230630878888132580711556321848596607716234398 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.58971397089644241212172185209742230630878888132580711556321848596607716234398
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.96320703914325964801317603527827681705005649197165420297594505208097835915881
Short name T279
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201240 kb
Host smart-d214e958-aeb0-48bf-814e-fc7d0049e82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96320703914325964801317603527827681705005649197165420297594505208097835915881 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.96320703914325964801317603527827681705005649197165420297594505208097835915881
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.16169078404601201998661069241631386499688906254708880627591989796404706189577
Short name T449
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.75 seconds
Started Oct 25 02:15:52 PM PDT 23
Finished Oct 25 02:15:57 PM PDT 23
Peak memory 201196 kb
Host smart-e3314eeb-73c4-4ff1-b20c-1460ab6902ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16169078404601201998661069241631386499688906254708880627591989796404706189577 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 42.sysrst_ctrl_smoke.16169078404601201998661069241631386499688906254708880627591989796404706189577
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.68198844608163899351118645060160837128884599130585044028365024885246729108017
Short name T380
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.09 seconds
Started Oct 25 02:14:32 PM PDT 23
Finished Oct 25 02:16:47 PM PDT 23
Peak memory 201284 kb
Host smart-f66be57a-61fe-463b-8095-fd103fbc6d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68198844608163899351118645060160837128884599130585044028365024885246729108017 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.68198844608163899351118645060160837128884599130585044028365024885246729108017
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.16455504766739323158254661249406811544875045037393244553886500999418201425721
Short name T48
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201240 kb
Host smart-c0d7c0cb-d019-418b-a08d-411689737f88
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16455504766739323158254661249406811544875045037393244553886500999418201425721 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.164555047667393231582546612494068115448750450373932445538865
00999418201425721
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.52648196374285061600778940318265226763893311199856343620472556466472726888662
Short name T157
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 25 02:15:09 PM PDT 23
Finished Oct 25 02:15:13 PM PDT 23
Peak memory 201208 kb
Host smart-3c4b6e20-e913-4784-a984-63560a6fef79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52648196374285061600778940318265226763893311199856343620472556466472726888662 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.52648196374285061600778940318265226763893311199856343620472556466472726888662
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.26727225152431371691866181299039189821080855348013906130278445418001149689840
Short name T207
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.4 seconds
Started Oct 25 02:14:39 PM PDT 23
Finished Oct 25 02:14:45 PM PDT 23
Peak memory 201168 kb
Host smart-865cc999-26cf-469d-958f-0561d88dd63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26727225152431371691866181299039189821080855348013906130278445418001149689840 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.26727225152431371691866181299039189821080855348013906130278445418001149689840
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.96035852984643475951659896299848739753797014569408085626345199063403665306052
Short name T516
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.11 seconds
Started Oct 25 02:14:32 PM PDT 23
Finished Oct 25 02:17:34 PM PDT 23
Peak memory 201524 kb
Host smart-c7fc3002-0ad8-4690-9742-8d56e2b5704d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96035852984643475951659896299848739753797014569408085626345199063403665306052 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.96035852984643475951659896299848739753797014569408085626345199
063403665306052
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.10011241385935531709257816885099078924037681357344496661851659472560389843218
Short name T668
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Oct 25 02:14:35 PM PDT 23
Finished Oct 25 02:14:42 PM PDT 23
Peak memory 201224 kb
Host smart-ae902a14-3394-4d88-83f8-c13c79f15a1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10011241385935531709257816885099078924037681357344496661851659472560389843218 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.100112413859355317092578168850990789240376813573444966618516
59472560389843218
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.45119990172545594039631239518024865161462187430812277314532343972664505501285
Short name T346
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Oct 25 02:15:06 PM PDT 23
Finished Oct 25 02:15:13 PM PDT 23
Peak memory 201228 kb
Host smart-1d76a3bf-596d-47a0-945b-fdd1c0009cec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45119990172545594039631239518024865161462187430812277314532343972664505501285 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.4511999017254559403963123951802486516146218743081227731453234397
2664505501285
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.84252316565663411543237278522668382064068761703539636383003347651250714769372
Short name T250
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Oct 25 02:14:48 PM PDT 23
Finished Oct 25 02:14:53 PM PDT 23
Peak memory 201216 kb
Host smart-6d1d147f-6092-4d5c-af16-8cc4c77965b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84252316565663411543237278522668382064068761703539636383003347651250714769372 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.84252316565663411543237278522668382064068761703539636383003347651250714769372
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.42610645421298322308818632297262689387430098882056963625342893788143615250161
Short name T615
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Oct 25 02:14:28 PM PDT 23
Finished Oct 25 02:14:33 PM PDT 23
Peak memory 201204 kb
Host smart-19715ec3-aa83-455a-affb-6522f0c4b195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42610645421298322308818632297262689387430098882056963625342893788143615250161 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.42610645421298322308818632297262689387430098882056963625342893788143615250161
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.75441821600326246205199231479819188286036306004054319646952817910973494385637
Short name T614
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 25 02:14:44 PM PDT 23
Finished Oct 25 02:14:48 PM PDT 23
Peak memory 201216 kb
Host smart-94474da0-84e1-4354-9fbd-08d18d19ac6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75441821600326246205199231479819188286036306004054319646952817910973494385637 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.75441821600326246205199231479819188286036306004054319646952817910973494385637
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.16116848530572189254537040114986397956048439206833343306842687172260205323062
Short name T182
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.48 seconds
Started Oct 25 02:14:27 PM PDT 23
Finished Oct 25 02:14:32 PM PDT 23
Peak memory 201092 kb
Host smart-fccbd9be-8efa-446b-95e4-8d77a763f63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16116848530572189254537040114986397956048439206833343306842687172260205323062 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.16116848530572189254537040114986397956048439206833343306842687172260205323062
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.78589324771770055076782311826177725490975954699015113372936416358116081121102
Short name T598
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Oct 25 02:14:39 PM PDT 23
Finished Oct 25 02:14:44 PM PDT 23
Peak memory 201044 kb
Host smart-3807cfe9-e13f-4310-81d2-17e06faaabfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78589324771770055076782311826177725490975954699015113372936416358116081121102 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_smoke.78589324771770055076782311826177725490975954699015113372936416358116081121102
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.74197129154400732808097870950540736098866426487574221280522656879527699309183
Short name T500
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.69 seconds
Started Oct 25 02:15:13 PM PDT 23
Finished Oct 25 02:17:28 PM PDT 23
Peak memory 201296 kb
Host smart-0086fba5-5dd8-4173-abd5-d05906e6e42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74197129154400732808097870950540736098866426487574221280522656879527699309183 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.74197129154400732808097870950540736098866426487574221280522656879527699309183
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.58269761377061694698105251246940522453094910927913975205202336722173808002790
Short name T387
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.65 seconds
Started Oct 25 02:14:34 PM PDT 23
Finished Oct 25 02:14:39 PM PDT 23
Peak memory 201072 kb
Host smart-644fc95d-9e58-45f1-81e5-fcf1aea1df8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58269761377061694698105251246940522453094910927913975205202336722173808002790 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.582697613770616946981052512469405224530949109279139752052023
36722173808002790
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.72562968382855238022254368353322801076570985169242605100563514535365227566506
Short name T565
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.77 seconds
Started Oct 25 02:15:55 PM PDT 23
Finished Oct 25 02:15:59 PM PDT 23
Peak memory 201212 kb
Host smart-a93db872-af04-4561-9d0d-145f32c7ff0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72562968382855238022254368353322801076570985169242605100563514535365227566506 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.72562968382855238022254368353322801076570985169242605100563514535365227566506
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.13341963417158700258675902767425096754647251098292139328893485130036351692555
Short name T623
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 25 02:15:06 PM PDT 23
Finished Oct 25 02:15:12 PM PDT 23
Peak memory 201232 kb
Host smart-1fedd7a4-3f8d-4285-99ac-04b1498754bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13341963417158700258675902767425096754647251098292139328893485130036351692555 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.13341963417158700258675902767425096754647251098292139328893485130036351692555
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.37721428699832500230517985439137231253174446544603733901915769147969775977563
Short name T211
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.94 seconds
Started Oct 25 02:15:28 PM PDT 23
Finished Oct 25 02:18:30 PM PDT 23
Peak memory 201300 kb
Host smart-5916c9cc-80b5-4c5d-b978-8b16d9fb0f18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37721428699832500230517985439137231253174446544603733901915769147969775977563 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.37721428699832500230517985439137231253174446544603733901915769
147969775977563
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.68770697707143067052429096673758657884346616659652022032506793581083927593491
Short name T109
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.3 seconds
Started Oct 25 02:15:14 PM PDT 23
Finished Oct 25 02:15:22 PM PDT 23
Peak memory 201124 kb
Host smart-2157d75f-0ee7-4d39-b77c-81a9a4898a45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68770697707143067052429096673758657884346616659652022032506793581083927593491 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.687706977071430670524290966737586578843466166596520220325067
93581083927593491
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.51109391725732820500940809527348643795584437290114572524983060397681777591410
Short name T129
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.2 seconds
Started Oct 25 02:15:56 PM PDT 23
Finished Oct 25 02:16:02 PM PDT 23
Peak memory 201100 kb
Host smart-e8efea1b-66f0-4c52-a31c-1041efdd270c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51109391725732820500940809527348643795584437290114572524983060397681777591410 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.5110939172573282050094080952734864379558443729011457252498306039
7681777591410
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.34188939369447972471562988895535816842775042535485234785887962451801795011469
Short name T348
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 25 02:15:29 PM PDT 23
Finished Oct 25 02:15:35 PM PDT 23
Peak memory 201256 kb
Host smart-f390463c-e7b3-4681-83bb-1b51e5997361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34188939369447972471562988895535816842775042535485234785887962451801795011469 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.34188939369447972471562988895535816842775042535485234785887962451801795011469
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.24123365719491366536264076844836476116076749985709224890860835834179031063906
Short name T403
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.73 seconds
Started Oct 25 02:15:13 PM PDT 23
Finished Oct 25 02:15:18 PM PDT 23
Peak memory 201068 kb
Host smart-7033d86e-77a1-44a9-a443-25a90a67b8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24123365719491366536264076844836476116076749985709224890860835834179031063906 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.24123365719491366536264076844836476116076749985709224890860835834179031063906
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.105437547149801056677707072417776485842405170158633149605709617164550364268271
Short name T421
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Oct 25 02:15:13 PM PDT 23
Finished Oct 25 02:15:17 PM PDT 23
Peak memory 201088 kb
Host smart-685e1f02-6e2e-4db2-b8f6-394098d9ec67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105437547149801056677707072417776485842405170158633149605709617164550364268271 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.105437547149801056677707072417776485842405170158633149605709617164550364268271
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.30568727487425189739683675795769421060924028308095434740845096007561157491380
Short name T427
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Oct 25 02:15:17 PM PDT 23
Finished Oct 25 02:15:22 PM PDT 23
Peak memory 201284 kb
Host smart-f060a893-143f-4546-95de-720e4ff8fe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30568727487425189739683675795769421060924028308095434740845096007561157491380 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.30568727487425189739683675795769421060924028308095434740845096007561157491380
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.94678305069461296534948533949038129735202909092718591630828877240966518879210
Short name T429
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Oct 25 02:15:06 PM PDT 23
Finished Oct 25 02:15:10 PM PDT 23
Peak memory 201200 kb
Host smart-147743c2-4d22-4641-b0c9-28598d5c3c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94678305069461296534948533949038129735202909092718591630828877240966518879210 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sysrst_ctrl_smoke.94678305069461296534948533949038129735202909092718591630828877240966518879210
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.4406679252609749045531421848812502817781335640984659755202055078217725344296
Short name T630
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.46 seconds
Started Oct 25 02:15:46 PM PDT 23
Finished Oct 25 02:18:01 PM PDT 23
Peak memory 201512 kb
Host smart-c758c4af-66be-45a5-9277-54360f126bdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4406679252609749045531421848812502817781335640984659755202055078217725344296 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.4406679252609749045531421848812502817781335640984659755202055078217725344296
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.97545683054684904527646011653356035633096918909942429163198927358262607540268
Short name T51
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Oct 25 02:15:31 PM PDT 23
Finished Oct 25 02:15:37 PM PDT 23
Peak memory 201140 kb
Host smart-51324943-e724-4bf8-9c23-0dceaef68071
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97545683054684904527646011653356035633096918909942429163198927358262607540268 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.975456830546849045276460116533560356330969189099424291631989
27358262607540268
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.87635085674884751703120218879819730288879257293803897253518406096766901357750
Short name T426
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 25 02:15:58 PM PDT 23
Finished Oct 25 02:16:02 PM PDT 23
Peak memory 201116 kb
Host smart-fee240a2-3b18-4c3d-b9d7-e4ff7447a6a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87635085674884751703120218879819730288879257293803897253518406096766901357750 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.87635085674884751703120218879819730288879257293803897253518406096766901357750
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.42453847513594358530019636547851727418438360206861040470922275132038934760608
Short name T288
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:40 PM PDT 23
Peak memory 201276 kb
Host smart-a4f9adee-c7f9-444b-991e-d8fc0c1bcabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42453847513594358530019636547851727418438360206861040470922275132038934760608 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.42453847513594358530019636547851727418438360206861040470922275132038934760608
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.99798895184219045670295883765352994003249303319011094872452956299178445534348
Short name T205
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.19 seconds
Started Oct 25 02:16:04 PM PDT 23
Finished Oct 25 02:19:06 PM PDT 23
Peak memory 201324 kb
Host smart-a13fa574-7651-48de-a63a-38b49a7fb695
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99798895184219045670295883765352994003249303319011094872452956299178445534348 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.99798895184219045670295883765352994003249303319011094872452956
299178445534348
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.104747448550515389365075657745872230659909166132068105236110080835257655451248
Short name T178
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Oct 25 02:15:56 PM PDT 23
Finished Oct 25 02:16:04 PM PDT 23
Peak memory 201140 kb
Host smart-b98f8738-7837-4934-b279-08569afdbba4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104747448550515389365075657745872230659909166132068105236110080835257655451248 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.10474744855051538936507565774587223065990916613206810523611
0080835257655451248
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.12614040404224745610158598567877012314600252048274713711944151470645709401826
Short name T617
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Oct 25 02:15:58 PM PDT 23
Finished Oct 25 02:16:05 PM PDT 23
Peak memory 201304 kb
Host smart-b6fdeb47-ac21-4162-adf9-77745b891802
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12614040404224745610158598567877012314600252048274713711944151470645709401826 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.1261404040422474561015859856787701231460025204827471371194415147
0645709401826
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.27258160564920753983833964044797586276321188520103370852424912041839414480942
Short name T545
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.63 seconds
Started Oct 25 02:15:33 PM PDT 23
Finished Oct 25 02:15:38 PM PDT 23
Peak memory 201324 kb
Host smart-9229913e-1e81-496b-8c78-e2b0cbad008b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27258160564920753983833964044797586276321188520103370852424912041839414480942 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.27258160564920753983833964044797586276321188520103370852424912041839414480942
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.25664931561372341556626671843282017942880845161493310783655240059267078260425
Short name T107
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:39 PM PDT 23
Peak memory 201244 kb
Host smart-77c43123-4aaa-4e7e-92cc-3074c839dc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25664931561372341556626671843282017942880845161493310783655240059267078260425 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.25664931561372341556626671843282017942880845161493310783655240059267078260425
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.83239415074083530547711818144958206569447548333305796478441249657423494464608
Short name T667
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Oct 25 02:15:27 PM PDT 23
Finished Oct 25 02:15:31 PM PDT 23
Peak memory 201184 kb
Host smart-667bcfe9-21aa-4c3d-80f5-1e1d9df9e85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83239415074083530547711818144958206569447548333305796478441249657423494464608 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.83239415074083530547711818144958206569447548333305796478441249657423494464608
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.66232264117466807260912515517232959749753484313930544724974733393655371492902
Short name T167
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Oct 25 02:15:44 PM PDT 23
Finished Oct 25 02:15:49 PM PDT 23
Peak memory 201200 kb
Host smart-9350f1de-f4c4-4b6c-aa54-e3349de42f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66232264117466807260912515517232959749753484313930544724974733393655371492902 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.66232264117466807260912515517232959749753484313930544724974733393655371492902
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.79627250454747233786542207616131091496305538425272730924536136099868383794624
Short name T402
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 25 02:15:53 PM PDT 23
Finished Oct 25 02:15:58 PM PDT 23
Peak memory 201280 kb
Host smart-ca388880-c475-4d7a-a8dc-c92a8ef0ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79627250454747233786542207616131091496305538425272730924536136099868383794624 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_smoke.79627250454747233786542207616131091496305538425272730924536136099868383794624
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.46249929682233098585799419078433988688087867695297448597753087608920040708886
Short name T336
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.78 seconds
Started Oct 25 02:16:24 PM PDT 23
Finished Oct 25 02:18:40 PM PDT 23
Peak memory 201416 kb
Host smart-bdb391ee-b6c6-42fd-b568-75ca3a7f95da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46249929682233098585799419078433988688087867695297448597753087608920040708886 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.46249929682233098585799419078433988688087867695297448597753087608920040708886
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.102877822744935615650224169461032664424051530303440024072943271533793213841140
Short name T311
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.82 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:40 PM PDT 23
Peak memory 201188 kb
Host smart-b57d96ba-3eb6-4ee3-acad-19b48f69d7b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102877822744935615650224169461032664424051530303440024072943271533793213841140 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.10287782274493561565022416946103266442405153030344002407294
3271533793213841140
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.47126090139353006167086640418304399103789835833527574776353473508083627961669
Short name T591
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.69 seconds
Started Oct 25 02:16:06 PM PDT 23
Finished Oct 25 02:16:10 PM PDT 23
Peak memory 201212 kb
Host smart-6c94eac7-c471-4aa2-8d27-2b43ad293639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47126090139353006167086640418304399103789835833527574776353473508083627961669 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.47126090139353006167086640418304399103789835833527574776353473508083627961669
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.86237511462823775018037445904711962676621840626965672397153143557010784395544
Short name T521
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 25 02:16:27 PM PDT 23
Finished Oct 25 02:16:35 PM PDT 23
Peak memory 201296 kb
Host smart-97656b01-7b99-4baa-93ca-c48912568e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86237511462823775018037445904711962676621840626965672397153143557010784395544 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.86237511462823775018037445904711962676621840626965672397153143557010784395544
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.97824390669854668196674052343920373181285848553883858949997326461449545630925
Short name T363
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.95 seconds
Started Oct 25 02:16:10 PM PDT 23
Finished Oct 25 02:19:14 PM PDT 23
Peak memory 201468 kb
Host smart-4e4108c5-384d-4977-b51e-4f520dd7b4f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97824390669854668196674052343920373181285848553883858949997326461449545630925 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.97824390669854668196674052343920373181285848553883858949997326
461449545630925
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3968185779370005639428442341190988990604193345719199808629522077909076429786
Short name T656
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Oct 25 02:16:03 PM PDT 23
Finished Oct 25 02:16:11 PM PDT 23
Peak memory 201104 kb
Host smart-d507e7a4-49d9-45e1-bbe6-f182637604ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968185779370005639428442341190988990604193345719199808629522077909076429786 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.3968185779370005639428442341190988990604193345719199808629522
077909076429786
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.88960058033402851924467826900301663928807965371151354271908397123865411361770
Short name T439
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Oct 25 02:16:06 PM PDT 23
Finished Oct 25 02:16:12 PM PDT 23
Peak memory 201212 kb
Host smart-7c0166cd-9a7d-495c-aaec-96da15f442bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88960058033402851924467826900301663928807965371151354271908397123865411361770 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.8896005803340285192446782690030166392880796537115135427190839712
3865411361770
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.79401136049384916584419601031888726627154914830259159985151688011072431343925
Short name T197
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Oct 25 02:16:20 PM PDT 23
Finished Oct 25 02:16:25 PM PDT 23
Peak memory 201084 kb
Host smart-f9caf4d0-a2ed-4006-89ab-1b05f0474c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79401136049384916584419601031888726627154914830259159985151688011072431343925 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.79401136049384916584419601031888726627154914830259159985151688011072431343925
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.71117876042774730324489481548276092242505259955425005411300696221156437815079
Short name T649
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Oct 25 02:15:59 PM PDT 23
Finished Oct 25 02:16:04 PM PDT 23
Peak memory 201156 kb
Host smart-c432370d-f6e4-4c95-8779-7d44634c309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71117876042774730324489481548276092242505259955425005411300696221156437815079 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.71117876042774730324489481548276092242505259955425005411300696221156437815079
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.56279658036072150623915842247640081233929560085224507951493087838382778727857
Short name T488
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.88 seconds
Started Oct 25 02:16:22 PM PDT 23
Finished Oct 25 02:16:26 PM PDT 23
Peak memory 201240 kb
Host smart-c635e3e6-e44f-4b21-bf06-4f3aa937a7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56279658036072150623915842247640081233929560085224507951493087838382778727857 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.56279658036072150623915842247640081233929560085224507951493087838382778727857
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.24600761485292769025383892405624165400300662938210728609540650444344209545572
Short name T121
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 25 02:16:24 PM PDT 23
Finished Oct 25 02:16:29 PM PDT 23
Peak memory 201296 kb
Host smart-721a9647-731e-4014-94e5-4b941c5fa4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24600761485292769025383892405624165400300662938210728609540650444344209545572 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.24600761485292769025383892405624165400300662938210728609540650444344209545572
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.79046985072199014984319583639309922679927975693737465936569085699968006122067
Short name T604
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Oct 25 02:16:09 PM PDT 23
Finished Oct 25 02:16:14 PM PDT 23
Peak memory 201180 kb
Host smart-29a2a28b-7706-4320-bc5e-15d0066e1b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79046985072199014984319583639309922679927975693737465936569085699968006122067 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_smoke.79046985072199014984319583639309922679927975693737465936569085699968006122067
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.29941410708543583961156420657133755738121733682608557144473249778637486624299
Short name T491
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.81 seconds
Started Oct 25 02:16:51 PM PDT 23
Finished Oct 25 02:19:05 PM PDT 23
Peak memory 201496 kb
Host smart-47fdfd22-62c6-48a6-9959-2cd08c6aad57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29941410708543583961156420657133755738121733682608557144473249778637486624299 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.29941410708543583961156420657133755738121733682608557144473249778637486624299
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.51245314913555230384737895168113717935521935697958761565041007564710104738405
Short name T49
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.83 seconds
Started Oct 25 02:16:05 PM PDT 23
Finished Oct 25 02:16:11 PM PDT 23
Peak memory 201212 kb
Host smart-81ef49a9-5e1a-4bb5-a069-462ce5b32fab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51245314913555230384737895168113717935521935697958761565041007564710104738405 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.512453149135552303847378951681137179355219356979587615650410
07564710104738405
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.27055897170813619625474966419423086281219149212318018880053027395041861914997
Short name T612
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Oct 25 02:15:14 PM PDT 23
Finished Oct 25 02:15:18 PM PDT 23
Peak memory 201236 kb
Host smart-c14e0716-ea94-41dd-a06e-7fc99f6e825b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27055897170813619625474966419423086281219149212318018880053027395041861914997 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.27055897170813619625474966419423086281219149212318018880053027395041861914997
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.72129097970736803284404171098978962876774318416478589929987936040295439104306
Short name T89
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Oct 25 02:15:08 PM PDT 23
Finished Oct 25 02:15:14 PM PDT 23
Peak memory 201196 kb
Host smart-7ee52550-8743-4908-86a6-731ec9ef245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72129097970736803284404171098978962876774318416478589929987936040295439104306 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.72129097970736803284404171098978962876774318416478589929987936040295439104306
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.64708670931614789193116602122412302609511442427600542986473259497472440033072
Short name T452
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.17 seconds
Started Oct 25 02:15:14 PM PDT 23
Finished Oct 25 02:18:16 PM PDT 23
Peak memory 201340 kb
Host smart-14a501b5-f059-48fe-8907-aa010bad45e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64708670931614789193116602122412302609511442427600542986473259497472440033072 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.64708670931614789193116602122412302609511442427600542986473259
497472440033072
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.114085900273027802259943452101221230836714479646813022440999295489496768384198
Short name T542
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Oct 25 02:16:37 PM PDT 23
Finished Oct 25 02:16:44 PM PDT 23
Peak memory 201224 kb
Host smart-8e1809fc-4382-4725-bd1c-2f7fc6c80cad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114085900273027802259943452101221230836714479646813022440999295489496768384198 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.11408590027302780225994345210122123083671447964681302244099
9295489496768384198
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.4830658809358907236662798153505986351193953845911880705509303610020376810301
Short name T372
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Oct 25 02:15:13 PM PDT 23
Finished Oct 25 02:15:19 PM PDT 23
Peak memory 201188 kb
Host smart-5f3a32c9-0d5a-4126-815f-9c5fad608900
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4830658809358907236662798153505986351193953845911880705509303610020376810301 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.4830658809358907236662798153505986351193953845911880705509303610020376810301
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.14458642481300152623166168424481365568823051824594583653416809018190715330508
Short name T554
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 25 02:15:07 PM PDT 23
Finished Oct 25 02:15:12 PM PDT 23
Peak memory 201268 kb
Host smart-37734d91-3516-434e-bd8e-e51190a36fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14458642481300152623166168424481365568823051824594583653416809018190715330508 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.14458642481300152623166168424481365568823051824594583653416809018190715330508
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.75329782557654650425645356662051800268621910534319195680392391049539374405365
Short name T234
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.76 seconds
Started Oct 25 02:15:50 PM PDT 23
Finished Oct 25 02:15:56 PM PDT 23
Peak memory 201276 kb
Host smart-bdb4c37d-5aa5-4eb8-b4cb-fbe48adf261c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75329782557654650425645356662051800268621910534319195680392391049539374405365 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.75329782557654650425645356662051800268621910534319195680392391049539374405365
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.77320170182499923987033141493182987841064404952276404706743257196888992848833
Short name T375
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.97 seconds
Started Oct 25 02:16:38 PM PDT 23
Finished Oct 25 02:16:42 PM PDT 23
Peak memory 201200 kb
Host smart-e311df27-f78f-49ac-a628-13b6f2d8a98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77320170182499923987033141493182987841064404952276404706743257196888992848833 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.77320170182499923987033141493182987841064404952276404706743257196888992848833
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.92790422576676344775767004615301004844606287087572561352295922596406901884741
Short name T438
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 25 02:16:37 PM PDT 23
Finished Oct 25 02:16:42 PM PDT 23
Peak memory 201140 kb
Host smart-34c8ccc2-54db-48b9-9095-4889cdd1e27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92790422576676344775767004615301004844606287087572561352295922596406901884741 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.92790422576676344775767004615301004844606287087572561352295922596406901884741
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.90788155845739776729797327079687481280471434305451956336969683714245995254212
Short name T440
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 25 02:16:05 PM PDT 23
Finished Oct 25 02:16:09 PM PDT 23
Peak memory 201140 kb
Host smart-9f672556-4a6e-4ada-bb31-555fc024ea1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90788155845739776729797327079687481280471434305451956336969683714245995254212 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_smoke.90788155845739776729797327079687481280471434305451956336969683714245995254212
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.34407248546218100862590538774880034670637347153051521501661079377132549618230
Short name T119
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.1 seconds
Started Oct 25 02:15:07 PM PDT 23
Finished Oct 25 02:17:22 PM PDT 23
Peak memory 201516 kb
Host smart-e171e462-13a3-43bb-a210-ae65d6ad7892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34407248546218100862590538774880034670637347153051521501661079377132549618230 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.34407248546218100862590538774880034670637347153051521501661079377132549618230
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.85530359461690520982858220522869803396222087342440816490527550806342066796722
Short name T424
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Oct 25 02:16:58 PM PDT 23
Finished Oct 25 02:17:03 PM PDT 23
Peak memory 201032 kb
Host smart-ba77c4e1-fd84-498e-be2e-837fd7a0225a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85530359461690520982858220522869803396222087342440816490527550806342066796722 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.855303594616905209828582205228698033962220873424408164905275
50806342066796722
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.105084935631628910158427022893566570820021464194174995779581931560819893318556
Short name T362
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Oct 25 02:15:30 PM PDT 23
Finished Oct 25 02:15:34 PM PDT 23
Peak memory 201236 kb
Host smart-9a88144a-7108-43a8-8c89-a0c605970fc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105084935631628910158427022893566570820021464194174995779581931560819893318556 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.105084935631628910158427022893566570820021464194174995779581931560819893318556
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.106709495656131970934777592549319931653389433969991916526179616524241830559707
Short name T98
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.38 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:40 PM PDT 23
Peak memory 201300 kb
Host smart-52e1a9b0-03fc-4127-aeca-a560461321e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106709495656131970934777592549319931653389433969991916526179616524241830559707 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.106709495656131970934777592549319931653389433969991916526179616524241830559707
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.90366647021434762864002197228027328897527498694170625610380638033758647197482
Short name T527
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.98 seconds
Started Oct 25 02:15:53 PM PDT 23
Finished Oct 25 02:18:54 PM PDT 23
Peak memory 201496 kb
Host smart-e40f43b6-344e-4109-af2a-e0d5d9f5d711
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90366647021434762864002197228027328897527498694170625610380638033758647197482 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.90366647021434762864002197228027328897527498694170625610380638
033758647197482
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.53935489687875799674382801659060619422956118430189852430027964756876565475568
Short name T595
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.35 seconds
Started Oct 25 02:15:52 PM PDT 23
Finished Oct 25 02:16:00 PM PDT 23
Peak memory 201268 kb
Host smart-fa2825a3-2479-46f6-998f-398361a01f89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53935489687875799674382801659060619422956118430189852430027964756876565475568 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.539354896878757996743828016590606194229561184301898524300279
64756876565475568
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.62537156880392319870749325554621782037922729909354192892174942816553261349615
Short name T478
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 25 02:15:35 PM PDT 23
Finished Oct 25 02:15:41 PM PDT 23
Peak memory 200496 kb
Host smart-a7cccec0-9f7e-45a4-bb95-960a83292dc1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62537156880392319870749325554621782037922729909354192892174942816553261349615 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.6253715688039231987074932555462178203792272990935419289217494281
6553261349615
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.19830056560225519876164895212321454029700284375414576167379990646613783951926
Short name T368
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Oct 25 02:15:26 PM PDT 23
Finished Oct 25 02:15:32 PM PDT 23
Peak memory 201216 kb
Host smart-b4e719fa-92c7-40ef-9bb0-dd3e35ae0119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19830056560225519876164895212321454029700284375414576167379990646613783951926 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.19830056560225519876164895212321454029700284375414576167379990646613783951926
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.58369302493561073947175491361908534661093054982062097988123930869972720116203
Short name T575
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Oct 25 02:15:17 PM PDT 23
Finished Oct 25 02:15:22 PM PDT 23
Peak memory 201236 kb
Host smart-ac877d4d-06ae-4e54-af60-5d1aecae3548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58369302493561073947175491361908534661093054982062097988123930869972720116203 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.58369302493561073947175491361908534661093054982062097988123930869972720116203
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.79873506915132149904013353977115070755558572984410259057323201441698506258261
Short name T286
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.68 seconds
Started Oct 25 02:15:29 PM PDT 23
Finished Oct 25 02:15:33 PM PDT 23
Peak memory 201108 kb
Host smart-2ff5649b-983e-43e6-8dd2-acc116a3e224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79873506915132149904013353977115070755558572984410259057323201441698506258261 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.79873506915132149904013353977115070755558572984410259057323201441698506258261
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.106937671570944774186969432536453145550067144305642175123383319638687933318008
Short name T285
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Oct 25 02:15:27 PM PDT 23
Finished Oct 25 02:15:34 PM PDT 23
Peak memory 201240 kb
Host smart-0f5fb5e6-90c6-43e9-bd57-c38d3bb6a26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106937671570944774186969432536453145550067144305642175123383319638687933318008 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.106937671570944774186969432536453145550067144305642175123383319638687933318008
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.100630803820901962195190469166028950792742729273720158170556642066864264647045
Short name T320
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 25 02:15:07 PM PDT 23
Finished Oct 25 02:15:11 PM PDT 23
Peak memory 201208 kb
Host smart-1513fe5c-e4e3-4fa7-b263-4e148325b25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100630803820901962195190469166028950792742729273720158170556642066864264647045 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 48.sysrst_ctrl_smoke.100630803820901962195190469166028950792742729273720158170556642066864264647045
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.42006250689299214238984382816793914638505731721528739977721790773149014952055
Short name T327
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.7 seconds
Started Oct 25 02:15:54 PM PDT 23
Finished Oct 25 02:18:08 PM PDT 23
Peak memory 201364 kb
Host smart-50812a6e-79ae-400c-9fec-079220107977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42006250689299214238984382816793914638505731721528739977721790773149014952055 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.42006250689299214238984382816793914638505731721528739977721790773149014952055
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.84815831659391932127894904230636321274621683961446532720218305288006847571464
Short name T243
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 25 02:15:27 PM PDT 23
Finished Oct 25 02:15:34 PM PDT 23
Peak memory 201216 kb
Host smart-bb6c3f00-d82c-403a-a1d7-523990d5e17c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84815831659391932127894904230636321274621683961446532720218305288006847571464 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.848158316593919321278949042306363212746216839614465327202183
05288006847571464
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.108826877632333866089916016365468103100670917053018040315058284238176544983153
Short name T524
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:38 PM PDT 23
Peak memory 201228 kb
Host smart-3c6d8d92-d540-4b31-81ed-85b74bf2495e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108826877632333866089916016365468103100670917053018040315058284238176544983153 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.108826877632333866089916016365468103100670917053018040315058284238176544983153
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1027047503931472122870353719746810147833337779288998330151359637691449031153
Short name T87
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.39 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:40 PM PDT 23
Peak memory 201332 kb
Host smart-d99c834a-70e9-4168-a991-3b896e7196ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027047503931472122870353719746810147833337779288998330151359637691449031153 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.1027047503931472122870353719746810147833337779288998330151359637691449031153
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.27097561475050219603225508113390252631893733893814885843670119485603408401979
Short name T637
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.05 seconds
Started Oct 25 02:15:59 PM PDT 23
Finished Oct 25 02:19:02 PM PDT 23
Peak memory 201512 kb
Host smart-f751a88c-12db-44f2-95cd-ffba1a137cb8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27097561475050219603225508113390252631893733893814885843670119485603408401979 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.27097561475050219603225508113390252631893733893814885843670119
485603408401979
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.21064577449885376514636226976490530405940607687153487547310525428195916800090
Short name T627
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.58 seconds
Started Oct 25 02:15:58 PM PDT 23
Finished Oct 25 02:16:06 PM PDT 23
Peak memory 201288 kb
Host smart-0b266dae-0f27-4aea-9867-90e04916ea76
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21064577449885376514636226976490530405940607687153487547310525428195916800090 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.210645774498853765146362269764905304059406076871534875473105
25428195916800090
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.88239982112895423777798550813663695033894621917213639064993501737832772181475
Short name T572
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Oct 25 02:16:00 PM PDT 23
Finished Oct 25 02:16:07 PM PDT 23
Peak memory 201224 kb
Host smart-05142d6c-d959-43a8-915a-ebaf21698810
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88239982112895423777798550813663695033894621917213639064993501737832772181475 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.8823998211289542377779855081366369503389462191721363906499350173
7832772181475
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.30719884977077373457532813705435319776147177607597482192488782450388954672575
Short name T489
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Oct 25 02:15:35 PM PDT 23
Finished Oct 25 02:15:40 PM PDT 23
Peak memory 201252 kb
Host smart-87d27de5-0ced-4bfa-87c5-03c3336759b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30719884977077373457532813705435319776147177607597482192488782450388954672575 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.30719884977077373457532813705435319776147177607597482192488782450388954672575
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3425113167368780432314387703912214589625537583955670132380641572674866604900
Short name T168
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Oct 25 02:15:35 PM PDT 23
Finished Oct 25 02:15:40 PM PDT 23
Peak memory 200664 kb
Host smart-283a8a1f-04f1-4108-8dfa-c678cd3f45fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425113167368780432314387703912214589625537583955670132380641572674866604900 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3425113167368780432314387703912214589625537583955670132380641572674866604900
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.77140970898688934866259171184560562999283371917455890715297555753095939184316
Short name T300
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Oct 25 02:16:17 PM PDT 23
Finished Oct 25 02:16:21 PM PDT 23
Peak memory 201280 kb
Host smart-8507862f-eb5b-46e2-b44a-f57f014ba333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77140970898688934866259171184560562999283371917455890715297555753095939184316 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.77140970898688934866259171184560562999283371917455890715297555753095939184316
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.27294037529964651768799930195540515526334125465680606359203121098794302066487
Short name T219
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 25 02:15:33 PM PDT 23
Finished Oct 25 02:15:38 PM PDT 23
Peak memory 201224 kb
Host smart-cfec5399-82fc-4d31-aeb2-07e4470b95d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27294037529964651768799930195540515526334125465680606359203121098794302066487 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.27294037529964651768799930195540515526334125465680606359203121098794302066487
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.43152053295327253529085627340743287531024542907751009531688119268433637850254
Short name T481
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 25 02:15:34 PM PDT 23
Finished Oct 25 02:15:39 PM PDT 23
Peak memory 201176 kb
Host smart-ecdc3017-1e40-4a19-a26b-4884bf4e8981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43152053295327253529085627340743287531024542907751009531688119268433637850254 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sysrst_ctrl_smoke.43152053295327253529085627340743287531024542907751009531688119268433637850254
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.31659230894998046406598695108716723600112877020058205488986455632557739739749
Short name T395
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.86 seconds
Started Oct 25 02:16:33 PM PDT 23
Finished Oct 25 02:18:48 PM PDT 23
Peak memory 201540 kb
Host smart-314caa98-6faa-4f5c-a578-5e608978b016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31659230894998046406598695108716723600112877020058205488986455632557739739749 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.31659230894998046406598695108716723600112877020058205488986455632557739739749
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.112168207795633029554528347939455898796502197252656948958867985318053932628965
Short name T568
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Oct 25 02:15:58 PM PDT 23
Finished Oct 25 02:16:04 PM PDT 23
Peak memory 201104 kb
Host smart-ec98797f-d2ab-4bbd-8ecc-cd9d696eb040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112168207795633029554528347939455898796502197252656948958867985318053932628965 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.11216820779563302955452834793945589879650219725265694895886
7985318053932628965
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.37180659436910098085918828735575923250630330140341052546539507137051043567612
Short name T396
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:12:58 PM PDT 23
Peak memory 201184 kb
Host smart-09565ca3-f862-466e-bed0-c186f432c5ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37180659436910098085918828735575923250630330140341052546539507137051043567612 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.37180659436910098085918828735575923250630330140341052546539507137051043567612
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.63992601119339238909417430013983776585714337842330394250097785668658647520534
Short name T296
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:13:00 PM PDT 23
Peak memory 201284 kb
Host smart-2a94a9f2-b74c-4100-a138-bc99b1542203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63992601119339238909417430013983776585714337842330394250097785668658647520534 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.63992601119339238909417430013983776585714337842330394250097785668658647520534
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.105449283194233554545754577718499058757604721132842608773632856261354658772996
Short name T382
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.95 seconds
Started Oct 25 02:12:40 PM PDT 23
Finished Oct 25 02:15:43 PM PDT 23
Peak memory 201444 kb
Host smart-1d78b0b0-a48f-4a41-92e9-85e5366cacce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105449283194233554545754577718499058757604721132842608773632856261354658772996 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.10544928319423355454575457771849905875760472113284260877363285
6261354658772996
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.70900779152291263857650967591695516920720013371998466165017043821169864020943
Short name T512
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Oct 25 02:12:38 PM PDT 23
Finished Oct 25 02:12:47 PM PDT 23
Peak memory 201264 kb
Host smart-0c226273-2cb2-4031-b547-85ded3273a8a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70900779152291263857650967591695516920720013371998466165017043821169864020943 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.7090077915229126385765096759169551692072001337199846616501704
3821169864020943
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.14250425143633846937187335082251952305814467708883162434786458268346656067148
Short name T619
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 25 02:12:42 PM PDT 23
Finished Oct 25 02:12:48 PM PDT 23
Peak memory 201256 kb
Host smart-f3bc2ff1-8848-4b0d-9ecd-36b9cec06f2d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14250425143633846937187335082251952305814467708883162434786458268346656067148 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.14250425143633846937187335082251952305814467708883162434786458268346656067148
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.96937671548489357543967638583467532512772780441792703028541772350113345464592
Short name T112
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Oct 25 02:12:41 PM PDT 23
Finished Oct 25 02:12:46 PM PDT 23
Peak memory 201268 kb
Host smart-7ea34eef-efda-478f-be47-e31d78d0af7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96937671548489357543967638583467532512772780441792703028541772350113345464592 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.96937671548489357543967638583467532512772780441792703028541772350113345464592
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.3444201634200589128496781466512493398972170224954204307975217857086657294768
Short name T370
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:12:27 PM PDT 23
Peak memory 201260 kb
Host smart-b04ad4a4-7bca-431f-9f86-131e649af4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444201634200589128496781466512493398972170224954204307975217857086657294768 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3444201634200589128496781466512493398972170224954204307975217857086657294768
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.44339948488364680448836057468681270101122077638764254662355399669294706929213
Short name T664
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Oct 25 02:12:39 PM PDT 23
Finished Oct 25 02:12:44 PM PDT 23
Peak memory 201200 kb
Host smart-ff9333ac-363f-4e8c-98cd-c8fc0f03e140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44339948488364680448836057468681270101122077638764254662355399669294706929213 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.44339948488364680448836057468681270101122077638764254662355399669294706929213
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.352902090775314577066522272311495693413288309334532170558603717910765680680
Short name T653
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 201076 kb
Host smart-8de6779b-c671-43a9-ad86-5ee6d5510037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352902090775314577066522272311495693413288309334532170558603717910765680680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.352902090775314577066522272311495693413288309334532170558603717910765680680
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.54685764230272991574255465173533323796406778609661590767637722135170941202536
Short name T544
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 25 02:12:38 PM PDT 23
Finished Oct 25 02:12:44 PM PDT 23
Peak memory 201280 kb
Host smart-8df0059a-e17f-4b32-804f-44dbe6faf95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54685764230272991574255465173533323796406778609661590767637722135170941202536 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.sysrst_ctrl_smoke.54685764230272991574255465173533323796406778609661590767637722135170941202536
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.94878115215251574504183568779403612923035901664923417965481213519029008408733
Short name T634
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.88 seconds
Started Oct 25 02:12:52 PM PDT 23
Finished Oct 25 02:15:07 PM PDT 23
Peak memory 201340 kb
Host smart-17dd2622-549e-46b1-9319-bfe5b549a955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94878115215251574504183568779403612923035901664923417965481213519029008408733 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.94878115215251574504183568779403612923035901664923417965481213519029008408733
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2266046886828655983412522175255554008587290682636237080146271619895282277936
Short name T551
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 25 02:12:40 PM PDT 23
Finished Oct 25 02:12:45 PM PDT 23
Peak memory 201192 kb
Host smart-59c5bd73-a38c-47d8-92b9-10ee5708a094
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266046886828655983412522175255554008587290682636237080146271619895282277936 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.22660468868286559834125221752555540085872906826362370801462716
19895282277936
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.38948644642810007556346386557761167259574734142190928009885567517861207697447
Short name T162
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 25 02:12:56 PM PDT 23
Finished Oct 25 02:13:00 PM PDT 23
Peak memory 201260 kb
Host smart-b1b285ed-cbbd-4a0d-beb1-e3bab8c7661d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38948644642810007556346386557761167259574734142190928009885567517861207697447 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.38948644642810007556346386557761167259574734142190928009885567517861207697447
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.78747140827994185792001935587829888225205813937975913686982913820516454516041
Short name T471
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:13:00 PM PDT 23
Peak memory 201276 kb
Host smart-cf40991a-f7a4-4fe7-87cf-aa192ad32ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78747140827994185792001935587829888225205813937975913686982913820516454516041 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.78747140827994185792001935587829888225205813937975913686982913820516454516041
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.20099554698014950766149922475469873400631909849045098217814936342569201843906
Short name T222
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.5 seconds
Started Oct 25 02:13:03 PM PDT 23
Finished Oct 25 02:16:05 PM PDT 23
Peak memory 201476 kb
Host smart-3b86c3b2-a830-477a-9497-3cf0240fbb1d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20099554698014950766149922475469873400631909849045098217814936342569201843906 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.200995546980149507661499224754698734006319098490450982178149363
42569201843906
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.72508207684003376645372438713037575514535303606458598301580113267356662310086
Short name T654
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Oct 25 02:12:55 PM PDT 23
Finished Oct 25 02:13:03 PM PDT 23
Peak memory 201172 kb
Host smart-261863de-42fe-4b8e-b9ab-e40c5e4b3999
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72508207684003376645372438713037575514535303606458598301580113267356662310086 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.7250820768400337664537243871303757551453530360645859830158011
3267356662310086
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.110782416113021251676011022616276327742531207576220439763839649482104755923568
Short name T381
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Oct 25 02:13:01 PM PDT 23
Finished Oct 25 02:13:08 PM PDT 23
Peak memory 201100 kb
Host smart-d7e441d5-a52e-437c-b134-217e2896ba52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110782416113021251676011022616276327742531207576220439763839649482104755923568 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.1107824161130212516760110226162763277425312075762204397638396494
82104755923568
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.58399102564664245407935879870083391088831211621333808780421285829693994738652
Short name T616
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Oct 25 02:12:56 PM PDT 23
Finished Oct 25 02:13:01 PM PDT 23
Peak memory 201240 kb
Host smart-99e8b204-7540-4333-a0b7-5a49fa79e65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58399102564664245407935879870083391088831211621333808780421285829693994738652 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.58399102564664245407935879870083391088831211621333808780421285829693994738652
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.68053470192688273177354785373383199931289019373255177222683717998770613125315
Short name T329
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Oct 25 02:12:53 PM PDT 23
Finished Oct 25 02:12:58 PM PDT 23
Peak memory 201288 kb
Host smart-ea48a4db-cd71-4db1-969a-c6ae6e2d6c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68053470192688273177354785373383199931289019373255177222683717998770613125315 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.68053470192688273177354785373383199931289019373255177222683717998770613125315
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.42981857808328195895519886496395072629454610626917958434483180785972253542645
Short name T534
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.81 seconds
Started Oct 25 02:12:57 PM PDT 23
Finished Oct 25 02:13:01 PM PDT 23
Peak memory 201256 kb
Host smart-00cedca9-3c7e-47ea-9604-9bce3fdfa908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42981857808328195895519886496395072629454610626917958434483180785972253542645 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.42981857808328195895519886496395072629454610626917958434483180785972253542645
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.80722440841606442668081083378626883486111610906239873472413009757715490754580
Short name T392
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.48 seconds
Started Oct 25 02:12:54 PM PDT 23
Finished Oct 25 02:12:59 PM PDT 23
Peak memory 201260 kb
Host smart-358070b9-0186-4e38-ac0a-a7ef440922e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80722440841606442668081083378626883486111610906239873472413009757715490754580 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.80722440841606442668081083378626883486111610906239873472413009757715490754580
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.86627382709666012119101047746460992581323859161883160043975573658766323329019
Short name T130
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Oct 25 02:12:52 PM PDT 23
Finished Oct 25 02:12:56 PM PDT 23
Peak memory 201076 kb
Host smart-3f9ec7ed-2bd2-4a7b-8076-4df3d30aedec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86627382709666012119101047746460992581323859161883160043975573658766323329019 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_smoke.86627382709666012119101047746460992581323859161883160043975573658766323329019
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.75392980956351266306716022833753965299563147436012644019971796320441994303140
Short name T377
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.53 seconds
Started Oct 25 02:12:57 PM PDT 23
Finished Oct 25 02:15:12 PM PDT 23
Peak memory 201536 kb
Host smart-6e31faeb-bfdc-4006-be72-f81db736a3db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75392980956351266306716022833753965299563147436012644019971796320441994303140 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.75392980956351266306716022833753965299563147436012644019971796320441994303140
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.73065877302430498871416156015937944757518175375498036831813782695779338805979
Short name T450
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 25 02:12:56 PM PDT 23
Finished Oct 25 02:13:01 PM PDT 23
Peak memory 201296 kb
Host smart-53680702-8a93-4af2-bdb5-14b030c4e09d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73065877302430498871416156015937944757518175375498036831813782695779338805979 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.7306587730243049887141615601593794475751817537549803683181378
2695779338805979
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.55071037980671863752010641482243108681337272409281939578651073117041538589898
Short name T600
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 25 02:12:13 PM PDT 23
Finished Oct 25 02:12:17 PM PDT 23
Peak memory 201104 kb
Host smart-367f54b4-bb82-462a-b685-1c2ce734d834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55071037980671863752010641482243108681337272409281939578651073117041538589898 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.55071037980671863752010641482243108681337272409281939578651073117041538589898
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.95950444124293020723097453767531928949799890625036715468500777720315754013950
Short name T479
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 25 02:12:21 PM PDT 23
Finished Oct 25 02:12:27 PM PDT 23
Peak memory 201296 kb
Host smart-70bae22d-5e9d-4698-bf5a-63237020e55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95950444124293020723097453767531928949799890625036715468500777720315754013950 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.95950444124293020723097453767531928949799890625036715468500777720315754013950
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.84133018458465846206051221744943229702169978743144247998530759787153614175721
Short name T499
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.09 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:15:20 PM PDT 23
Peak memory 201432 kb
Host smart-f47feb47-3b5c-4d94-a1f5-b599e1db2704
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84133018458465846206051221744943229702169978743144247998530759787153614175721 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.841330184584658462060512217449432297021699787431442479985307597
87153614175721
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3337014185431715085726917452615357848475637097479468265913656173102666547012
Short name T548
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Oct 25 02:13:09 PM PDT 23
Finished Oct 25 02:13:16 PM PDT 23
Peak memory 201308 kb
Host smart-6ba07294-8e3c-4230-86bc-358a25625204
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337014185431715085726917452615357848475637097479468265913656173102666547012 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.33370141854317150857269174526153578484756370974794682659136561
73102666547012
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.80550501860775128471265220631863214649508858910480301303025211622216014707025
Short name T27
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:21 PM PDT 23
Peak memory 201232 kb
Host smart-90faad3d-c460-4027-8039-6203150b3491
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80550501860775128471265220631863214649508858910480301303025211622216014707025 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.80550501860775128471265220631863214649508858910480301303025211622216014707025
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.33614972940379704836155778945624528675430024302399815181416022446339376866379
Short name T483
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Oct 25 02:13:00 PM PDT 23
Finished Oct 25 02:13:05 PM PDT 23
Peak memory 201128 kb
Host smart-ef017e95-6413-471f-a2ee-dc26c2bcba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33614972940379704836155778945624528675430024302399815181416022446339376866379 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.33614972940379704836155778945624528675430024302399815181416022446339376866379
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.101746092333837530551761440325889095176446754185211588990107704618060236714483
Short name T64
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Oct 25 02:12:59 PM PDT 23
Finished Oct 25 02:13:04 PM PDT 23
Peak memory 201160 kb
Host smart-bc036213-b62e-4159-8e9b-23e068d6033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101746092333837530551761440325889095176446754185211588990107704618060236714483 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.101746092333837530551761440325889095176446754185211588990107704618060236714483
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.75028932807053328350236308321198935951183178615217509402721290726877400671225
Short name T552
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Oct 25 02:13:04 PM PDT 23
Finished Oct 25 02:13:08 PM PDT 23
Peak memory 200588 kb
Host smart-3b6c7ea6-bee0-4c6d-b256-b196afcb45d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75028932807053328350236308321198935951183178615217509402721290726877400671225 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.75028932807053328350236308321198935951183178615217509402721290726877400671225
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.73496485097096087096278661366417386133568001717796330456759721010850026483
Short name T360
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.73 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201220 kb
Host smart-ff8c6ab9-4ed2-47ed-8205-b66258f3a56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73496485097096087096278661366417386133568001717796330456759721010850026483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_
base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.73496485097096087096278661366417386133568001717796330456759721010850026483
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.73775743009725988812198768380607797727933694680322932735615575596007385672772
Short name T150
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Oct 25 02:13:04 PM PDT 23
Finished Oct 25 02:13:08 PM PDT 23
Peak memory 201180 kb
Host smart-c1951d9b-d117-4452-9cd3-921722d9bd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73775743009725988812198768380607797727933694680322932735615575596007385672772 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_smoke.73775743009725988812198768380607797727933694680322932735615575596007385672772
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.35094412924559085985166614807830039772579937878920293213919079889621283048471
Short name T631
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.1 seconds
Started Oct 25 02:12:15 PM PDT 23
Finished Oct 25 02:14:30 PM PDT 23
Peak memory 201504 kb
Host smart-2c9c1b19-b8b2-4847-8bb3-32439015ee1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35094412924559085985166614807830039772579937878920293213919079889621283048471 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.35094412924559085985166614807830039772579937878920293213919079889621283048471
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.109173215583023243736977011814405180135942338395077719457304523060179548413372
Short name T383
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201220 kb
Host smart-289d6ded-9eda-4ee3-97b5-21528350ce84
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109173215583023243736977011814405180135942338395077719457304523060179548413372 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.109173215583023243736977011814405180135942338395077719457304
523060179548413372
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.3536875811643174936007217683187925993147231124249371124198368054855927267939
Short name T657
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Oct 25 02:13:10 PM PDT 23
Finished Oct 25 02:13:15 PM PDT 23
Peak memory 201248 kb
Host smart-e3a9b186-9fc9-4d79-adaa-1ca5f430462f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536875811643174936007217683187925993147231124249371124198368054855927267939 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.3536875811643174936007217683187925993147231124249371124198368054855927267939
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.76214531753555371897937640383106942989123263106799914205146320713602057183920
Short name T472
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 201248 kb
Host smart-a2dc014c-95d8-4fb2-844c-b8597ea4502c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76214531753555371897937640383106942989123263106799914205146320713602057183920 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.76214531753555371897937640383106942989123263106799914205146320713602057183920
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.67630467123894833172765914055006795232925353320403456763481744919391631334301
Short name T476
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.33 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:16:17 PM PDT 23
Peak memory 201440 kb
Host smart-1a7fcd39-fe86-47a1-956a-0296f92e3158
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67630467123894833172765914055006795232925353320403456763481744919391631334301 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.676304671238948331727659140550067952329253533204034567634817449
19391631334301
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.110916628534896119850017189484208839444002355913401837410583066612912671574116
Short name T523
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Oct 25 02:12:20 PM PDT 23
Finished Oct 25 02:12:29 PM PDT 23
Peak memory 201220 kb
Host smart-263dec9b-dc39-4f8d-9f25-13651fcce0a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110916628534896119850017189484208839444002355913401837410583066612912671574116 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.110916628534896119850017189484208839444002355913401837410583
066612912671574116
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.672285394755348441845623361121581820892134993343267078266528601816623290553
Short name T340
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201160 kb
Host smart-7488a3fd-a3f9-4981-8896-1ff0fc8c016b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672285394755348441845623361121581820892134993343267078266528601816623290553 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.672285394755348441845623361121581820892134993343267078266528601816623290553
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.101188893449761085463976567958627365344274184044022439420234778330367530601145
Short name T192
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:26 PM PDT 23
Peak memory 201200 kb
Host smart-1b8e4eee-b55d-498e-acc4-fc21fc0e6f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101188893449761085463976567958627365344274184044022439420234778330367530601145 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.101188893449761085463976567958627365344274184044022439420234778330367530601145
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.55801161153320894533437820480982837751049022730161854235764369134786512045275
Short name T585
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Oct 25 02:12:17 PM PDT 23
Finished Oct 25 02:12:22 PM PDT 23
Peak memory 201224 kb
Host smart-a3e1b454-a259-44e2-b679-205853e7e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55801161153320894533437820480982837751049022730161854235764369134786512045275 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.55801161153320894533437820480982837751049022730161854235764369134786512045275
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.7517098004743511493381281612753237860446102049407019539118564495585421345985
Short name T315
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Oct 25 02:12:19 PM PDT 23
Finished Oct 25 02:12:25 PM PDT 23
Peak memory 201156 kb
Host smart-d28ef7f5-68ab-432a-b699-0636076bf360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7517098004743511493381281612753237860446102049407019539118564495585421345985 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.7517098004743511493381281612753237860446102049407019539118564495585421345985
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.110077511204525397629701167934516464638418803968581886707134650834952233642156
Short name T628
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Oct 25 02:12:16 PM PDT 23
Finished Oct 25 02:12:21 PM PDT 23
Peak memory 201168 kb
Host smart-dd1274bc-1fc7-4291-8010-cfd70ba106fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110077511204525397629701167934516464638418803968581886707134650834952233642156 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.110077511204525397629701167934516464638418803968581886707134650834952233642156
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.87929822996563829252361850468922617700662598586050314704022702537027921112209
Short name T566
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Oct 25 02:12:14 PM PDT 23
Finished Oct 25 02:12:19 PM PDT 23
Peak memory 201264 kb
Host smart-8dfa640d-730a-4736-ab99-617a4f5d0297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87929822996563829252361850468922617700662598586050314704022702537027921112209 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_smoke.87929822996563829252361850468922617700662598586050314704022702537027921112209
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.2171552735976429615929405894258638919534015869607366379378346869930002898720
Short name T38
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.2 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:15:28 PM PDT 23
Peak memory 201536 kb
Host smart-8aae3bd9-8b08-4238-a750-cfe9fcb08516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171552735976429615929405894258638919534015869607366379378346869930002898720 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.2171552735976429615929405894258638919534015869607366379378346869930002898720
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.38759821843458994058269785612633328597423784475449774245373233953241277935144
Short name T20
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201232 kb
Host smart-cfc63169-4f83-46a7-b11e-39fc41091330
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38759821843458994058269785612633328597423784475449774245373233953241277935144 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.3875982184345899405826978561263332859742378447544977424537323
3953241277935144
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.37424128940111513015787835943646725790077946037034042059764909260769699898464
Short name T404
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201268 kb
Host smart-7f3c05c8-878c-4df8-9d90-de73f964c1f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37424128940111513015787835943646725790077946037034042059764909260769699898464 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.37424128940111513015787835943646725790077946037034042059764909260769699898464
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.12555713102010248799585605316719769890965179327136685121166119659150872815584
Short name T412
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:13:20 PM PDT 23
Peak memory 201392 kb
Host smart-cd8c49be-8020-4cbf-8446-feeff6168299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12555713102010248799585605316719769890965179327136685121166119659150872815584 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.12555713102010248799585605316719769890965179327136685121166119659150872815584
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.45750828816432735070699539694764903911601496103729528800337938182827148031590
Short name T217
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.11 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:16:21 PM PDT 23
Peak memory 201332 kb
Host smart-8ac5ea27-b5fc-4896-ac69-e52e34d2d0ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45750828816432735070699539694764903911601496103729528800337938182827148031590 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.457508288164327350706995396947649039116014961037295288003379381
82827148031590
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.44013128761168396296906499557991918291136053591763690251213758784912616307059
Short name T469
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Oct 25 02:13:10 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201140 kb
Host smart-27222902-b707-406d-8f77-651e5403e0ed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44013128761168396296906499557991918291136053591763690251213758784912616307059 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.4401312876116839629690649955799191829113605359176369025121375
8784912616307059
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.114880566458890283860981237185745755774296746095391327040611997316265783218
Short name T577
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.18 seconds
Started Oct 25 02:13:19 PM PDT 23
Finished Oct 25 02:13:26 PM PDT 23
Peak memory 201116 kb
Host smart-d94b31b6-bca8-4353-aed1-a7c3c884aaed
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114880566458890283860981237185745755774296746095391327040611997316265783218 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.114880566458890283860981237185745755774296746095391327040611997316265783218
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.73946101647649273620411893422101653904742125355154365196284063597438454390900
Short name T459
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201224 kb
Host smart-8d9361ec-1c7e-43b5-82e5-78f4e720b8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73946101647649273620411893422101653904742125355154365196284063597438454390900 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.73946101647649273620411893422101653904742125355154365196284063597438454390900
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.7171032069312686260637904654334796594901074615897593719613272591979712744803
Short name T639
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:13:17 PM PDT 23
Peak memory 201256 kb
Host smart-c7e85d2c-ff53-4dd4-a380-735e03b11042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7171032069312686260637904654334796594901074615897593719613272591979712744803 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.7171032069312686260637904654334796594901074615897593719613272591979712744803
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.38987154269044707672821946047476316584814718876040959481004771779547225481393
Short name T188
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Oct 25 02:13:14 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201220 kb
Host smart-4c9b5138-daf3-450d-bf6b-183cb4d1a0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38987154269044707672821946047476316584814718876040959481004771779547225481393 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.38987154269044707672821946047476316584814718876040959481004771779547225481393
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.73947736489660840049438954951582322410828477774014946580124992997833570184478
Short name T569
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:16 PM PDT 23
Peak memory 201272 kb
Host smart-77879935-6567-46e5-91f0-ee858f510905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73947736489660840049438954951582322410828477774014946580124992997833570184478 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.73947736489660840049438954951582322410828477774014946580124992997833570184478
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.33793190359158382802531914138036992194185876738052479911484547085729815048636
Short name T180
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Oct 25 02:13:11 PM PDT 23
Finished Oct 25 02:13:15 PM PDT 23
Peak memory 201148 kb
Host smart-f5c8090b-60fa-4497-9581-f4a9f11e5e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33793190359158382802531914138036992194185876738052479911484547085729815048636 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_smoke.33793190359158382802531914138036992194185876738052479911484547085729815048636
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.65062730846467744212958480945180668046956646287634799468295944991691207679854
Short name T99
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.08 seconds
Started Oct 25 02:13:12 PM PDT 23
Finished Oct 25 02:15:26 PM PDT 23
Peak memory 201416 kb
Host smart-74371190-96ab-4d39-b3ab-36b46b12a103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65062730846467744212958480945180668046956646287634799468295944991691207679854 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.65062730846467744212958480945180668046956646287634799468295944991691207679854
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.41790487447975462588807417217026097953656850446247574932452103730470460645010
Short name T22
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Oct 25 02:13:13 PM PDT 23
Finished Oct 25 02:13:18 PM PDT 23
Peak memory 201316 kb
Host smart-f287b4f4-77ef-4329-b722-e4e027e5063b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41790487447975462588807417217026097953656850446247574932452103730470460645010 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.4179048744797546258880741721702609795365685044624757493245210
3730470460645010
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest
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