Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
25.61	25.61	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	25.61	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
25.61	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	5	15	75.00
Crosses	62	56	6	9.68

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	1	1	50.00	100	1	1	2
cp_precondition_key0_in_sel	2	1	1	50.00	100	1	1	2
cp_precondition_key1_in_sel	2	1	1	50.00	100	1	1	2
cp_precondition_key2_in_sel	2	1	1	50.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	1	1	50.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	30	1	3.23	100	1	1	0
cross_key_combinations_combo_detection_sel	31	26	5	16.13	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800

1

T20

8

T22

8

T24

8

auto[1]

200

1

T20

4

T24

4

T25

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T20

6

T22

8

T24

6

auto[1]

300

1

T20

6

T24

6

T25

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

700

1

T20

6

T22

8

T24

6

auto[1]

300

1

T20

6

T24

6

T25

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

200

1

T20

4

T24

4

T25

4

auto[1]

800

1

T20

8

T22

8

T24

8

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

12

T22

8

T24

12

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

12

T22

8

T24

12

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

12

T22

8

T24

12

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

12

T22

8

T24

12

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

12

T22

8

T24

12

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

600

1

T20

4

T22

8

T24

4

auto[1]

400

1

T20

8

T24

8

T25

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	30	1	3.23	30
Automatically Generated Cross Bins	31	30	1	3.23	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[0]]	[auto[0]]	[auto[1]]	*	*	--	--	4
[auto[0]]	[auto[1]]	*	*	*	--	--	8
[auto[1]]	[auto[0]]	*	*	*	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	*	*	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1000

1

T20

12

T22

8

T24

12

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	26	5	16.13	26
Automatically Generated Cross Bins	31	26	5	16.13	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Element holes

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[0]]	[auto[1]]	[auto[0]]	*	*	--	--	4
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2
[auto[1]]	[auto[0]]	[auto[0]]	*	*	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	*	*	--	--	4

Uncovered bins

cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

400

1

T22

8

T26

8

T28

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

200

1

T20

4

T24

4

T25

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

100

1

T20

2

T24

2

T25

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

100

1

T20

2

T24

2

T25

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

200

1

T20

4

T24

4

T25

4

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded