Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_in_out_inverted_vseq::sysrst_ctrl_key_invert_ctl_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/seq_lib/sysrst_ctrl_in_out_inverted_vseq.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_invert_ctl_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_invert_ctl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_invert_ctl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	48	0	48	100.00
Crosses	44	0	44	100.00

Variables for Group Instance sysrst_ctrl_key_invert_ctl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cfg.vif.ac_present	2	0	2	100.00	100	1	1	2
cfg.vif.bat_disable	2	0	2	100.00	100	1	1	2
cfg.vif.key0_in	2	0	2	100.00	100	1	1	2
cfg.vif.key0_out	2	0	2	100.00	100	1	1	2
cfg.vif.key1_in	2	0	2	100.00	100	1	1	2
cfg.vif.key1_out	2	0	2	100.00	100	1	1	2
cfg.vif.key2_in	2	0	2	100.00	100	1	1	2
cfg.vif.key2_out	2	0	2	100.00	100	1	1	2
cfg.vif.lid_open	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_in	2	0	2	100.00	100	1	1	2
cfg.vif.pwrb_out	2	0	2	100.00	100	1	1	2
cfg.vif.z3_wakeup	2	0	2	100.00	100	1	1	2
cp_ac_present	2	0	2	100.00	100	1	1	2
cp_bat_disable	2	0	2	100.00	100	1	1	2
cp_key0_in	2	0	2	100.00	100	1	1	2
cp_key0_out	2	0	2	100.00	100	1	1	2
cp_key1_in	2	0	2	100.00	100	1	1	2
cp_key1_out	2	0	2	100.00	100	1	1	2
cp_key2_in	2	0	2	100.00	100	1	1	2
cp_key2_out	2	0	2	100.00	100	1	1	2
cp_lid_open	2	0	2	100.00	100	1	1	2
cp_pwrb_in	2	0	2	100.00	100	1	1	2
cp_pwrb_out	2	0	2	100.00	100	1	1	2
cp_z3_wakeup	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_key_invert_ctl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key0_inXval	4	0	4	100.00	100	1	1	0
key0_outXval	4	0	4	100.00	100	1	1	0
key1_inXval	4	0	4	100.00	100	1	1	0
key1_outXval	4	0	4	100.00	100	1	1	0
key2_inXval	4	0	4	100.00	100	1	1	0
key2_outXval	4	0	4	100.00	100	1	1	0
pwrb_inXval	4	0	4	100.00	100	1	1	0
pwrb_outXval	4	0	4	100.00	100	1	1	0
ac_presentXval	4	0	4	100.00	100	1	1	0
bat_disableXval	2	0	2	100.00	100	1	1	0
lid_openXval	4	0	4	100.00	100	1	1	0
z3_wakeupXval	2	0	2	100.00	100	1	1	0

Summary for Variable cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

850

1

T20

8

T43

9

T24

8

auto[1]

1150

1

T20

12

T43

11

T24

12

---

Summary for Variable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800

1

T20

8

T43

8

T24

8

auto[1]

1200

1

T20

12

T43

12

T24

12

---

Summary for Variable cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800

1

T20

10

T43

6

T24

10

auto[1]

1200

1

T20

10

T43

14

T24

10

---

Summary for Variable cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T20

10

T43

12

T24

10

auto[1]

900

1

T20

10

T43

8

T24

10

---

Summary for Variable cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T20

12

T43

12

T24

12

auto[1]

800

1

T20

8

T43

8

T24

8

---

Summary for Variable cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

11

T43

9

T24

11

auto[1]

1000

1

T20

9

T43

11

T24

9

---

Summary for Variable cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T20

12

T43

9

T24

12

auto[1]

950

1

T20

8

T43

11

T24

8

---

Summary for Variable cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1250

1

T20

12

T43

13

T24

12

auto[1]

750

1

T20

8

T43

7

T24

8

---

Summary for Variable cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T20

9

T43

12

T24

9

auto[1]

950

1

T20

11

T43

8

T24

11

---

Summary for Variable cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1100

1

T20

11

T43

11

T24

11

auto[1]

900

1

T20

9

T43

9

T24

9

---

Summary for Variable cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T20

11

T43

7

T24

11

auto[1]

1100

1

T20

9

T43

13

T24

9

---

Summary for Variable cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cfg.vif.z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

10

T43

10

T24

10

auto[1]

1000

1

T20

10

T43

10

T24

10

---

Summary for Variable cp_ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T20

9

T43

9

T24

9

auto[1]

1100

1

T20

11

T43

11

T24

11

---

Summary for Variable cp_bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_bat_disable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

800

1

T20

8

T43

8

T24

8

auto[1]

1200

1

T20

12

T43

12

T24

12

---

Summary for Variable cp_key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T20

12

T43

12

T24

12

auto[1]

800

1

T20

8

T43

8

T24

8

---

Summary for Variable cp_key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

600

1

T20

6

T43

6

T24

6

auto[1]

1400

1

T20

14

T43

14

T24

14

---

Summary for Variable cp_key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T20

9

T43

9

T24

9

auto[1]

1100

1

T20

11

T43

11

T24

11

---

Summary for Variable cp_key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T20

12

T43

12

T24

12

auto[1]

800

1

T20

8

T43

8

T24

8

---

Summary for Variable cp_key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T20

9

T43

9

T24

9

auto[1]

1100

1

T20

11

T43

11

T24

11

---

Summary for Variable cp_key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T20

9

T43

9

T24

9

auto[1]

1100

1

T20

11

T43

11

T24

11

---

Summary for Variable cp_lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_lid_open

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

900

1

T20

9

T43

9

T24

9

auto[1]

1100

1

T20

11

T43

11

T24

11

---

Summary for Variable cp_pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1200

1

T20

12

T43

12

T24

12

auto[1]

800

1

T20

8

T43

8

T24

8

---

Summary for Variable cp_pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

10

T43

10

T24

10

auto[1]

1000

1

T20

10

T43

10

T24

10

---

Summary for Variable cp_z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_z3_wakeup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1000

1

T20

10

T43

10

T24

10

auto[1]

1000

1

T20

10

T43

10

T24

10

---

Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_inXval

Bins

cp_key0_in

cfg.vif.key0_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

400

1

T20

5

T43

3

T24

5

auto[0]

auto[1]

800

1

T20

7

T43

9

T24

7

auto[1]

auto[0]

400

1

T20

5

T43

3

T24

5

auto[1]

auto[1]

400

1

T20

3

T43

5

T24

3

---

Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key0_outXval

Bins

cp_key0_out

cfg.vif.key0_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

250

1

T20

2

T43

3

T24

2

auto[0]

auto[1]

350

1

T20

4

T43

3

T24

4

auto[1]

auto[0]

850

1

T20

8

T43

9

T24

8

auto[1]

auto[1]

550

1

T20

6

T43

5

T24

6

---

Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_inXval

Bins

cp_key1_in

cfg.vif.key1_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

550

1

T20

4

T43

7

T24

4

auto[0]

auto[1]

350

1

T20

5

T43

2

T24

5

auto[1]

auto[0]

650

1

T20

8

T43

5

T24

8

auto[1]

auto[1]

450

1

T20

3

T43

6

T24

3

---

Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key1_outXval

Bins

cp_key1_out

cfg.vif.key1_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

600

1

T20

5

T43

7

T24

5

auto[0]

auto[1]

600

1

T20

7

T43

5

T24

7

auto[1]

auto[0]

400

1

T20

6

T43

2

T24

6

auto[1]

auto[1]

400

1

T20

2

T43

6

T24

2

---

Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_inXval

Bins

cp_key2_in

cfg.vif.key2_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

450

1

T20

6

T43

3

T24

6

auto[0]

auto[1]

450

1

T20

3

T43

6

T24

3

auto[1]

auto[0]

600

1

T20

6

T43

6

T24

6

auto[1]

auto[1]

500

1

T20

5

T43

5

T24

5

---

Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for key2_outXval

Bins

cp_key2_out

cfg.vif.key2_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

550

1

T20

6

T43

5

T24

6

auto[0]

auto[1]

350

1

T20

3

T43

4

T24

3

auto[1]

auto[0]

700

1

T20

6

T43

8

T24

6

auto[1]

auto[1]

400

1

T20

5

T43

3

T24

5

---

Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_inXval

Bins

cp_pwrb_in

cfg.vif.pwrb_in

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

750

1

T20

7

T43

8

T24

7

auto[0]

auto[1]

450

1

T20

5

T43

4

T24

5

auto[1]

auto[0]

350

1

T20

4

T43

3

T24

4

auto[1]

auto[1]

450

1

T20

4

T43

5

T24

4

---

Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for pwrb_outXval

Bins

cp_pwrb_out

cfg.vif.pwrb_out

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

550

1

T20

6

T43

5

T24

6

auto[0]

auto[1]

450

1

T20

4

T43

5

T24

4

auto[1]

auto[0]

350

1

T20

5

T43

2

T24

5

auto[1]

auto[1]

650

1

T20

5

T43

8

T24

5

---

Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for ac_presentXval

Bins

cp_ac_present

cfg.vif.ac_present

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

600

1

T20

5

T43

7

T24

5

auto[0]

auto[1]

300

1

T20

4

T43

2

T24

4

auto[1]

auto[0]

250

1

T20

3

T43

2

T24

3

auto[1]

auto[1]

850

1

T20

8

T43

9

T24

8

---

Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for bat_disableXval

Bins

cp_bat_disable

cfg.vif.bat_disable

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

800

1

T20

8

T43

8

T24

8

auto[1]

auto[1]

1200

1

T20

12

T43

12

T24

12

User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded

---

Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for lid_openXval

Bins

cp_lid_open

cfg.vif.lid_open

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

400

1

T20

2

T43

6

T24

2

auto[0]

auto[1]

500

1

T20

7

T43

3

T24

7

auto[1]

auto[0]

650

1

T20

7

T43

6

T24

7

auto[1]

auto[1]

450

1

T20

4

T43

5

T24

4

---

Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	0	2	100.00
Automatically Generated Cross Bins	2	0	2	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for z3_wakeupXval

Bins

cp_z3_wakeup

cfg.vif.z3_wakeup

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

1000

1

T20

10

T43

10

T24

10

auto[1]

auto[1]

1000

1

T20

10

T43

10

T24

10

User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded
invalid1	0	Excluded