Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

99291

1

T15

14

T16

5

T17

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132924	1			T15	23		T16	2		T17	3
values[0x0]	38672	1			T15	5		T16	4		T17	1
values[0x1]	42840	1			T15	6		T16	1		T17	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

126226

1

T15

19

T16

6

T17

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	556	1			T92	3		T95	3		T64	1
valid_sources[0x01]	986	1			T22	3		T26	3		T28	3
valid_sources[0x02]	1715	1			T20	11		T24	11		T25	11
valid_sources[0x03]	1542	1			T15	4		T38	1		T20	4
valid_sources[0x04]	950	1			T20	8		T24	8		T25	8
valid_sources[0x05]	620	1			T87	12		T1	13		T2	1
valid_sources[0x06]	1290	1			T20	5		T21	1		T22	2
valid_sources[0x07]	625	1			T87	3		T1	19		T2	3
valid_sources[0x08]	692	1			T38	5		T41	5		T22	1
valid_sources[0x09]	922	1			T22	4		T26	4		T28	4
valid_sources[0x0a]	1160	1			T20	3		T22	1		T24	3
valid_sources[0x0b]	380	1			T87	6		T2	2		T13	6
valid_sources[0x0c]	1707	1			T20	7		T22	1		T24	7
valid_sources[0x0d]	755	1			T22	8		T26	8		T28	8
valid_sources[0x0e]	5364	1			T15	11		T16	6		T17	3
valid_sources[0x0f]	345	1			T64	2		T1	6		T2	3
valid_sources[0x10]	655	1			T20	3		T24	3		T25	3
valid_sources[0x11]	425	1			T64	4		T87	4		T1	4
valid_sources[0x12]	950	1			T87	9		T1	27		T2	1
valid_sources[0x13]	565	1			T22	2		T26	2		T28	2
valid_sources[0x14]	1102	1			T20	9		T22	1		T24	9
valid_sources[0x15]	865	1			T20	5		T24	5		T25	5
valid_sources[0x16]	590	1			T20	5		T24	5		T25	5
valid_sources[0x17]	450	1			T64	4		T87	9		T1	3
valid_sources[0x18]	760	1			T20	7		T24	7		T25	7
valid_sources[0x19]	1050	1			T20	4		T24	4		T25	4
valid_sources[0x1a]	500	1			T20	2		T24	2		T25	2
valid_sources[0x1b]	280	1			T87	1		T1	6		T3	6
valid_sources[0x1c]	334	1			T22	2		T26	2		T112	2
valid_sources[0x1d]	655	1			T20	2		T22	7		T24	2
valid_sources[0x1e]	1630	1			T20	17		T22	4		T24	17
valid_sources[0x1f]	515	1			T87	13		T1	9		T3	9
valid_sources[0x20]	705	1			T22	1		T26	1		T28	1
valid_sources[0x21]	1176	1			T20	2		T22	3		T24	2
valid_sources[0x22]	612	1			T22	2		T26	2		T28	2
valid_sources[0x23]	540	1			T87	8		T1	4		T2	2
valid_sources[0x24]	760	1			T1	23		T2	2		T3	23
valid_sources[0x25]	1904	1			T22	13		T26	13		T28	13
valid_sources[0x26]	430	1			T1	12		T3	12		T4	12
valid_sources[0x27]	857	1			T22	5		T26	5		T28	5
valid_sources[0x28]	280	1			T1	7		T3	7		T4	7
valid_sources[0x29]	555	1			T87	2		T1	13		T3	13
valid_sources[0x2a]	440	1			T1	16		T2	1		T3	16
valid_sources[0x2b]	515	1			T20	4		T24	4		T25	4
valid_sources[0x2c]	1065	1			T22	4		T26	4		T28	4
valid_sources[0x2d]	1525	1			T20	8		T24	8		T25	8
valid_sources[0x2e]	220	1			T20	1		T24	1		T25	1
valid_sources[0x2f]	1290	1			T38	2		T41	2		T43	2
valid_sources[0x30]	625	1			T20	2		T22	5		T24	2
valid_sources[0x31]	930	1			T20	4		T24	4		T25	4
valid_sources[0x32]	675	1			T64	1		T87	8		T1	13
valid_sources[0x33]	540	1			T20	2		T24	2		T25	2
valid_sources[0x34]	1585	1			T20	11		T22	8		T24	11
valid_sources[0x35]	395	1			T87	3		T65	10		T1	4
valid_sources[0x36]	430	1			T1	12		T3	12		T4	12
valid_sources[0x37]	1049	1			T15	2		T38	3		T41	3
valid_sources[0x38]	770	1			T22	4		T26	4		T28	4
valid_sources[0x39]	665	1			T20	9		T24	9		T25	9
valid_sources[0x3a]	564	1			T20	2		T22	2		T24	2
valid_sources[0x3b]	712	1			T22	11		T26	11		T28	11
valid_sources[0x3c]	950	1			T22	7		T26	7		T28	7
valid_sources[0x3d]	540	1			T20	1		T22	2		T24	1
valid_sources[0x3e]	1140	1			T20	1		T24	1		T25	1
valid_sources[0x3f]	2047	1			T20	11		T22	12		T24	11
valid_sources[0x40]	520	1			T20	3		T24	3		T25	3
valid_sources[0x41]	445	1			T87	6		T1	3		T2	1
valid_sources[0x42]	580	1			T20	1		T24	1		T25	1
valid_sources[0x43]	455	1			T22	1		T26	1		T28	1
valid_sources[0x44]	290	1			T87	1		T2	4		T13	1
valid_sources[0x45]	1300	1			T20	14		T22	5		T24	14
valid_sources[0x46]	820	1			T22	4		T26	4		T28	4
valid_sources[0x47]	815	1			T87	20		T1	7		T2	2
valid_sources[0x48]	405	1			T87	1		T1	10		T3	10
valid_sources[0x49]	1189	1			T20	5		T43	2		T22	2
valid_sources[0x4a]	380	1			T87	2		T1	11		T3	11
valid_sources[0x4b]	430	1			T22	1		T26	1		T28	1
valid_sources[0x4c]	1468	1			T20	13		T24	13		T25	13
valid_sources[0x4d]	620	1			T87	8		T65	1		T1	15
valid_sources[0x4e]	815	1			T22	7		T26	7		T28	7
valid_sources[0x4f]	790	1			T20	10		T24	10		T25	10
valid_sources[0x50]	445	1			T109	6		T93	6		T152	6
valid_sources[0x51]	620	1			T20	1		T22	1		T24	1
valid_sources[0x52]	220	1			T1	6		T2	1		T3	6
valid_sources[0x53]	520	1			T20	5		T24	5		T25	5
valid_sources[0x54]	929	1			T92	7		T95	7		T87	14
valid_sources[0x55]	1285	1			T20	6		T22	14		T24	6
valid_sources[0x56]	940	1			T20	2		T24	2		T25	2
valid_sources[0x57]	1116	1			T22	8		T26	8		T28	8
valid_sources[0x58]	520	1			T87	10		T1	4		T2	2
valid_sources[0x59]	745	1			T20	3		T24	3		T25	3
valid_sources[0x5a]	1565	1			T20	5		T22	16		T24	5
valid_sources[0x5b]	1215	1			T20	16		T24	16		T25	16
valid_sources[0x5c]	1745	1			T20	23		T24	23		T25	23
valid_sources[0x5d]	470	1			T87	5		T1	3		T2	8
valid_sources[0x5e]	1249	1			T15	2		T38	2		T20	2
valid_sources[0x5f]	992	1			T22	2		T26	2		T28	2
valid_sources[0x60]	235	1			T87	6		T65	1		T13	6
valid_sources[0x61]	365	1			T87	3		T1	4		T2	1
valid_sources[0x62]	1550	1			T20	19		T24	19		T25	19
valid_sources[0x63]	175	1			T87	5		T65	2		T13	5
valid_sources[0x64]	1090	1			T20	6		T22	6		T24	6
valid_sources[0x65]	1645	1			T38	4		T20	4		T41	4
valid_sources[0x66]	280	1			T20	1		T24	1		T25	1
valid_sources[0x67]	1260	1			T15	5		T20	10		T22	3
valid_sources[0x68]	647	1			T92	1		T95	1		T64	9
valid_sources[0x69]	422	1			T22	4		T26	4		T28	4
valid_sources[0x6a]	565	1			T87	4		T65	6		T1	9
valid_sources[0x6b]	665	1			T20	2		T24	2		T25	2
valid_sources[0x6c]	290	1			T1	6		T2	2		T3	6
valid_sources[0x6d]	530	1			T20	4		T24	4		T25	4
valid_sources[0x6e]	1274	1			T22	13		T26	13		T112	6
valid_sources[0x6f]	495	1			T20	2		T24	2		T25	2
valid_sources[0x70]	780	1			T22	6		T26	6		T28	6
valid_sources[0x71]	720	1			T1	23		T2	1		T3	23
valid_sources[0x72]	966	1			T20	4		T21	2		T22	3
valid_sources[0x73]	560	1			T20	2		T24	2		T25	2
valid_sources[0x74]	810	1			T20	1		T22	6		T24	1
valid_sources[0x75]	1660	1			T38	11		T41	11		T43	5
valid_sources[0x76]	760	1			T20	6		T21	3		T23	3
valid_sources[0x77]	1380	1			T20	1		T22	5		T24	1
valid_sources[0x78]	1342	1			T20	3		T22	1		T24	3
valid_sources[0x79]	840	1			T20	1		T24	1		T25	1
valid_sources[0x7a]	620	1			T22	1		T26	1		T28	1
valid_sources[0x7b]	871	1			T22	9		T26	9		T28	9
valid_sources[0x7c]	785	1			T20	2		T24	2		T25	2
valid_sources[0x7d]	615	1			T22	1		T26	1		T28	1
valid_sources[0x7e]	860	1			T20	10		T24	10		T25	10
valid_sources[0x7f]	1957	1			T17	2		T38	6		T40	2
valid_sources[0x80]	415	1			T20	2		T24	2		T25	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56449

1

T15

9

T16

2

T17

1

values[0x0]

all_enables

biggest_size

23727

1

T15

3

T16

3

T38

12

values[0x1]

all_enables

biggest_size

19115

1

T15

2

T38

6

T20

32