Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.75	96.43	91.86		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	81.68	89.13	80.95		66.67	85.00	86.67
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	81.68	89.13	80.95		66.67	85.00	86.67
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	81.68	89.13	80.95		66.67	85.00	86.67
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	81.85	89.13	80.95		66.67	85.00	87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	81.85	89.13	80.95		66.67	85.00	87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	81.85	89.13	80.95		66.67	85.00	87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	81.85	89.13	80.95		66.67	85.00	87.50
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	84.92	89.13	90.48		66.67	85.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	84.92	89.13	90.48		66.67	85.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	84.92	89.13	90.48		66.67	85.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	84.92	89.13	90.48		66.67	85.00	93.33
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	85.00	89.13	90.48		66.67	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	85.00	89.13	90.48		66.67	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	85.00	89.13	90.48		66.67	85.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	86.62	91.30	80.95		83.33	90.00	87.50
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	89.13	93.02	86.67		83.33	88.89	93.75
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	89.81	93.48	88.89		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	89.89	93.48	88.89		83.33	90.00	93.75
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	95.37	97.83	90.48		100.00	95.24	93.33
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	95.37	97.83	90.48		100.00	95.24	93.33
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	97.71	100.00	95.24		100.00	100.00	93.33
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
85.00	89.13

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
89.89	93.48

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
81.85	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
85.00	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
85.00	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
81.85	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
81.85	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
86.62	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
81.85	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
89.81	93.48

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
81.68	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
81.68	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
81.68	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
84.92	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
84.92	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
84.92	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
84.92	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
89.13	93.02

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	40	93.02
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
95.37	97.83

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
97.71	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
95.37	97.83

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
95.37	90.48

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
97.71	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
95.37	90.48

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T20,T22,T24
1	Covered	T15,T16,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T24
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T22,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T22,T24

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T22,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T20,T22,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T22,T24
0	1	Covered	T92,T95
1	0	Covered	T92,T95

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T22,T24
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T22,T24
1	-	Covered	T20,T22,T24

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
85.00	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
81.85	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
85.00	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
85.00	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
81.85	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
81.85	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
86.62	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
81.85	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T16,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T21,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T21,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T21,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T24
1	0	Covered	T15,T17,T38
1	1	Covered	T20,T21,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T24
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T23
0	1	Covered	T20,T21,T24
1	0	Covered	T92,T95

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T21,T23
1	-	Covered	T20,T21,T24

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T92,T95
1	Covered	T15,T16,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T92,T93,T94

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T92,T93,T94

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T92,T93,T94

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T92,T95
1	0	Covered	T92,T95
1	1	Covered	T92,T93,T94

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T92,T93,T94
0	1	Covered	T92,T95
1	0	Covered	T92,T95

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T92,T93,T94
0	1	Covered	T92,T95
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T92,T93,T94
1	-	Covered	T92,T95

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.13	86.67

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T38,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T38,T20
1	1	Covered	T15,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Unreachable
1	0	Covered	T15,T18,T19

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
81.68	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
81.68	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
81.68	80.95

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
84.92	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
84.92	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
84.92	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
84.92	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T16,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T21,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T21,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T20,T21,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T23
1	0	Covered	T15,T16,T17
1	1	Covered	T20,T21,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T23
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T21,T23
0	1	Covered	T20,T21,T23
1	0	Covered	T92,T95

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T21,T23
1	-	Covered	T20,T21,T23

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.81	88.89

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	17	89.47
Logical	19	17	89.47
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T38,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T38,T20
1	1	Covered	T15,T38,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T38,T20
1	1	Covered	T15,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Unreachable
1	0	Covered	T15,T18,T19

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.89	88.89

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	17	89.47
Logical	19	17	89.47
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T15,T38,T20
1	Covered	T15,T16,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T38,T20
1	0	Covered	T15,T16,T17
1	1	Covered	T15,T16,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T15,T16,T17
1	Covered	T15,T18,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T38,T20
1	1	Covered	T15,T18,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T18,T19
0	1	Unreachable
1	0	Covered	T15,T18,T19

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T20,T21,T24
DetectSt	168	Covered	T20,T21,T24
IdleSt	163	Covered	T15,T16,T17
StableSt	191	Covered	T20,T21,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T20,T21,T24
DebounceSt->IdleSt	163	Covered	T20,T21,T23
DetectSt->IdleSt	186	Covered	T92,T95
DetectSt->StableSt	191	Covered	T20,T21,T24
IdleSt->DebounceSt	148	Covered	T20,T21,T24
StableSt->IdleSt	206	Covered	T20,T21,T24

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
85.00	85.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
81.85	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
85.00	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
85.00	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
81.85	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
81.85	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
86.62	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
81.85	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.89	90.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
89.81	90.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
81.68	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
81.68	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
81.68	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
84.92	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
84.92	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
84.92	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
84.92	85.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
95.37	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
97.71	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
95.37	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T21,T24
0	1	Covered	T20,T21,T24
0	0	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T20,T21,T24
0	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T20,T21,T24
IdleSt	0	-	-	-	-	-	-	Covered	T15,T16,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T92,T95
DebounceSt	-	0	1	1	-	-	-	Covered	T20,T21,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T21,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T20,T21,T24
DetectSt	-	-	-	-	1	-	-	Covered	T92,T95
DetectSt	-	-	-	-	0	1	-	Covered	T20,T21,T24
DetectSt	-	-	-	-	0	0	-	Covered	T20,T22,T24
StableSt	-	-	-	-	-	-	1	Covered	T20,T21,T24
StableSt	-	-	-	-	-	-	0	Covered	T20,T21,T23
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
89.13	88.89

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T18,T19
0	1	Covered	T15,T18,T19
0	0	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T18,T19
0	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T18,T19
IdleSt	0	-	-	-	-	-	-	Covered	T15,T38,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T92,T95
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T18,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T92,T95
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T18,T19
DetectSt	-	-	-	-	1	-	-	Covered	T92,T95
DetectSt	-	-	-	-	0	1	-	Covered	T15,T18,T19
DetectSt	-	-	-	-	0	0	-	Covered	T92,T93,T94
StableSt	-	-	-	-	-	-	1	Covered	T15,T18,T19
StableSt	-	-	-	-	-	-	0	Covered	T15,T18,T19
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	63017032	4594	0	0
CntIncr_A	63017032	222867	0	0
CntNoWrap_A	63017032	52826496	0	0
DetectStDropOut_A	63017032	10	0	0
DetectedOut_A	63017032	106524	0	0
DetectedPulseOut_A	63017032	2143	0	0
DisabledIdleSt_A	63017032	50610382	0	0
DisabledNoDetection_A	63017032	50643559	0	0
EnterDebounceSt_A	63017032	2419	0	0
EnterDetectSt_A	63017032	2175	0	0
EnterStableSt_A	63017032	2143	0	0
PulseIsPulse_A	63017032	2143	0	0
StayInStableSt	63017032	104026	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	21813588	25100	0	0
gen_high_event_sva.HighLevelEvent_A	12118660	10166910	0	0
gen_high_level_sva.HighLevelEvent_A	41203444	34567494	0	0
gen_low_level_sva.LowLevelEvent_A	21813588	18300438	0	0
gen_not_sticky_sva.StableStDropOut_A	55745836	1600	0	0
gen_sticky_sva.StableStDropOut_A	7271196	9600	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	4594	0	0
T20	17445	4	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	4	0	0
T25	0	4	0	0
T28	23657	0	0	0
T29	0	4	0	0
T32	0	4	0	0
T33	0	4	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	4	0	0
T63	494	0	0	0
T90	627	4	0	0
T91	627	4	0	0
T92	7721	26	0	0
T93	0	2	0	0
T94	0	2	0	0
T96	0	4	0	0
T97	0	4	0	0
T98	0	4	0	0
T99	0	4	0	0
T100	0	4	0	0
T101	0	4	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	4	0	0
T130	0	4	0	0
T131	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	222867	0	0
T20	17445	170	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	170	0	0
T25	0	170	0	0
T28	23657	0	0	0
T29	0	170	0	0
T32	0	170	0	0
T33	0	170	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	81	0	0
T63	494	0	0	0
T90	627	81	0	0
T91	627	81	0	0
T92	7721	838	0	0
T93	0	21	0	0
T94	0	21	0	0
T96	0	81	0	0
T97	0	81	0	0
T98	0	81	0	0
T99	0	81	0	0
T100	0	81	0	0
T101	0	81	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	170	0	0
T130	0	170	0	0
T131	0	170	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	52826496	0	0
T15	26962	16530	0	0
T16	10478	52	0	0
T17	22984	12558	0	0
T20	453570	390377	0	0
T21	21242	10797	0	0
T38	13598	3172	0	0
T39	10478	52	0	0
T40	22984	12558	0	0
T41	13598	3172	0	0
T42	10998	572	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	10	0	0
T48	5185	0	0	0
T92	38605	5	0	0
T95	38605	5	0	0
T118	2515	0	0	0
T119	3135	0	0	0
T120	2015	0	0	0
T125	5185	0	0	0
T126	118285	0	0	0
T127	3135	0	0	0
T128	118285	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	106524	0	0
T20	17445	152	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	152	0	0
T25	0	152	0	0
T28	23657	0	0	0
T29	0	152	0	0
T32	0	152	0	0
T33	0	152	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	8	0	0
T63	494	0	0	0
T90	627	8	0	0
T91	627	8	0	0
T92	7721	443	0	0
T93	0	80	0	0
T94	0	80	0	0
T96	0	8	0	0
T97	0	8	0	0
T98	0	8	0	0
T99	0	8	0	0
T100	0	8	0	0
T101	0	8	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	152	0	0
T130	0	152	0	0
T131	0	152	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	2143	0	0
T20	17445	2	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	2	0	0
T25	0	2	0	0
T28	23657	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	2	0	0
T63	494	0	0	0
T90	627	2	0	0
T91	627	2	0	0
T92	7721	7	0	0
T93	0	1	0	0
T94	0	1	0	0
T96	0	2	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	50610382	0	0
T15	26962	15765	0	0
T16	10478	52	0	0
T17	22984	12558	0	0
T20	453570	370795	0	0
T21	21242	7520	0	0
T38	13598	3172	0	0
T39	10478	52	0	0
T40	22984	12558	0	0
T41	13598	3172	0	0
T42	10998	572	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	50643559	0	0
T15	26962	15791	0	0
T16	10478	78	0	0
T17	22984	12584	0	0
T20	453570	371000	0	0
T21	21242	7538	0	0
T38	13598	3198	0	0
T39	10478	78	0	0
T40	22984	12584	0	0
T41	13598	3198	0	0
T42	10998	598	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	2419	0	0
T20	17445	2	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	2	0	0
T25	0	2	0	0
T28	23657	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	2	0	0
T63	494	0	0	0
T90	627	2	0	0
T91	627	2	0	0
T92	7721	15	0	0
T93	0	1	0	0
T94	0	1	0	0
T96	0	2	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	2175	0	0
T20	17445	2	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	2	0	0
T25	0	2	0	0
T28	23657	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	2	0	0
T63	494	0	0	0
T90	627	2	0	0
T91	627	2	0	0
T92	7721	11	0	0
T93	0	1	0	0
T94	0	1	0	0
T96	0	2	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	2143	0	0
T20	17445	2	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	2	0	0
T25	0	2	0	0
T28	23657	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	2	0	0
T63	494	0	0	0
T90	627	2	0	0
T91	627	2	0	0
T92	7721	7	0	0
T93	0	1	0	0
T94	0	1	0	0
T96	0	2	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	2143	0	0
T20	17445	2	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	2	0	0
T25	0	2	0	0
T28	23657	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	2	0	0
T63	494	0	0	0
T90	627	2	0	0
T91	627	2	0	0
T92	7721	7	0	0
T93	0	1	0	0
T94	0	1	0	0
T96	0	2	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	63017032	104026	0	0
T20	17445	150	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	150	0	0
T25	0	150	0	0
T28	23657	0	0	0
T29	0	150	0	0
T32	0	150	0	0
T33	0	150	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	6	0	0
T63	494	0	0	0
T90	627	6	0	0
T91	627	6	0	0
T92	7721	436	0	0
T93	0	78	0	0
T94	0	78	0	0
T96	0	6	0	0
T97	0	6	0	0
T98	0	6	0	0
T99	0	6	0	0
T100	0	6	0	0
T101	0	6	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T129	0	150	0	0
T130	0	150	0	0
T131	0	150	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21813588	25100	0	0
T15	4148	20	0	0
T16	1612	0	0	0
T17	4420	5	0	0
T20	157005	204	0	0
T21	7353	13	0	0
T22	94628	72	0	0
T23	0	13	0	0
T24	0	187	0	0
T38	4707	48	0	0
T39	3627	0	0	0
T40	7956	5	0	0
T41	4707	48	0	0
T42	3807	20	0	0
T43	2470	54	0	0
T44	2015	0	0	0
T45	0	5	0	0
T61	0	25	0	0
T63	0	4	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12118660	10166910	0	0
T15	5185	3185	0	0
T16	2015	15	0	0
T17	4420	2420	0	0
T20	87225	75125	0	0
T21	4085	2085	0	0
T38	2615	615	0	0
T39	2015	15	0	0
T40	4420	2420	0	0
T41	2615	615	0	0
T42	2115	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41203444	34567494	0	0
T15	17629	10829	0	0
T16	6851	51	0	0
T17	15028	8228	0	0
T20	296565	255425	0	0
T21	13889	7089	0	0
T38	8891	2091	0	0
T39	6851	51	0	0
T40	15028	8228	0	0
T41	8891	2091	0	0
T42	7191	391	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	21813588	18300438	0	0
T15	9333	5733	0	0
T16	3627	27	0	0
T17	7956	4356	0	0
T20	157005	135225	0	0
T21	7353	3753	0	0
T38	4707	1107	0	0
T39	3627	27	0	0
T40	7956	4356	0	0
T41	4707	1107	0	0
T42	3807	207	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55745836	1600	0	0
T20	17445	2	0	0
T21	817	0	0	0
T22	23657	0	0	0
T23	817	0	0	0
T24	17445	2	0	0
T25	0	2	0	0
T28	23657	0	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	2	0	0
T41	523	0	0	0
T42	423	0	0	0
T43	494	0	0	0
T44	403	0	0	0
T45	884	0	0	0
T62	627	2	0	0
T63	494	0	0	0
T90	627	2	0	0
T91	627	2	0	0
T92	7721	5	0	0
T96	0	2	0	0
T97	0	2	0	0
T98	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0
T102	523	0	0	0
T103	523	0	0	0
T104	423	0	0	0
T105	494	0	0	0
T106	423	0	0	0
T119	0	2	0	0
T129	0	2	0	0
T130	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7271196	9600	0	0
T15	3111	192	0	0
T16	1209	0	0	0
T17	2652	0	0	0
T18	0	192	0	0
T19	0	192	0	0
T20	52335	0	0	0
T21	2451	0	0	0
T35	0	192	0	0
T36	0	192	0	0
T37	0	192	0	0
T38	1569	0	0	0
T39	1209	0	0	0
T40	2652	0	0	0
T41	1569	0	0	0
T42	1269	0	0	0
T46	0	192	0	0
T47	0	192	0	0
T48	0	192	0	0
T49	0	192	0	0