Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T17,T40
1	0	Covered	T15,T17,T40
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T17,T40
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T17,T40

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	125837	0	0
SrcPulseCheck_M	2147483647	127146	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	125837
T20	4047448	80
T21	1632376	0
T22	5488664	144
T23	1632376	0
T24	4047448	80
T25	0	80
T26	0	144
T28	1372166	144
T29	0	80
T30	0	144
T31	0	144
T32	0	80
T41	1177832	0
T42	951752	0
T43	1110688	0
T44	906136	0
T45	1989536	0
T62	352820	16
T63	277672	0
T90	352820	16
T91	352820	16
T92	215076	15
T93	0	1
T96	0	16
T97	0	16
T98	0	16
T99	0	16
T100	0	16
T101	0	16
T102	294458	0
T103	294458	0
T104	237938	0
T105	277672	0
T106	237938	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	127146
T20	4047448	80
T21	1632376	0
T22	5488664	144
T23	1632376	0
T24	4047448	80
T25	0	80
T26	0	144
T28	1372166	144
T29	0	80
T30	0	144
T31	0	144
T32	0	80
T41	1177832	0
T42	951752	0
T43	1110688	0
T44	906136	0
T45	1989536	0
T62	352820	16
T63	277672	0
T90	352820	16
T91	352820	16
T92	7721	15
T93	0	1
T96	0	16
T97	0	16
T98	0	16
T99	0	16
T100	0	16
T101	0	16
T102	294458	0
T103	294458	0
T104	237938	0
T105	277672	0
T106	237938	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T40,T20
1	0	Covered	T17,T40,T20
1	1	Covered	T64,T87,T13

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T40,T20
1	0	Covered	T64,T87,T13
1	1	Covered	T17,T40,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1932	0	0
SrcPulseCheck_M	754515696	1962	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1932
T17	884	1
T20	17445	5
T21	817	0
T22	0	9
T24	0	5
T25	0	5
T26	0	9
T38	523	0
T39	403	0
T40	884	1
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	0	1
T107	0	1
T108	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1962
T17	247808	1
T20	488486	5
T21	203230	0
T22	0	9
T24	0	5
T25	0	5
T26	0	9
T38	146706	0
T39	112864	0
T40	247808	1
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	0	1
T107	0	1
T108	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T40,T20
1	0	Covered	T17,T40,T20
1	1	Covered	T64,T87,T13

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T40,T20
1	0	Covered	T64,T87,T13
1	1	Covered	T17,T40,T20

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1932	0	0
SrcPulseCheck_M	2727417	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1932
T17	247808	1
T20	488486	5
T21	203230	0
T22	0	9
T24	0	5
T25	0	5
T26	0	9
T38	146706	0
T39	112864	0
T40	247808	1
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	0	1
T107	0	1
T108	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1932
T17	884	1
T20	17445	5
T21	817	0
T22	0	9
T24	0	5
T25	0	5
T26	0	9
T38	523	0
T39	403	0
T40	884	1
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	0	1
T107	0	1
T108	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1197	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1197
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1147	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1147
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1147	0	0
SrcPulseCheck_M	2727417	1147	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1147
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1147
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1238	0	0
SrcPulseCheck_M	754515696	1268	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1238
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1268
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1238	0	0
SrcPulseCheck_M	2727417	1238	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1238
T15	130789	2
T16	112864	0
T17	247808	0
T18	0	2
T19	0	2
T20	488486	0
T21	203230	0
T35	0	2
T36	0	2
T37	0	2
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	2
T47	0	2
T48	0	2
T92	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1238
T15	1037	2
T16	403	0
T17	884	0
T18	0	2
T19	0	2
T20	17445	0
T21	817	0
T35	0	2
T36	0	2
T37	0	2
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	2
T47	0	2
T48	0	2
T92	0	4

Line Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T15,T18,T19
1	1	Covered	T64,T87,T13

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T18,T19
1	0	Covered	T64,T87,T13
1	1	Covered	T15,T18,T19

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	800	0	0
SrcPulseCheck_M	754515696	830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	800
T15	1037	1
T16	403	0
T17	884	0
T18	0	1
T19	0	1
T20	17445	0
T21	817	0
T35	0	1
T36	0	1
T37	0	1
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0
T46	0	1
T47	0	1
T48	0	1
T49	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	830
T15	130789	1
T16	112864	0
T17	247808	0
T18	0	1
T19	0	1
T20	488486	0
T21	203230	0
T35	0	1
T36	0	1
T37	0	1
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0
T46	0	1
T47	0	1
T48	0	1
T49	0	1

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T20,T22
1	0	Covered	T15,T20,T22
1	1	Covered	T20,T24,T25

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T15,T20,T22
1	0	Covered	T20,T24,T25
1	1	Covered	T15,T20,T22

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1510	0	0
SrcPulseCheck_M	754515696	1552	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1510
T15	1037	1
T16	403	0
T17	884	0
T18	0	1
T20	17445	7
T21	817	0
T22	0	8
T24	0	7
T25	0	7
T26	0	8
T28	0	8
T29	0	7
T30	0	8
T38	523	0
T39	403	0
T40	884	0
T41	523	0
T42	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1552
T15	130789	1
T16	112864	0
T17	247808	0
T18	0	1
T20	488486	7
T21	203230	0
T22	0	8
T24	0	7
T25	0	7
T26	0	8
T28	0	8
T29	0	7
T30	0	8
T38	146706	0
T39	112864	0
T40	247808	0
T41	146706	0
T42	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T43,T24
1	0	Covered	T20,T43,T24
1	1	Covered	T20,T43,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T43,T24
1	0	Covered	T20,T43,T24
1	1	Covered	T20,T43,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	3105	0	0
SrcPulseCheck_M	754515696	3135	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	3105
T20	17445	20
T21	817	0
T22	23657	0
T23	817	0
T24	17445	20
T25	0	20
T29	0	20
T41	523	0
T42	423	0
T43	494	20
T44	403	0
T45	884	0
T61	0	20
T63	0	20
T105	0	20
T110	0	20
T111	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	3135
T20	488486	20
T21	203230	0
T22	662426	0
T23	203230	0
T24	488486	20
T25	0	20
T29	0	20
T41	146706	0
T42	118546	0
T43	138342	20
T44	112864	0
T45	247808	0
T61	0	20
T63	0	20
T105	0	20
T110	0	20
T111	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T43,T24
1	0	Covered	T20,T43,T24
1	1	Covered	T20,T43,T24

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T43,T24
1	0	Covered	T20,T43,T24
1	1	Covered	T20,T43,T24

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	3105	0	0
SrcPulseCheck_M	2727417	3105	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	3105
T20	488486	20
T21	203230	0
T22	662426	0
T23	203230	0
T24	488486	20
T25	0	20
T29	0	20
T41	146706	0
T42	118546	0
T43	138342	20
T44	112864	0
T45	247808	0
T61	0	20
T63	0	20
T105	0	20
T110	0	20
T111	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	3105
T20	17445	20
T21	817	0
T22	23657	0
T23	817	0
T24	17445	20
T25	0	20
T29	0	20
T41	523	0
T42	423	0
T43	494	20
T44	403	0
T45	884	0
T61	0	20
T63	0	20
T105	0	20
T110	0	20
T111	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5170	0	0
SrcPulseCheck_M	754515696	5200	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5170
T20	17445	41
T21	817	0
T22	23657	0
T24	0	41
T25	0	41
T38	523	20
T39	403	0
T40	884	0
T41	523	20
T42	423	0
T43	494	1
T44	403	0
T61	0	1
T63	0	1
T110	0	1
T111	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5200
T20	488486	41
T21	203230	0
T22	662426	0
T24	0	41
T25	0	41
T38	146706	20
T39	112864	0
T40	247808	0
T41	146706	20
T42	118546	0
T43	138342	1
T44	112864	0
T61	0	1
T63	0	1
T110	0	1
T111	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5170	0	0
SrcPulseCheck_M	2727417	5170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5170
T20	488486	41
T21	203230	0
T22	662426	0
T24	0	41
T25	0	41
T38	146706	20
T39	112864	0
T40	247808	0
T41	146706	20
T42	118546	0
T43	138342	1
T44	112864	0
T61	0	1
T63	0	1
T110	0	1
T111	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5170
T20	17445	41
T21	817	0
T22	23657	0
T24	0	41
T25	0	41
T38	523	20
T39	403	0
T40	884	0
T41	523	20
T42	423	0
T43	494	1
T44	403	0
T61	0	1
T63	0	1
T110	0	1
T111	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T38,T40
1	0	Covered	T17,T38,T40
1	1	Covered	T38,T20,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T38,T40
1	0	Covered	T38,T20,T41
1	1	Covered	T17,T38,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	5967	0	0
SrcPulseCheck_M	754515696	5997	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	5967
T17	884	1
T20	17445	46
T21	817	0
T22	0	9
T24	0	46
T38	523	20
T39	403	0
T40	884	1
T41	523	20
T42	423	0
T43	494	1
T44	403	0
T45	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	5997
T17	247808	1
T20	488486	46
T21	203230	0
T22	0	9
T24	0	46
T38	146706	20
T39	112864	0
T40	247808	1
T41	146706	20
T42	118546	0
T43	138342	1
T44	112864	0
T45	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T38,T40
1	0	Covered	T17,T38,T40
1	1	Covered	T38,T20,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T17,T38,T40
1	0	Covered	T38,T20,T41
1	1	Covered	T17,T38,T40

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	5967	0	0
SrcPulseCheck_M	2727417	5967	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	5967
T17	247808	1
T20	488486	46
T21	203230	0
T22	0	9
T24	0	46
T38	146706	20
T39	112864	0
T40	247808	1
T41	146706	20
T42	118546	0
T43	138342	1
T44	112864	0
T45	0	1
T61	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	5967
T17	884	1
T20	17445	46
T21	817	0
T22	0	9
T24	0	46
T38	523	20
T39	403	0
T40	884	1
T41	523	20
T42	423	0
T43	494	1
T44	403	0
T45	0	1
T61	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	4925	0	0
SrcPulseCheck_M	754515696	4955	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	4925
T20	17445	40
T21	817	0
T22	23657	0
T24	0	40
T25	0	40
T38	523	20
T39	403	0
T40	884	0
T41	523	20
T42	423	0
T43	494	0
T44	403	0
T102	0	20
T103	0	20
T112	0	20
T113	0	20
T114	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	4955
T20	488486	40
T21	203230	0
T22	662426	0
T24	0	40
T25	0	40
T38	146706	20
T39	112864	0
T40	247808	0
T41	146706	20
T42	118546	0
T43	138342	0
T44	112864	0
T102	0	20
T103	0	20
T112	0	20
T113	0	20
T114	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T38,T20,T41
1	0	Covered	T38,T20,T41
1	1	Covered	T38,T20,T41

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	4925	0	0
SrcPulseCheck_M	2727417	4925	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	4925
T20	488486	40
T21	203230	0
T22	662426	0
T24	0	40
T25	0	40
T38	146706	20
T39	112864	0
T40	247808	0
T41	146706	20
T42	118546	0
T43	138342	0
T44	112864	0
T102	0	20
T103	0	20
T112	0	20
T113	0	20
T114	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	4925
T20	17445	40
T21	817	0
T22	23657	0
T24	0	40
T25	0	40
T38	523	20
T39	403	0
T40	884	0
T41	523	20
T42	423	0
T43	494	0
T44	403	0
T102	0	20
T103	0	20
T112	0	20
T113	0	20
T114	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T23
1	0	Covered	T20,T21,T23
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T23
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T21,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1246	0	0
SrcPulseCheck_M	754515696	1276	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1246
T20	17445	1
T21	817	1
T22	23657	0
T23	817	1
T24	17445	1
T25	0	1
T27	0	1
T29	0	1
T32	0	1
T33	0	1
T34	0	1
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1276
T20	488486	1
T21	203230	1
T22	662426	0
T23	203230	1
T24	488486	1
T25	0	1
T27	0	1
T29	0	1
T32	0	1
T33	0	1
T34	0	1
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T23
1	0	Covered	T20,T21,T23
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T23
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T21,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1246	0	0
SrcPulseCheck_M	2727417	1246	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1246
T20	488486	1
T21	203230	1
T22	662426	0
T23	203230	1
T24	488486	1
T25	0	1
T27	0	1
T29	0	1
T32	0	1
T33	0	1
T34	0	1
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1246
T20	17445	1
T21	817	1
T22	23657	0
T23	817	1
T24	17445	1
T25	0	1
T27	0	1
T29	0	1
T32	0	1
T33	0	1
T34	0	1
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T22
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1924	0	0
SrcPulseCheck_M	754515696	1974	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1924
T20	17445	6
T21	817	1
T22	23657	9
T23	817	1
T24	17445	6
T25	0	6
T26	0	9
T27	0	1
T28	0	9
T29	0	6
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1974
T20	488486	6
T21	203230	1
T22	662426	9
T23	203230	1
T24	488486	6
T25	0	6
T26	0	9
T27	0	1
T28	0	9
T29	0	6
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T22
1	0	Covered	T20,T21,T22
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T22
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1924	0	0
SrcPulseCheck_M	2727417	1924	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1924
T20	488486	6
T21	203230	1
T22	662426	9
T23	203230	1
T24	488486	6
T25	0	6
T26	0	9
T27	0	1
T28	0	9
T29	0	6
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1924
T20	17445	6
T21	817	1
T22	23657	9
T23	817	1
T24	17445	6
T25	0	6
T26	0	9
T27	0	1
T28	0	9
T29	0	6
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1254	0	0
SrcPulseCheck_M	754515696	1289	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1254
T28	23657	0
T62	627	5
T63	494	0
T90	627	5
T91	627	5
T92	0	2
T96	0	5
T97	0	5
T98	0	5
T99	0	5
T100	0	5
T101	0	5
T102	523	0
T103	523	0
T104	423	0
T105	494	0
T106	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1289
T28	662426	0
T62	175783	5
T63	138342	0
T90	175783	5
T91	175783	5
T92	0	2
T96	0	5
T97	0	5
T98	0	5
T99	0	5
T100	0	5
T101	0	5
T102	146706	0
T103	146706	0
T104	118546	0
T105	138342	0
T106	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1259	0	0
SrcPulseCheck_M	2727417	1259	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1259
T28	662426	0
T62	175783	5
T63	138342	0
T90	175783	5
T91	175783	5
T92	0	2
T96	0	5
T97	0	5
T98	0	5
T99	0	5
T100	0	5
T101	0	5
T102	146706	0
T103	146706	0
T104	118546	0
T105	138342	0
T106	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1259
T28	23657	0
T62	627	5
T63	494	0
T90	627	5
T91	627	5
T92	0	2
T96	0	5
T97	0	5
T98	0	5
T99	0	5
T100	0	5
T101	0	5
T102	523	0
T103	523	0
T104	423	0
T105	494	0
T106	423	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1192	0	0
SrcPulseCheck_M	754515696	1222	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1192
T28	23657	0
T62	627	3
T63	494	0
T90	627	3
T91	627	3
T92	0	1
T96	0	3
T97	0	3
T98	0	3
T99	0	3
T100	0	3
T101	0	3
T102	523	0
T103	523	0
T104	423	0
T105	494	0
T106	423	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1222
T28	662426	0
T62	175783	3
T63	138342	0
T90	175783	3
T91	175783	3
T92	0	1
T96	0	3
T97	0	3
T98	0	3
T99	0	3
T100	0	3
T101	0	3
T102	146706	0
T103	146706	0
T104	118546	0
T105	138342	0
T106	118546	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T62,T90,T91
1	0	Covered	T62,T90,T91
1	1	Covered	T62,T90,T91

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1192	0	0
SrcPulseCheck_M	2727417	1192	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1192
T28	662426	0
T62	175783	3
T63	138342	0
T90	175783	3
T91	175783	3
T92	0	1
T96	0	3
T97	0	3
T98	0	3
T99	0	3
T100	0	3
T101	0	3
T102	146706	0
T103	146706	0
T104	118546	0
T105	138342	0
T106	118546	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1192
T28	23657	0
T62	627	3
T63	494	0
T90	627	3
T91	627	3
T92	0	1
T96	0	3
T97	0	3
T98	0	3
T99	0	3
T100	0	3
T101	0	3
T102	523	0
T103	523	0
T104	423	0
T105	494	0
T106	423	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T93,T94
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T93,T94

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1052	0	0
SrcPulseCheck_M	754515696	1102	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1052
T1	0	19
T48	1037	0
T64	0	2
T87	0	13
T92	7721	11
T93	506	1
T94	0	1
T95	0	11
T115	0	1
T116	0	1
T117	0	1
T118	503	0
T119	627	0
T120	403	0
T121	23657	0
T122	414	0
T123	627	0
T124	414	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1102
T48	130789	0
T64	0	2
T65	0	2
T87	0	13
T92	215076	11
T93	141936	1
T94	0	1
T95	0	11
T115	0	1
T116	0	1
T117	0	1
T118	140863	0
T119	175783	0
T120	112864	0
T121	662426	0
T122	116176	0
T123	175783	0
T124	116176	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T93,T94
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T93,T94

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1052	0	0
SrcPulseCheck_M	2727417	1052	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1052
T1	0	19
T48	130789	0
T64	0	2
T87	0	13
T92	215076	11
T93	141936	1
T94	0	1
T95	0	11
T115	0	1
T116	0	1
T117	0	1
T118	140863	0
T119	175783	0
T120	112864	0
T121	662426	0
T122	116176	0
T123	175783	0
T124	116176	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1052
T1	0	19
T48	1037	0
T64	0	2
T87	0	13
T92	7721	11
T93	506	1
T94	0	1
T95	0	11
T115	0	1
T116	0	1
T117	0	1
T118	503	0
T119	627	0
T120	403	0
T121	23657	0
T122	414	0
T123	627	0
T124	414	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	982	0	0
SrcPulseCheck_M	754515696	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	982
T1	0	20
T3	0	20
T4	0	20
T13	0	9
T14	0	9
T48	1037	0
T60	0	9
T64	0	2
T87	0	9
T92	7721	11
T95	7721	11
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1012
T1	0	20
T3	0	20
T4	0	20
T6	0	1
T13	0	9
T48	130789	0
T64	0	2
T65	0	2
T87	0	9
T92	215076	11
T95	215076	11
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	982	0	0
SrcPulseCheck_M	2727417	982	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	982
T1	0	20
T3	0	20
T4	0	20
T13	0	9
T14	0	9
T48	130789	0
T60	0	9
T64	0	2
T87	0	9
T92	215076	11
T95	215076	11
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	982
T1	0	20
T3	0	20
T4	0	20
T13	0	9
T14	0	9
T48	1037	0
T60	0	9
T64	0	2
T87	0	9
T92	7721	11
T95	7721	11
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1127	0	0
SrcPulseCheck_M	754515696	1177	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1127
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	1037	0
T60	0	16
T64	0	2
T87	0	16
T92	7721	11
T95	7721	11
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1177
T1	0	20
T3	0	20
T4	0	20
T6	0	2
T13	0	16
T48	130789	0
T64	0	2
T65	0	2
T87	0	16
T92	215076	11
T95	215076	11
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1127	0	0
SrcPulseCheck_M	2727417	1127	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1127
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	130789	0
T60	0	16
T64	0	2
T87	0	16
T92	215076	11
T95	215076	11
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1127
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	1037	0
T60	0	16
T64	0	2
T87	0	16
T92	7721	11
T95	7721	11
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1012	0	0
SrcPulseCheck_M	754515696	1042	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1012
T1	0	20
T3	0	20
T4	0	20
T13	0	10
T14	0	10
T48	1037	0
T60	0	10
T64	0	2
T87	0	10
T92	7721	11
T95	7721	11
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1042
T1	0	20
T3	0	20
T4	0	20
T6	0	1
T13	0	10
T48	130789	0
T64	0	2
T65	0	2
T87	0	10
T92	215076	11
T95	215076	11
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1012	0	0
SrcPulseCheck_M	2727417	1012	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1012
T1	0	20
T3	0	20
T4	0	20
T13	0	10
T14	0	10
T48	130789	0
T60	0	10
T64	0	2
T87	0	10
T92	215076	11
T95	215076	11
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1012
T1	0	20
T3	0	20
T4	0	20
T13	0	10
T14	0	10
T48	1037	0
T60	0	10
T64	0	2
T87	0	10
T92	7721	11
T95	7721	11
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T93,T94
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T93,T94

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1023	0	0
SrcPulseCheck_M	754515696	1053	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1023
T1	0	20
T48	1037	0
T64	0	2
T87	0	11
T92	7721	9
T93	506	1
T94	0	1
T95	0	9
T115	0	1
T116	0	1
T117	0	1
T118	503	0
T119	627	0
T120	403	0
T121	23657	0
T122	414	0
T123	627	0
T124	414	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1053
T48	130789	0
T64	0	2
T65	0	2
T87	0	11
T92	215076	9
T93	141936	1
T94	0	1
T95	0	9
T115	0	1
T116	0	1
T117	0	1
T118	140863	0
T119	175783	0
T120	112864	0
T121	662426	0
T122	116176	0
T123	175783	0
T124	116176	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T93,T94
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T93,T94
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T93,T94

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1023	0	0
SrcPulseCheck_M	2727417	1023	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1023
T1	0	20
T48	130789	0
T64	0	2
T87	0	11
T92	215076	9
T93	141936	1
T94	0	1
T95	0	9
T115	0	1
T116	0	1
T117	0	1
T118	140863	0
T119	175783	0
T120	112864	0
T121	662426	0
T122	116176	0
T123	175783	0
T124	116176	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1023
T1	0	20
T48	1037	0
T64	0	2
T87	0	11
T92	7721	9
T93	506	1
T94	0	1
T95	0	9
T115	0	1
T116	0	1
T117	0	1
T118	503	0
T119	627	0
T120	403	0
T121	23657	0
T122	414	0
T123	627	0
T124	414	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1123	0	0
SrcPulseCheck_M	754515696	1173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1123
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	1037	0
T60	0	16
T64	0	2
T87	0	16
T92	7721	9
T95	7721	9
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1173
T1	0	20
T3	0	20
T4	0	20
T6	0	2
T13	0	16
T48	130789	0
T64	0	2
T65	0	2
T87	0	16
T92	215076	9
T95	215076	9
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1123	0	0
SrcPulseCheck_M	2727417	1123	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1123
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	130789	0
T60	0	16
T64	0	2
T87	0	16
T92	215076	9
T95	215076	9
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1123
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	1037	0
T60	0	16
T64	0	2
T87	0	16
T92	7721	9
T95	7721	9
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1118	0	0
SrcPulseCheck_M	754515696	1168	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1118
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	1037	0
T60	0	16
T64	0	2
T87	0	16
T92	7721	9
T95	7721	9
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1168
T1	0	20
T3	0	20
T4	0	20
T6	0	2
T13	0	16
T48	130789	0
T64	0	2
T65	0	2
T87	0	16
T92	215076	9
T95	215076	9
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1118	0	0
SrcPulseCheck_M	2727417	1118	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1118
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	130789	0
T60	0	16
T64	0	2
T87	0	16
T92	215076	9
T95	215076	9
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1118
T1	0	20
T3	0	20
T4	0	20
T13	0	16
T14	0	16
T48	1037	0
T60	0	16
T64	0	2
T87	0	16
T92	7721	9
T95	7721	9
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1048	0	0
SrcPulseCheck_M	754515696	1078	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1048
T1	0	20
T3	0	20
T4	0	20
T13	0	12
T14	0	12
T48	1037	0
T60	0	12
T64	0	2
T87	0	12
T92	7721	9
T95	7721	9
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1078
T1	0	20
T3	0	20
T4	0	20
T6	0	1
T13	0	12
T48	130789	0
T64	0	2
T65	0	2
T87	0	12
T92	215076	9
T95	215076	9
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T92,T95,T64
1	0	Covered	T92,T95,T64
1	1	Covered	T92,T95,T64

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1048	0	0
SrcPulseCheck_M	2727417	1048	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1048
T1	0	20
T3	0	20
T4	0	20
T13	0	12
T14	0	12
T48	130789	0
T60	0	12
T64	0	2
T87	0	12
T92	215076	9
T95	215076	9
T118	140863	0
T119	175783	0
T120	112864	0
T125	130789	0
T126	662426	0
T127	175783	0
T128	662426	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1048
T1	0	20
T3	0	20
T4	0	20
T13	0	12
T14	0	12
T48	1037	0
T60	0	12
T64	0	2
T87	0	12
T92	7721	9
T95	7721	9
T118	503	0
T119	627	0
T120	403	0
T125	1037	0
T126	23657	0
T127	627	0
T128	23657	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1777	0	0
SrcPulseCheck_M	754515696	1827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1777
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1827
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1777	0	0
SrcPulseCheck_M	2727417	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1777
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1777
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1597	0	0
SrcPulseCheck_M	754515696	1627	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1597
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1627
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1597	0	0
SrcPulseCheck_M	2727417	1597	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1597
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1597
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1747	0	0
SrcPulseCheck_M	754515696	1777	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1747
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1777
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1747	0	0
SrcPulseCheck_M	2727417	1747	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1747
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1747
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1692	0	0
SrcPulseCheck_M	754515696	1722	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1692
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1722
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1692	0	0
SrcPulseCheck_M	2727417	1692	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1692
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1692
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1968	0	0
SrcPulseCheck_M	754515696	1998	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1968
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1998
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1968	0	0
SrcPulseCheck_M	2727417	1968	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1968
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1968
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1763	0	0
SrcPulseCheck_M	754515696	1793	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1763
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1793
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1763	0	0
SrcPulseCheck_M	2727417	1763	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1763
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1763
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1738	0	0
SrcPulseCheck_M	754515696	1768	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1738
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1768
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1738	0	0
SrcPulseCheck_M	2727417	1738	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1738
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1738
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1813	0	0
SrcPulseCheck_M	754515696	1863	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1813
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1863
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1813	0	0
SrcPulseCheck_M	2727417	1813	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1813
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1813
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1773	0	0
SrcPulseCheck_M	754515696	1803	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1773
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1803
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1773	0	0
SrcPulseCheck_M	2727417	1773	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1773
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1773
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1663	0	0
SrcPulseCheck_M	754515696	1693	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1663
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1693
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1663	0	0
SrcPulseCheck_M	2727417	1663	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1663
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1663
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1603	0	0
SrcPulseCheck_M	754515696	1633	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1603
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1633
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1603	0	0
SrcPulseCheck_M	2727417	1603	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1603
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1603
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1683	0	0
SrcPulseCheck_M	754515696	1733	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1683
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1733
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T92,T95,T64

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T92,T95,T64
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	754515696	1683	0	0
SrcPulseCheck_M	2727417	1683	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	754515696	1683
T20	488486	5
T21	203230	0
T22	662426	9
T23	203230	0
T24	488486	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2727417	1683
T20	17445	5
T21	817	0
T22	23657	9
T23	817	0
T24	17445	5
T25	0	5
T26	0	9
T28	0	9
T29	0	5
T30	0	9
T31	0	9
T32	0	5
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

Line Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T22,T24
1	1	Covered	T20,T24,T25

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T22,T24
1	0	Covered	T20,T24,T25
1	1	Covered	T20,T22,T24

Branch Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_combo_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	1410	0	0
SrcPulseCheck_M	754515696	1440	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	1410
T20	17445	7
T21	817	0
T22	23657	8
T23	817	0
T24	17445	7
T25	0	7
T26	0	8
T28	0	8
T29	0	7
T30	0	8
T31	0	8
T32	0	7
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1440
T20	488486	7
T21	203230	0
T22	662426	8
T23	203230	0
T24	488486	7
T25	0	7
T26	0	8
T28	0	8
T29	0	7
T30	0	8
T31	0	8
T32	0	7
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T23
1	0	Covered	T20,T21,T23
1	1	Covered	T21,T23,T27

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T15,T16,T17
0	1	Covered	T20,T21,T23
1	0	Covered	T21,T23,T27
1	1	Covered	T20,T21,T23

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00



	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17



	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T15,T16,T17

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2727417	990	0	0
SrcPulseCheck_M	754515696	1022	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2727417	990
T20	17445	1
T21	817	3
T22	23657	0
T23	817	3
T24	17445	1
T25	0	1
T27	0	3
T29	0	1
T32	0	1
T33	0	1
T34	0	3
T41	523	0
T42	423	0
T43	494	0
T44	403	0
T45	884	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	754515696	1022
T20	488486	1
T21	203230	3
T22	662426	0
T23	203230	3
T24	488486	1
T25	0	1
T27	0	3
T29	0	1
T32	0	1
T33	0	1
T34	0	3
T41	146706	0
T42	118546	0
T43	138342	0
T44	112864	0
T45	247808	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc