Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	115145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

99291

1

T16

1

T17

1

T18

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	132924	1			T16	2		T17	3		T18	13
values[0x0]	38672	1			T17	1		T18	2		T39	4
values[0x1]	42840	1			T17	1		T18	6		T39	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88210	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

126226

1

T16

1

T17

3

T18

13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	556	1			T103	3		T104	3		T95	7
valid_sources[0x01]	986	1			T22	3		T23	3		T25	3
valid_sources[0x02]	1715	1			T28	11		T33	11		T36	11
valid_sources[0x03]	1542	1			T22	6		T19	4		T23	6
valid_sources[0x04]	950	1			T28	8		T33	8		T36	8
valid_sources[0x05]	620	1			T95	12		T80	12		T96	12
valid_sources[0x06]	1290	1			T18	1		T22	2		T23	2
valid_sources[0x07]	625	1			T95	3		T80	3		T96	3
valid_sources[0x08]	692	1			T22	1		T23	1		T25	1
valid_sources[0x09]	922	1			T22	4		T23	4		T25	4
valid_sources[0x0a]	1160	1			T22	1		T23	1		T25	1
valid_sources[0x0b]	380	1			T95	6		T80	6		T96	6
valid_sources[0x0c]	1707	1			T22	1		T23	1		T25	1
valid_sources[0x0d]	755	1			T22	8		T23	8		T25	8
valid_sources[0x0e]	5364	1			T16	2		T17	3		T18	10
valid_sources[0x0f]	345	1			T73	2		T74	2		T82	2
valid_sources[0x10]	655	1			T28	3		T33	3		T36	3
valid_sources[0x11]	425	1			T95	4		T73	4		T74	4
valid_sources[0x12]	950	1			T95	9		T80	9		T96	9
valid_sources[0x13]	565	1			T22	2		T23	2		T25	2
valid_sources[0x14]	1102	1			T22	1		T23	1		T25	1
valid_sources[0x15]	865	1			T28	5		T33	5		T36	5
valid_sources[0x16]	590	1			T28	5		T33	5		T36	5
valid_sources[0x17]	450	1			T95	9		T73	4		T74	4
valid_sources[0x18]	760	1			T28	7		T33	7		T36	7
valid_sources[0x19]	1050	1			T28	4		T33	4		T36	4
valid_sources[0x1a]	500	1			T28	2		T33	2		T36	2
valid_sources[0x1b]	280	1			T95	1		T80	1		T96	1
valid_sources[0x1c]	334	1			T22	2		T23	2		T41	2
valid_sources[0x1d]	655	1			T22	7		T23	7		T25	7
valid_sources[0x1e]	1630	1			T22	4		T23	4		T25	4
valid_sources[0x1f]	515	1			T95	13		T80	13		T96	13
valid_sources[0x20]	705	1			T22	1		T23	1		T25	1
valid_sources[0x21]	1176	1			T22	3		T23	3		T25	3
valid_sources[0x22]	612	1			T22	2		T23	2		T25	2
valid_sources[0x23]	540	1			T95	8		T80	8		T96	8
valid_sources[0x24]	760	1			T1	6		T2	23		T3	6
valid_sources[0x25]	1904	1			T22	13		T23	13		T25	13
valid_sources[0x26]	430	1			T2	12		T11	22		T5	12
valid_sources[0x27]	857	1			T22	5		T23	5		T25	5
valid_sources[0x28]	280	1			T2	7		T11	1		T5	7
valid_sources[0x29]	555	1			T1	10		T95	2		T80	2
valid_sources[0x2a]	440	1			T2	16		T11	6		T5	16
valid_sources[0x2b]	515	1			T28	4		T33	4		T36	4
valid_sources[0x2c]	1065	1			T22	4		T23	4		T25	4
valid_sources[0x2d]	1525	1			T28	8		T33	8		T36	8
valid_sources[0x2e]	220	1			T28	1		T33	1		T36	1
valid_sources[0x2f]	1290	1			T22	5		T23	5		T41	2
valid_sources[0x30]	625	1			T22	5		T23	5		T25	5
valid_sources[0x31]	930	1			T28	4		T33	4		T36	4
valid_sources[0x32]	675	1			T1	6		T95	8		T73	1
valid_sources[0x33]	540	1			T28	2		T33	2		T36	2
valid_sources[0x34]	1585	1			T22	8		T23	8		T25	8
valid_sources[0x35]	395	1			T1	1		T95	3		T80	3
valid_sources[0x36]	430	1			T2	12		T11	3		T5	12
valid_sources[0x37]	1049	1			T18	3		T22	2		T19	2
valid_sources[0x38]	770	1			T22	4		T23	4		T25	4
valid_sources[0x39]	665	1			T28	9		T33	9		T36	9
valid_sources[0x3a]	564	1			T22	2		T23	2		T25	2
valid_sources[0x3b]	712	1			T22	11		T23	11		T25	11
valid_sources[0x3c]	950	1			T22	7		T23	7		T25	7
valid_sources[0x3d]	540	1			T22	2		T23	2		T25	2
valid_sources[0x3e]	1140	1			T28	1		T33	1		T36	1
valid_sources[0x3f]	2047	1			T22	12		T23	12		T41	1
valid_sources[0x40]	520	1			T28	3		T33	3		T36	3
valid_sources[0x41]	445	1			T95	6		T80	6		T96	6
valid_sources[0x42]	580	1			T28	1		T33	1		T36	1
valid_sources[0x43]	455	1			T22	1		T23	1		T25	1
valid_sources[0x44]	290	1			T95	1		T80	1		T96	1
valid_sources[0x45]	1300	1			T22	5		T23	5		T25	5
valid_sources[0x46]	820	1			T22	4		T23	4		T25	4
valid_sources[0x47]	815	1			T95	20		T80	20		T96	20
valid_sources[0x48]	405	1			T95	1		T80	1		T96	1
valid_sources[0x49]	1189	1			T22	2		T23	2		T41	2
valid_sources[0x4a]	380	1			T95	2		T80	2		T96	2
valid_sources[0x4b]	430	1			T22	1		T23	1		T25	1
valid_sources[0x4c]	1468	1			T41	3		T28	13		T33	13
valid_sources[0x4d]	620	1			T95	8		T80	8		T96	8
valid_sources[0x4e]	815	1			T22	7		T23	7		T25	7
valid_sources[0x4f]	790	1			T28	10		T33	10		T36	10
valid_sources[0x50]	445	1			T24	6		T117	6		T100	6
valid_sources[0x51]	620	1			T22	1		T23	1		T25	1
valid_sources[0x52]	220	1			T2	6		T11	2		T5	6
valid_sources[0x53]	520	1			T28	5		T33	5		T36	5
valid_sources[0x54]	929	1			T103	7		T104	7		T1	6
valid_sources[0x55]	1285	1			T22	14		T23	14		T25	14
valid_sources[0x56]	940	1			T28	2		T33	2		T36	2
valid_sources[0x57]	1116	1			T22	8		T23	8		T25	8
valid_sources[0x58]	520	1			T1	1		T95	10		T80	10
valid_sources[0x59]	745	1			T28	3		T33	3		T36	3
valid_sources[0x5a]	1565	1			T22	16		T23	16		T25	16
valid_sources[0x5b]	1215	1			T28	16		T33	16		T36	16
valid_sources[0x5c]	1745	1			T28	23		T33	23		T36	23
valid_sources[0x5d]	470	1			T95	5		T80	5		T96	5
valid_sources[0x5e]	1249	1			T22	8		T19	2		T23	8
valid_sources[0x5f]	992	1			T22	2		T23	2		T25	2
valid_sources[0x60]	235	1			T95	6		T80	6		T96	6
valid_sources[0x61]	365	1			T95	3		T80	3		T96	3
valid_sources[0x62]	1550	1			T28	19		T33	19		T36	19
valid_sources[0x63]	175	1			T95	5		T80	5		T96	5
valid_sources[0x64]	1090	1			T22	6		T23	6		T25	6
valid_sources[0x65]	1645	1			T22	5		T23	5		T41	5
valid_sources[0x66]	280	1			T28	1		T33	1		T36	1
valid_sources[0x67]	1260	1			T22	3		T19	5		T23	3
valid_sources[0x68]	647	1			T103	1		T104	1		T73	9
valid_sources[0x69]	422	1			T22	4		T23	4		T25	4
valid_sources[0x6a]	565	1			T95	4		T80	4		T96	4
valid_sources[0x6b]	665	1			T28	2		T33	2		T36	2
valid_sources[0x6c]	290	1			T2	6		T11	12		T5	6
valid_sources[0x6d]	530	1			T28	4		T33	4		T36	4
valid_sources[0x6e]	1274	1			T22	13		T23	13		T41	6
valid_sources[0x6f]	495	1			T28	2		T33	2		T36	2
valid_sources[0x70]	780	1			T22	6		T23	6		T25	6
valid_sources[0x71]	720	1			T2	23		T11	23		T5	23
valid_sources[0x72]	966	1			T18	2		T22	3		T23	3
valid_sources[0x73]	560	1			T28	2		T33	2		T36	2
valid_sources[0x74]	810	1			T22	6		T23	6		T25	6
valid_sources[0x75]	1660	1			T22	2		T23	2		T41	4
valid_sources[0x76]	760	1			T18	3		T26	3		T28	6
valid_sources[0x77]	1380	1			T22	5		T23	5		T25	5
valid_sources[0x78]	1342	1			T22	1		T23	1		T41	11
valid_sources[0x79]	840	1			T28	1		T33	1		T36	1
valid_sources[0x7a]	620	1			T22	1		T23	1		T25	1
valid_sources[0x7b]	871	1			T22	9		T23	9		T25	9
valid_sources[0x7c]	785	1			T28	2		T33	2		T36	2
valid_sources[0x7d]	615	1			T22	1		T23	1		T25	1
valid_sources[0x7e]	860	1			T28	10		T33	10		T36	10
valid_sources[0x7f]	1957	1			T17	2		T22	6		T23	6
valid_sources[0x80]	415	1			T28	2		T33	2		T36	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

56449

1

T16

1

T17

1

T18

5

values[0x0]

all_enables

biggest_size

23727

1

T18

1

T39

3

T22

34

values[0x1]

all_enables

biggest_size

19115

1

T18

1

T22

30

T19

2