Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.00	89.13	90.48		66.67	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.89	93.48	88.89		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.89	93.48	88.89		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	100.00	75.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	93.48	88.89		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.81	93.48	88.89		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	100.00	75.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.13	93.02	86.67		83.33	88.89	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.13	93.02	86.67		83.33	88.89	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.50	100.00	75.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.68	89.13	80.95		66.67	85.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.68	89.13	80.95		66.67	85.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.85	89.13	80.95		66.67	85.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.85	89.13	80.95		66.67	85.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T40
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T40
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T97,T98,T99

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T97,T98,T99

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T97,T98,T99

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T97,T98,T99
1	0	Covered	T16,T18,T40
1	1	Covered	T97,T98,T99

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T97,T98,T99
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T97,T98,T99
0	1	Covered	T97,T98,T99
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T97,T98,T99
1	-	Covered	T97,T98,T99

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T97,T98,T99
DetectSt	168	Covered	T97,T98,T99
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T97,T98,T99

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T97,T98,T99
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T97,T98,T99
IdleSt->DebounceSt	148	Covered	T97,T98,T99
StableSt->IdleSt	206	Covered	T97,T98,T99

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T97,T98,T99
0	1	Covered	T97,T98,T99
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T97,T98,T99
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T97,T98,T99
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T97,T98,T99
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T97,T98,T99
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T97,T98,T99
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T97,T98,T99
StableSt	-	-	-	-	-	-	0	Covered	T97,T98,T99
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	204	0	0
CntIncr_A	2423732	4090	0	0
CntNoWrap_A	2423732	2031761	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	408	0	0
DetectedPulseOut_A	2423732	102	0	0
DisabledIdleSt_A	2423732	2023105	0	0
DisabledNoDetection_A	2423732	2024522	0	0
EnterDebounceSt_A	2423732	102	0	0
EnterDetectSt_A	2423732	102	0	0
EnterStableSt_A	2423732	102	0	0
PulseIsPulse_A	2423732	102	0	0
StayInStableSt	2423732	306	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	3358	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	100	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	204	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	4	0	0
T98	627	4	0	0
T99	0	4	0	0
T105	0	4	0	0
T106	0	4	0	0
T107	0	4	0	0
T108	0	4	0	0
T109	0	4	0	0
T110	0	4	0	0
T111	0	4	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4090	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	81	0	0
T98	627	81	0	0
T99	0	81	0	0
T105	0	81	0	0
T106	0	81	0	0
T107	0	81	0	0
T108	0	81	0	0
T109	0	81	0	0
T110	0	81	0	0
T111	0	81	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031761	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	408	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	8	0	0
T98	627	8	0	0
T99	0	8	0	0
T105	0	8	0	0
T106	0	8	0	0
T107	0	8	0	0
T108	0	8	0	0
T109	0	8	0	0
T110	0	8	0	0
T111	0	8	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	2	0	0
T98	627	2	0	0
T99	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	2	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2023105	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2024522	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	2	0	0
T98	627	2	0	0
T99	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	2	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	2	0	0
T98	627	2	0	0
T99	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	2	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	2	0	0
T98	627	2	0	0
T99	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	2	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	2	0	0
T98	627	2	0	0
T99	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	2	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	306	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	6	0	0
T98	627	6	0	0
T99	0	6	0	0
T105	0	6	0	0
T106	0	6	0	0
T107	0	6	0	0
T108	0	6	0	0
T109	0	6	0	0
T110	0	6	0	0
T111	0	6	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	3358	0	0
T16	423	3	0	0
T17	884	0	0	0
T18	817	2	0	0
T19	1037	5	0	0
T22	23657	11	0	0
T23	23657	11	0	0
T24	479	0	0	0
T25	0	11	0	0
T39	403	0	0	0
T40	414	1	0	0
T41	503	7	0	0
T42	0	6	0	0
T43	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	100	0	0
T35	23657	0	0	0
T36	17445	0	0	0
T45	1037	0	0	0
T97	627	2	0	0
T98	627	2	0	0
T99	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	0	2	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	2	0	0
T111	0	2	0	0
T112	403	0	0	0
T113	414	0	0	0
T114	414	0	0	0
T115	884	0	0	0
T116	523	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T40
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T40
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T19,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T16,T18,T40
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Unreachable
1	0	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T21
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T21
DebounceSt->IdleSt	163	Covered	T103,T104
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T19,T20,T21
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Covered	T103,T104
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T21
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	2002	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5500	0	0
DetectedPulseOut_A	2423732	50	0	0
DisabledIdleSt_A	2423732	2018953	0	0
DisabledNoDetection_A	2423732	2020370	0	0
EnterDebounceSt_A	2423732	54	0	0
EnterDetectSt_A	2423732	50	0	0
EnterStableSt_A	2423732	50	0	0
PulseIsPulse_A	2423732	50	0	0
StayInStableSt	2423732	5450	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	3358	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_sticky_sva.StableStDropOut_A	2423732	4750	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	104	0	0
T19	1037	2	0	0
T20	1037	2	0	0
T21	0	2	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2002	0	0
T19	1037	37	0	0
T20	1037	37	0	0
T21	0	37	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	37	0	0
T46	0	37	0	0
T47	0	37	0	0
T48	0	37	0	0
T49	0	37	0	0
T50	0	37	0	0
T51	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031861	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	634	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5500	0	0
T19	1037	110	0	0
T20	1037	110	0	0
T21	0	110	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	110	0	0
T46	0	110	0	0
T47	0	110	0	0
T48	0	110	0	0
T49	0	110	0	0
T50	0	110	0	0
T51	0	110	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2018953	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	379	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2020370	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	380	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	54	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5450	0	0
T19	1037	109	0	0
T20	1037	109	0	0
T21	0	109	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	109	0	0
T46	0	109	0	0
T47	0	109	0	0
T48	0	109	0	0
T49	0	109	0	0
T50	0	109	0	0
T51	0	109	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	3358	0	0
T16	423	3	0	0
T17	884	0	0	0
T18	817	2	0	0
T19	1037	5	0	0
T22	23657	11	0	0
T23	23657	11	0	0
T24	479	0	0	0
T25	0	11	0	0
T39	403	0	0	0
T40	414	1	0	0
T41	503	7	0	0
T42	0	6	0	0
T43	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4750	0	0
T19	1037	95	0	0
T20	1037	95	0	0
T21	0	95	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	95	0	0
T46	0	95	0	0
T47	0	95	0	0
T48	0	95	0	0
T49	0	95	0	0
T50	0	95	0	0
T51	0	95	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T18,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T18,T40
1	1	Covered	T16,T18,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T19,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T16,T18,T40
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Unreachable
1	0	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T21
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T21
DebounceSt->IdleSt	163	Covered	T103,T104
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T19,T20,T21
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T103,T104
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T21
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	3600	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5800	0	0
DetectedPulseOut_A	2423732	50	0	0
DisabledIdleSt_A	2423732	2018953	0	0
DisabledNoDetection_A	2423732	2020370	0	0
EnterDebounceSt_A	2423732	54	0	0
EnterDetectSt_A	2423732	50	0	0
EnterStableSt_A	2423732	50	0	0
PulseIsPulse_A	2423732	50	0	0
StayInStableSt	2423732	5750	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_sticky_sva.StableStDropOut_A	2423732	2600	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	104	0	0
T19	1037	2	0	0
T20	1037	2	0	0
T21	0	2	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	3600	0	0
T19	1037	69	0	0
T20	1037	69	0	0
T21	0	69	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	69	0	0
T46	0	69	0	0
T47	0	69	0	0
T48	0	69	0	0
T49	0	69	0	0
T50	0	69	0	0
T51	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031861	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	634	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5800	0	0
T19	1037	116	0	0
T20	1037	116	0	0
T21	0	116	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	116	0	0
T46	0	116	0	0
T47	0	116	0	0
T48	0	116	0	0
T49	0	116	0	0
T50	0	116	0	0
T51	0	116	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2018953	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	379	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2020370	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	380	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	54	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5750	0	0
T19	1037	115	0	0
T20	1037	115	0	0
T21	0	115	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	115	0	0
T46	0	115	0	0
T47	0	115	0	0
T48	0	115	0	0
T49	0	115	0	0
T50	0	115	0	0
T51	0	115	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2600	0	0
T19	1037	52	0	0
T20	1037	52	0	0
T21	0	52	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	52	0	0
T46	0	52	0	0
T47	0	52	0	0
T48	0	52	0	0
T49	0	52	0	0
T50	0	52	0	0
T51	0	52	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	40	93.02
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T18,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T19,T20,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T19,T20,T21

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T19,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T16,T18,T40
1	1	Covered	T19,T20,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T21
0	1	Unreachable
1	0	Covered	T19,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T21
DetectSt	168	Covered	T19,T20,T21
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T21
DebounceSt->IdleSt	163	Covered	T103,T104
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T19,T20,T21
IdleSt->DebounceSt	148	Covered	T19,T20,T21
StableSt->IdleSt	206	Covered	T19,T20,T21

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	16	88.89
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T21
0	1	Covered	T19,T20,T21
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T21
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T40
DebounceSt	-	1	-	-	-	-	-	Covered	T103,T104
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T21
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T21
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	5006	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5400	0	0
DetectedPulseOut_A	2423732	50	0	0
DisabledIdleSt_A	2423732	2018953	0	0
DisabledNoDetection_A	2423732	2020370	0	0
EnterDebounceSt_A	2423732	54	0	0
EnterDetectSt_A	2423732	50	0	0
EnterStableSt_A	2423732	50	0	0
PulseIsPulse_A	2423732	50	0	0
StayInStableSt	2423732	5350	0	0
gen_high_event_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_sticky_sva.StableStDropOut_A	2423732	2250	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	104	0	0
T19	1037	2	0	0
T20	1037	2	0	0
T21	0	2	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5006	0	0
T19	1037	97	0	0
T20	1037	97	0	0
T21	0	97	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	97	0	0
T46	0	97	0	0
T47	0	97	0	0
T48	0	97	0	0
T49	0	97	0	0
T50	0	97	0	0
T51	0	97	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031861	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	634	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5400	0	0
T19	1037	108	0	0
T20	1037	108	0	0
T21	0	108	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	108	0	0
T46	0	108	0	0
T47	0	108	0	0
T48	0	108	0	0
T49	0	108	0	0
T50	0	108	0	0
T51	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2018953	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	379	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2020370	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	380	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	54	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T19	1037	1	0	0
T20	1037	1	0	0
T21	0	1	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5350	0	0
T19	1037	107	0	0
T20	1037	107	0	0
T21	0	107	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	107	0	0
T46	0	107	0	0
T47	0	107	0	0
T48	0	107	0	0
T49	0	107	0	0
T50	0	107	0	0
T51	0	107	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2250	0	0
T19	1037	45	0	0
T20	1037	45	0	0
T21	0	45	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	817	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T43	494	0	0	0
T44	423	0	0	0
T45	0	45	0	0
T46	0	45	0	0
T47	0	45	0	0
T48	0	45	0	0
T49	0	45	0	0
T50	0	45	0	0
T51	0	45	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T28,T33,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T28,T33,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T28,T33,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T33,T36
1	0	Covered	T16,T17,T18
1	1	Covered	T28,T33,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T33,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T33,T36
0	1	Not Covered
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T33,T36
1	-	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T33,T36
DetectSt	168	Covered	T28,T33,T36
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T28,T33,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T33,T36
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T28,T33,T36
IdleSt->DebounceSt	148	Covered	T28,T33,T36
StableSt->IdleSt	206	Covered	T28,T33,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T33,T36
0	1	Covered	T28,T33,T36
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T33,T36
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T33,T36
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T33,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T33,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T28,T33,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T103,T104
StableSt	-	-	-	-	-	-	0	Covered	T28,T33,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	13	86.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	13	86.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	4554	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	1858	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2020647	0	0
DisabledNoDetection_A	2423732	2022014	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	1756	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	104	0	0
T21	1037	0	0	0
T28	17445	2	0	0
T29	23657	0	0	0
T33	17445	2	0	0
T34	817	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T118	494	0	0	0
T120	0	2	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4554	0	0
T21	1037	0	0	0
T28	17445	90	0	0
T29	23657	0	0	0
T33	17445	90	0	0
T34	817	0	0	0
T36	0	90	0	0
T37	0	90	0	0
T118	494	0	0	0
T120	0	90	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	90	0	0
T149	0	90	0	0
T150	0	90	0	0
T151	0	90	0	0
T152	0	90	0	0
T153	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031861	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	1858	0	0
T21	1037	0	0	0
T28	17445	37	0	0
T29	23657	0	0	0
T33	17445	37	0	0
T34	817	0	0	0
T36	0	37	0	0
T37	0	37	0	0
T118	494	0	0	0
T120	0	37	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	37	0	0
T149	0	37	0	0
T150	0	37	0	0
T151	0	37	0	0
T152	0	37	0	0
T153	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2020647	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2022014	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	1756	0	0
T21	1037	0	0	0
T28	17445	35	0	0
T29	23657	0	0	0
T33	17445	35	0	0
T34	817	0	0	0
T36	0	35	0	0
T37	0	35	0	0
T118	494	0	0	0
T120	0	35	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	35	0	0
T149	0	35	0	0
T150	0	35	0	0
T151	0	35	0	0
T152	0	35	0	0
T153	403	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T103,T104

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T103,T104

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T103,T104

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T103,T104
1	0	Covered	T16,T18,T40
1	1	Covered	T103,T104

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104
0	1	Not Covered
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T103,T104
1	-	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T103,T104
DetectSt	168	Covered	T103,T104
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T103,T104

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T103,T104
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T103,T104
IdleSt->DebounceSt	148	Covered	T103,T104
StableSt->IdleSt	206	Covered	T103,T104

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T103,T104
0	1	Covered	T103,T104
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T103,T104
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T103,T104
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T103,T104
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T103,T104
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T103,T104
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T103,T104
StableSt	-	-	-	-	-	-	0	Covered	T103,T104
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	4	0	0
CntIncr_A	2423732	54	0	0
CntNoWrap_A	2423732	2031961	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	6	0	0
DetectedPulseOut_A	2423732	2	0	0
DisabledIdleSt_A	2423732	2031899	0	0
DisabledNoDetection_A	2423732	2033316	0	0
EnterDebounceSt_A	2423732	2	0	0
EnterDetectSt_A	2423732	2	0	0
EnterStableSt_A	2423732	2	0	0
PulseIsPulse_A	2423732	2	0	0
StayInStableSt	2423732	4	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	1806	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4	0	0
T103	7721	2	0	0
T104	0	2	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	54	0	0
T103	7721	27	0	0
T104	0	27	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031961	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	6	0	0
T103	7721	3	0	0
T104	0	3	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031899	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033316	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4	0	0
T103	7721	2	0	0
T104	0	2	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	1806	0	0
T16	423	2	0	0
T17	884	0	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T26	0	2	0	0
T28	0	19	0	0
T30	0	2	0	0
T39	403	0	0	0
T40	414	1	0	0
T41	503	4	0	0
T42	0	4	0	0
T43	0	4	0	0
T44	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0