Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.85	89.13	80.95		66.67	85.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.85	89.13	80.95		66.67	85.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.62	91.30	80.95		83.33	90.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.62	91.30	80.95		83.33	90.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92	89.13	90.48		66.67	85.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.85	89.13	80.95		66.67	85.00	87.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.85	89.13	80.95		66.67	85.00	87.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T18,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T18,T40
1	1	Covered	T16,T18,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T26,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T18,T26,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T26,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T28
1	0	Covered	T16,T40,T22
1	1	Covered	T18,T26,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T28
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T28
0	1	Covered	T18,T26,T28
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T26,T28
1	-	Covered	T18,T26,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T26,T28
DetectSt	168	Covered	T18,T26,T28
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T18,T26,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T26,T28
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T18,T26,T28
IdleSt->DebounceSt	148	Covered	T18,T26,T28
StableSt->IdleSt	206	Covered	T18,T26,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T26,T28
0	1	Covered	T18,T26,T28
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T26,T28
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T26,T28
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T40
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T26,T28
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T26,T28
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T18,T26,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T26,T28
StableSt	-	-	-	-	-	-	0	Covered	T18,T26,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	304	0	0
CntIncr_A	2423732	10554	0	0
CntNoWrap_A	2423732	2031661	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5256	0	0
DetectedPulseOut_A	2423732	152	0	0
DisabledIdleSt_A	2423732	2000049	0	0
DisabledNoDetection_A	2423732	2001366	0	0
EnterDebounceSt_A	2423732	152	0	0
EnterDetectSt_A	2423732	152	0	0
EnterStableSt_A	2423732	152	0	0
PulseIsPulse_A	2423732	152	0	0
StayInStableSt	2423732	5054	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	100	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	304	0	0
T18	817	4	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	4	0	0
T28	0	2	0	0
T30	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	10554	0	0
T18	817	120	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	120	0	0
T28	0	90	0	0
T30	0	120	0	0
T32	0	120	0	0
T33	0	90	0	0
T34	0	120	0	0
T36	0	90	0	0
T37	0	90	0	0
T38	0	120	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031661	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	412	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5256	0	0
T18	817	103	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	103	0	0
T28	0	2	0	0
T30	0	103	0	0
T32	0	103	0	0
T33	0	2	0	0
T34	0	103	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	103	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2000049	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	4	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2001366	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	4	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5054	0	0
T18	817	100	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	100	0	0
T28	0	1	0	0
T30	0	100	0	0
T32	0	100	0	0
T33	0	1	0	0
T34	0	100	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	100	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	100	0	0
T18	817	1	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T40
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T40
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T28,T33,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T28,T33,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T28,T33,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T33,T36
1	0	Covered	T16,T18,T40
1	1	Covered	T28,T33,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T33,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T33,T36
0	1	Not Covered
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T33,T36
1	-	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T33,T36
DetectSt	168	Covered	T28,T33,T36
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T28,T33,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T33,T36
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T28,T33,T36
IdleSt->DebounceSt	148	Covered	T28,T33,T36
StableSt->IdleSt	206	Covered	T28,T33,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T33,T36
0	1	Covered	T28,T33,T36
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T33,T36
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T33,T36
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T33,T36
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T33,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T28,T33,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T103,T104
StableSt	-	-	-	-	-	-	0	Covered	T28,T33,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	104	0	0
CntIncr_A	2423732	4554	0	0
CntNoWrap_A	2423732	2031861	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	1860	0	0
DetectedPulseOut_A	2423732	52	0	0
DisabledIdleSt_A	2423732	2020645	0	0
DisabledNoDetection_A	2423732	2022012	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	52	0	0
EnterStableSt_A	2423732	52	0	0
PulseIsPulse_A	2423732	52	0	0
StayInStableSt	2423732	1758	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	2518	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	104	0	0
T21	1037	0	0	0
T28	17445	2	0	0
T29	23657	0	0	0
T33	17445	2	0	0
T34	817	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T118	494	0	0	0
T120	0	2	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	2	0	0
T152	0	2	0	0
T153	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4554	0	0
T21	1037	0	0	0
T28	17445	90	0	0
T29	23657	0	0	0
T33	17445	90	0	0
T34	817	0	0	0
T36	0	90	0	0
T37	0	90	0	0
T118	494	0	0	0
T120	0	90	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	90	0	0
T149	0	90	0	0
T150	0	90	0	0
T151	0	90	0	0
T152	0	90	0	0
T153	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031861	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	1860	0	0
T21	1037	0	0	0
T28	17445	37	0	0
T29	23657	0	0	0
T33	17445	37	0	0
T34	817	0	0	0
T36	0	37	0	0
T37	0	37	0	0
T118	494	0	0	0
T120	0	37	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	37	0	0
T149	0	37	0	0
T150	0	37	0	0
T151	0	37	0	0
T152	0	37	0	0
T153	403	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2020645	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2022012	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T21	1037	0	0	0
T28	17445	1	0	0
T29	23657	0	0	0
T33	17445	1	0	0
T34	817	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T118	494	0	0	0
T120	0	1	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	403	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	1758	0	0
T21	1037	0	0	0
T28	17445	35	0	0
T29	23657	0	0	0
T33	17445	35	0	0
T34	817	0	0	0
T36	0	35	0	0
T37	0	35	0	0
T118	494	0	0	0
T120	0	35	0	0
T122	403	0	0	0
T123	523	0	0	0
T124	523	0	0	0
T148	0	35	0	0
T149	0	35	0	0
T150	0	35	0	0
T151	0	35	0	0
T152	0	35	0	0
T153	403	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2518	0	0
T16	423	2	0	0
T17	884	0	0	0
T18	817	1	0	0
T19	1037	0	0	0
T22	23657	8	0	0
T23	23657	8	0	0
T24	479	1	0	0
T25	0	8	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	2	0	0
T42	0	6	0	0
T43	0	6	0	0
T44	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T18,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T18,T40
1	1	Covered	T16,T18,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T26,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T18,T26,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T26,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T30
1	0	Covered	T16,T40,T22
1	1	Covered	T18,T26,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T30
0	1	Covered	T18,T26,T30
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T26,T30
1	-	Covered	T18,T26,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T26,T30
DetectSt	168	Covered	T18,T26,T30
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T18,T26,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T26,T30
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T18,T26,T30
IdleSt->DebounceSt	148	Covered	T18,T26,T30
StableSt->IdleSt	206	Covered	T18,T26,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T26,T30
0	1	Covered	T18,T26,T30
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T26,T30
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T26,T30
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T40
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T26,T30
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T26,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T18,T26,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T26,T30
StableSt	-	-	-	-	-	-	0	Covered	T18,T26,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	204	0	0
CntIncr_A	2423732	6054	0	0
CntNoWrap_A	2423732	2031761	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	4110	0	0
DetectedPulseOut_A	2423732	102	0	0
DisabledIdleSt_A	2423732	2011295	0	0
DisabledNoDetection_A	2423732	2012662	0	0
EnterDebounceSt_A	2423732	102	0	0
EnterDetectSt_A	2423732	102	0	0
EnterStableSt_A	2423732	102	0	0
PulseIsPulse_A	2423732	102	0	0
StayInStableSt	2423732	3958	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	50	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	204	0	0
T18	817	4	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	4	0	0
T30	0	4	0	0
T32	0	4	0	0
T34	0	4	0	0
T38	0	4	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	4	0	0
T155	0	4	0	0
T156	0	4	0	0
T157	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	6054	0	0
T18	817	120	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	120	0	0
T30	0	120	0	0
T32	0	120	0	0
T34	0	120	0	0
T38	0	120	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	120	0	0
T155	0	120	0	0
T156	0	120	0	0
T157	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031761	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	412	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4110	0	0
T18	817	82	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	82	0	0
T30	0	82	0	0
T32	0	82	0	0
T34	0	82	0	0
T38	0	82	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	82	0	0
T155	0	82	0	0
T156	0	82	0	0
T157	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2011295	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	4	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2012662	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	4	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	102	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	3958	0	0
T18	817	79	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	79	0	0
T30	0	79	0	0
T32	0	79	0	0
T34	0	79	0	0
T38	0	79	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	79	0	0
T155	0	79	0	0
T156	0	79	0	0
T157	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	50	0	0
T18	817	1	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T40
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T40
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T26,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T18,T26,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T103,T104

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T30
1	0	Covered	T16,T40,T22
1	1	Covered	T18,T26,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104
0	1	Not Covered
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T103,T104
1	-	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T26,T30
DetectSt	168	Covered	T103,T104
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T103,T104

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T103,T104
DebounceSt->IdleSt	163	Covered	T18,T26,T30
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T103,T104
IdleSt->DebounceSt	148	Covered	T18,T26,T30
StableSt->IdleSt	206	Covered	T103,T104

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T26,T30
0	1	Covered	T18,T26,T30
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T103,T104
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T26,T30
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T103,T104
DebounceSt	-	0	1	0	-	-	-	Covered	T18,T26,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T26,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T103,T104
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T103,T104
StableSt	-	-	-	-	-	-	0	Covered	T103,T104
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	54	0	0
CntIncr_A	2423732	3054	0	0
CntNoWrap_A	2423732	2031911	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	6	0	0
DetectedPulseOut_A	2423732	2	0	0
DisabledIdleSt_A	2423732	2011297	0	0
DisabledNoDetection_A	2423732	2012664	0	0
EnterDebounceSt_A	2423732	52	0	0
EnterDetectSt_A	2423732	2	0	0
EnterStableSt_A	2423732	2	0	0
PulseIsPulse_A	2423732	2	0	0
StayInStableSt	2423732	4	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	2668	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	54	0	0
T18	817	1	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	3054	0	0
T18	817	60	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	60	0	0
T30	0	60	0	0
T32	0	60	0	0
T34	0	60	0	0
T38	0	60	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	60	0	0
T155	0	60	0	0
T156	0	60	0	0
T157	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031911	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	415	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	6	0	0
T103	7721	3	0	0
T104	0	3	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2011297	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	4	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2012664	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	4	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	52	0	0
T18	817	1	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4	0	0
T103	7721	2	0	0
T104	0	2	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2668	0	0
T16	423	1	0	0
T17	884	0	0	0
T18	817	1	0	0
T19	1037	0	0	0
T22	23657	9	0	0
T23	23657	9	0	0
T24	479	1	0	0
T25	0	9	0	0
T39	403	0	0	0
T40	414	1	0	0
T41	503	4	0	0
T42	0	6	0	0
T43	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T16,T18,T40

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T18
1	0	Covered	T16,T18,T40
1	1	Covered	T16,T18,T40

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T26,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T18,T26,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T18,T26,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T26,T28
1	0	Covered	T16,T40,T22
1	1	Covered	T18,T26,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T28
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T26,T28
0	1	Covered	T18,T26,T28
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T26,T28
1	-	Covered	T18,T26,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T26,T28
DetectSt	168	Covered	T18,T26,T28
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T18,T26,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T26,T28
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T18,T26,T28
IdleSt->DebounceSt	148	Covered	T18,T26,T28
StableSt->IdleSt	206	Covered	T18,T26,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T18,T26,T28
0	1	Covered	T18,T26,T28
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T26,T28
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T18,T26,T28
IdleSt	0	-	-	-	-	-	-	Covered	T16,T18,T40
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T26,T28
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T26,T28
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T18,T26,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T18,T26,T28
StableSt	-	-	-	-	-	-	0	Covered	T18,T26,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	304	0	0
CntIncr_A	2423732	10554	0	0
CntNoWrap_A	2423732	2031661	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	5258	0	0
DetectedPulseOut_A	2423732	152	0	0
DisabledIdleSt_A	2423732	2000047	0	0
DisabledNoDetection_A	2423732	2001364	0	0
EnterDebounceSt_A	2423732	152	0	0
EnterDetectSt_A	2423732	152	0	0
EnterStableSt_A	2423732	152	0	0
PulseIsPulse_A	2423732	152	0	0
StayInStableSt	2423732	5106	0	0
gen_high_level_sva.HighLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	150	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	304	0	0
T18	817	4	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	4	0	0
T28	0	2	0	0
T30	0	4	0	0
T32	0	4	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	10554	0	0
T18	817	120	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	120	0	0
T28	0	90	0	0
T30	0	120	0	0
T32	0	120	0	0
T33	0	90	0	0
T34	0	120	0	0
T36	0	90	0	0
T37	0	90	0	0
T38	0	120	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031661	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	412	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5258	0	0
T18	817	102	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	102	0	0
T28	0	3	0	0
T30	0	102	0	0
T32	0	102	0	0
T33	0	3	0	0
T34	0	102	0	0
T36	0	3	0	0
T37	0	3	0	0
T38	0	102	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2000047	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	4	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2001364	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	4	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	152	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	5106	0	0
T18	817	100	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	100	0	0
T28	0	2	0	0
T30	0	100	0	0
T32	0	100	0	0
T33	0	2	0	0
T34	0	100	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	100	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	150	0	0
T18	817	2	0	0
T19	1037	0	0	0
T22	23657	0	0	0
T23	23657	0	0	0
T24	479	0	0	0
T25	23657	0	0	0
T26	0	2	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	403	0	0	0
T40	414	0	0	0
T41	503	0	0	0
T42	494	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	17	80.95
Logical	21	17	80.95
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T16,T18,T40
1	Covered	T16,T17,T18

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T18,T40
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T103,T104

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T16,T17,T18	VC_COV_UNR
1	Covered	T103,T104

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T16,T17,T18
1	Covered	T103,T104

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T103,T104
1	0	Covered	T16,T18,T40
1	1	Covered	T103,T104

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104
0	1	Not Covered
1	0	Covered	T103,T104

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T103,T104
1	-	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T103,T104
DetectSt	168	Covered	T103,T104
IdleSt	163	Covered	T16,T17,T18
StableSt	191	Covered	T103,T104

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T103,T104
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T103,T104
IdleSt->DebounceSt	148	Covered	T103,T104
StableSt->IdleSt	206	Covered	T103,T104

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T103,T104
0	1	Covered	T103,T104
0	0	Excluded	T16,T17,T18	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T103,T104
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T103,T104
IdleSt	0	-	-	-	-	-	-	Covered	T16,T17,T18
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T103,T104
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T103,T104
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T103,T104
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T103,T104
StableSt	-	-	-	-	-	-	0	Covered	T103,T104
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T16,T17,T18
0	Covered	T16,T17,T18

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	14	87.50
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	14	87.50

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	2423732	4	0	0
CntIncr_A	2423732	54	0	0
CntNoWrap_A	2423732	2031961	0	0
DetectStDropOut_A	2423732	0	0	0
DetectedOut_A	2423732	8	0	0
DetectedPulseOut_A	2423732	2	0	0
DisabledIdleSt_A	2423732	2031897	0	0
DisabledNoDetection_A	2423732	2033314	0	0
EnterDebounceSt_A	2423732	2	0	0
EnterDetectSt_A	2423732	2	0	0
EnterStableSt_A	2423732	2	0	0
PulseIsPulse_A	2423732	2	0	0
StayInStableSt	2423732	6	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	2423732	3358	0	0
gen_low_level_sva.LowLevelEvent_A	2423732	2033382	0	0
gen_not_sticky_sva.StableStDropOut_A	2423732	0	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	4	0	0
T103	7721	2	0	0
T104	0	2	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	54	0	0
T103	7721	27	0	0
T104	0	27	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031961	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	8	0	0
T103	7721	4	0	0
T104	0	4	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2031897	0	0
T16	423	22	0	0
T17	884	483	0	0
T18	817	416	0	0
T19	1037	636	0	0
T22	23657	23197	0	0
T23	23657	23197	0	0
T24	479	78	0	0
T39	403	2	0	0
T40	414	13	0	0
T41	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033314	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2	0	0
T103	7721	1	0	0
T104	0	1	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	6	0	0
T103	7721	3	0	0
T104	0	3	0	0
T139	479	0	0	0
T140	8403	0	0	0
T141	17445	0	0	0
T142	17445	0	0	0
T143	503	0	0	0
T144	414	0	0	0
T145	1037	0	0	0
T146	403	0	0	0
T147	494	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	3358	0	0
T16	423	3	0	0
T17	884	0	0	0
T18	817	2	0	0
T19	1037	5	0	0
T22	23657	11	0	0
T23	23657	11	0	0
T24	479	0	0	0
T25	0	11	0	0
T39	403	0	0	0
T40	414	1	0	0
T41	503	7	0	0
T42	0	6	0	0
T43	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	2033382	0	0
T16	423	23	0	0
T17	884	484	0	0
T18	817	417	0	0
T19	1037	637	0	0
T22	23657	23206	0	0
T23	23657	23206	0	0
T24	479	79	0	0
T39	403	3	0	0
T40	414	14	0	0
T41	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2423732	0	0	0