Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
| Total | Covered | Percent |
Conditions | 19 | 18 | 94.74 |
Logical | 19 | 18 | 94.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T103,T104 |
1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T100,T101,T102 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T100,T101,T102 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T100,T101,T102 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T103,T104 |
1 | 0 | Covered | T103,T104 |
1 | 1 | Covered | T100,T101,T102 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T100,T101,T102 |
0 | 1 | Covered | T103,T104 |
1 | 0 | Covered | T103,T104 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T100,T101,T102 |
0 | 1 | Covered | T103,T104 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T100,T101,T102 |
1 | - | Covered | T103,T104 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T100,T101,T102 |
DetectSt |
168 |
Covered |
T100,T101,T102 |
IdleSt |
163 |
Covered |
T16,T17,T18 |
StableSt |
191 |
Covered |
T100,T101,T102 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T100,T101,T102 |
DebounceSt->IdleSt |
163 |
Covered |
T103,T104 |
DetectSt->IdleSt |
186 |
Covered |
T103,T104 |
DetectSt->StableSt |
191 |
Covered |
T100,T101,T102 |
IdleSt->DebounceSt |
148 |
Covered |
T100,T101,T102 |
StableSt->IdleSt |
206 |
Covered |
T103,T104 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T100,T101,T102 |
0 |
1 |
Covered |
T100,T101,T102 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T100,T101,T102 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T100,T101,T102 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T100,T101,T102 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T100,T101,T102 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T103,T104 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T100,T101,T102 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T100,T101,T102 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T103,T104 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T100,T101,T102 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
42 |
0 |
0 |
T100 |
506 |
2 |
0 |
0 |
T101 |
0 |
2 |
0 |
0 |
T102 |
0 |
2 |
0 |
0 |
T103 |
0 |
16 |
0 |
0 |
T104 |
0 |
16 |
0 |
0 |
T128 |
0 |
2 |
0 |
0 |
T129 |
0 |
2 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1313 |
0 |
0 |
T100 |
506 |
21 |
0 |
0 |
T101 |
0 |
21 |
0 |
0 |
T102 |
0 |
21 |
0 |
0 |
T103 |
0 |
604 |
0 |
0 |
T104 |
0 |
604 |
0 |
0 |
T128 |
0 |
21 |
0 |
0 |
T129 |
0 |
21 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031923 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2 |
0 |
0 |
T103 |
7721 |
1 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1122 |
0 |
0 |
T100 |
506 |
80 |
0 |
0 |
T101 |
0 |
80 |
0 |
0 |
T102 |
0 |
80 |
0 |
0 |
T103 |
0 |
361 |
0 |
0 |
T104 |
0 |
361 |
0 |
0 |
T128 |
0 |
80 |
0 |
0 |
T129 |
0 |
80 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
15 |
0 |
0 |
T100 |
506 |
1 |
0 |
0 |
T101 |
0 |
1 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T103 |
0 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T128 |
0 |
1 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2029362 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2030774 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
23 |
0 |
0 |
T100 |
506 |
1 |
0 |
0 |
T101 |
0 |
1 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T103 |
0 |
9 |
0 |
0 |
T104 |
0 |
9 |
0 |
0 |
T128 |
0 |
1 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
19 |
0 |
0 |
T100 |
506 |
1 |
0 |
0 |
T101 |
0 |
1 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T103 |
0 |
7 |
0 |
0 |
T104 |
0 |
7 |
0 |
0 |
T128 |
0 |
1 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
15 |
0 |
0 |
T100 |
506 |
1 |
0 |
0 |
T101 |
0 |
1 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T103 |
0 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T128 |
0 |
1 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
15 |
0 |
0 |
T100 |
506 |
1 |
0 |
0 |
T101 |
0 |
1 |
0 |
0 |
T102 |
0 |
1 |
0 |
0 |
T103 |
0 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T128 |
0 |
1 |
0 |
0 |
T129 |
0 |
1 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1102 |
0 |
0 |
T100 |
506 |
78 |
0 |
0 |
T101 |
0 |
78 |
0 |
0 |
T102 |
0 |
78 |
0 |
0 |
T103 |
0 |
356 |
0 |
0 |
T104 |
0 |
356 |
0 |
0 |
T128 |
0 |
78 |
0 |
0 |
T129 |
0 |
78 |
0 |
0 |
T130 |
1037 |
0 |
0 |
0 |
T131 |
1037 |
0 |
0 |
0 |
T132 |
494 |
0 |
0 |
0 |
T133 |
884 |
0 |
0 |
0 |
T134 |
494 |
0 |
0 |
0 |
T135 |
403 |
0 |
0 |
0 |
T136 |
423 |
0 |
0 |
0 |
T137 |
503 |
0 |
0 |
0 |
T138 |
1037 |
0 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 45 | 97.83 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 31 | 96.88 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
0 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T22,T23,T24 |
1 | Covered | T16,T17,T18 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T24,T28,T33 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T16,T17,T18 |
VC_COV_UNR |
1 | Covered | T24,T28,T33 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T24,T28,T33 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T24 |
1 | 0 | Covered | T22,T23,T25 |
1 | 1 | Covered | T24,T28,T33 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T24,T28,T33 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T103,T104 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T24,T28,T33 |
0 | 1 | Covered | T24,T28,T33 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T24,T28,T33 |
1 | - | Covered | T24,T28,T33 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T24,T28,T33 |
DetectSt |
168 |
Covered |
T24,T28,T33 |
IdleSt |
163 |
Covered |
T16,T17,T18 |
StableSt |
191 |
Covered |
T24,T28,T33 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T24,T28,T33 |
DebounceSt->IdleSt |
163 |
Covered |
T103,T104 |
DetectSt->IdleSt |
186 |
Covered |
T103,T104 |
DetectSt->StableSt |
191 |
Covered |
T24,T28,T33 |
IdleSt->DebounceSt |
148 |
Covered |
T24,T28,T33 |
StableSt->IdleSt |
206 |
Covered |
T24,T28,T33 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
11 |
10 |
90.91 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T24,T28,T33 |
|
0 |
1 |
Covered |
T24,T28,T33 |
|
0 |
0 |
Excluded |
T16,T17,T18 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T24,T28,T33 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T24,T28,T33 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T16,T17,T18 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T24,T28,T33 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Not Covered |
|
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T24,T28,T33 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T103,T104 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T24,T28,T33 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T24,T28,T33 |
|
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T24,T28,T33 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T24,T28,T33 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
236 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
2 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
4 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
4 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
2 |
0 |
0 |
T120 |
0 |
4 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
4 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
9178 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
25 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
170 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
170 |
0 |
0 |
T36 |
0 |
170 |
0 |
0 |
T37 |
0 |
170 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
25 |
0 |
0 |
T120 |
0 |
170 |
0 |
0 |
T148 |
0 |
170 |
0 |
0 |
T149 |
0 |
170 |
0 |
0 |
T150 |
0 |
170 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031729 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
76 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
7786 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
3 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
152 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
152 |
0 |
0 |
T36 |
0 |
152 |
0 |
0 |
T37 |
0 |
152 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
3 |
0 |
0 |
T120 |
0 |
152 |
0 |
0 |
T148 |
0 |
152 |
0 |
0 |
T149 |
0 |
152 |
0 |
0 |
T150 |
0 |
152 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
112 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
1 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1557228 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
18131 |
0 |
0 |
T23 |
23657 |
18131 |
0 |
0 |
T24 |
479 |
4 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1557935 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
18131 |
0 |
0 |
T23 |
23657 |
18131 |
0 |
0 |
T24 |
479 |
4 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
120 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
1 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
116 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
1 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
112 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
1 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
112 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
1 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
7674 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
2 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
150 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
150 |
0 |
0 |
T36 |
0 |
150 |
0 |
0 |
T37 |
0 |
150 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
2 |
0 |
0 |
T120 |
0 |
150 |
0 |
0 |
T148 |
0 |
150 |
0 |
0 |
T149 |
0 |
150 |
0 |
0 |
T150 |
0 |
150 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
110 |
0 |
0 |
T20 |
1037 |
0 |
0 |
0 |
T24 |
479 |
1 |
0 |
0 |
T25 |
23657 |
0 |
0 |
0 |
T26 |
817 |
0 |
0 |
0 |
T27 |
23657 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
0 |
2 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T42 |
494 |
0 |
0 |
0 |
T43 |
494 |
0 |
0 |
0 |
T44 |
423 |
0 |
0 |
0 |
T117 |
0 |
1 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
| Total | Covered | Percent |
Conditions | 19 | 18 | 94.74 |
Logical | 19 | 18 | 94.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T103,T104 |
1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T103,T104 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T103,T104 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T103,T104 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T103,T104 |
1 | 0 | Covered | T103,T104 |
1 | 1 | Covered | T103,T104 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T103,T104 |
0 | 1 | Covered | T103,T104 |
1 | 0 | Covered | T103,T104 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T103,T104 |
0 | 1 | Covered | T103,T104 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T103,T104 |
1 | - | Covered | T103,T104 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T103,T104 |
DetectSt |
168 |
Covered |
T103,T104 |
IdleSt |
163 |
Covered |
T16,T17,T18 |
StableSt |
191 |
Covered |
T103,T104 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T103,T104 |
DebounceSt->IdleSt |
163 |
Covered |
T103,T104 |
DetectSt->IdleSt |
186 |
Covered |
T103,T104 |
DetectSt->StableSt |
191 |
Covered |
T103,T104 |
IdleSt->DebounceSt |
148 |
Covered |
T103,T104 |
StableSt->IdleSt |
206 |
Covered |
T103,T104 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T103,T104 |
0 |
1 |
Covered |
T103,T104 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T103,T104 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T103,T104 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T103,T104 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T103,T104 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T103,T104 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T103,T104 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T103,T104 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
32 |
0 |
0 |
T103 |
7721 |
16 |
0 |
0 |
T104 |
0 |
16 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1080 |
0 |
0 |
T103 |
7721 |
540 |
0 |
0 |
T104 |
0 |
540 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031933 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2 |
0 |
0 |
T103 |
7721 |
1 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
846 |
0 |
0 |
T103 |
7721 |
423 |
0 |
0 |
T104 |
0 |
423 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2029867 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031284 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
18 |
0 |
0 |
T103 |
7721 |
9 |
0 |
0 |
T104 |
0 |
9 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
14 |
0 |
0 |
T103 |
7721 |
7 |
0 |
0 |
T104 |
0 |
7 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
836 |
0 |
0 |
T103 |
7721 |
418 |
0 |
0 |
T104 |
0 |
418 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 46 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
| Total | Covered | Percent |
Conditions | 21 | 20 | 95.24 |
Logical | 21 | 20 | 95.24 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T22,T23,T25 |
1 | Covered | T16,T17,T18 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T25 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T28,T33,T36 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T16,T17,T18 |
VC_COV_UNR |
1 | Covered | T28,T33,T36 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T28,T33,T36 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T25 |
1 | 0 | Covered | T22,T23,T25 |
1 | 1 | Covered | T28,T33,T36 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T28,T33,T36 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T103,T104 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T28,T33,T36 |
0 | 1 | Covered | T28,T33,T36 |
1 | 0 | Covered | T103,T104 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T28,T33,T36 |
1 | - | Covered | T28,T33,T36 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T28,T33,T36 |
DetectSt |
168 |
Covered |
T28,T33,T36 |
IdleSt |
163 |
Covered |
T16,T17,T18 |
StableSt |
191 |
Covered |
T28,T33,T36 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T28,T33,T36 |
DebounceSt->IdleSt |
163 |
Covered |
T28,T33,T36 |
DetectSt->IdleSt |
186 |
Covered |
T103,T104 |
DetectSt->StableSt |
191 |
Covered |
T28,T33,T36 |
IdleSt->DebounceSt |
148 |
Covered |
T28,T33,T36 |
StableSt->IdleSt |
206 |
Covered |
T28,T33,T36 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
21 |
100.00 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
11 |
11 |
100.00 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T28,T33,T36 |
|
0 |
1 |
Covered |
T28,T33,T36 |
|
0 |
0 |
Excluded |
T16,T17,T18 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T28,T33,T36 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T28,T33,T36 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T16,T17,T18 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T28,T33,T36 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T28,T33,T36 |
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T28,T33,T36 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T103,T104 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T28,T33,T36 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T28,T33,T36 |
|
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T28,T33,T36 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T28,T33,T36 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
466 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
9 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
9 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
9 |
0 |
0 |
T37 |
0 |
9 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
9 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
9 |
0 |
0 |
T149 |
0 |
9 |
0 |
0 |
T150 |
0 |
9 |
0 |
0 |
T151 |
0 |
9 |
0 |
0 |
T152 |
0 |
9 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
35500 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
699 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
699 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
699 |
0 |
0 |
T37 |
0 |
699 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
699 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
699 |
0 |
0 |
T149 |
0 |
699 |
0 |
0 |
T150 |
0 |
699 |
0 |
0 |
T151 |
0 |
699 |
0 |
0 |
T152 |
0 |
699 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031499 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1156 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
20 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
20 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
20 |
0 |
0 |
T37 |
0 |
20 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
20 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
20 |
0 |
0 |
T149 |
0 |
20 |
0 |
0 |
T150 |
0 |
20 |
0 |
0 |
T151 |
0 |
20 |
0 |
0 |
T152 |
0 |
20 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
202 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
4 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
4 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
4 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
4 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1557865 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
18131 |
0 |
0 |
T23 |
23657 |
18131 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1558582 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
18131 |
0 |
0 |
T23 |
23657 |
18131 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
260 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
5 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
5 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
5 |
0 |
0 |
T37 |
0 |
5 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
5 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
5 |
0 |
0 |
T149 |
0 |
5 |
0 |
0 |
T150 |
0 |
5 |
0 |
0 |
T151 |
0 |
5 |
0 |
0 |
T152 |
0 |
5 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
206 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
4 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
4 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
4 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
4 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
202 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
4 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
4 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
4 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
4 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
202 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
4 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
4 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
4 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
4 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
954 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
16 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
16 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
16 |
0 |
0 |
T37 |
0 |
16 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
16 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
16 |
0 |
0 |
T149 |
0 |
16 |
0 |
0 |
T150 |
0 |
16 |
0 |
0 |
T151 |
0 |
16 |
0 |
0 |
T152 |
0 |
16 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
200 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
4 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
4 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
4 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
4 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
TOTAL | | 43 | 43 | 100.00 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 32 | 100.00 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
79 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
1 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
| Total | Covered | Percent |
Conditions | 19 | 18 | 94.74 |
Logical | 19 | 18 | 94.74 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T103,T104 |
1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T103,T104 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T103,T104 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T103,T104 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T103,T104 |
1 | 0 | Covered | T103,T104 |
1 | 1 | Covered | T103,T104 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T103,T104 |
0 | 1 | Covered | T103,T104 |
1 | 0 | Covered | T103,T104 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T103,T104 |
0 | 1 | Covered | T103,T104 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T103,T104 |
1 | - | Covered | T103,T104 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T103,T104 |
DetectSt |
168 |
Covered |
T103,T104 |
IdleSt |
163 |
Covered |
T16,T17,T18 |
StableSt |
191 |
Covered |
T103,T104 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T103,T104 |
DebounceSt->IdleSt |
163 |
Covered |
T103,T104 |
DetectSt->IdleSt |
186 |
Covered |
T103,T104 |
DetectSt->StableSt |
191 |
Covered |
T103,T104 |
IdleSt->DebounceSt |
148 |
Covered |
T103,T104 |
StableSt->IdleSt |
206 |
Covered |
T103,T104 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
3 |
3 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
12 |
11 |
91.67 |
IF |
219 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T103,T104 |
0 |
1 |
Covered |
T103,T104 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T103,T104 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T103,T104 |
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T103,T104 |
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T103,T104 |
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T103,T104 |
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T103,T104 |
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T103,T104 |
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T103,T104 |
default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
32 |
0 |
0 |
T103 |
7721 |
16 |
0 |
0 |
T104 |
0 |
16 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1206 |
0 |
0 |
T103 |
7721 |
603 |
0 |
0 |
T104 |
0 |
603 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031933 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2 |
0 |
0 |
T103 |
7721 |
1 |
0 |
0 |
T104 |
0 |
1 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
662 |
0 |
0 |
T103 |
7721 |
331 |
0 |
0 |
T104 |
0 |
331 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2029921 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031338 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
18 |
0 |
0 |
T103 |
7721 |
9 |
0 |
0 |
T104 |
0 |
9 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
14 |
0 |
0 |
T103 |
7721 |
7 |
0 |
0 |
T104 |
0 |
7 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
652 |
0 |
0 |
T103 |
7721 |
326 |
0 |
0 |
T104 |
0 |
326 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10 |
0 |
0 |
T103 |
7721 |
5 |
0 |
0 |
T104 |
0 |
5 |
0 |
0 |
T139 |
479 |
0 |
0 |
0 |
T140 |
8403 |
0 |
0 |
0 |
T141 |
17445 |
0 |
0 |
0 |
T142 |
17445 |
0 |
0 |
0 |
T143 |
503 |
0 |
0 |
0 |
T144 |
414 |
0 |
0 |
0 |
T145 |
1037 |
0 |
0 |
0 |
T146 |
403 |
0 |
0 |
0 |
T147 |
494 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
TOTAL | | 46 | 45 | 97.83 |
CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
ALWAYS | 69 | 3 | 3 | 100.00 |
CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
ALWAYS | 104 | 3 | 3 | 100.00 |
ALWAYS | 125 | 32 | 31 | 96.88 |
ALWAYS | 219 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
60 |
1 |
1 |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
76 |
1 |
1 |
92 |
1 |
1 |
99 |
1 |
1 |
101 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
107 |
1 |
1 |
125 |
1 |
1 |
128 |
1 |
1 |
129 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
138 |
1 |
1 |
140 |
1 |
1 |
147 |
1 |
1 |
148 |
1 |
1 |
149 |
1 |
1 |
|
|
|
MISSING_ELSE |
160 |
1 |
1 |
162 |
1 |
1 |
163 |
1 |
1 |
164 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
167 |
1 |
1 |
168 |
1 |
1 |
170 |
0 |
1 |
|
|
|
MISSING_ELSE |
181 |
1 |
1 |
182 |
1 |
1 |
185 |
1 |
1 |
186 |
1 |
1 |
187 |
1 |
1 |
190 |
1 |
1 |
191 |
1 |
1 |
192 |
1 |
1 |
193 |
1 |
1 |
194 |
1 |
1 |
|
|
|
MISSING_ELSE |
205 |
1 |
1 |
206 |
1 |
1 |
209 |
1 |
1 |
|
|
|
Exclude Annotation: VC_COV_UNR |
219 |
1 |
1 |
220 |
1 |
1 |
222 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
| Total | Covered | Percent |
Conditions | 21 | 19 | 90.48 |
Logical | 21 | 19 | 90.48 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
-1- | Status | Tests |
0 | Covered | T22,T23,T25 |
1 | Covered | T16,T17,T18 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T25 |
1 | 0 | Covered | T16,T17,T18 |
1 | 1 | Covered | T16,T17,T18 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T28,T33,T36 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
-1- | Status | Tests | Exclude Annotation |
0 | Excluded | T16,T17,T18 |
VC_COV_UNR |
1 | Covered | T28,T33,T36 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
-1- | Status | Tests |
0 | Covered | T16,T17,T18 |
1 | Covered | T28,T33,T36 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T22,T23,T25 |
1 | 0 | Covered | T22,T23,T25 |
1 | 1 | Covered | T28,T33,T36 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T28,T33,T36 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T103,T104 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T28,T33,T36 |
0 | 1 | Covered | T28,T33,T36 |
1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
-1- | -2- | Status | Tests |
0 | - | Covered | T28,T33,T36 |
1 | - | Covered | T28,T33,T36 |
FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
States |
4 |
4 |
100.00 |
(Not included in score) |
Transitions |
6 |
6 |
100.00 |
|
Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
states | Line No. | Covered | Tests |
DebounceSt |
148 |
Covered |
T28,T33,T36 |
DetectSt |
168 |
Covered |
T28,T33,T36 |
IdleSt |
163 |
Covered |
T16,T17,T18 |
StableSt |
191 |
Covered |
T28,T33,T36 |
transitions | Line No. | Covered | Tests |
DebounceSt->DetectSt |
168 |
Covered |
T28,T33,T36 |
DebounceSt->IdleSt |
163 |
Covered |
T103,T104 |
DetectSt->IdleSt |
186 |
Covered |
T103,T104 |
DetectSt->StableSt |
191 |
Covered |
T28,T33,T36 |
IdleSt->DebounceSt |
148 |
Covered |
T28,T33,T36 |
StableSt->IdleSt |
206 |
Covered |
T28,T33,T36 |
Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
| Line No. | Total | Covered | Percent |
Branches |
|
21 |
20 |
95.24 |
TERNARY |
92 |
2 |
2 |
100.00 |
TERNARY |
99 |
2 |
2 |
100.00 |
IF |
104 |
2 |
2 |
100.00 |
CASE |
140 |
11 |
10 |
90.91 |
IF |
219 |
2 |
2 |
100.00 |
IF |
69 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 92 (cnt_clr) ?
-2-: 92 (cnt_en) ?
Branches:
-1- | -2- | Status | Tests | Exclude Annotation |
1 |
- |
Covered |
T28,T33,T36 |
|
0 |
1 |
Covered |
T28,T33,T36 |
|
0 |
0 |
Excluded |
T16,T17,T18 |
VC_COV_UNR |
LineNo. Expression
-1-: 99 (thresh_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T28,T33,T36 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 140 case (state_q)
-2-: 147 if ((trigger_event && cfg_enable_i))
-3-: 162 if ((!cfg_enable_i))
-4-: 165 if (cnt_done)
-5-: 167 if (trigger_active)
-6-: 185 if (((!cfg_enable_i) || (!trigger_active)))
-7-: 190 if (cnt_done)
-8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))
Branches:
-1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests | Exclude Annotation |
IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T28,T33,T36 |
|
IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T16,T17,T18 |
|
DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T103,T104 |
|
DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T28,T33,T36 |
|
DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Not Covered |
|
|
DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T28,T33,T36 |
|
DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T103,T104 |
|
DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T28,T33,T36 |
|
DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T28,T33,T36 |
|
StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T28,T33,T36 |
|
StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T28,T33,T36 |
|
default |
- |
- |
- |
- |
- |
- |
- |
Excluded |
|
VC_COV_UNR |
LineNo. Expression
-1-: 219 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T16,T17,T18 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect
Assertion Details
CntClr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
216 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
4 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
4 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
4 |
0 |
0 |
T37 |
0 |
4 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
4 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
4 |
0 |
0 |
T149 |
0 |
4 |
0 |
0 |
T150 |
0 |
4 |
0 |
0 |
T151 |
0 |
4 |
0 |
0 |
T152 |
0 |
4 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
CntIncr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
10572 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
204 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
204 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
204 |
0 |
0 |
T37 |
0 |
204 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
204 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
204 |
0 |
0 |
T149 |
0 |
204 |
0 |
0 |
T150 |
0 |
204 |
0 |
0 |
T151 |
0 |
204 |
0 |
0 |
T152 |
0 |
204 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
CntNoWrap_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2031749 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
23197 |
0 |
0 |
T23 |
23657 |
23197 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DetectStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
0 |
0 |
0 |
DetectedOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
6156 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
120 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
120 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
120 |
0 |
0 |
T37 |
0 |
120 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
120 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
120 |
0 |
0 |
T149 |
0 |
120 |
0 |
0 |
T150 |
0 |
120 |
0 |
0 |
T151 |
0 |
120 |
0 |
0 |
T152 |
0 |
120 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
DetectedPulseOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
102 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
2 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
DisabledIdleSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1558049 |
0 |
0 |
T16 |
423 |
22 |
0 |
0 |
T17 |
884 |
483 |
0 |
0 |
T18 |
817 |
416 |
0 |
0 |
T19 |
1037 |
636 |
0 |
0 |
T22 |
23657 |
18131 |
0 |
0 |
T23 |
23657 |
18131 |
0 |
0 |
T24 |
479 |
78 |
0 |
0 |
T39 |
403 |
2 |
0 |
0 |
T40 |
414 |
13 |
0 |
0 |
T41 |
503 |
102 |
0 |
0 |
DisabledNoDetection_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
1558766 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
18131 |
0 |
0 |
T23 |
23657 |
18131 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
EnterDebounceSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
110 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
2 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
EnterDetectSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
106 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
2 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
EnterStableSt_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
102 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
2 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
PulseIsPulse_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
102 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
2 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
StayInStableSt
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
6054 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
118 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
118 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
118 |
0 |
0 |
T37 |
0 |
118 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
118 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
118 |
0 |
0 |
T149 |
0 |
118 |
0 |
0 |
T150 |
0 |
118 |
0 |
0 |
T151 |
0 |
118 |
0 |
0 |
T152 |
0 |
118 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
2033382 |
0 |
0 |
T16 |
423 |
23 |
0 |
0 |
T17 |
884 |
484 |
0 |
0 |
T18 |
817 |
417 |
0 |
0 |
T19 |
1037 |
637 |
0 |
0 |
T22 |
23657 |
23206 |
0 |
0 |
T23 |
23657 |
23206 |
0 |
0 |
T24 |
479 |
79 |
0 |
0 |
T39 |
403 |
3 |
0 |
0 |
T40 |
414 |
14 |
0 |
0 |
T41 |
503 |
103 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2423732 |
100 |
0 |
0 |
T21 |
1037 |
0 |
0 |
0 |
T28 |
17445 |
2 |
0 |
0 |
T29 |
23657 |
0 |
0 |
0 |
T33 |
17445 |
2 |
0 |
0 |
T34 |
817 |
0 |
0 |
0 |
T36 |
0 |
2 |
0 |
0 |
T37 |
0 |
2 |
0 |
0 |
T118 |
494 |
0 |
0 |
0 |
T120 |
0 |
2 |
0 |
0 |
T122 |
403 |
0 |
0 |
0 |
T123 |
523 |
0 |
0 |
0 |
T124 |
523 |
0 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
T149 |
0 |
2 |
0 |
0 |
T150 |
0 |
2 |
0 |
0 |
T151 |
0 |
2 |
0 |
0 |
T152 |
0 |
2 |
0 |
0 |
T153 |
403 |
0 |
0 |
0 |