Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
ALWAYS | 60 | 6 | 6 | 100.00 |
CONT_ASSIGN | 74 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
ALWAYS | 104 | 9 | 9 | 100.00 |
CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
54 |
1 |
1 |
60 |
1 |
1 |
61 |
1 |
1 |
62 |
1 |
1 |
63 |
1 |
1 |
64 |
1 |
1 |
65 |
1 |
1 |
|
|
|
MISSING_ELSE |
74 |
1 |
1 |
98 |
1 |
1 |
104 |
1 |
1 |
105 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
112 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
|
|
|
MISSING_ELSE |
139 |
1 |
1 |
144 |
1 |
1 |
145 |
1 |
1 |
187 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T17,T18 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T17,T22,T19 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T17,T22,T19 |
1 | 1 | Covered | T17,T22,T19 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T17,T18 |
0 | 1 | Covered | T18,T22,T23 |
1 | 0 | Covered | T17,T22,T19 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T17,T22,T19 |
1 | 1 | Covered | T17,T22,T19 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T18,T22,T23 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 16 | 14 | 87.50 |
Logical | 16 | 14 | 87.50 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 54
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T17,T18 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T22,T19,T23 |
LINE 98
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Covered | T22,T19,T23 |
1 | 1 | Covered | T22,T19,T23 |
LINE 112
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T19,T24,T20 |
1 | - | Covered | T22,T19,T23 |
LINE 114
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T16,T17,T18 |
0 | 1 | Covered | T18,T22,T19 |
1 | 0 | Covered | T22,T19,T23 |
LINE 114
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T22,T19,T23 |
1 | 1 | Covered | T22,T19,T23 |
LINE 114
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T16,T17,T18 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T18,T22,T19 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
60 |
4 |
4 |
100.00 |
IF |
104 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 60 if ((!rst_src_ni))
-2-: 62 if (src_req)
-3-: 64 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T16,T17,T18 |
0 |
1 |
- |
Covered |
T17,T22,T19 |
0 |
0 |
1 |
Covered |
T17,T22,T19 |
0 |
0 |
0 |
Covered |
T16,T17,T18 |
LineNo. Expression
-1-: 104 if ((!rst_src_ni))
-2-: 107 if (src_req)
-3-: 114 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T16,T17,T18 |
0 |
1 |
- |
Covered |
T17,T22,T19 |
0 |
0 |
1 |
Covered |
T17,T18,T22 |
0 |
0 |
0 |
Covered |
T16,T17,T18 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
62449715 |
0 |
0 |
T19 |
1046312 |
0 |
0 |
0 |
T22 |
5299408 |
17252 |
0 |
0 |
T23 |
5299408 |
17252 |
0 |
0 |
T24 |
1074640 |
1102 |
0 |
0 |
T25 |
5299408 |
17252 |
0 |
0 |
T26 |
1625840 |
0 |
0 |
0 |
T27 |
0 |
17252 |
0 |
0 |
T28 |
0 |
8565 |
0 |
0 |
T29 |
0 |
17252 |
0 |
0 |
T31 |
0 |
17252 |
0 |
0 |
T33 |
0 |
8565 |
0 |
0 |
T35 |
1324852 |
17252 |
0 |
0 |
T36 |
976972 |
4262 |
0 |
0 |
T41 |
1126904 |
0 |
0 |
0 |
T42 |
1106736 |
0 |
0 |
0 |
T43 |
1106736 |
0 |
0 |
0 |
T44 |
948368 |
0 |
0 |
0 |
T45 |
261578 |
0 |
0 |
0 |
T97 |
351566 |
7773 |
0 |
0 |
T98 |
351566 |
7773 |
0 |
0 |
T99 |
0 |
7773 |
0 |
0 |
T100 |
141936 |
0 |
0 |
0 |
T105 |
0 |
7773 |
0 |
0 |
T106 |
0 |
7773 |
0 |
0 |
T107 |
0 |
7773 |
0 |
0 |
T108 |
0 |
7773 |
0 |
0 |
T109 |
0 |
7773 |
0 |
0 |
T110 |
0 |
7773 |
0 |
0 |
T111 |
0 |
7773 |
0 |
0 |
T112 |
225728 |
0 |
0 |
0 |
T113 |
232352 |
0 |
0 |
0 |
T114 |
232352 |
0 |
0 |
0 |
T115 |
495616 |
0 |
0 |
0 |
T116 |
293412 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
100914429 |
77947419 |
0 |
0 |
T16 |
15651 |
851 |
0 |
0 |
T17 |
32708 |
17908 |
0 |
0 |
T18 |
30229 |
15429 |
0 |
0 |
T19 |
38369 |
23569 |
0 |
0 |
T22 |
875309 |
858622 |
0 |
0 |
T23 |
875309 |
858622 |
0 |
0 |
T24 |
17723 |
2923 |
0 |
0 |
T39 |
14911 |
111 |
0 |
0 |
T40 |
15318 |
518 |
0 |
0 |
T41 |
18611 |
3811 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
65276 |
0 |
0 |
T19 |
1046312 |
0 |
0 |
0 |
T22 |
5299408 |
18 |
0 |
0 |
T23 |
5299408 |
18 |
0 |
0 |
T24 |
1074640 |
1 |
0 |
0 |
T25 |
5299408 |
18 |
0 |
0 |
T26 |
1625840 |
0 |
0 |
0 |
T27 |
0 |
18 |
0 |
0 |
T28 |
0 |
10 |
0 |
0 |
T29 |
0 |
18 |
0 |
0 |
T31 |
0 |
18 |
0 |
0 |
T33 |
0 |
10 |
0 |
0 |
T35 |
1324852 |
18 |
0 |
0 |
T36 |
976972 |
5 |
0 |
0 |
T41 |
1126904 |
0 |
0 |
0 |
T42 |
1106736 |
0 |
0 |
0 |
T43 |
1106736 |
0 |
0 |
0 |
T44 |
948368 |
0 |
0 |
0 |
T45 |
261578 |
0 |
0 |
0 |
T97 |
351566 |
8 |
0 |
0 |
T98 |
351566 |
8 |
0 |
0 |
T99 |
0 |
8 |
0 |
0 |
T100 |
141936 |
0 |
0 |
0 |
T105 |
0 |
8 |
0 |
0 |
T106 |
0 |
8 |
0 |
0 |
T107 |
0 |
8 |
0 |
0 |
T108 |
0 |
8 |
0 |
0 |
T109 |
0 |
8 |
0 |
0 |
T110 |
0 |
8 |
0 |
0 |
T111 |
0 |
8 |
0 |
0 |
T112 |
225728 |
0 |
0 |
0 |
T113 |
232352 |
0 |
0 |
0 |
T114 |
232352 |
0 |
0 |
0 |
T115 |
495616 |
0 |
0 |
0 |
T116 |
293412 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T16 |
4386202 |
4383094 |
0 |
0 |
T17 |
9168896 |
9165788 |
0 |
0 |
T18 |
7519510 |
7516402 |
0 |
0 |
T19 |
4839193 |
4836085 |
0 |
0 |
T22 |
24509762 |
24456593 |
0 |
0 |
T23 |
24509762 |
24456593 |
0 |
0 |
T24 |
4970210 |
4967102 |
0 |
0 |
T39 |
4175968 |
4172860 |
0 |
0 |
T40 |
4298512 |
4295404 |
0 |
0 |
T41 |
5211931 |
5208823 |
0 |
0 |