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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
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T565 /workspace/coverage/default/13.sysrst_ctrl_alert_test.60039092878569671495985545145375877606693110397622444694275679338267750905971 Nov 01 12:35:08 PM PDT 23 Nov 01 12:35:18 PM PDT 23 2015424120 ps
T566 /workspace/coverage/default/40.sysrst_ctrl_edge_detect.107551695990026037845853493863607054858333011811465674203126596809238757906502 Nov 01 12:37:49 PM PDT 23 Nov 01 12:38:02 PM PDT 23 4089103959 ps
T567 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.52170270321658189864619699582179210242713533755278437539916370816771128642425 Nov 01 12:35:09 PM PDT 23 Nov 01 12:35:21 PM PDT 23 4089103959 ps
T568 /workspace/coverage/default/49.sysrst_ctrl_stress_all.2142939778579121774871623742614207479138926949022023847843834228667874464214 Nov 01 12:38:41 PM PDT 23 Nov 01 12:40:58 PM PDT 23 87228974549 ps
T569 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.73847242537524874971455029195608473621825691328952200947979100003029394117124 Nov 01 12:36:31 PM PDT 23 Nov 01 12:39:34 PM PDT 23 118289458206 ps
T570 /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.51348155406379955929767622608856404489842003407357598410611617339008455144448 Nov 01 12:35:21 PM PDT 23 Nov 01 12:35:26 PM PDT 23 2074566504 ps
T571 /workspace/coverage/default/19.sysrst_ctrl_stress_all.101413398105730146651525667112596355607969216124745741500608935093206542171313 Nov 01 12:35:31 PM PDT 23 Nov 01 12:37:52 PM PDT 23 87228974549 ps
T572 /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.15153910363567055234088597368732387921007964528987003276066716554048812543885 Nov 01 12:36:44 PM PDT 23 Nov 01 12:36:50 PM PDT 23 2619740714 ps
T573 /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.57615042107322561605574760305372455783806207583592025020508111912214496435342 Nov 01 12:37:52 PM PDT 23 Nov 01 12:38:03 PM PDT 23 5189470156 ps
T574 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.83924001767746472067896080977248009316811624690779923325496252966596417717742 Nov 01 12:35:18 PM PDT 23 Nov 01 12:35:26 PM PDT 23 2619740714 ps
T575 /workspace/coverage/default/41.sysrst_ctrl_smoke.54238768316213387646795977020849646916123780685066266307274914807801029587476 Nov 01 12:37:45 PM PDT 23 Nov 01 12:37:56 PM PDT 23 2116887594 ps
T576 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.76839168196448165165977706419076558106912336896954502501859332833312745548947 Nov 01 12:37:09 PM PDT 23 Nov 01 12:37:15 PM PDT 23 5189470156 ps
T577 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.111603766391265045674849677056457407935156336144248864957841539825524369782112 Nov 01 12:35:31 PM PDT 23 Nov 01 12:35:40 PM PDT 23 3138968703 ps
T578 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.21827960012967448051217538676385227989259006624585023952354857003496117055219 Nov 01 12:34:56 PM PDT 23 Nov 01 12:38:08 PM PDT 23 118289458206 ps
T579 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.99625160933081067704372690413109635496595107151605606669335677500717431933724 Nov 01 12:36:35 PM PDT 23 Nov 01 12:39:38 PM PDT 23 118289458206 ps
T580 /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.34986577681317279477700705690960656296151372339928963129750141296102686976633 Nov 01 12:36:43 PM PDT 23 Nov 01 12:36:50 PM PDT 23 2470384766 ps
T581 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.56952346978267200253818514465076747244581670431861120078546485001160369857413 Nov 01 12:35:08 PM PDT 23 Nov 01 12:35:18 PM PDT 23 2074566504 ps
T582 /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.92870633494460946685443733545386289935429400255365118135659675625687092627776 Nov 01 12:36:57 PM PDT 23 Nov 01 12:37:03 PM PDT 23 5189470156 ps
T583 /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.34312983349280947191946560416231597574337112950142978276151848488567767631496 Nov 01 12:37:37 PM PDT 23 Nov 01 12:37:47 PM PDT 23 4425119128 ps
T584 /workspace/coverage/default/48.sysrst_ctrl_stress_all.74910201019186938099232820408222024298882107979363149739341022238410898053347 Nov 01 12:37:55 PM PDT 23 Nov 01 12:40:15 PM PDT 23 87228974549 ps
T585 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.77485692064177467854757863818635192610981520202478097038203614479276043865067 Nov 01 12:34:20 PM PDT 23 Nov 01 12:34:32 PM PDT 23 5189470156 ps
T586 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.46853755190730045110817918645818342828660881535035466308362543092442250461367 Nov 01 12:37:02 PM PDT 23 Nov 01 12:37:08 PM PDT 23 2515402263 ps
T587 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.92502412032710048713637657706999653406124215022761308671815860199406245493162 Nov 01 12:35:04 PM PDT 23 Nov 01 12:35:16 PM PDT 23 4089103959 ps
T588 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.37930035035513375367435412687477921159658673928112457584148411510925611231132 Nov 01 12:37:14 PM PDT 23 Nov 01 12:37:20 PM PDT 23 2470384766 ps
T589 /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.5864069179605041446443410869870305337883373908491581037882261893204312074616 Nov 01 12:36:42 PM PDT 23 Nov 01 12:36:48 PM PDT 23 2074566504 ps
T590 /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.23093852207424344596502858412225929083071055862576964796522389064632603600187 Nov 01 12:37:54 PM PDT 23 Nov 01 12:38:04 PM PDT 23 2470384766 ps
T591 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.18197978944165283175543142624638840612366382000414038711701645617681609392502 Nov 01 12:35:31 PM PDT 23 Nov 01 12:35:39 PM PDT 23 2515402263 ps
T592 /workspace/coverage/default/39.sysrst_ctrl_alert_test.175444118643110165106024513892097894558614758505839257551934699544468298802 Nov 01 12:37:19 PM PDT 23 Nov 01 12:37:26 PM PDT 23 2015424120 ps
T593 /workspace/coverage/default/1.sysrst_ctrl_alert_test.78352448174743186333075065016441508759120764031308846468675425097294424976286 Nov 01 12:34:40 PM PDT 23 Nov 01 12:34:46 PM PDT 23 2015424120 ps
T594 /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.59565408040631402912199368018803023369207103684382070040249239692535466110396 Nov 01 12:35:07 PM PDT 23 Nov 01 12:35:18 PM PDT 23 2619740714 ps
T595 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.56056308212008921502637147204102974593869248191156704666116172323858521005335 Nov 01 12:35:59 PM PDT 23 Nov 01 12:36:05 PM PDT 23 5189470156 ps
T596 /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.57481315776065096387032926257875817774008254628340752005403326919225747994649 Nov 01 12:36:32 PM PDT 23 Nov 01 12:36:38 PM PDT 23 2470384766 ps
T597 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.61907195389131326102471167068602321659503094867641260605285407433659414762560 Nov 01 12:36:39 PM PDT 23 Nov 01 12:36:49 PM PDT 23 4089103959 ps
T598 /workspace/coverage/default/0.sysrst_ctrl_stress_all.104854599022798488092953260786154403650560210195983019322545181801221288547924 Nov 01 12:34:19 PM PDT 23 Nov 01 12:36:42 PM PDT 23 87228974549 ps
T599 /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.47608684590644500905890111288751467717356896129306028674399690324545205017033 Nov 01 12:37:13 PM PDT 23 Nov 01 12:37:22 PM PDT 23 4425119128 ps
T600 /workspace/coverage/default/14.sysrst_ctrl_stress_all.85775445640876668438455857631379559400021998545018814258886927418536469567236 Nov 01 12:35:04 PM PDT 23 Nov 01 12:37:25 PM PDT 23 87228974549 ps
T601 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.52247491293700103891629722713496412508298772969873669772909908520294512222851 Nov 01 12:34:42 PM PDT 23 Nov 01 12:34:49 PM PDT 23 5189470156 ps
T602 /workspace/coverage/default/36.sysrst_ctrl_stress_all.66754887486759491920910882454412672394952276613046870220081870887367578567671 Nov 01 12:37:17 PM PDT 23 Nov 01 12:39:34 PM PDT 23 87228974549 ps
T603 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.31781634812199136982744308115628116211433906155360422649062427315945393444138 Nov 01 12:36:36 PM PDT 23 Nov 01 12:36:44 PM PDT 23 2619740714 ps
T604 /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.56222411238815679911639974548746690860601283896914038923218196791729526184233 Nov 01 12:37:49 PM PDT 23 Nov 01 12:38:00 PM PDT 23 2515402263 ps
T128 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.95117846407700433485732008328841836573847250078607966922291475991024155246164 Nov 01 12:33:56 PM PDT 23 Nov 01 12:34:01 PM PDT 23 2534562824 ps
T605 /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.22048966933127974626638848938870740474228436666189831530467266541517657670833 Nov 01 12:37:59 PM PDT 23 Nov 01 12:38:07 PM PDT 23 2515402263 ps
T606 /workspace/coverage/default/17.sysrst_ctrl_smoke.30316734909998092086069713337818000846175200493451892933223745436900156168701 Nov 01 12:35:06 PM PDT 23 Nov 01 12:35:16 PM PDT 23 2116887594 ps
T607 /workspace/coverage/default/22.sysrst_ctrl_alert_test.94950040455254801059588378468980828591664775734535491307244599248491983240251 Nov 01 12:35:26 PM PDT 23 Nov 01 12:35:31 PM PDT 23 2015424120 ps
T608 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.71512727104563068618785667098071711233195903422671117282358689032232435833268 Nov 01 12:36:43 PM PDT 23 Nov 01 12:36:52 PM PDT 23 4425119128 ps
T609 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.32820603815320650122020249503898558675997638697437112199160369684246283794374 Nov 01 12:35:31 PM PDT 23 Nov 01 12:35:41 PM PDT 23 4089103959 ps
T610 /workspace/coverage/default/44.sysrst_ctrl_smoke.66129507509386290398802917629697148993238697845692145419210417829968523399793 Nov 01 12:37:51 PM PDT 23 Nov 01 12:38:01 PM PDT 23 2116887594 ps
T611 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.82163831661238315198889182406610846616898673780514288843097591755004390791971 Nov 01 12:37:48 PM PDT 23 Nov 01 12:38:00 PM PDT 23 2515402263 ps
T612 /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.46729789970887407078067559667680428840644606930234075248153382165638184436903 Nov 01 12:34:51 PM PDT 23 Nov 01 12:34:57 PM PDT 23 2074566504 ps
T613 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.101158682137726283486029031732770715004000443967797012361516838371387781103329 Nov 01 12:35:08 PM PDT 23 Nov 01 12:35:19 PM PDT 23 2515402263 ps
T614 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.110291498435233873535213030552644468745183269746707047204007437606159344937077 Nov 01 12:35:06 PM PDT 23 Nov 01 12:35:16 PM PDT 23 2074566504 ps
T615 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.55698684146375498821863402720583840548671263569814460332731116805391160062440 Nov 01 12:37:44 PM PDT 23 Nov 01 12:37:57 PM PDT 23 2515402263 ps
T616 /workspace/coverage/default/1.sysrst_ctrl_smoke.65493222231576938883765418394127448269918401839232677845642451618184626571880 Nov 01 12:34:29 PM PDT 23 Nov 01 12:34:39 PM PDT 23 2116887594 ps
T617 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.51094186876749209011260543781745044379188490338750867026161506317732858255415 Nov 01 12:35:07 PM PDT 23 Nov 01 12:35:18 PM PDT 23 2470384766 ps
T618 /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.28862458133704663774386031688421925497492181437447688135392929431978433137209 Nov 01 12:37:45 PM PDT 23 Nov 01 12:37:57 PM PDT 23 2619740714 ps
T619 /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.14509897345799878500719449195398110417325505224477776173020471588761678038422 Nov 01 12:34:58 PM PDT 23 Nov 01 12:35:09 PM PDT 23 2619740714 ps
T620 /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.24682237704173156085402146609946135628540478098772522033122630950117375531930 Nov 01 12:35:09 PM PDT 23 Nov 01 12:35:20 PM PDT 23 2619740714 ps
T621 /workspace/coverage/default/17.sysrst_ctrl_alert_test.24825603268036851302364569031001025567055917404667960916374351458630805800380 Nov 01 12:35:26 PM PDT 23 Nov 01 12:35:31 PM PDT 23 2015424120 ps
T622 /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.50307026541451915198708799744095710885200058370097663108460105355292857059394 Nov 01 12:35:05 PM PDT 23 Nov 01 12:35:17 PM PDT 23 5189470156 ps
T623 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.40535584902462186189336942468776531121251393444056748720037919570680840781954 Nov 01 12:37:19 PM PDT 23 Nov 01 12:37:29 PM PDT 23 4089103959 ps
T624 /workspace/coverage/default/14.sysrst_ctrl_alert_test.74757316418780804544371122119613168209437458829553785725346626759180887680278 Nov 01 12:35:21 PM PDT 23 Nov 01 12:35:26 PM PDT 23 2015424120 ps
T625 /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.28061959481826429907387358121618496349704142504624830972439165334705930884235 Nov 01 12:35:24 PM PDT 23 Nov 01 12:35:30 PM PDT 23 2619740714 ps
T626 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.70362280971981363951282744603915717578930588869424313173227244128461188187875 Nov 01 12:37:20 PM PDT 23 Nov 01 12:37:27 PM PDT 23 2619740714 ps
T627 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.32533097494859000327692981427076995087117985904319342317800717306350798383001 Nov 01 12:36:43 PM PDT 23 Nov 01 12:36:51 PM PDT 23 4089103959 ps
T129 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.16177011713568220769106771226944060392140275319754426238033772505294219065882 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2534562824 ps
T628 /workspace/coverage/default/43.sysrst_ctrl_alert_test.45808124609026426644688208077223567453377199136741271826876289532180192755725 Nov 01 12:37:52 PM PDT 23 Nov 01 12:38:02 PM PDT 23 2015424120 ps
T629 /workspace/coverage/default/47.sysrst_ctrl_stress_all.20850993894619544708517620353855564471425082937864531049730521692983445992901 Nov 01 12:37:51 PM PDT 23 Nov 01 12:40:13 PM PDT 23 87228974549 ps
T630 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.747653493888425875612765667877763830493796435510725084024365974578580095044 Nov 01 12:36:34 PM PDT 23 Nov 01 12:36:41 PM PDT 23 3138968703 ps
T631 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.76226718318149737133144405476673137531279127728541554416637992301031359571697 Nov 01 12:37:34 PM PDT 23 Nov 01 12:37:41 PM PDT 23 2619740714 ps
T632 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.75178447465144345994646047276235132731766341173198296059808867360131159704372 Nov 01 12:34:49 PM PDT 23 Nov 01 12:34:56 PM PDT 23 2515402263 ps
T633 /workspace/coverage/default/42.sysrst_ctrl_alert_test.34922862844338352391044147718871178465734517552456746141088121954330441228804 Nov 01 12:37:51 PM PDT 23 Nov 01 12:38:02 PM PDT 23 2015424120 ps
T634 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.55467764438213196905281365453359781235768638310906794143055425940714123379423 Nov 01 12:36:09 PM PDT 23 Nov 01 12:36:16 PM PDT 23 5189470156 ps
T635 /workspace/coverage/default/2.sysrst_ctrl_alert_test.43583740357758018319061711806380830255576826147435066308356496674370174452497 Nov 01 12:34:06 PM PDT 23 Nov 01 12:34:11 PM PDT 23 2015424120 ps
T636 /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.63468493758572628564518759445115974308474634559394150092456719388756098358954 Nov 01 12:34:24 PM PDT 23 Nov 01 12:34:34 PM PDT 23 2470384766 ps
T637 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.77437596633363273620497543203388034349863914914412061247921329323801815437688 Nov 01 12:34:37 PM PDT 23 Nov 01 12:34:47 PM PDT 23 4089103959 ps
T638 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3589621245264330445776089850236421811317448964824306039757576464118536778996 Nov 01 12:35:00 PM PDT 23 Nov 01 12:38:10 PM PDT 23 118289458206 ps
T639 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.82788057793230057471699542160225328321253723676071934002020744443449416154402 Nov 01 12:37:55 PM PDT 23 Nov 01 12:38:03 PM PDT 23 2074566504 ps
T640 /workspace/coverage/default/6.sysrst_ctrl_alert_test.111422786995485129067701074091947031637715526968622256363922512699913155685060 Nov 01 12:34:53 PM PDT 23 Nov 01 12:35:03 PM PDT 23 2015424120 ps
T641 /workspace/coverage/default/4.sysrst_ctrl_combo_detect.63931952671694979258717179535868812431461191625331646554608695933829066575175 Nov 01 12:34:41 PM PDT 23 Nov 01 12:37:49 PM PDT 23 118289458206 ps
T642 /workspace/coverage/default/5.sysrst_ctrl_alert_test.58799814979085714665249795011310629092587089598757062652321035917665717968591 Nov 01 12:34:50 PM PDT 23 Nov 01 12:34:56 PM PDT 23 2015424120 ps
T643 /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.45976254916251415368853445071950955061279402116401888479387130211171649628801 Nov 01 12:37:21 PM PDT 23 Nov 01 12:37:38 PM PDT 23 4425119128 ps
T644 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.12128769605456458955484767904900574565320089346829455725457972088264262489589 Nov 01 12:33:58 PM PDT 23 Nov 01 12:34:04 PM PDT 23 2515402263 ps
T645 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.10905843244317049026240896163800403695298892700309620387163664309990421710728 Nov 01 12:37:50 PM PDT 23 Nov 01 12:38:01 PM PDT 23 2619740714 ps
T646 /workspace/coverage/default/43.sysrst_ctrl_combo_detect.105807912803379014102122461213220545331486124074686749728875355249078865950694 Nov 01 12:37:47 PM PDT 23 Nov 01 12:40:58 PM PDT 23 118289458206 ps
T647 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.59175960042001166529376562842508638390890933520471033718768131406916991319772 Nov 01 12:35:27 PM PDT 23 Nov 01 12:35:33 PM PDT 23 2515402263 ps
T648 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.55916389896334904936271355888972273781488924652935760416816420995886443843103 Nov 01 12:34:18 PM PDT 23 Nov 01 12:34:32 PM PDT 23 4089103959 ps
T649 /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3966242886812716796383192912455764554693008177434292419472867643758368632480 Nov 01 12:34:56 PM PDT 23 Nov 01 12:35:08 PM PDT 23 2074566504 ps
T650 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.65305539977217561565473963958579698028270016014076991923176533852714801484862 Nov 01 12:36:48 PM PDT 23 Nov 01 12:36:55 PM PDT 23 4089103959 ps
T651 /workspace/coverage/default/10.sysrst_ctrl_smoke.21780780016401229693303006814310414645851080241532481148306609166317632640805 Nov 01 12:34:55 PM PDT 23 Nov 01 12:35:07 PM PDT 23 2116887594 ps
T652 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.75783628642896837214856602410329796821651265944878585233807192120553868896543 Nov 01 12:34:52 PM PDT 23 Nov 01 12:34:59 PM PDT 23 2470384766 ps
T653 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.39417389360329090369191068657310905478728595669802540737225763181273481733330 Nov 01 12:37:11 PM PDT 23 Nov 01 12:37:17 PM PDT 23 2470384766 ps
T654 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.103396002941042664682899318256500949274732594308708515030919446845366223080113 Nov 01 12:35:05 PM PDT 23 Nov 01 12:35:16 PM PDT 23 5189470156 ps
T655 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.10172340966795379588379387255176949407973298260883984787401521474559820251278 Nov 01 12:35:24 PM PDT 23 Nov 01 12:35:30 PM PDT 23 3138968703 ps
T656 /workspace/coverage/default/13.sysrst_ctrl_smoke.30002114355868792929538129599365314184158894637015930987487856892947045174100 Nov 01 12:35:05 PM PDT 23 Nov 01 12:35:15 PM PDT 23 2116887594 ps
T657 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.8409671363132677617488087202463096646537073960639942906651075234806113957820 Nov 01 12:35:03 PM PDT 23 Nov 01 12:35:15 PM PDT 23 3138968703 ps
T658 /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.96080804002315043598346048332378992998811266924798392260103156874546658701160 Nov 01 12:35:59 PM PDT 23 Nov 01 12:36:07 PM PDT 23 4425119128 ps
T659 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.5412080595160413558472563892237906127001128780615195704754794490560843746749 Nov 01 12:36:17 PM PDT 23 Nov 01 12:39:25 PM PDT 23 118289458206 ps
T660 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.70165610621011117969565364429547693093048540664141946898981008920839907484824 Nov 01 12:36:16 PM PDT 23 Nov 01 12:36:24 PM PDT 23 5189470156 ps
T661 /workspace/coverage/default/40.sysrst_ctrl_stress_all.93830169117524460601976189425214085865500123508551639614942103596210355555961 Nov 01 12:37:46 PM PDT 23 Nov 01 12:40:10 PM PDT 23 87228974549 ps
T662 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.87863811523978768064500668237150187930534874284735335327593670913371910684355 Nov 01 12:37:40 PM PDT 23 Nov 01 12:37:52 PM PDT 23 5189470156 ps
T663 /workspace/coverage/default/34.sysrst_ctrl_smoke.82161459082770796905742986742422582231937395414137932569781441078104472157782 Nov 01 12:36:39 PM PDT 23 Nov 01 12:36:46 PM PDT 23 2116887594 ps
T664 /workspace/coverage/default/31.sysrst_ctrl_alert_test.15083935202402134191565203786997729777199938841193924296300990965678787854190 Nov 01 12:36:26 PM PDT 23 Nov 01 12:36:31 PM PDT 23 2015424120 ps
T665 /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.44785315129061532504239176869502535594242067926554824615193396698382365354256 Nov 01 12:35:03 PM PDT 23 Nov 01 12:35:15 PM PDT 23 3138968703 ps
T666 /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1799354365030219731182580673761151046059695263565016884339521193359720883482 Nov 01 12:34:50 PM PDT 23 Nov 01 12:34:59 PM PDT 23 4089103959 ps
T667 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.94034436220406931916788196326815351537984167504581871665258702876174172510731 Nov 01 12:35:34 PM PDT 23 Nov 01 12:35:40 PM PDT 23 2515402263 ps
T668 /workspace/coverage/default/7.sysrst_ctrl_alert_test.37286739605729095067391462545182233628991085001089733374721200704441552351420 Nov 01 12:34:55 PM PDT 23 Nov 01 12:35:07 PM PDT 23 2015424120 ps
T669 /workspace/coverage/default/27.sysrst_ctrl_smoke.112600877671766503635833626597625881095023621504916317312814383767748552787919 Nov 01 12:36:15 PM PDT 23 Nov 01 12:36:22 PM PDT 23 2116887594 ps
T670 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.88199787045187972502792868160761489713055885980654508880303768249793390819066 Nov 01 12:36:31 PM PDT 23 Nov 01 12:36:37 PM PDT 23 2515402263 ps
T671 /workspace/coverage/default/48.sysrst_ctrl_alert_test.80591983654813686654327100746195148304512562888846064991767205574042480674710 Nov 01 12:38:13 PM PDT 23 Nov 01 12:38:20 PM PDT 23 2015424120 ps
T104 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.25435448296149703111520874036244317037284107417230313077525510154043602862847 Nov 01 12:34:38 PM PDT 23 Nov 01 12:35:42 PM PDT 23 38606274248 ps
T672 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.84646204043146927853682715354261359171640123261795598368034324793272685589077 Nov 01 12:36:11 PM PDT 23 Nov 01 12:36:23 PM PDT 23 4425119128 ps
T673 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.42419117106076562355090171535599996548505217073644090011157969643731171147719 Nov 01 12:38:04 PM PDT 23 Nov 01 12:38:11 PM PDT 23 2074566504 ps
T674 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.54071132231958505311080923010658013569466098832015980247692667283235804288397 Nov 01 12:36:16 PM PDT 23 Nov 01 12:36:23 PM PDT 23 5189470156 ps
T675 /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.104418541169594907586578636873001566493203031035067766076401452784141149845771 Nov 01 12:37:12 PM PDT 23 Nov 01 12:37:18 PM PDT 23 2619740714 ps
T676 /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.34491600229724351864514918193177059732622890190818624277980951930351843453776 Nov 01 12:37:53 PM PDT 23 Nov 01 12:38:06 PM PDT 23 4425119128 ps
T677 /workspace/coverage/default/8.sysrst_ctrl_stress_all.114500717474323799371582721739714638416299850740339426918046928614134819826105 Nov 01 12:34:58 PM PDT 23 Nov 01 12:37:18 PM PDT 23 87228974549 ps
T678 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.18491990413956709112983035304833009921987879629469654268591645371925590171158 Nov 01 12:37:58 PM PDT 23 Nov 01 12:38:06 PM PDT 23 2619740714 ps
T160 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.25753139607461517350680968135745974248082071646282760549151215477254252578955 Nov 01 12:34:15 PM PDT 23 Nov 01 12:34:25 PM PDT 23 2023227629 ps
T161 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3329999491510152449141337198770993328094308383187198132542445242024729717423 Nov 01 12:34:19 PM PDT 23 Nov 01 12:34:30 PM PDT 23 2023227629 ps
T1 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.97183075109448591752630899814240045319222792240247134403794830700714838090278 Nov 01 12:34:00 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2142012393 ps
T95 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.102356448637781210637599369715624518648677727366464146407065325215235327818399 Nov 01 12:33:54 PM PDT 23 Nov 01 12:34:20 PM PDT 23 9477310853 ps
T73 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.81987290483949994762501721506715662977894082265694337236871665427650771865100 Nov 01 12:32:55 PM PDT 23 Nov 01 12:33:04 PM PDT 23 2074977215 ps
T74 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.74716804507709415090863133166965902809661906233658294705099738284218763508856 Nov 01 12:33:51 PM PDT 23 Nov 01 12:33:57 PM PDT 23 2074977215 ps
T75 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.943917946617898085401991254705369881080405645182593540532662813686127380507 Nov 01 12:33:54 PM PDT 23 Nov 01 12:33:59 PM PDT 23 2023227629 ps
T76 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.82051363820212894495175648868608690209855440897091982230063942828614926109368 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2023227629 ps
T77 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.69684545143763362033596596983809981046018143243494135732548364226100422339742 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2023227629 ps
T78 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.28370621206480264015756273119346910204778006329725849615698173227232753963189 Nov 01 12:32:49 PM PDT 23 Nov 01 12:32:54 PM PDT 23 2023227629 ps
T79 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.72112567420118255894315365642103205513067616984301142005058199679341011830783 Nov 01 12:33:57 PM PDT 23 Nov 01 12:34:02 PM PDT 23 2023227629 ps
T80 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.71849573008659823636006262493188620087312028249946769501778134959752337896491 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:46 PM PDT 23 9477310853 ps
T81 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.113834701125569026869020521983369369672954992564200771835628476675817024064120 Nov 01 12:34:02 PM PDT 23 Nov 01 12:34:09 PM PDT 23 2023227629 ps
T82 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.47787199423131825915026527239356209686768069306705278859826539659917197929905 Nov 01 12:34:00 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2074977215 ps
T96 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.110656475782580013743209011118713094793406866873632406313925174486800884165581 Nov 01 12:32:50 PM PDT 23 Nov 01 12:33:16 PM PDT 23 9477310853 ps
T2 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1267375251769653122994758530503234935698583336706594356935723418108714247390 Nov 01 12:34:07 PM PDT 23 Nov 01 12:35:20 PM PDT 23 42510939439 ps
T3 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.93153097720255102850904062830572789093249428953988007711844302607802862597385 Nov 01 12:33:57 PM PDT 23 Nov 01 12:34:02 PM PDT 23 2142012393 ps
T11 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.103226429971627416501438283080155981316313569080443960003590010269179803356370 Nov 01 12:32:53 PM PDT 23 Nov 01 12:33:03 PM PDT 23 2890827831 ps
T4 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.91689190944588315164403323215931663367915654255492476392396179774576593004222 Nov 01 12:34:08 PM PDT 23 Nov 01 12:34:17 PM PDT 23 2142012393 ps
T12 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.77450512279224235292296361771229327185117484395480212738049114680295078393228 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2074977215 ps
T13 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.24239926345981254007527124907664031480093062861533224421023415225332940736738 Nov 01 12:34:00 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2074977215 ps
T14 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.80924376892087139387738827232199687622200677433449834186141353048776353078343 Nov 01 12:33:58 PM PDT 23 Nov 01 12:34:04 PM PDT 23 2074977215 ps
T15 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.90536010550480324986135702999349640981790758385456396216968121681213393555998 Nov 01 12:34:02 PM PDT 23 Nov 01 12:34:30 PM PDT 23 9477310853 ps
T83 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.52326842105324320357932724872687756116059046103431160285507266750244214730041 Nov 01 12:32:53 PM PDT 23 Nov 01 12:32:58 PM PDT 23 2074977215 ps
T679 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.81275778889127532168688851639231316378620771256245251792700309780915911152638 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:25 PM PDT 23 2023227629 ps
T5 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.51932362638132077611627973148305126128359836926915973227487501277977309027814 Nov 01 12:34:09 PM PDT 23 Nov 01 12:35:25 PM PDT 23 42510939439 ps
T6 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.102788428945403564326928513853874978121089720569462031766384701319814107707825 Nov 01 12:34:24 PM PDT 23 Nov 01 12:34:33 PM PDT 23 2142012393 ps
T680 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.11157352644179179540198456401091916106132409591371446102414335926030782837751 Nov 01 12:32:48 PM PDT 23 Nov 01 12:33:14 PM PDT 23 9477310853 ps
T681 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.92902826497144398442773262563473525856270616453623221307560245059110932669751 Nov 01 12:34:05 PM PDT 23 Nov 01 12:34:10 PM PDT 23 2023227629 ps
T84 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.80815579575240660970505382688501348153977782607813592991079678713797572120785 Nov 01 12:32:55 PM PDT 23 Nov 01 12:34:52 PM PDT 23 41047879715 ps
T85 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.109377926632809838278462871859482325991461621158544408832189169243929332825064 Nov 01 12:32:46 PM PDT 23 Nov 01 12:32:57 PM PDT 23 2890827831 ps
T7 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.16731887835589486049904624851604794575940489011213279489072485815162140734831 Nov 01 12:32:56 PM PDT 23 Nov 01 12:33:06 PM PDT 23 2142012393 ps
T8 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.69711774107045171123849291793203015135172523752418618017345112949848172899802 Nov 01 12:34:09 PM PDT 23 Nov 01 12:35:25 PM PDT 23 42510939439 ps
T86 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.42708890186965436463288721390522416205222940809902184707662740732074058873946 Nov 01 12:32:50 PM PDT 23 Nov 01 12:34:46 PM PDT 23 41047879715 ps
T92 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.17084061575834671269913462478852428467461394642307463161873383692306892722730 Nov 01 12:32:50 PM PDT 23 Nov 01 12:33:02 PM PDT 23 6030981281 ps
T9 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.46889905232374007827624164036823776373468529760103493671115573936043216300546 Nov 01 12:32:49 PM PDT 23 Nov 01 12:32:56 PM PDT 23 2186637036 ps
T64 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.69704858901936276190714632758563241991627952079132453678310198993200111033085 Nov 01 12:34:05 PM PDT 23 Nov 01 12:34:32 PM PDT 23 9477310853 ps
T65 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.11401293202428538917972241100678912613365875942933711047906647726039384777024 Nov 01 12:34:15 PM PDT 23 Nov 01 12:34:47 PM PDT 23 9477310853 ps
T66 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.28802039796121614560830367478387545935103483736497762238760818213788218640101 Nov 01 12:34:06 PM PDT 23 Nov 01 12:34:32 PM PDT 23 9477310853 ps
T67 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.25573959590073380585729824474454319670351875073065331796546151925541812241477 Nov 01 12:32:47 PM PDT 23 Nov 01 12:33:13 PM PDT 23 9477310853 ps
T68 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.62613803023583039634583478205238464070653407631249995268166425964905865289559 Nov 01 12:32:46 PM PDT 23 Nov 01 12:34:39 PM PDT 23 41047879715 ps
T69 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.66902124279545657483404367177753281918446466643448845390555747326226494338543 Nov 01 12:34:09 PM PDT 23 Nov 01 12:34:16 PM PDT 23 2023227629 ps
T70 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.9129797563452337013376491137876490483443889705598971417268037041825176872938 Nov 01 12:32:50 PM PDT 23 Nov 01 12:32:56 PM PDT 23 2074977215 ps
T10 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.110475390242308723368564884409176858652904596763681230795496022703561974331990 Nov 01 12:33:53 PM PDT 23 Nov 01 12:34:00 PM PDT 23 2186637036 ps
T71 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.112941293833695496080136997869205675686888835473282482998777009314700559422002 Nov 01 12:32:49 PM PDT 23 Nov 01 12:32:54 PM PDT 23 2074977215 ps
T682 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.79900808349738469302751434247891242637723585672111748631701773232425704237970 Nov 01 12:34:08 PM PDT 23 Nov 01 12:34:36 PM PDT 23 9477310853 ps
T52 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.112745009731811886786743828322451831544014695037703178351438814251438909863456 Nov 01 12:34:15 PM PDT 23 Nov 01 12:35:31 PM PDT 23 42510939439 ps
T683 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.44640769358687539102968991497672505897292502360540467349721422610226514277820 Nov 01 12:34:01 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2023227629 ps
T684 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.51711528553485023398810797120624030597841786310312084762000003999290871337735 Nov 01 12:34:08 PM PDT 23 Nov 01 12:34:15 PM PDT 23 2023227629 ps
T53 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.74764158507443590358644794505033049831332433088708803476170462568805733166833 Nov 01 12:32:50 PM PDT 23 Nov 01 12:34:01 PM PDT 23 42510939439 ps
T685 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.67171629698537822149372169686145499175180108481695703311429361881680527436 Nov 01 12:34:19 PM PDT 23 Nov 01 12:34:31 PM PDT 23 2074977215 ps
T686 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.57241968447011275193463150032568518658462578814208768797082195440102340865359 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2074977215 ps
T687 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.69130020848029711900721226524586329259783516230879487595529369120301915274879 Nov 01 12:34:03 PM PDT 23 Nov 01 12:34:09 PM PDT 23 2023227629 ps
T688 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.41503069985153558893734500376596393965417536003621463508845743625093102411724 Nov 01 12:34:05 PM PDT 23 Nov 01 12:34:11 PM PDT 23 2142012393 ps
T54 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.41464041887781280582688551196326204254628996182579612885415945193010812702209 Nov 01 12:32:57 PM PDT 23 Nov 01 12:33:08 PM PDT 23 2186637036 ps
T55 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.41631340792835990773407627565918298120309428171981377862889093216997326398193 Nov 01 12:33:54 PM PDT 23 Nov 01 12:35:04 PM PDT 23 42510939439 ps
T689 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.100939466491603759364861650473617216298405039368614859123047229277274105846421 Nov 01 12:34:19 PM PDT 23 Nov 01 12:34:30 PM PDT 23 2023227629 ps
T93 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.80034543898565389497795483453390454281921564074769242620922382579113436742679 Nov 01 12:32:55 PM PDT 23 Nov 01 12:33:11 PM PDT 23 6030981281 ps
T690 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.55715123584677958265814885050082330776990583477405561543826520480748378068427 Nov 01 12:34:12 PM PDT 23 Nov 01 12:34:43 PM PDT 23 9477310853 ps
T691 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.59014060490566970439589456943208842662411838660992760332822171920267578836992 Nov 01 12:34:06 PM PDT 23 Nov 01 12:34:11 PM PDT 23 2023227629 ps
T692 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.7021833094933622872508666409400419512104849460930843821535397753127083475730 Nov 01 12:32:48 PM PDT 23 Nov 01 12:32:53 PM PDT 23 2023227629 ps
T87 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.18070121154722093871968303725771753940654796915073793219708033755429939287082 Nov 01 12:32:47 PM PDT 23 Nov 01 12:34:41 PM PDT 23 41047879715 ps
T56 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.35315618775600341388791515225938329495987063486261491818860615685707543249025 Nov 01 12:32:45 PM PDT 23 Nov 01 12:33:55 PM PDT 23 42510939439 ps
T693 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.101831103167433087259249885868180325118010990456754520642780302726446944720240 Nov 01 12:33:59 PM PDT 23 Nov 01 12:34:07 PM PDT 23 2023227629 ps
T57 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.66808342011128128353848477422909801204116537814409379034615333779354373015186 Nov 01 12:34:15 PM PDT 23 Nov 01 12:34:27 PM PDT 23 2186637036 ps
T58 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.110073314820149455492477158588858338038635393127653481469294453253419498084370 Nov 01 12:34:15 PM PDT 23 Nov 01 12:34:27 PM PDT 23 2186637036 ps
T694 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.6265010974294072765356778702621767834211902678534530868844520348641571435886 Nov 01 12:34:05 PM PDT 23 Nov 01 12:35:16 PM PDT 23 42510939439 ps
T695 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.79925122495544264770656751072407170635352113809398045947194308195711636495055 Nov 01 12:33:57 PM PDT 23 Nov 01 12:34:23 PM PDT 23 9477310853 ps
T696 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.25827717905742469246017237965948389612664112160906879678899690276668449306814 Nov 01 12:34:04 PM PDT 23 Nov 01 12:34:31 PM PDT 23 9477310853 ps
T697 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.91503654075832948947342248244166444690187450980711087753277628613001699208587 Nov 01 12:33:55 PM PDT 23 Nov 01 12:34:00 PM PDT 23 2023227629 ps
T698 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.77328938947802661931936404557470402582913499566414888397805338834377248622554 Nov 01 12:34:04 PM PDT 23 Nov 01 12:34:10 PM PDT 23 2142012393 ps
T699 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.17487416404788725550650964843395166918054308250757360562225188438548021992210 Nov 01 12:33:59 PM PDT 23 Nov 01 12:34:07 PM PDT 23 2023227629 ps
T59 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.60335705110632790236701475319257914208873502088440808677085927277399533114008 Nov 01 12:32:50 PM PDT 23 Nov 01 12:32:57 PM PDT 23 2186637036 ps
T700 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.5675981154659992647732603803910964757900446528880462084819174837210737955608 Nov 01 12:32:50 PM PDT 23 Nov 01 12:32:56 PM PDT 23 2142012393 ps
T701 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.41607604601889940823748554470623591916806358441059849617039516192434490553260 Nov 01 12:34:00 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2023227629 ps
T702 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.60958679187146661818492803574240503162565989159733483609705402684080582357192 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2023227629 ps
T703 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.59923381936593792070995271609782827195934922524020797985173879915722319472962 Nov 01 12:34:04 PM PDT 23 Nov 01 12:34:10 PM PDT 23 2074977215 ps
T704 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.110679479429523991785634536832469980500403111025306105912218533135072925272527 Nov 01 12:32:48 PM PDT 23 Nov 01 12:33:13 PM PDT 23 9477310853 ps
T705 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.78907352500969132855752899942614980940231565375688747711024002813644686169393 Nov 01 12:32:44 PM PDT 23 Nov 01 12:32:49 PM PDT 23 2142012393 ps
T706 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3400030629568732632503027905866994848143642991624385530479798269365306159109 Nov 01 12:32:50 PM PDT 23 Nov 01 12:33:17 PM PDT 23 9477310853 ps
T94 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.69376677514998067291604121393877699913263634963320707878505706167525866870853 Nov 01 12:32:51 PM PDT 23 Nov 01 12:33:02 PM PDT 23 6030981281 ps
T707 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.56333373789172131783929753632286878658311689301532590996862811168322662418821 Nov 01 12:34:20 PM PDT 23 Nov 01 12:34:31 PM PDT 23 2023227629 ps
T60 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.96926492651986693858785330358540356385228761431810200324881973618133168571629 Nov 01 12:32:49 PM PDT 23 Nov 01 12:32:57 PM PDT 23 2186637036 ps
T88 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.38989035345626369780594066753209565108414663567906066020805861422865280763489 Nov 01 12:32:45 PM PDT 23 Nov 01 12:32:54 PM PDT 23 2890827831 ps
T61 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.46466184636766122988191311171982988438760731807137484182837633498409128588502 Nov 01 12:33:58 PM PDT 23 Nov 01 12:34:04 PM PDT 23 2186637036 ps
T708 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.11502986993049545495837525467646883195796881638687481408388135881580912186669 Nov 01 12:33:57 PM PDT 23 Nov 01 12:34:02 PM PDT 23 2023227629 ps
T709 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.34628512299085220214907175019693896187564933689436299217878931546237057887148 Nov 01 12:33:54 PM PDT 23 Nov 01 12:34:20 PM PDT 23 9477310853 ps
T62 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.89926625237535984027467320997757960577245533343503415539775293439703894436299 Nov 01 12:32:46 PM PDT 23 Nov 01 12:32:53 PM PDT 23 2186637036 ps
T710 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.44418506126846846418445404429236927534141800820955155721173245020951780933522 Nov 01 12:34:06 PM PDT 23 Nov 01 12:34:32 PM PDT 23 9477310853 ps
T711 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1153030728690165492843282736889028091205387501729544671890528882766714715237 Nov 01 12:34:18 PM PDT 23 Nov 01 12:34:28 PM PDT 23 2023227629 ps
T712 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.78521348549167046434427876882466176439276222106469950776669844074514580421187 Nov 01 12:32:47 PM PDT 23 Nov 01 12:32:58 PM PDT 23 6030981281 ps
T713 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.73389470765611601818383176010683951668496245671017244116365527911957432320735 Nov 01 12:34:21 PM PDT 23 Nov 01 12:34:31 PM PDT 23 2023227629 ps
T714 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.99568672430443885733083247322332874648455173563413951133338943617481479297115 Nov 01 12:32:46 PM PDT 23 Nov 01 12:32:52 PM PDT 23 2074977215 ps
T715 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.109798200341382608533411792346116356445690422639904476035168420334853162599726 Nov 01 12:34:01 PM PDT 23 Nov 01 12:34:09 PM PDT 23 2142012393 ps
T716 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.107788996767404200236216402013566806100518746753392525384896968716544773597044 Nov 01 12:33:53 PM PDT 23 Nov 01 12:33:58 PM PDT 23 2074977215 ps
T717 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.89411058262378221628139849626247973964980768336085309675052663708564287194471 Nov 01 12:34:04 PM PDT 23 Nov 01 12:35:16 PM PDT 23 42510939439 ps
T718 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.28531308536468415361265678316193053403938656976725948700201935215473942666664 Nov 01 12:34:19 PM PDT 23 Nov 01 12:34:30 PM PDT 23 2023227629 ps
T719 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.68838788270718195408225332420189415203392881620002687457768105102804690003726 Nov 01 12:32:51 PM PDT 23 Nov 01 12:32:56 PM PDT 23 2023227629 ps
T720 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.78071263797109483445048463871898673010654913121312200578519025509534981337757 Nov 01 12:33:51 PM PDT 23 Nov 01 12:33:57 PM PDT 23 2023227629 ps
T721 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.51081935538629167832295106856549176088492478112617469072615350510211327872363 Nov 01 12:34:00 PM PDT 23 Nov 01 12:35:13 PM PDT 23 42510939439 ps
T63 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.83153867648018391972125059018629224948206593548465584125029664207756670963473 Nov 01 12:34:18 PM PDT 23 Nov 01 12:34:30 PM PDT 23 2186637036 ps
T722 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.97791203177557543089821697521402661507813782874715289255420154275408726703927 Nov 01 12:34:12 PM PDT 23 Nov 01 12:34:23 PM PDT 23 2023227629 ps
T723 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.87843812985566881047383738449827247362242154700749305598157559751378225594199 Nov 01 12:34:02 PM PDT 23 Nov 01 12:34:09 PM PDT 23 2142012393 ps
T724 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.86412694544283376201094795353632591615967541296987408146592821753375996304709 Nov 01 12:33:57 PM PDT 23 Nov 01 12:35:08 PM PDT 23 42510939439 ps
T725 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.65377411222006171883240838362494177621201112362518477048984604626482533793974 Nov 01 12:34:26 PM PDT 23 Nov 01 12:34:35 PM PDT 23 2186637036 ps
T726 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.81198049747229444664163945598025893488216778231018339043746963651029174053708 Nov 01 12:32:54 PM PDT 23 Nov 01 12:33:06 PM PDT 23 2142012393 ps
T727 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.23379608019568173362002569007307628980717039693430963843873406977816651398882 Nov 01 12:33:54 PM PDT 23 Nov 01 12:33:59 PM PDT 23 2074977215 ps
T728 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.12285822368806828792028544557379912513140309604324810173836862130416707723678 Nov 01 12:34:24 PM PDT 23 Nov 01 12:34:32 PM PDT 23 2023227629 ps
T729 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.15310475837780578008967084717104552474437140277524209597016385282763555403505 Nov 01 12:33:56 PM PDT 23 Nov 01 12:34:01 PM PDT 23 2023227629 ps
T730 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.78772762448637126278264792889432550838758165998299135385848050539311439550761 Nov 01 12:33:58 PM PDT 23 Nov 01 12:34:05 PM PDT 23 2186637036 ps
T731 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.77277998562347796807920436431170703685343015112928331335474664499490319405776 Nov 01 12:34:01 PM PDT 23 Nov 01 12:34:09 PM PDT 23 2074977215 ps
T732 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.45643550417232965804235825896782078753995594623749452708777208391518913732251 Nov 01 12:33:54 PM PDT 23 Nov 01 12:33:59 PM PDT 23 2142012393 ps
T733 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.114179176506734437498072015917402733028185650868416744933087023184564914655560 Nov 01 12:33:56 PM PDT 23 Nov 01 12:35:07 PM PDT 23 42510939439 ps
T734 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.47044031432496439006243542838094630481582123549847205099572476958460225843451 Nov 01 12:32:51 PM PDT 23 Nov 01 12:33:17 PM PDT 23 9477310853 ps
T735 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.52136374637097754203518733245371769362170656752825950793408276427635587815752 Nov 01 12:34:20 PM PDT 23 Nov 01 12:35:37 PM PDT 23 42510939439 ps
T736 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.105218521897476458228765628390752168830035657161562401148058478657044089483218 Nov 01 12:33:52 PM PDT 23 Nov 01 12:33:57 PM PDT 23 2023227629 ps
T737 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.64385019764643359084530361216423424791052421609548942919186245402296742624000 Nov 01 12:33:57 PM PDT 23 Nov 01 12:34:02 PM PDT 23 2142012393 ps
T738 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.14543914773149697102595098877915168384152330194851816298126092438059876938928 Nov 01 12:33:54 PM PDT 23 Nov 01 12:33:59 PM PDT 23 2023227629 ps
T739 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.89525392948659552926441402981610112992129196049543969871719757843068438370247 Nov 01 12:34:11 PM PDT 23 Nov 01 12:34:21 PM PDT 23 2023227629 ps
T740 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2936778669446728834362096451106209027749558143497945803745248617840835190522 Nov 01 12:33:58 PM PDT 23 Nov 01 12:34:03 PM PDT 23 2023227629 ps
T741 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.36536666512021862704457247326351215794885803843492208108073484465744951052413 Nov 01 12:34:09 PM PDT 23 Nov 01 12:34:16 PM PDT 23 2023227629 ps
T742 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.90725616873788635406708177671310249262569009764529931512210244047677859569681 Nov 01 12:34:20 PM PDT 23 Nov 01 12:34:31 PM PDT 23 2023227629 ps
T743 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.101448126091742614425561209714266938266003793124488776737647768966368146148807 Nov 01 12:33:54 PM PDT 23 Nov 01 12:34:00 PM PDT 23 2186637036 ps
T744 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.29471207149115879299502953926811939827004039274852262957988743974629380773893 Nov 01 12:34:17 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2023227629 ps
T745 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4694246786686997917266414159890482560669325768535974962486208724769942953702 Nov 01 12:33:55 PM PDT 23 Nov 01 12:34:21 PM PDT 23 9477310853 ps
T746 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.54966370457154998908509108029081926888673879136030856399499923094195783783792 Nov 01 12:34:06 PM PDT 23 Nov 01 12:34:13 PM PDT 23 2186637036 ps
T747 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.64349641972675557129092607258038754330068823608092490643989361939821432069791 Nov 01 12:34:02 PM PDT 23 Nov 01 12:34:11 PM PDT 23 2186637036 ps
T748 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.8325261560100034686590261380689834903651952682743425900353435527155577144623 Nov 01 12:34:19 PM PDT 23 Nov 01 12:34:30 PM PDT 23 2023227629 ps
T749 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.15448639361604443556350591739989161270546603343066745087437958940038905404997 Nov 01 12:34:27 PM PDT 23 Nov 01 12:34:34 PM PDT 23 2142012393 ps
T750 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.60727352582342005374071716277808036035491379222800887805523745481884153987368 Nov 01 12:34:15 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2142012393 ps
T751 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.32035702787533775751993740542950941989371410218036152747153627572422151250784 Nov 01 12:32:48 PM PDT 23 Nov 01 12:33:57 PM PDT 23 42510939439 ps
T752 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.46309734702344819601943599228068724258742012674928281275403720494611203864898 Nov 01 12:32:47 PM PDT 23 Nov 01 12:33:57 PM PDT 23 42510939439 ps
T753 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.81880298467112793605905687139256458971860481242851613373209869187262403609366 Nov 01 12:33:54 PM PDT 23 Nov 01 12:34:00 PM PDT 23 2074977215 ps
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