Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.95 97.93 94.86 100.00 79.49 97.01 94.01 66.35


Total test records in report: 782
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T754 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.57724348303568409150006974199886077604541168159660517190804409335864828026335 Nov 01 12:32:46 PM PDT 23 Nov 01 12:32:52 PM PDT 23 2074977215 ps
T755 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.95639233344723405034904355832476543644869577416030545870201478309435006082336 Nov 01 12:33:55 PM PDT 23 Nov 01 12:34:02 PM PDT 23 2186637036 ps
T756 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.85186760240034681158034840198442247032308284934467885534768626295878983793351 Nov 01 12:32:47 PM PDT 23 Nov 01 12:32:52 PM PDT 23 2023227629 ps
T757 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.96031381554798838404475491986558287302734890519105984512583082433090737681052 Nov 01 12:34:09 PM PDT 23 Nov 01 12:34:20 PM PDT 23 2023227629 ps
T758 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.59102889714910194787481780324379268238263803736276844179794218785985699149434 Nov 01 12:34:12 PM PDT 23 Nov 01 12:34:23 PM PDT 23 2023227629 ps
T759 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.18619326819706331228778186123420097419860156269428745425860480943424985020030 Nov 01 12:32:50 PM PDT 23 Nov 01 12:32:56 PM PDT 23 2023227629 ps
T760 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.110924451330289886268580040787498309973290548722704461765762286459003445991630 Nov 01 12:34:14 PM PDT 23 Nov 01 12:34:26 PM PDT 23 2074977215 ps
T761 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.92855222750318035977649168188709648419890171448623625631151178596601096950194 Nov 01 12:34:10 PM PDT 23 Nov 01 12:35:26 PM PDT 23 42510939439 ps
T762 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.30231419278716867884172244197930003745167397387418813555314864273597771564978 Nov 01 12:33:54 PM PDT 23 Nov 01 12:34:00 PM PDT 23 2142012393 ps
T763 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.19926265884785103449576024096346390243758292553774334063297261859140779481761 Nov 01 12:34:01 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2023227629 ps
T764 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.56831565592114138496020652243803671644933370120060407740603969367347131133970 Nov 01 12:33:57 PM PDT 23 Nov 01 12:34:04 PM PDT 23 2186637036 ps
T765 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.87646990423357818423381067887459229291024136682113526938131696570655627827116 Nov 01 12:33:54 PM PDT 23 Nov 01 12:34:01 PM PDT 23 2186637036 ps
T766 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.49984553545266851376463079898319659381281880411185695411681260893692199449701 Nov 01 12:33:55 PM PDT 23 Nov 01 12:34:00 PM PDT 23 2142012393 ps
T767 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.23798226610432785195829070734279382535810515473283101568450070260330318167863 Nov 01 12:32:50 PM PDT 23 Nov 01 12:32:56 PM PDT 23 2142012393 ps
T768 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.48356834263811015181761864993711798331606210333289924414318523894128970200662 Nov 01 12:32:48 PM PDT 23 Nov 01 12:33:58 PM PDT 23 42510939439 ps
T769 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1499426369496624553378727669541660951530602978029244850755075256382344299593 Nov 01 12:32:45 PM PDT 23 Nov 01 12:33:56 PM PDT 23 42510939439 ps
T770 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.77370907365570510554246219730548121587654008623143268886840339492118823788165 Nov 01 12:32:50 PM PDT 23 Nov 01 12:32:57 PM PDT 23 2186637036 ps
T89 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1195112164507326454185760269197237131511574674342792168660005236494363778087 Nov 01 12:32:43 PM PDT 23 Nov 01 12:34:37 PM PDT 23 41047879715 ps
T771 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.32690602199379324738700655570796784406654625636338391190522475051720051617902 Nov 01 12:34:00 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2023227629 ps
T772 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.27694502180754275541148943358131631908474041339692159508102230672097600650353 Nov 01 12:33:56 PM PDT 23 Nov 01 12:34:03 PM PDT 23 2186637036 ps
T773 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.50233865790265448125644858960940745100290818849085684469430936720376777679952 Nov 01 12:34:19 PM PDT 23 Nov 01 12:34:30 PM PDT 23 2023227629 ps
T90 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.19340541243979376633789410662503095399144519279607947067941208451973170098356 Nov 01 12:32:56 PM PDT 23 Nov 01 12:33:11 PM PDT 23 2890827831 ps
T91 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.89536624349478299326967852857092464147919591862562550510668862417857196762662 Nov 01 12:32:46 PM PDT 23 Nov 01 12:32:56 PM PDT 23 2890827831 ps
T774 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.112555316944960542327313497510201130662652696992523558684258230812501766218386 Nov 01 12:32:47 PM PDT 23 Nov 01 12:32:52 PM PDT 23 2142012393 ps
T775 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.89654444175322434871374371404745896307795993119985062863091759102363237101594 Nov 01 12:33:58 PM PDT 23 Nov 01 12:34:04 PM PDT 23 2074977215 ps
T776 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4590411985248332970188113551848565058204715055273215589919141513109214248513 Nov 01 12:34:00 PM PDT 23 Nov 01 12:34:07 PM PDT 23 2023227629 ps
T777 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.27517523559928964787501472878775229204007880201281600766754555546006169612689 Nov 01 12:33:59 PM PDT 23 Nov 01 12:34:27 PM PDT 23 9477310853 ps
T778 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.44906645993363754340628442135805647732979564791928531381272741736916350493046 Nov 01 12:32:48 PM PDT 23 Nov 01 12:32:53 PM PDT 23 2023227629 ps
T779 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.37801073087217639745919515647526794181874546609608477121488500528415537005342 Nov 01 12:32:45 PM PDT 23 Nov 01 12:32:57 PM PDT 23 6030981281 ps
T780 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.77668516334331310269487124144724230195501887791454034821778722915038980660931 Nov 01 12:34:01 PM PDT 23 Nov 01 12:34:08 PM PDT 23 2023227629 ps
T781 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.67527613683182536667499295018892159573713872024110001918727801888636769229596 Nov 01 12:33:54 PM PDT 23 Nov 01 12:35:05 PM PDT 23 42510939439 ps
T782 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.42360364620469756737347656847056678797354605799263911290127228312502697152548 Nov 01 12:33:59 PM PDT 23 Nov 01 12:35:12 PM PDT 23 42510939439 ps

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.54101964499085958459570108021951211578338539503550074159155841561577853914397
Short name T23
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.65 seconds
Started Nov 01 12:35:18 PM PDT 23
Finished Nov 01 12:38:25 PM PDT 23
Peak memory 201312 kb
Host smart-ee373f04-2826-4935-be30-8a22310188c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54101964499085958459570108021951211578338539503550074159155841561577853914397 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.54101964499085958459570108021951211578338539503550074159155841
561577853914397
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.15992837095877640351765204091662819765037365588776555596172955446145291522749
Short name T28
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.01 seconds
Started Nov 01 12:34:53 PM PDT 23
Finished Nov 01 12:37:09 PM PDT 23
Peak memory 201312 kb
Host smart-59c9a21b-4bde-4f40-88e4-19857f32044f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15992837095877640351765204091662819765037365588776555596172955446145291522749 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.15992837095877640351765204091662819765037365588776555596172955446145291522749
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.79405147107908467455715302120331487305187868945832028621682349906058244002070
Short name T103
Test name
Test status
Simulation time 38606274248 ps
CPU time 60.93 seconds
Started Nov 01 12:34:11 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 201168 kb
Host smart-9f5ee688-8b31-4cfd-bc04-2d918a40790c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79405147107908467455715302120331487305187868945832028621682349906058244002070 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.79405147107908467455715302120331487305187868945832028621682349906058244002070
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.71935336627298364004430351157178383463178023689909641582451517797507659866360
Short name T19
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Nov 01 12:36:09 PM PDT 23
Finished Nov 01 12:36:15 PM PDT 23
Peak memory 201044 kb
Host smart-dee241a1-bc80-4dbe-b4eb-71a808dfc726
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71935336627298364004430351157178383463178023689909641582451517797507659866360 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.719353366272983640044303511571783834631780236899096415824515
17797507659866360
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.44113737527177941741293664063359324335078132752061311092277509551915377358064
Short name T155
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Nov 01 12:34:14 PM PDT 23
Finished Nov 01 12:34:28 PM PDT 23
Peak memory 201024 kb
Host smart-c993fd7b-ed58-41ba-9509-7c44b1654535
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44113737527177941741293664063359324335078132752061311092277509551915377358064 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.44113737527177941741293664063359324335078132752061311092277509551915377358064
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1267375251769653122994758530503234935698583336706594356935723418108714247390
Short name T2
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.54 seconds
Started Nov 01 12:34:07 PM PDT 23
Finished Nov 01 12:35:20 PM PDT 23
Peak memory 201168 kb
Host smart-59e43825-00f0-41ec-8b23-f3ba1feb0fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267375251769653122994758530503234935698583336706594356935723418108714247390 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.126737525176965312299475853050323493569858333670659435693572341
8108714247390
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.74194189582001253730216240824279267005123457272384984212009205963432235924493
Short name T106
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 201196 kb
Host smart-749cc2ef-50af-4065-a903-8e2f0bb8341f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74194189582001253730216240824279267005123457272384984212009205963432235924493 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.74194189582001253730216240824279267005123457272384984212009205963432235924493
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.46889905232374007827624164036823776373468529760103493671115573936043216300546
Short name T9
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.82 seconds
Started Nov 01 12:32:49 PM PDT 23
Finished Nov 01 12:32:56 PM PDT 23
Peak memory 201164 kb
Host smart-d8ab9853-7a12-4520-9ca3-c515389acec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46889905232374007827624164036823776373468529760103493671115573936043216300546 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.46889905232374007827624164036823776373468529760103493671115573936043216300546
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.39288713876500025369340096373056104102446973161468324966399198319375155795101
Short name T174
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.62 seconds
Started Nov 01 12:36:13 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 201044 kb
Host smart-5ea3c0d0-d2f3-4bee-8bbb-5a6e9512fc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39288713876500025369340096373056104102446973161468324966399198319375155795101 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.39288713876500025369340096373056104102446973161468324966399198319375155795101
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.71849573008659823636006262493188620087312028249946769501778134959752337896491
Short name T80
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.27 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:46 PM PDT 23
Peak memory 201060 kb
Host smart-76988604-055e-4619-a36d-0de3b0d0206d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71849573008659823636006262493188620087312028249946769501778134959752337896491
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.71849573008659823636006262493188620087312028
249946769501778134959752337896491
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.53466127952281109352755076010327236426967245052900390698887449861621446683269
Short name T176
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.69 seconds
Started Nov 01 12:35:31 PM PDT 23
Finished Nov 01 12:35:38 PM PDT 23
Peak memory 201008 kb
Host smart-95e41d7f-cc53-41fb-bccb-1c950d432ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53466127952281109352755076010327236426967245052900390698887449861621446683269 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.53466127952281109352755076010327236426967245052900390698887449861621446683269
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.107015294688693868622386958191923721396908042287631448219476563387127417722548
Short name T162
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.94 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:35:28 PM PDT 23
Peak memory 221420 kb
Host smart-8283b65d-584d-49aa-a8db-6b3805543dec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107015294688693868622386958191923721396908042287631448219476563387127417722548 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.107015294688693868622386958191923721396908042287631448219476563387127417722548
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.28370621206480264015756273119346910204778006329725849615698173227232753963189
Short name T78
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.84 seconds
Started Nov 01 12:32:49 PM PDT 23
Finished Nov 01 12:32:54 PM PDT 23
Peak memory 200920 kb
Host smart-f6bff05d-25f5-47fc-9bae-5752d8b96b94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28370621206480264015756273119346910204778006329725849615698173227232753963189 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.28370621206480264015756273119346910204778006329725849615698173227232753963189
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.103226429971627416501438283080155981316313569080443960003590010269179803356370
Short name T11
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.57 seconds
Started Nov 01 12:32:53 PM PDT 23
Finished Nov 01 12:33:03 PM PDT 23
Peak memory 201108 kb
Host smart-646ca067-d446-4818-b48d-ddb032fb9c8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103226429971627416501438283080155981316313569080443960003590010269179803356370 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.1032264299716274165014382830801559813163135690804439600035900102
69179803356370
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2220556477446406670769183768602891094594417993033041880753499252969857960984
Short name T117
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.23 seconds
Started Nov 01 12:34:07 PM PDT 23
Finished Nov 01 12:34:13 PM PDT 23
Peak memory 201076 kb
Host smart-e6bbfaf5-4541-45f4-943b-273e5dd136d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220556477446406670769183768602891094594417993033041880753499252969857960984 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2220556477446406670769183768602891094594417993033041880753499252969857960984
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.105593753470254163698516362743961953021204670104782458911532427660328911121726
Short name T205
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.31 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 201020 kb
Host smart-8a4fee42-6f5a-493c-95a7-3bb3652f643c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105593753470254163698516362743961953021204670104782458911532427660328911121726 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.10559375347025416369851636274396195302120467010478245891153
2427660328911121726
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.89536624349478299326967852857092464147919591862562550510668862417857196762662
Short name T91
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.41 seconds
Started Nov 01 12:32:46 PM PDT 23
Finished Nov 01 12:32:56 PM PDT 23
Peak memory 201128 kb
Host smart-7a43cd98-24fe-4ff3-a62f-bfa335515c09
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89536624349478299326967852857092464147919591862562550510668862417857196762662 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.89536624349478299326967852857092464147919591862562550510668862417857196762662
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.42708890186965436463288721390522416205222940809902184707662740732074058873946
Short name T86
Test name
Test status
Simulation time 41047879715 ps
CPU time 114.06 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:34:46 PM PDT 23
Peak memory 201104 kb
Host smart-0faba297-3c34-423b-88c2-143c82b3c86c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42708890186965436463288721390522416205222940809902184707662740732074058873946 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.42708890186965436463288721390522416205222940809902184707662740732074058873946
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.69376677514998067291604121393877699913263634963320707878505706167525866870853
Short name T94
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.9 seconds
Started Nov 01 12:32:51 PM PDT 23
Finished Nov 01 12:33:02 PM PDT 23
Peak memory 200972 kb
Host smart-1f2df764-2a28-4e3f-be35-514e53db8897
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69376677514998067291604121393877699913263634963320707878505706167525866870853 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.69376677514998067291604121393877699913263634963320707878505706167525866870853
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.5675981154659992647732603803910964757900446528880462084819174837210737955608
Short name T700
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.22 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:32:56 PM PDT 23
Peak memory 200932 kb
Host smart-6fe39f49-b59c-4502-bc3a-a7ecd67308b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5675981154659992647732603803910964757900446
528880462084819174837210737955608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.56759
81154659992647732603803910964757900446528880462084819174837210737955608
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.9129797563452337013376491137876490483443889705598971417268037041825176872938
Short name T70
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:32:56 PM PDT 23
Peak memory 200888 kb
Host smart-fbf09ee2-e7cd-42f8-9854-b2a8c7568885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9129797563452337013376491137876490483443889705598971417268037041825176872938 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.9129797563452337013376491137876490483443889705598971417268037041825176872938
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.110679479429523991785634536832469980500403111025306105912218533135072925272527
Short name T704
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.35 seconds
Started Nov 01 12:32:48 PM PDT 23
Finished Nov 01 12:33:13 PM PDT 23
Peak memory 201108 kb
Host smart-70735189-fc2f-478d-a7dd-51916e9eab20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110679479429523991785634536832469980500403111025306105912218533135072925272527
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.11067947942952399178563453683246998050040311
1025306105912218533135072925272527
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.77370907365570510554246219730548121587654008623143268886840339492118823788165
Short name T770
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.79 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:32:57 PM PDT 23
Peak memory 201196 kb
Host smart-f33d83f4-3eab-414c-a403-e92ac96f2da0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77370907365570510554246219730548121587654008623143268886840339492118823788165 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.77370907365570510554246219730548121587654008623143268886840339492118823788165
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.74764158507443590358644794505033049831332433088708803476170462568805733166833
Short name T53
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.55 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:34:01 PM PDT 23
Peak memory 201224 kb
Host smart-823e5d9b-ead8-4c88-9c83-b84fe1573881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74764158507443590358644794505033049831332433088708803476170462568805733166833 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.747641585074435903586447945050330498313324330887088034761704625
68805733166833
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.18070121154722093871968303725771753940654796915073793219708033755429939287082
Short name T87
Test name
Test status
Simulation time 41047879715 ps
CPU time 112.27 seconds
Started Nov 01 12:32:47 PM PDT 23
Finished Nov 01 12:34:41 PM PDT 23
Peak memory 201072 kb
Host smart-9e030d03-a5fe-4592-9aca-0202ab24dc98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070121154722093871968303725771753940654796915073793219708033755429939287082 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.18070121154722093871968303725771753940654796915073793219708033755429939287082
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.17084061575834671269913462478852428467461394642307463161873383692306892722730
Short name T92
Test name
Test status
Simulation time 6030981281 ps
CPU time 10.05 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:33:02 PM PDT 23
Peak memory 200976 kb
Host smart-10d6cb0c-ab06-4ff9-9652-85a3e4eb8593
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17084061575834671269913462478852428467461394642307463161873383692306892722730 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.17084061575834671269913462478852428467461394642307463161873383692306892722730
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.81198049747229444664163945598025893488216778231018339043746963651029174053708
Short name T726
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.23 seconds
Started Nov 01 12:32:54 PM PDT 23
Finished Nov 01 12:33:06 PM PDT 23
Peak memory 200956 kb
Host smart-24754ad1-2a41-408e-8f1b-b1b1d1ef0c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8119804974722944466416394559802589348821677
8231018339043746963651029174053708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.8119
8049747229444664163945598025893488216778231018339043746963651029174053708
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.52326842105324320357932724872687756116059046103431160285507266750244214730041
Short name T83
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.45 seconds
Started Nov 01 12:32:53 PM PDT 23
Finished Nov 01 12:32:58 PM PDT 23
Peak memory 200788 kb
Host smart-3169ddcd-3810-4dc8-b823-fedacec2c911
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52326842105324320357932724872687756116059046103431160285507266750244214730041 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.52326842105324320357932724872687756116059046103431160285507266750244214730041
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.68838788270718195408225332420189415203392881620002687457768105102804690003726
Short name T719
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 01 12:32:51 PM PDT 23
Finished Nov 01 12:32:56 PM PDT 23
Peak memory 200860 kb
Host smart-225c7635-8186-4188-885c-515f029a74b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68838788270718195408225332420189415203392881620002687457768105102804690003726 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.68838788270718195408225332420189415203392881620002687457768105102804690003726
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.3400030629568732632503027905866994848143642991624385530479798269365306159109
Short name T706
Test name
Test status
Simulation time 9477310853 ps
CPU time 25 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:33:17 PM PDT 23
Peak memory 201108 kb
Host smart-a0b1acd1-d339-40c0-b0e1-a0746c19a42c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400030629568732632503027905866994848143642991624385530479798269365306159109 -
assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.3400030629568732632503027905866994848143642991
624385530479798269365306159109
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.60335705110632790236701475319257914208873502088440808677085927277399533114008
Short name T59
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.65 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:32:57 PM PDT 23
Peak memory 201104 kb
Host smart-be5418f7-994d-44a6-bd19-b170d7ad21d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60335705110632790236701475319257914208873502088440808677085927277399533114008 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.60335705110632790236701475319257914208873502088440808677085927277399533114008
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.32035702787533775751993740542950941989371410218036152747153627572422151250784
Short name T751
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.53 seconds
Started Nov 01 12:32:48 PM PDT 23
Finished Nov 01 12:33:57 PM PDT 23
Peak memory 201160 kb
Host smart-6408200c-81c7-41f2-b9c3-95af5240fc72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32035702787533775751993740542950941989371410218036152747153627572422151250784 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.320357027875337757519937405429509419893714102180361527471536275
72422151250784
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.97183075109448591752630899814240045319222792240247134403794830700714838090278
Short name T1
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 200932 kb
Host smart-83180f37-3a16-4120-89eb-8a0e779a5616
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9718307510944859175263089981424004531922279
2240247134403794830700714838090278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.971
83075109448591752630899814240045319222792240247134403794830700714838090278
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.24239926345981254007527124907664031480093062861533224421023415225332940736738
Short name T13
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.06 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 200900 kb
Host smart-c0c94ade-97b2-4080-8a1d-342f9f8ae1d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24239926345981254007527124907664031480093062861533224421023415225332940736738 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.24239926345981254007527124907664031480093062861533224421023415225332940736738
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.101831103167433087259249885868180325118010990456754520642780302726446944720240
Short name T693
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 01 12:33:59 PM PDT 23
Finished Nov 01 12:34:07 PM PDT 23
Peak memory 200836 kb
Host smart-c80e8d79-6b31-43cf-ae06-1d37bd52d76b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101831103167433087259249885868180325118010990456754520642780302726446944720240 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.101831103167433087259249885868180325118010990456754520642780302726446944720240
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.55715123584677958265814885050082330776990583477405561543826520480748378068427
Short name T690
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.61 seconds
Started Nov 01 12:34:12 PM PDT 23
Finished Nov 01 12:34:43 PM PDT 23
Peak memory 201008 kb
Host smart-357940eb-1bb5-44b1-89bf-c0e9711f1be0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55715123584677958265814885050082330776990583477405561543826520480748378068427
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.55715123584677958265814885050082330776990583
477405561543826520480748378068427
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.64349641972675557129092607258038754330068823608092490643989361939821432069791
Short name T747
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.73 seconds
Started Nov 01 12:34:02 PM PDT 23
Finished Nov 01 12:34:11 PM PDT 23
Peak memory 201220 kb
Host smart-cd539b34-5e57-412a-9b09-601f1c8e3ab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64349641972675557129092607258038754330068823608092490643989361939821432069791 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.64349641972675557129092607258038754330068823608092490643989361939821432069791
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.51932362638132077611627973148305126128359836926915973227487501277977309027814
Short name T5
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.13 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:35:25 PM PDT 23
Peak memory 201148 kb
Host smart-0ef61af6-3d5d-4f7e-ac84-298f10657e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51932362638132077611627973148305126128359836926915973227487501277977309027814 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.51932362638132077611627973148305126128359836926915973227487501
277977309027814
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.91689190944588315164403323215931663367915654255492476392396179774576593004222
Short name T4
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.14 seconds
Started Nov 01 12:34:08 PM PDT 23
Finished Nov 01 12:34:17 PM PDT 23
Peak memory 200984 kb
Host smart-bc8e7f53-228b-4f78-815a-f9a6a50f128f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9168919094458831516440332321593166336791565
4255492476392396179774576593004222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.916
89190944588315164403323215931663367915654255492476392396179774576593004222
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.77450512279224235292296361771229327185117484395480212738049114680295078393228
Short name T12
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.14 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200776 kb
Host smart-57cbb377-143a-48e8-b979-b60aa0b811fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77450512279224235292296361771229327185117484395480212738049114680295078393228 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.77450512279224235292296361771229327185117484395480212738049114680295078393228
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.96031381554798838404475491986558287302734890519105984512583082433090737681052
Short name T757
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:34:20 PM PDT 23
Peak memory 200880 kb
Host smart-37bc6577-a66a-4421-b298-10b905092780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96031381554798838404475491986558287302734890519105984512583082433090737681052 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.96031381554798838404475491986558287302734890519105984512583082433090737681052
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.79900808349738469302751434247891242637723585672111748631701773232425704237970
Short name T682
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.26 seconds
Started Nov 01 12:34:08 PM PDT 23
Finished Nov 01 12:34:36 PM PDT 23
Peak memory 201108 kb
Host smart-659c8482-f6c8-4e12-9c15-f659dfd89567
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79900808349738469302751434247891242637723585672111748631701773232425704237970
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.79900808349738469302751434247891242637723585
672111748631701773232425704237970
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.54966370457154998908509108029081926888673879136030856399499923094195783783792
Short name T746
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.64 seconds
Started Nov 01 12:34:06 PM PDT 23
Finished Nov 01 12:34:13 PM PDT 23
Peak memory 201112 kb
Host smart-f6545382-9bde-495e-8022-6ab804164f08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54966370457154998908509108029081926888673879136030856399499923094195783783792 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.54966370457154998908509108029081926888673879136030856399499923094195783783792
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.69711774107045171123849291793203015135172523752418618017345112949848172899802
Short name T8
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.88 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:35:25 PM PDT 23
Peak memory 201148 kb
Host smart-59d1d5af-a2df-4e40-b5ec-606d8d72ba5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69711774107045171123849291793203015135172523752418618017345112949848172899802 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.69711774107045171123849291793203015135172523752418618017345112
949848172899802
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.102788428945403564326928513853874978121089720569462031766384701319814107707825
Short name T6
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.24 seconds
Started Nov 01 12:34:24 PM PDT 23
Finished Nov 01 12:34:33 PM PDT 23
Peak memory 201012 kb
Host smart-15c0e39a-0b18-4711-af94-5a3a7a1b54c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027884289454035643269285138538749781210897
20569462031766384701319814107707825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.10
2788428945403564326928513853874978121089720569462031766384701319814107707825
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.57241968447011275193463150032568518658462578814208768797082195440102340865359
Short name T686
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.26 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200828 kb
Host smart-d3472a49-9d07-4e00-a6c3-38d36305b511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57241968447011275193463150032568518658462578814208768797082195440102340865359 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.57241968447011275193463150032568518658462578814208768797082195440102340865359
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.81275778889127532168688851639231316378620771256245251792700309780915911152638
Short name T679
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:25 PM PDT 23
Peak memory 200824 kb
Host smart-88e1f155-4310-4501-970f-7a0f97bbf936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81275778889127532168688851639231316378620771256245251792700309780915911152638 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.81275778889127532168688851639231316378620771256245251792700309780915911152638
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.110073314820149455492477158588858338038635393127653481469294453253419498084370
Short name T58
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.67 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:34:27 PM PDT 23
Peak memory 200956 kb
Host smart-48d1570c-945e-4634-b510-3f10aa40a4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110073314820149455492477158588858338038635393127653481469294453253419498084370 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.110073314820149455492477158588858338038635393127653481469294453253419498084370
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.15448639361604443556350591739989161270546603343066745087437958940038905404997
Short name T749
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Nov 01 12:34:27 PM PDT 23
Finished Nov 01 12:34:34 PM PDT 23
Peak memory 200952 kb
Host smart-d2b3f5c1-64bf-4ee1-8ed8-f12f6ebb04a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544863936160444355635059173998916127054660
3343066745087437958940038905404997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.154
48639361604443556350591739989161270546603343066745087437958940038905404997
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.110924451330289886268580040787498309973290548722704461765762286459003445991630
Short name T760
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.07 seconds
Started Nov 01 12:34:14 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200740 kb
Host smart-d1e945d7-1a34-48c9-b5af-4228f283a08a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110924451330289886268580040787498309973290548722704461765762286459003445991630 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.110924451330289886268580040787498309973290548722704461765762286459003445991630
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.12285822368806828792028544557379912513140309604324810173836862130416707723678
Short name T728
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Nov 01 12:34:24 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 200852 kb
Host smart-fcd62426-8918-4f5d-b75f-68bee00ef51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12285822368806828792028544557379912513140309604324810173836862130416707723678 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.12285822368806828792028544557379912513140309604324810173836862130416707723678
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.11401293202428538917972241100678912613365875942933711047906647726039384777024
Short name T65
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.09 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:34:47 PM PDT 23
Peak memory 201112 kb
Host smart-19233b02-ff61-487d-bde8-72861599f107
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11401293202428538917972241100678912613365875942933711047906647726039384777024
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.11401293202428538917972241100678912613365875
942933711047906647726039384777024
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.65377411222006171883240838362494177621201112362518477048984604626482533793974
Short name T725
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.73 seconds
Started Nov 01 12:34:26 PM PDT 23
Finished Nov 01 12:34:35 PM PDT 23
Peak memory 201124 kb
Host smart-22d4ab82-e092-48c5-9164-d8f960955320
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65377411222006171883240838362494177621201112362518477048984604626482533793974 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.65377411222006171883240838362494177621201112362518477048984604626482533793974
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.112745009731811886786743828322451831544014695037703178351438814251438909863456
Short name T52
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.78 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:35:31 PM PDT 23
Peak memory 201212 kb
Host smart-ae9deb1c-dfba-46a8-8c99-327dde1658cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112745009731811886786743828322451831544014695037703178351438814251438909863456 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.1127450097318118867867438283224518315440146950377031783514388
14251438909863456
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.49984553545266851376463079898319659381281880411185695411681260893692199449701
Short name T766
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.21 seconds
Started Nov 01 12:33:55 PM PDT 23
Finished Nov 01 12:34:00 PM PDT 23
Peak memory 200916 kb
Host smart-6eac6dbb-1b5c-4250-b405-3ccf1d61caca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4998455354526685137646307989831965938128188
0411185695411681260893692199449701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.499
84553545266851376463079898319659381281880411185695411681260893692199449701
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.81880298467112793605905687139256458971860481242851613373209869187262403609366
Short name T753
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.41 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:34:00 PM PDT 23
Peak memory 200900 kb
Host smart-5a30d34a-286a-42ad-ab2d-5cac59ecb522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81880298467112793605905687139256458971860481242851613373209869187262403609366 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.81880298467112793605905687139256458971860481242851613373209869187262403609366
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.943917946617898085401991254705369881080405645182593540532662813686127380507
Short name T75
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:33:59 PM PDT 23
Peak memory 200868 kb
Host smart-088e3b27-df57-404b-a640-4842fd034b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943917946617898085401991254705369881080405645182593540532662813686127380507 -assert nopostproc +UVM
_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.943917946617898085401991254705369881080405645182593540532662813686127380507
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.102356448637781210637599369715624518648677727366464146407065325215235327818399
Short name T95
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.62 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:34:20 PM PDT 23
Peak memory 201072 kb
Host smart-d8e11f8e-33d1-4436-b671-55ec20496156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102356448637781210637599369715624518648677727366464146407065325215235327818399
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.1023564486377812106375993697156245186486777
27366464146407065325215235327818399
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.83153867648018391972125059018629224948206593548465584125029664207756670963473
Short name T63
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.61 seconds
Started Nov 01 12:34:18 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 201152 kb
Host smart-ec32373f-bdc0-4b70-873b-f01edbcce55d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83153867648018391972125059018629224948206593548465584125029664207756670963473 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.83153867648018391972125059018629224948206593548465584125029664207756670963473
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.52136374637097754203518733245371769362170656752825950793408276427635587815752
Short name T735
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.92 seconds
Started Nov 01 12:34:20 PM PDT 23
Finished Nov 01 12:35:37 PM PDT 23
Peak memory 201140 kb
Host smart-6b092204-e6f2-4dda-bc5f-6ee5b936d76b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52136374637097754203518733245371769362170656752825950793408276427635587815752 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.52136374637097754203518733245371769362170656752825950793408276
427635587815752
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.30231419278716867884172244197930003745167397387418813555314864273597771564978
Short name T762
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:34:00 PM PDT 23
Peak memory 200916 kb
Host smart-24dc2564-b4c3-4c72-9408-1c1f226597c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023141927871686788417224419793000374516739
7387418813555314864273597771564978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.302
31419278716867884172244197930003745167397387418813555314864273597771564978
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.23379608019568173362002569007307628980717039693430963843873406977816651398882
Short name T727
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.16 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:33:59 PM PDT 23
Peak memory 200828 kb
Host smart-152f62a6-fe05-4d0b-b52b-a7f9f84135ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23379608019568173362002569007307628980717039693430963843873406977816651398882 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.23379608019568173362002569007307628980717039693430963843873406977816651398882
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.91503654075832948947342248244166444690187450980711087753277628613001699208587
Short name T697
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 01 12:33:55 PM PDT 23
Finished Nov 01 12:34:00 PM PDT 23
Peak memory 200844 kb
Host smart-57f29d1d-ba4a-4b72-9153-beb916a72bc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91503654075832948947342248244166444690187450980711087753277628613001699208587 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.91503654075832948947342248244166444690187450980711087753277628613001699208587
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4694246786686997917266414159890482560669325768535974962486208724769942953702
Short name T745
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.38 seconds
Started Nov 01 12:33:55 PM PDT 23
Finished Nov 01 12:34:21 PM PDT 23
Peak memory 201092 kb
Host smart-2b8321ad-9a84-455a-9de7-b4a6c0faca5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4694246786686997917266414159890482560669325768535974962486208724769942953702 -
assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.469424678668699791726641415989048256066932576
8535974962486208724769942953702
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.87646990423357818423381067887459229291024136682113526938131696570655627827116
Short name T765
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.7 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:34:01 PM PDT 23
Peak memory 201120 kb
Host smart-2901bf27-ddba-4290-9156-eb5c0be89181
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87646990423357818423381067887459229291024136682113526938131696570655627827116 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.87646990423357818423381067887459229291024136682113526938131696570655627827116
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.114179176506734437498072015917402733028185650868416744933087023184564914655560
Short name T733
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.56 seconds
Started Nov 01 12:33:56 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 201192 kb
Host smart-354199a5-0703-4ed6-93d7-3eb03be74d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114179176506734437498072015917402733028185650868416744933087023184564914655560 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.1141791765067344374980720159174027330281856508684167449330870
23184564914655560
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.93153097720255102850904062830572789093249428953988007711844302607802862597385
Short name T3
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:34:02 PM PDT 23
Peak memory 200936 kb
Host smart-cce62276-2da3-458c-a080-d7fb5520960f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9315309772025510285090406283057278909324942
8953988007711844302607802862597385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.931
53097720255102850904062830572789093249428953988007711844302607802862597385
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.59923381936593792070995271609782827195934922524020797985173879915722319472962
Short name T703
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.08 seconds
Started Nov 01 12:34:04 PM PDT 23
Finished Nov 01 12:34:10 PM PDT 23
Peak memory 200684 kb
Host smart-4bf8a30f-1199-442e-850c-2867189ab71d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59923381936593792070995271609782827195934922524020797985173879915722319472962 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.59923381936593792070995271609782827195934922524020797985173879915722319472962
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.69130020848029711900721226524586329259783516230879487595529369120301915274879
Short name T687
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.66 seconds
Started Nov 01 12:34:03 PM PDT 23
Finished Nov 01 12:34:09 PM PDT 23
Peak memory 200900 kb
Host smart-1b131ff6-edc6-42df-891a-9429318ad128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69130020848029711900721226524586329259783516230879487595529369120301915274879 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.69130020848029711900721226524586329259783516230879487595529369120301915274879
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.79925122495544264770656751072407170635352113809398045947194308195711636495055
Short name T695
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.59 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:34:23 PM PDT 23
Peak memory 201132 kb
Host smart-b96e4000-f239-4b3a-a8e7-6ac385a9ec20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79925122495544264770656751072407170635352113809398045947194308195711636495055
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.79925122495544264770656751072407170635352113
809398045947194308195711636495055
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.101448126091742614425561209714266938266003793124488776737647768966368146148807
Short name T743
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.66 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:34:00 PM PDT 23
Peak memory 201048 kb
Host smart-bad776da-a8f2-4704-a2c9-5b1a2d19bc91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101448126091742614425561209714266938266003793124488776737647768966368146148807 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.101448126091742614425561209714266938266003793124488776737647768966368146148807
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.42360364620469756737347656847056678797354605799263911290127228312502697152548
Short name T782
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.22 seconds
Started Nov 01 12:33:59 PM PDT 23
Finished Nov 01 12:35:12 PM PDT 23
Peak memory 201168 kb
Host smart-96f0b43c-a7ce-4ccd-bd02-a7ca9f24e5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42360364620469756737347656847056678797354605799263911290127228312502697152548 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.42360364620469756737347656847056678797354605799263911290127228
312502697152548
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.109798200341382608533411792346116356445690422639904476035168420334853162599726
Short name T715
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.24 seconds
Started Nov 01 12:34:01 PM PDT 23
Finished Nov 01 12:34:09 PM PDT 23
Peak memory 200972 kb
Host smart-41856225-82e4-45b3-abcb-2ea86985ed0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097982003413826085334117923461163564456904
22639904476035168420334853162599726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.10
9798200341382608533411792346116356445690422639904476035168420334853162599726
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.89654444175322434871374371404745896307795993119985062863091759102363237101594
Short name T775
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.12 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:04 PM PDT 23
Peak memory 200900 kb
Host smart-e5159b0b-73fd-4bc1-9810-852ea500c259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89654444175322434871374371404745896307795993119985062863091759102363237101594 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.89654444175322434871374371404745896307795993119985062863091759102363237101594
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.36536666512021862704457247326351215794885803843492208108073484465744951052413
Short name T741
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:34:16 PM PDT 23
Peak memory 200804 kb
Host smart-2aa0b034-ac63-485b-b276-9935bcc5a61c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36536666512021862704457247326351215794885803843492208108073484465744951052413 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.36536666512021862704457247326351215794885803843492208108073484465744951052413
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.90536010550480324986135702999349640981790758385456396216968121681213393555998
Short name T15
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.28 seconds
Started Nov 01 12:34:02 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 201228 kb
Host smart-b7219ca4-673c-461f-baf0-8c419af024ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90536010550480324986135702999349640981790758385456396216968121681213393555998
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.90536010550480324986135702999349640981790758
385456396216968121681213393555998
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.27694502180754275541148943358131631908474041339692159508102230672097600650353
Short name T772
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.85 seconds
Started Nov 01 12:33:56 PM PDT 23
Finished Nov 01 12:34:03 PM PDT 23
Peak memory 201084 kb
Host smart-d86e68f1-f424-4f9d-b735-820278082791
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27694502180754275541148943358131631908474041339692159508102230672097600650353 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.27694502180754275541148943358131631908474041339692159508102230672097600650353
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.89411058262378221628139849626247973964980768336085309675052663708564287194471
Short name T717
Test name
Test status
Simulation time 42510939439 ps
CPU time 70.35 seconds
Started Nov 01 12:34:04 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 200892 kb
Host smart-0cf8d593-c3e0-46f2-939e-e4613b9ac004
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89411058262378221628139849626247973964980768336085309675052663708564287194471 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.89411058262378221628139849626247973964980768336085309675052663
708564287194471
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.41503069985153558893734500376596393965417536003621463508845743625093102411724
Short name T688
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.24 seconds
Started Nov 01 12:34:05 PM PDT 23
Finished Nov 01 12:34:11 PM PDT 23
Peak memory 200952 kb
Host smart-b061c436-2dd6-47e4-acaf-b6639e64c8be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150306998515355889373450037659639396541753
6003621463508845743625093102411724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.415
03069985153558893734500376596393965417536003621463508845743625093102411724
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.47787199423131825915026527239356209686768069306705278859826539659917197929905
Short name T82
Test name
Test status
Simulation time 2074977215 ps
CPU time 4 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 200880 kb
Host smart-3e9db74e-6966-4dab-9700-8f391e9eb562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47787199423131825915026527239356209686768069306705278859826539659917197929905 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.47787199423131825915026527239356209686768069306705278859826539659917197929905
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.50233865790265448125644858960940745100290818849085684469430936720376777679952
Short name T773
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 200868 kb
Host smart-d9b1994e-81df-4687-b4ca-e90975eddd55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50233865790265448125644858960940745100290818849085684469430936720376777679952 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.50233865790265448125644858960940745100290818849085684469430936720376777679952
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.69704858901936276190714632758563241991627952079132453678310198993200111033085
Short name T64
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.12 seconds
Started Nov 01 12:34:05 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 201052 kb
Host smart-30be52e8-bd11-4a69-ada0-37f688d5928d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69704858901936276190714632758563241991627952079132453678310198993200111033085
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.69704858901936276190714632758563241991627952
079132453678310198993200111033085
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.46466184636766122988191311171982988438760731807137484182837633498409128588502
Short name T61
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.64 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:04 PM PDT 23
Peak memory 201120 kb
Host smart-67c971d8-f692-4a1a-95fa-30cb1c123738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46466184636766122988191311171982988438760731807137484182837633498409128588502 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.46466184636766122988191311171982988438760731807137484182837633498409128588502
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.51081935538629167832295106856549176088492478112617469072615350510211327872363
Short name T721
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.69 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:35:13 PM PDT 23
Peak memory 201148 kb
Host smart-1c0a6ca1-4f0e-484a-b7e2-5bb833ebf514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51081935538629167832295106856549176088492478112617469072615350510211327872363 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.51081935538629167832295106856549176088492478112617469072615350
510211327872363
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.60727352582342005374071716277808036035491379222800887805523745481884153987368
Short name T750
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.23 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200568 kb
Host smart-02178830-41de-4224-9bda-63c88bd8c977
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6072735258234200537407171627780803603549137
9222800887805523745481884153987368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.607
27352582342005374071716277808036035491379222800887805523745481884153987368
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.67171629698537822149372169686145499175180108481695703311429361881680527436
Short name T685
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.08 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 200800 kb
Host smart-61305d1b-560a-4e24-bcb3-bba8e184679f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67171629698537822149372169686145499175180108481695703311429361881680527436 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.67171629698537822149372169686145499175180108481695703311429361881680527436
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.92902826497144398442773262563473525856270616453623221307560245059110932669751
Short name T681
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 01 12:34:05 PM PDT 23
Finished Nov 01 12:34:10 PM PDT 23
Peak memory 200880 kb
Host smart-ab66de5e-194a-4f08-b78a-0b75b417ed60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92902826497144398442773262563473525856270616453623221307560245059110932669751 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.92902826497144398442773262563473525856270616453623221307560245059110932669751
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.44418506126846846418445404429236927534141800820955155721173245020951780933522
Short name T710
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.47 seconds
Started Nov 01 12:34:06 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 201092 kb
Host smart-63412569-2dac-4051-bd82-7bd5497c3f27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44418506126846846418445404429236927534141800820955155721173245020951780933522
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.44418506126846846418445404429236927534141800
820955155721173245020951780933522
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.66808342011128128353848477422909801204116537814409379034615333779354373015186
Short name T57
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.71 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:34:27 PM PDT 23
Peak memory 200816 kb
Host smart-c0d7a075-327f-453c-a92e-da64cf5c040b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66808342011128128353848477422909801204116537814409379034615333779354373015186 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.66808342011128128353848477422909801204116537814409379034615333779354373015186
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.6265010974294072765356778702621767834211902678534530868844520348641571435886
Short name T694
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.98 seconds
Started Nov 01 12:34:05 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 201104 kb
Host smart-ea339665-36d1-45c5-a4f3-8a449bea0c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6265010974294072765356778702621767834211902678534530868844520348641571435886 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.626501097429407276535677870262176783421190267853453086884452034
8641571435886
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.19340541243979376633789410662503095399144519279607947067941208451973170098356
Short name T90
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.31 seconds
Started Nov 01 12:32:56 PM PDT 23
Finished Nov 01 12:33:11 PM PDT 23
Peak memory 201048 kb
Host smart-3b5992d6-0836-4fc6-bab1-e8abaae37b73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19340541243979376633789410662503095399144519279607947067941208451973170098356 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.19340541243979376633789410662503095399144519279607947067941208451973170098356
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.80815579575240660970505382688501348153977782607813592991079678713797572120785
Short name T84
Test name
Test status
Simulation time 41047879715 ps
CPU time 111.15 seconds
Started Nov 01 12:32:55 PM PDT 23
Finished Nov 01 12:34:52 PM PDT 23
Peak memory 201088 kb
Host smart-40fdbc92-7b3d-4d18-bfa4-0db51ce6f0fe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80815579575240660970505382688501348153977782607813592991079678713797572120785 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.80815579575240660970505382688501348153977782607813592991079678713797572120785
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.80034543898565389497795483453390454281921564074769242620922382579113436742679
Short name T93
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.95 seconds
Started Nov 01 12:32:55 PM PDT 23
Finished Nov 01 12:33:11 PM PDT 23
Peak memory 201004 kb
Host smart-2ef6ed94-985f-43a7-98bd-ecd17d51699a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80034543898565389497795483453390454281921564074769242620922382579113436742679 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.80034543898565389497795483453390454281921564074769242620922382579113436742679
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.16731887835589486049904624851604794575940489011213279489072485815162140734831
Short name T7
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.2 seconds
Started Nov 01 12:32:56 PM PDT 23
Finished Nov 01 12:33:06 PM PDT 23
Peak memory 200900 kb
Host smart-fc9945ac-d292-4fe5-af71-2959dcf37547
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673188783558948604990462485160479457594048
9011213279489072485815162140734831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1673
1887835589486049904624851604794575940489011213279489072485815162140734831
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.81987290483949994762501721506715662977894082265694337236871665427650771865100
Short name T73
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.11 seconds
Started Nov 01 12:32:55 PM PDT 23
Finished Nov 01 12:33:04 PM PDT 23
Peak memory 200880 kb
Host smart-6613fb9f-0bea-422b-a514-f9bb4666823f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81987290483949994762501721506715662977894082265694337236871665427650771865100 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.81987290483949994762501721506715662977894082265694337236871665427650771865100
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.44906645993363754340628442135805647732979564791928531381272741736916350493046
Short name T778
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 01 12:32:48 PM PDT 23
Finished Nov 01 12:32:53 PM PDT 23
Peak memory 200848 kb
Host smart-4083e37c-9372-4321-8989-d375fc979d2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44906645993363754340628442135805647732979564791928531381272741736916350493046 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.44906645993363754340628442135805647732979564791928531381272741736916350493046
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.110656475782580013743209011118713094793406866873632406313925174486800884165581
Short name T96
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.43 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:33:16 PM PDT 23
Peak memory 201064 kb
Host smart-b3ad9882-bb13-4bcf-8dcf-441fb6e629f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110656475782580013743209011118713094793406866873632406313925174486800884165581
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.11065647578258001374320901111871309479340686
6873632406313925174486800884165581
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.96926492651986693858785330358540356385228761431810200324881973618133168571629
Short name T60
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.73 seconds
Started Nov 01 12:32:49 PM PDT 23
Finished Nov 01 12:32:57 PM PDT 23
Peak memory 201156 kb
Host smart-17102205-cf35-43f2-95cf-5cad05d349e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96926492651986693858785330358540356385228761431810200324881973618133168571629 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.96926492651986693858785330358540356385228761431810200324881973618133168571629
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.46309734702344819601943599228068724258742012674928281275403720494611203864898
Short name T752
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.53 seconds
Started Nov 01 12:32:47 PM PDT 23
Finished Nov 01 12:33:57 PM PDT 23
Peak memory 201136 kb
Host smart-76b96693-41b1-4bad-a51b-5c94df1b3788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46309734702344819601943599228068724258742012674928281275403720494611203864898 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.463097347023448196019435992280687242587420126749282812754037204
94611203864898
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.59102889714910194787481780324379268238263803736276844179794218785985699149434
Short name T758
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:34:12 PM PDT 23
Finished Nov 01 12:34:23 PM PDT 23
Peak memory 200828 kb
Host smart-c1f57bf6-b1c4-4433-9f7c-710f1ec3f522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59102889714910194787481780324379268238263803736276844179794218785985699149434 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.59102889714910194787481780324379268238263803736276844179794218785985699149434
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3329999491510152449141337198770993328094308383187198132542445242024729717423
Short name T161
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 200856 kb
Host smart-629f41cc-c0d6-4aef-a727-23a3d6b30525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329999491510152449141337198770993328094308383187198132542445242024729717423 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.3329999491510152449141337198770993328094308383187198132542445242024729717423
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.25753139607461517350680968135745974248082071646282760549151215477254252578955
Short name T160
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:34:25 PM PDT 23
Peak memory 200820 kb
Host smart-b4622af5-03b0-4c2e-9ac7-1db2cd3dcee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25753139607461517350680968135745974248082071646282760549151215477254252578955 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.25753139607461517350680968135745974248082071646282760549151215477254252578955
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.60958679187146661818492803574240503162565989159733483609705402684080582357192
Short name T702
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.82 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200844 kb
Host smart-02ce4410-725f-4e6d-90b6-e1ca9563c7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60958679187146661818492803574240503162565989159733483609705402684080582357192 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.60958679187146661818492803574240503162565989159733483609705402684080582357192
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.66902124279545657483404367177753281918446466643448845390555747326226494338543
Short name T69
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.67 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:34:16 PM PDT 23
Peak memory 200872 kb
Host smart-409be6b0-7a81-4844-bbbd-8016e3498861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66902124279545657483404367177753281918446466643448845390555747326226494338543 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.66902124279545657483404367177753281918446466643448845390555747326226494338543
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.28531308536468415361265678316193053403938656976725948700201935215473942666664
Short name T718
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 200728 kb
Host smart-79900018-606a-46a2-8b6c-eb6a41d39ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28531308536468415361265678316193053403938656976725948700201935215473942666664 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.28531308536468415361265678316193053403938656976725948700201935215473942666664
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.1153030728690165492843282736889028091205387501729544671890528882766714715237
Short name T711
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:34:18 PM PDT 23
Finished Nov 01 12:34:28 PM PDT 23
Peak memory 200760 kb
Host smart-2ec637ef-75d6-423b-8f01-040e28e4fc2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153030728690165492843282736889028091205387501729544671890528882766714715237 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.1153030728690165492843282736889028091205387501729544671890528882766714715237
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.100939466491603759364861650473617216298405039368614859123047229277274105846421
Short name T689
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 200864 kb
Host smart-597bd3e0-99ef-4745-b85f-a764050f8c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100939466491603759364861650473617216298405039368614859123047229277274105846421 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.100939466491603759364861650473617216298405039368614859123047229277274105846421
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.89525392948659552926441402981610112992129196049543969871719757843068438370247
Short name T739
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 01 12:34:11 PM PDT 23
Finished Nov 01 12:34:21 PM PDT 23
Peak memory 200844 kb
Host smart-ca6b7ea4-30cd-4814-9b8f-62a05c46d339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89525392948659552926441402981610112992129196049543969871719757843068438370247 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.89525392948659552926441402981610112992129196049543969871719757843068438370247
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.56333373789172131783929753632286878658311689301532590996862811168322662418821
Short name T707
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.85 seconds
Started Nov 01 12:34:20 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 200832 kb
Host smart-cb726da3-4987-4dab-94a7-59d8588b6ee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56333373789172131783929753632286878658311689301532590996862811168322662418821 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.56333373789172131783929753632286878658311689301532590996862811168322662418821
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.109377926632809838278462871859482325991461621158544408832189169243929332825064
Short name T85
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.57 seconds
Started Nov 01 12:32:46 PM PDT 23
Finished Nov 01 12:32:57 PM PDT 23
Peak memory 201048 kb
Host smart-6514a2f5-0cb7-42cb-8e37-30cfb7e6fd71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109377926632809838278462871859482325991461621158544408832189169243929332825064 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.1093779266328098382784628718594823259914616211585444088321891692
43929332825064
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.62613803023583039634583478205238464070653407631249995268166425964905865289559
Short name T68
Test name
Test status
Simulation time 41047879715 ps
CPU time 111.24 seconds
Started Nov 01 12:32:46 PM PDT 23
Finished Nov 01 12:34:39 PM PDT 23
Peak memory 201080 kb
Host smart-fd30b98f-6de1-47f6-b84c-da210085ce96
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62613803023583039634583478205238464070653407631249995268166425964905865289559 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.62613803023583039634583478205238464070653407631249995268166425964905865289559
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.78521348549167046434427876882466176439276222106469950776669844074514580421187
Short name T712
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.95 seconds
Started Nov 01 12:32:47 PM PDT 23
Finished Nov 01 12:32:58 PM PDT 23
Peak memory 201000 kb
Host smart-fbdcddb6-770d-4b9a-9da3-6eb2e043b1ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78521348549167046434427876882466176439276222106469950776669844074514580421187 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.78521348549167046434427876882466176439276222106469950776669844074514580421187
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.78907352500969132855752899942614980940231565375688747711024002813644686169393
Short name T705
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.14 seconds
Started Nov 01 12:32:44 PM PDT 23
Finished Nov 01 12:32:49 PM PDT 23
Peak memory 200868 kb
Host smart-f86cafa7-f0e9-4e1d-a9dd-f3b577355611
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7890735250096913285575289994261498094023156
5375688747711024002813644686169393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.7890
7352500969132855752899942614980940231565375688747711024002813644686169393
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.57724348303568409150006974199886077604541168159660517190804409335864828026335
Short name T754
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.02 seconds
Started Nov 01 12:32:46 PM PDT 23
Finished Nov 01 12:32:52 PM PDT 23
Peak memory 200840 kb
Host smart-7caa7184-bddc-45d2-b603-43259d49c2c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57724348303568409150006974199886077604541168159660517190804409335864828026335 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.57724348303568409150006974199886077604541168159660517190804409335864828026335
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.18619326819706331228778186123420097419860156269428745425860480943424985020030
Short name T759
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.7 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:32:56 PM PDT 23
Peak memory 200844 kb
Host smart-04f69263-af22-483f-81c1-bd0343b83fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18619326819706331228778186123420097419860156269428745425860480943424985020030 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.18619326819706331228778186123420097419860156269428745425860480943424985020030
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.25573959590073380585729824474454319670351875073065331796546151925541812241477
Short name T67
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.44 seconds
Started Nov 01 12:32:47 PM PDT 23
Finished Nov 01 12:33:13 PM PDT 23
Peak memory 201144 kb
Host smart-169865d3-a323-4fef-ba9e-d7ead6b2dbb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25573959590073380585729824474454319670351875073065331796546151925541812241477
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.255739595900733805857298244744543196703518750
73065331796546151925541812241477
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.41464041887781280582688551196326204254628996182579612885415945193010812702209
Short name T54
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.9 seconds
Started Nov 01 12:32:57 PM PDT 23
Finished Nov 01 12:33:08 PM PDT 23
Peak memory 201120 kb
Host smart-aad78aa7-5350-480c-a9f1-1f6807fb1541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464041887781280582688551196326204254628996182579612885415945193010812702209 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.41464041887781280582688551196326204254628996182579612885415945193010812702209
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.48356834263811015181761864993711798331606210333289924414318523894128970200662
Short name T768
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.14 seconds
Started Nov 01 12:32:48 PM PDT 23
Finished Nov 01 12:33:58 PM PDT 23
Peak memory 201072 kb
Host smart-f1e860b8-c897-4d4b-974e-cf13795000bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48356834263811015181761864993711798331606210333289924414318523894128970200662 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.483568342638110151817618649937117983316062103332899244143185238
94128970200662
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.82051363820212894495175648868608690209855440897091982230063942828614926109368
Short name T76
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.78 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200948 kb
Host smart-e4b48201-a428-4ba3-b696-f00061c3a239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82051363820212894495175648868608690209855440897091982230063942828614926109368 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.82051363820212894495175648868608690209855440897091982230063942828614926109368
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.29471207149115879299502953926811939827004039274852262957988743974629380773893
Short name T744
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200812 kb
Host smart-175169d3-0d9e-41cc-b0d9-55059b5a2320
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29471207149115879299502953926811939827004039274852262957988743974629380773893 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.29471207149115879299502953926811939827004039274852262957988743974629380773893
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.69684545143763362033596596983809981046018143243494135732548364226100422339742
Short name T77
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.81 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 200832 kb
Host smart-c6932cc2-3bf6-4761-b29f-c184908fb0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69684545143763362033596596983809981046018143243494135732548364226100422339742 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.69684545143763362033596596983809981046018143243494135732548364226100422339742
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.8325261560100034686590261380689834903651952682743425900353435527155577144623
Short name T748
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 200860 kb
Host smart-bf9c31b8-c5c4-48ea-86aa-c4a8802e327d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8325261560100034686590261380689834903651952682743425900353435527155577144623 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.8325261560100034686590261380689834903651952682743425900353435527155577144623
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.73389470765611601818383176010683951668496245671017244116365527911957432320735
Short name T713
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.78 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 200920 kb
Host smart-e2dbfbfa-4b23-4187-9778-021460ade339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73389470765611601818383176010683951668496245671017244116365527911957432320735 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.73389470765611601818383176010683951668496245671017244116365527911957432320735
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.90725616873788635406708177671310249262569009764529931512210244047677859569681
Short name T742
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.8 seconds
Started Nov 01 12:34:20 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 200812 kb
Host smart-084c23ab-54ce-4923-af84-3e61be787f01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90725616873788635406708177671310249262569009764529931512210244047677859569681 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.90725616873788635406708177671310249262569009764529931512210244047677859569681
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.32690602199379324738700655570796784406654625636338391190522475051720051617902
Short name T771
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 201180 kb
Host smart-b389bfae-bcb8-4359-b8de-d89bbae8c28f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32690602199379324738700655570796784406654625636338391190522475051720051617902 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.32690602199379324738700655570796784406654625636338391190522475051720051617902
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.77668516334331310269487124144724230195501887791454034821778722915038980660931
Short name T780
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 01 12:34:01 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 200812 kb
Host smart-5cf77ce7-becf-4c30-b91c-5d969fac2a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77668516334331310269487124144724230195501887791454034821778722915038980660931 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.77668516334331310269487124144724230195501887791454034821778722915038980660931
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.15310475837780578008967084717104552474437140277524209597016385282763555403505
Short name T729
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:33:56 PM PDT 23
Finished Nov 01 12:34:01 PM PDT 23
Peak memory 200844 kb
Host smart-cf389d03-8153-4339-8607-e992ba5148a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15310475837780578008967084717104552474437140277524209597016385282763555403505 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.15310475837780578008967084717104552474437140277524209597016385282763555403505
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.113834701125569026869020521983369369672954992564200771835628476675817024064120
Short name T81
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.69 seconds
Started Nov 01 12:34:02 PM PDT 23
Finished Nov 01 12:34:09 PM PDT 23
Peak memory 200928 kb
Host smart-dc41b400-5da8-49c7-8303-a612b00e80f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113834701125569026869020521983369369672954992564200771835628476675817024064120 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.113834701125569026869020521983369369672954992564200771835628476675817024064120
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.38989035345626369780594066753209565108414663567906066020805861422865280763489
Short name T88
Test name
Test status
Simulation time 2890827831 ps
CPU time 8.53 seconds
Started Nov 01 12:32:45 PM PDT 23
Finished Nov 01 12:32:54 PM PDT 23
Peak memory 200968 kb
Host smart-a3591592-d9c7-49ff-81f1-17be53066675
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38989035345626369780594066753209565108414663567906066020805861422865280763489 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.38989035345626369780594066753209565108414663567906066020805861422865280763489
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1195112164507326454185760269197237131511574674342792168660005236494363778087
Short name T89
Test name
Test status
Simulation time 41047879715 ps
CPU time 112.9 seconds
Started Nov 01 12:32:43 PM PDT 23
Finished Nov 01 12:34:37 PM PDT 23
Peak memory 201056 kb
Host smart-2fe7c6c0-9aca-43ca-9444-20bbcba3b0fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195112164507326454185760269197237131511574674342792168660005236494363778087 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.1195112164507326454185760269197237131511574674342792168660005236494363778087
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.37801073087217639745919515647526794181874546609608477121488500528415537005342
Short name T779
Test name
Test status
Simulation time 6030981281 ps
CPU time 9.91 seconds
Started Nov 01 12:32:45 PM PDT 23
Finished Nov 01 12:32:57 PM PDT 23
Peak memory 201020 kb
Host smart-1385de19-3889-40a0-ad2b-5b60cca90735
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37801073087217639745919515647526794181874546609608477121488500528415537005342 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.37801073087217639745919515647526794181874546609608477121488500528415537005342
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.112555316944960542327313497510201130662652696992523558684258230812501766218386
Short name T774
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.24 seconds
Started Nov 01 12:32:47 PM PDT 23
Finished Nov 01 12:32:52 PM PDT 23
Peak memory 200908 kb
Host smart-9e7c9014-a997-4960-bc0c-71938dd20e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125553169449605423273134975102011306626526
96992523558684258230812501766218386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.112
555316944960542327313497510201130662652696992523558684258230812501766218386
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.99568672430443885733083247322332874648455173563413951133338943617481479297115
Short name T714
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Nov 01 12:32:46 PM PDT 23
Finished Nov 01 12:32:52 PM PDT 23
Peak memory 200908 kb
Host smart-d20702a1-ee61-4f00-9f49-16c0695b5b59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99568672430443885733083247322332874648455173563413951133338943617481479297115 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.99568672430443885733083247322332874648455173563413951133338943617481479297115
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.85186760240034681158034840198442247032308284934467885534768626295878983793351
Short name T756
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.68 seconds
Started Nov 01 12:32:47 PM PDT 23
Finished Nov 01 12:32:52 PM PDT 23
Peak memory 200948 kb
Host smart-51e4daa6-020e-462e-a8a2-a52fb3ce9e19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85186760240034681158034840198442247032308284934467885534768626295878983793351 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.85186760240034681158034840198442247032308284934467885534768626295878983793351
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.11157352644179179540198456401091916106132409591371446102414335926030782837751
Short name T680
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.5 seconds
Started Nov 01 12:32:48 PM PDT 23
Finished Nov 01 12:33:14 PM PDT 23
Peak memory 201184 kb
Host smart-132c105d-9fc8-409d-9d3f-1e0912a1e5b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157352644179179540198456401091916106132409591371446102414335926030782837751
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.111573526441791795401984564010919161061324095
91371446102414335926030782837751
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.35315618775600341388791515225938329495987063486261491818860615685707543249025
Short name T56
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.14 seconds
Started Nov 01 12:32:45 PM PDT 23
Finished Nov 01 12:33:55 PM PDT 23
Peak memory 201012 kb
Host smart-138786d6-d9a7-413a-8fce-cfc507a8a129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35315618775600341388791515225938329495987063486261491818860615685707543249025 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.353156187756003413887915152259383294959870634862614918188606156
85707543249025
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.2936778669446728834362096451106209027749558143497945803745248617840835190522
Short name T740
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.65 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:03 PM PDT 23
Peak memory 200848 kb
Host smart-68e9bc54-7b66-49ce-8084-02086666ee25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936778669446728834362096451106209027749558143497945803745248617840835190522 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.2936778669446728834362096451106209027749558143497945803745248617840835190522
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.17487416404788725550650964843395166918054308250757360562225188438548021992210
Short name T699
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 01 12:33:59 PM PDT 23
Finished Nov 01 12:34:07 PM PDT 23
Peak memory 201180 kb
Host smart-e2815337-b156-47d0-b77c-33093e721e3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17487416404788725550650964843395166918054308250757360562225188438548021992210 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.17487416404788725550650964843395166918054308250757360562225188438548021992210
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.51711528553485023398810797120624030597841786310312084762000003999290871337735
Short name T684
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Nov 01 12:34:08 PM PDT 23
Finished Nov 01 12:34:15 PM PDT 23
Peak memory 200844 kb
Host smart-71a6de09-8edb-4472-a65f-e6543a49409f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51711528553485023398810797120624030597841786310312084762000003999290871337735 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.51711528553485023398810797120624030597841786310312084762000003999290871337735
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.19926265884785103449576024096346390243758292553774334063297261859140779481761
Short name T763
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 01 12:34:01 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 200812 kb
Host smart-347e9b57-779e-4c25-a29b-3b595199d781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19926265884785103449576024096346390243758292553774334063297261859140779481761 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.19926265884785103449576024096346390243758292553774334063297261859140779481761
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.14543914773149697102595098877915168384152330194851816298126092438059876938928
Short name T738
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.79 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:33:59 PM PDT 23
Peak memory 200844 kb
Host smart-af7e028a-9347-44c1-841f-9763afbbf6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14543914773149697102595098877915168384152330194851816298126092438059876938928 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.14543914773149697102595098877915168384152330194851816298126092438059876938928
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.41607604601889940823748554470623591916806358441059849617039516192434490553260
Short name T701
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.81 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 200884 kb
Host smart-7a02c1a9-f837-4505-9df5-2a5f0b1c1660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41607604601889940823748554470623591916806358441059849617039516192434490553260 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.41607604601889940823748554470623591916806358441059849617039516192434490553260
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4590411985248332970188113551848565058204715055273215589919141513109214248513
Short name T776
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:34:07 PM PDT 23
Peak memory 200860 kb
Host smart-a62d30d6-c48c-4f36-b243-b7819c2e9756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4590411985248332970188113551848565058204715055273215589919141513109214248513 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.4590411985248332970188113551848565058204715055273215589919141513109214248513
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.97791203177557543089821697521402661507813782874715289255420154275408726703927
Short name T722
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.73 seconds
Started Nov 01 12:34:12 PM PDT 23
Finished Nov 01 12:34:23 PM PDT 23
Peak memory 200840 kb
Host smart-1774c0b9-beec-4fc6-bb00-529cbbed6ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97791203177557543089821697521402661507813782874715289255420154275408726703927 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.97791203177557543089821697521402661507813782874715289255420154275408726703927
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.44640769358687539102968991497672505897292502360540467349721422610226514277820
Short name T683
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.77 seconds
Started Nov 01 12:34:01 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 200876 kb
Host smart-b5931151-07e3-4fc8-b6d7-ebe8d765f0ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44640769358687539102968991497672505897292502360540467349721422610226514277820 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.44640769358687539102968991497672505897292502360540467349721422610226514277820
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.59014060490566970439589456943208842662411838660992760332822171920267578836992
Short name T691
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.75 seconds
Started Nov 01 12:34:06 PM PDT 23
Finished Nov 01 12:34:11 PM PDT 23
Peak memory 200872 kb
Host smart-4b7a423a-2e4d-4900-8280-b0392f97473c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59014060490566970439589456943208842662411838660992760332822171920267578836992 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.59014060490566970439589456943208842662411838660992760332822171920267578836992
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.23798226610432785195829070734279382535810515473283101568450070260330318167863
Short name T767
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.11 seconds
Started Nov 01 12:32:50 PM PDT 23
Finished Nov 01 12:32:56 PM PDT 23
Peak memory 200928 kb
Host smart-b02b53c6-b228-4a48-99b1-73f7513cfb2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379822661043278519582907073427938253581051
5473283101568450070260330318167863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2379
8226610432785195829070734279382535810515473283101568450070260330318167863
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.112941293833695496080136997869205675686888835473282482998777009314700559422002
Short name T71
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.1 seconds
Started Nov 01 12:32:49 PM PDT 23
Finished Nov 01 12:32:54 PM PDT 23
Peak memory 200900 kb
Host smart-84217cc1-d339-4ad5-8bed-24cdb157bb16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112941293833695496080136997869205675686888835473282482998777009314700559422002 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.112941293833695496080136997869205675686888835473282482998777009314700559422002
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.7021833094933622872508666409400419512104849460930843821535397753127083475730
Short name T692
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:32:48 PM PDT 23
Finished Nov 01 12:32:53 PM PDT 23
Peak memory 200868 kb
Host smart-8741555c-4ba3-40e6-b9c0-47a4b07f3ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7021833094933622872508666409400419512104849460930843821535397753127083475730 -assert nopostproc +UV
M_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.7021833094933622872508666409400419512104849460930843821535397753127083475730
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.47044031432496439006243542838094630481582123549847205099572476958460225843451
Short name T734
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.56 seconds
Started Nov 01 12:32:51 PM PDT 23
Finished Nov 01 12:33:17 PM PDT 23
Peak memory 201092 kb
Host smart-ff6fef21-4be8-467a-aa58-5fc8f7436d20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47044031432496439006243542838094630481582123549847205099572476958460225843451
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.470440314324964390062435428380946304815821235
49847205099572476958460225843451
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.89926625237535984027467320997757960577245533343503415539775293439703894436299
Short name T62
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.69 seconds
Started Nov 01 12:32:46 PM PDT 23
Finished Nov 01 12:32:53 PM PDT 23
Peak memory 201140 kb
Host smart-9e024f0f-7596-410b-b79a-c7888df1b984
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89926625237535984027467320997757960577245533343503415539775293439703894436299 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.89926625237535984027467320997757960577245533343503415539775293439703894436299
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1499426369496624553378727669541660951530602978029244850755075256382344299593
Short name T769
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.39 seconds
Started Nov 01 12:32:45 PM PDT 23
Finished Nov 01 12:33:56 PM PDT 23
Peak memory 201128 kb
Host smart-ec13dc2d-c470-43cf-a514-86e00710a0d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499426369496624553378727669541660951530602978029244850755075256382344299593 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.1499426369496624553378727669541660951530602978029244850755075256382344299593
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.45643550417232965804235825896782078753995594623749452708777208391518913732251
Short name T732
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.25 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:33:59 PM PDT 23
Peak memory 200980 kb
Host smart-89eab01e-4495-4e5d-ba15-171e5ba5321a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4564355041723296580423582589678207875399559
4623749452708777208391518913732251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.4564
3550417232965804235825896782078753995594623749452708777208391518913732251
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.80924376892087139387738827232199687622200677433449834186141353048776353078343
Short name T14
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.14 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:04 PM PDT 23
Peak memory 200884 kb
Host smart-93e4c6e6-1f50-4595-a3c4-e33f33fd0a74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80924376892087139387738827232199687622200677433449834186141353048776353078343 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.80924376892087139387738827232199687622200677433449834186141353048776353078343
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.105218521897476458228765628390752168830035657161562401148058478657044089483218
Short name T736
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.71 seconds
Started Nov 01 12:33:52 PM PDT 23
Finished Nov 01 12:33:57 PM PDT 23
Peak memory 200828 kb
Host smart-4e56312a-5adb-4b2e-8e22-cf47c1a83ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105218521897476458228765628390752168830035657161562401148058478657044089483218 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.105218521897476458228765628390752168830035657161562401148058478657044089483218
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.27517523559928964787501472878775229204007880201281600766754555546006169612689
Short name T777
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.58 seconds
Started Nov 01 12:33:59 PM PDT 23
Finished Nov 01 12:34:27 PM PDT 23
Peak memory 201092 kb
Host smart-ebba5a1f-8073-44c7-847c-b5b0c0b2eb86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27517523559928964787501472878775229204007880201281600766754555546006169612689
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.275175235599289647875014728787752292040078802
01281600766754555546006169612689
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.110475390242308723368564884409176858652904596763681230795496022703561974331990
Short name T10
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.79 seconds
Started Nov 01 12:33:53 PM PDT 23
Finished Nov 01 12:34:00 PM PDT 23
Peak memory 201148 kb
Host smart-17dd00b3-5913-444b-b4e9-564f218b952f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110475390242308723368564884409176858652904596763681230795496022703561974331990 -assert nopostproc +
UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.110475390242308723368564884409176858652904596763681230795496022703561974331990
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.86412694544283376201094795353632591615967541296987408146592821753375996304709
Short name T724
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.39 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:35:08 PM PDT 23
Peak memory 201160 kb
Host smart-2950dc59-ac0d-4b6b-89a4-bf05b8d891a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86412694544283376201094795353632591615967541296987408146592821753375996304709 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.864126945442833762010947953536325916159675412969874081465928217
53375996304709
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.87843812985566881047383738449827247362242154700749305598157559751378225594199
Short name T723
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.16 seconds
Started Nov 01 12:34:02 PM PDT 23
Finished Nov 01 12:34:09 PM PDT 23
Peak memory 200996 kb
Host smart-25ce778a-5bec-48c2-afae-ddb355ab54d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8784381298556688104738373844982724736224215
4700749305598157559751378225594199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.8784
3812985566881047383738449827247362242154700749305598157559751378225594199
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.107788996767404200236216402013566806100518746753392525384896968716544773597044
Short name T716
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.03 seconds
Started Nov 01 12:33:53 PM PDT 23
Finished Nov 01 12:33:58 PM PDT 23
Peak memory 200864 kb
Host smart-1bec5db6-261e-450d-9a07-5d03660ea604
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107788996767404200236216402013566806100518746753392525384896968716544773597044 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.107788996767404200236216402013566806100518746753392525384896968716544773597044
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.78071263797109483445048463871898673010654913121312200578519025509534981337757
Short name T720
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.65 seconds
Started Nov 01 12:33:51 PM PDT 23
Finished Nov 01 12:33:57 PM PDT 23
Peak memory 200832 kb
Host smart-0c21b793-670b-46cf-8841-1811948c6d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78071263797109483445048463871898673010654913121312200578519025509534981337757 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.78071263797109483445048463871898673010654913121312200578519025509534981337757
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.34628512299085220214907175019693896187564933689436299217878931546237057887148
Short name T709
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.44 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:34:20 PM PDT 23
Peak memory 201028 kb
Host smart-e0234ef3-ad83-4737-b2bf-984d731e415f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34628512299085220214907175019693896187564933689436299217878931546237057887148
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.346285122990852202149071750196938961875649336
89436299217878931546237057887148
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.95639233344723405034904355832476543644869577416030545870201478309435006082336
Short name T755
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.75 seconds
Started Nov 01 12:33:55 PM PDT 23
Finished Nov 01 12:34:02 PM PDT 23
Peak memory 201120 kb
Host smart-d6855720-6fd8-45ee-b771-7399f4cbaa25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95639233344723405034904355832476543644869577416030545870201478309435006082336 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.95639233344723405034904355832476543644869577416030545870201478309435006082336
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.67527613683182536667499295018892159573713872024110001918727801888636769229596
Short name T781
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.87 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:35:05 PM PDT 23
Peak memory 201136 kb
Host smart-52238b71-7f9a-45da-a84d-ddabc3996e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67527613683182536667499295018892159573713872024110001918727801888636769229596 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.675276136831825366674992950188921595737138720241100019187278018
88636769229596
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.64385019764643359084530361216423424791052421609548942919186245402296742624000
Short name T737
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.18 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:34:02 PM PDT 23
Peak memory 200952 kb
Host smart-fcf07ad1-5a57-41fd-a662-b63f16521af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6438501976464335908453036121642342479105242
1609548942919186245402296742624000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.6438
5019764643359084530361216423424791052421609548942919186245402296742624000
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.74716804507709415090863133166965902809661906233658294705099738284218763508856
Short name T74
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.05 seconds
Started Nov 01 12:33:51 PM PDT 23
Finished Nov 01 12:33:57 PM PDT 23
Peak memory 200952 kb
Host smart-6b312440-5948-41d7-9e89-bd80638b81bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74716804507709415090863133166965902809661906233658294705099738284218763508856 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.74716804507709415090863133166965902809661906233658294705099738284218763508856
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.72112567420118255894315365642103205513067616984301142005058199679341011830783
Short name T79
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.72 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:34:02 PM PDT 23
Peak memory 200844 kb
Host smart-9c384a7b-cc00-4fa4-ac7f-5294d73aa4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72112567420118255894315365642103205513067616984301142005058199679341011830783 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.72112567420118255894315365642103205513067616984301142005058199679341011830783
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.28802039796121614560830367478387545935103483736497762238760818213788218640101
Short name T66
Test name
Test status
Simulation time 9477310853 ps
CPU time 24.48 seconds
Started Nov 01 12:34:06 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 201104 kb
Host smart-f6a59ba4-921d-4325-a632-0853b107b45d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28802039796121614560830367478387545935103483736497762238760818213788218640101
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.288020397961216145608303674783875459351034837
36497762238760818213788218640101
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.78772762448637126278264792889432550838758165998299135385848050539311439550761
Short name T730
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.85 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:05 PM PDT 23
Peak memory 201136 kb
Host smart-9ea14cb9-77b0-4d2a-bb04-875a7325ba3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78772762448637126278264792889432550838758165998299135385848050539311439550761 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.78772762448637126278264792889432550838758165998299135385848050539311439550761
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.41631340792835990773407627565918298120309428171981377862889093216997326398193
Short name T55
Test name
Test status
Simulation time 42510939439 ps
CPU time 68.94 seconds
Started Nov 01 12:33:54 PM PDT 23
Finished Nov 01 12:35:04 PM PDT 23
Peak memory 201088 kb
Host smart-9e613837-629a-4966-8b53-fcfab65f63d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41631340792835990773407627565918298120309428171981377862889093216997326398193 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.416313407928359907734076275659182981203094281719813778628890932
16997326398193
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.77328938947802661931936404557470402582913499566414888397805338834377248622554
Short name T698
Test name
Test status
Simulation time 2142012393 ps
CPU time 4.3 seconds
Started Nov 01 12:34:04 PM PDT 23
Finished Nov 01 12:34:10 PM PDT 23
Peak memory 200868 kb
Host smart-388c4eab-ee3c-4264-8a3f-033aab25f310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7732893894780266193193640455747040258291349
9566414888397805338834377248622554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.7732
8938947802661931936404557470402582913499566414888397805338834377248622554
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.77277998562347796807920436431170703685343015112928331335474664499490319405776
Short name T731
Test name
Test status
Simulation time 2074977215 ps
CPU time 4.05 seconds
Started Nov 01 12:34:01 PM PDT 23
Finished Nov 01 12:34:09 PM PDT 23
Peak memory 200908 kb
Host smart-e974cefa-fe80-4560-9d06-6cbd81863e03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77277998562347796807920436431170703685343015112928331335474664499490319405776 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.77277998562347796807920436431170703685343015112928331335474664499490319405776
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.11502986993049545495837525467646883195796881638687481408388135881580912186669
Short name T708
Test name
Test status
Simulation time 2023227629 ps
CPU time 3.74 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:34:02 PM PDT 23
Peak memory 200716 kb
Host smart-f5e33736-660f-471c-a3fc-db1b7c8ffbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11502986993049545495837525467646883195796881638687481408388135881580912186669 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.11502986993049545495837525467646883195796881638687481408388135881580912186669
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.25827717905742469246017237965948389612664112160906879678899690276668449306814
Short name T696
Test name
Test status
Simulation time 9477310853 ps
CPU time 25.16 seconds
Started Nov 01 12:34:04 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 201032 kb
Host smart-c57e75a3-38ec-4cae-91c6-d43c10e28766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25827717905742469246017237965948389612664112160906879678899690276668449306814
-assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.258277179057424692460172379659483896126641121
60906879678899690276668449306814
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.56831565592114138496020652243803671644933370120060407740603969367347131133970
Short name T764
Test name
Test status
Simulation time 2186637036 ps
CPU time 5.69 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:34:04 PM PDT 23
Peak memory 200904 kb
Host smart-d8d3a732-8ef0-4eac-928c-3adfce6440cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56831565592114138496020652243803671644933370120060407740603969367347131133970 -assert nopostproc +U
VM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.56831565592114138496020652243803671644933370120060407740603969367347131133970
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.92855222750318035977649168188709648419890171448623625631151178596601096950194
Short name T761
Test name
Test status
Simulation time 42510939439 ps
CPU time 69.48 seconds
Started Nov 01 12:34:10 PM PDT 23
Finished Nov 01 12:35:26 PM PDT 23
Peak memory 201148 kb
Host smart-ec80d5a9-d89b-40b9-bc7e-f6641eb82dc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92855222750318035977649168188709648419890171448623625631151178596601096950194 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.928552227503180359776491681887096484198901714486236256311511785
96601096950194
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.60061239842938072112756333542585901582541464091975492253932253395217853102912
Short name T397
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 201188 kb
Host smart-4b35a4b0-8d78-40b9-b244-1ecfd7734502
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60061239842938072112756333542585901582541464091975492253932253395217853102912 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.60061239842938072112756333542585901582541464091975492253932253395217853102912
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.83340703242060987106727752759860950676956624441632100142285399407459189989548
Short name T301
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 200980 kb
Host smart-c74d4b72-e5b0-4238-9f79-52766a93c87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83340703242060987106727752759860950676956624441632100142285399407459189989548 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.83340703242060987106727752759860950676956624441632100142285399407459189989548
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.23743739820595082991550799212365255849939919528881126776453258424540602349515
Short name T363
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.32 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:37:24 PM PDT 23
Peak memory 201292 kb
Host smart-abab2d99-802f-459f-baaa-616a59442721
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23743739820595082991550799212365255849939919528881126776453258424540602349515 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.237437398205950829915507992123652558499399195288811267764532584
24540602349515
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.43937284543398290676024437286162704200907583544844364969009417166391679117830
Short name T101
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.62 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 200876 kb
Host smart-abcfce99-9893-4da0-89fb-cc2e145f2de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43937284543398290676024437286162704200907583544844364969009417166391679117830 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.43937284543398290676024437286162704200907583544844364
969009417166391679117830
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.64301680145918043119736949353394331553613180491052238817020148794922015477189
Short name T348
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:34:23 PM PDT 23
Peak memory 201100 kb
Host smart-bc65b6d3-5aff-47ae-af75-954169e55f9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64301680145918043119736949353394331553613180491052238817020148794922015477189 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.6430168014591804311973694935339433155361318049105223881702014
8794922015477189
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.55916389896334904936271355888972273781488924652935760416816420995886443843103
Short name T648
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.38 seconds
Started Nov 01 12:34:18 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 200972 kb
Host smart-1bc2ff46-c985-4d9f-a573-37844328cd9a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55916389896334904936271355888972273781488924652935760416816420995886443843103 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.55916389896334904936271355888972273781488924652935760416816420995886443843103
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.66464026044370210108529943074529841585844162977367253014661096353495194387032
Short name T191
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.7 seconds
Started Nov 01 12:34:04 PM PDT 23
Finished Nov 01 12:34:11 PM PDT 23
Peak memory 201068 kb
Host smart-46714861-d182-45a0-9ee6-d17b54153f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66464026044370210108529943074529841585844162977367253014661096353495194387032 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.66464026044370210108529943074529841585844162977367253014661096353495194387032
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.69988459375889373419603150107376683620462199773377899217154705704495191586029
Short name T121
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.89 seconds
Started Nov 01 12:34:16 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 201104 kb
Host smart-61fd3176-8837-4887-9b30-90ca2a86e185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69988459375889373419603150107376683620462199773377899217154705704495191586029 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.69988459375889373419603150107376683620462199773377899217154705704495191586029
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.41321991119156718634650122903062903938773688336359339373984973062576332726750
Short name T487
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 01 12:34:04 PM PDT 23
Finished Nov 01 12:34:10 PM PDT 23
Peak memory 200996 kb
Host smart-728ffc69-4de2-4e5c-b949-54fecf1a4f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41321991119156718634650122903062903938773688336359339373984973062576332726750 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.41321991119156718634650122903062903938773688336359339373984973062576332726750
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.57316489566934603577618234586922312535130158664311495505889738815359472952068
Short name T549
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 01 12:34:13 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 201052 kb
Host smart-ed2e84dc-00cd-4754-a1eb-332011ad094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57316489566934603577618234586922312535130158664311495505889738815359472952068 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.57316489566934603577618234586922312535130158664311495505889738815359472952068
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.32797807983478293472790518190384404860614898704418658398008117508685203052950
Short name T186
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.89 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:34:21 PM PDT 23
Peak memory 201156 kb
Host smart-c512225c-ad03-4e47-9829-5915a6e87eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32797807983478293472790518190384404860614898704418658398008117508685203052950 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_smoke.32797807983478293472790518190384404860614898704418658398008117508685203052950
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.104854599022798488092953260786154403650560210195983019322545181801221288547924
Short name T598
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.77 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:36:42 PM PDT 23
Peak memory 201220 kb
Host smart-6faec55e-5bf7-4c03-b756-c1b0d508fc4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104854599022798488092953260786154403650560210195983019322545181801221288547924 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.104854599022798488092953260786154403650560210195983019322545181801221288547924
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.88920486956475866628658560199930956317138197952267652235639102943746331394542
Short name T50
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Nov 01 12:34:10 PM PDT 23
Finished Nov 01 12:34:22 PM PDT 23
Peak memory 201024 kb
Host smart-8808e44d-ba91-42e4-8237-69636b5c291c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88920486956475866628658560199930956317138197952267652235639102943746331394542 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.8892048695647586662865856019993095631713819795226765223563910
2943746331394542
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.78352448174743186333075065016441508759120764031308846468675425097294424976286
Short name T593
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 01 12:34:40 PM PDT 23
Finished Nov 01 12:34:46 PM PDT 23
Peak memory 201052 kb
Host smart-a13715e0-2fb2-41b6-855b-5bdef9ce7156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78352448174743186333075065016441508759120764031308846468675425097294424976286 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.78352448174743186333075065016441508759120764031308846468675425097294424976286
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.12330095013336624862512086863617231784888341013907175923749600130630179365020
Short name T284
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.4 seconds
Started Nov 01 12:34:35 PM PDT 23
Finished Nov 01 12:34:44 PM PDT 23
Peak memory 201224 kb
Host smart-0f8cf127-02ab-48eb-9155-47c3eb950bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12330095013336624862512086863617231784888341013907175923749600130630179365020 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.12330095013336624862512086863617231784888341013907175923749600130630179365020
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.31076477866435258594493025785286269730287217489918082249153657441154257871337
Short name T342
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.09 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:37:30 PM PDT 23
Peak memory 201392 kb
Host smart-aaebbe7d-c230-4ae6-b2ac-af06464cf0df
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31076477866435258594493025785286269730287217489918082249153657441154257871337 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.310764778664352585944930257852862697302872174899180822491536574
41154257871337
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.76801965582982412007195621602691344301628455269779242492867551322700180688159
Short name T531
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.32 seconds
Started Nov 01 12:34:22 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 201224 kb
Host smart-28069e54-a3e9-48a9-832d-4dcd3b304bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76801965582982412007195621602691344301628455269779242492867551322700180688159 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.76801965582982412007195621602691344301628455269779242492867551322700180688159
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.31271102605389552532685946833273862253785161108370699259207180080747408267512
Short name T102
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.5 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 201024 kb
Host smart-597f2f90-180e-4f4b-8365-84eaf7faead6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31271102605389552532685946833273862253785161108370699259207180080747408267512 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.31271102605389552532685946833273862253785161108370699
259207180080747408267512
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.13429673596125901721495679478275311843638725413145385459241055109442933218854
Short name T400
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.47 seconds
Started Nov 01 12:34:26 PM PDT 23
Finished Nov 01 12:34:37 PM PDT 23
Peak memory 201160 kb
Host smart-b53c29b4-337a-41cb-bb6c-cce09af9264e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13429673596125901721495679478275311843638725413145385459241055109442933218854 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.1342967359612590172149567947827531184363872541314538545924105
5109442933218854
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.25435448296149703111520874036244317037284107417230313077525510154043602862847
Short name T104
Test name
Test status
Simulation time 38606274248 ps
CPU time 60.38 seconds
Started Nov 01 12:34:38 PM PDT 23
Finished Nov 01 12:35:42 PM PDT 23
Peak memory 201016 kb
Host smart-775af8a5-2773-43bc-a5d5-d1a5f592c123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25435448296149703111520874036244317037284107417230313077525510154043602862847 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.25435448296149703111520874036244317037284107417230313077525510154043602862847
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.77853169610834512891793548350034770451620029621854443642394333579035215982622
Short name T316
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Nov 01 12:34:29 PM PDT 23
Finished Nov 01 12:34:40 PM PDT 23
Peak memory 201032 kb
Host smart-7fa9bb7e-4603-4c1b-8f2f-88c140b38c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77853169610834512891793548350034770451620029621854443642394333579035215982622 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.77853169610834512891793548350034770451620029621854443642394333579035215982622
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.91365405893800823772146364342546240772076124886078786688872485275146497341994
Short name T369
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.89 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 201180 kb
Host smart-abe29b10-2e90-48a4-9272-a1e5d9239637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91365405893800823772146364342546240772076124886078786688872485275146497341994 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.91365405893800823772146364342546240772076124886078786688872485275146497341994
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.74587969738635711008696754205294114439785538049777923383920472227456029895231
Short name T315
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Nov 01 12:34:34 PM PDT 23
Finished Nov 01 12:34:41 PM PDT 23
Peak memory 200984 kb
Host smart-db0cad76-9116-4cc3-bd9e-78a550db394e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74587969738635711008696754205294114439785538049777923383920472227456029895231 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.74587969738635711008696754205294114439785538049777923383920472227456029895231
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.5831896361074954231717303483572416919191294890449198978731192815266213419970
Short name T437
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.48 seconds
Started Nov 01 12:34:30 PM PDT 23
Finished Nov 01 12:34:40 PM PDT 23
Peak memory 201028 kb
Host smart-9ea982c2-0c0c-4359-8057-93fc5edc21c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5831896361074954231717303483572416919191294890449198978731192815266213419970 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.5831896361074954231717303483572416919191294890449198978731192815266213419970
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.26959696193860824778953182553744905539491852238836506287203422849445549667306
Short name T158
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.17 seconds
Started Nov 01 12:34:27 PM PDT 23
Finished Nov 01 12:35:35 PM PDT 23
Peak memory 221420 kb
Host smart-6bda3a33-1d38-42f9-9bc4-10b466c0d6bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26959696193860824778953182553744905539491852238836506287203422849445549667306 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.26959696193860824778953182553744905539491852238836506287203422849445549667306
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.65493222231576938883765418394127448269918401839232677845642451618184626571880
Short name T616
Test name
Test status
Simulation time 2116887594 ps
CPU time 4.07 seconds
Started Nov 01 12:34:29 PM PDT 23
Finished Nov 01 12:34:39 PM PDT 23
Peak memory 200912 kb
Host smart-4bd76c1e-2ab0-4179-9080-0ce397b11fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65493222231576938883765418394127448269918401839232677845642451618184626571880 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_smoke.65493222231576938883765418394127448269918401839232677845642451618184626571880
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.112253285831252468344169947617095763282006362854580439224954610261528228247077
Short name T33
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.82 seconds
Started Nov 01 12:34:28 PM PDT 23
Finished Nov 01 12:36:49 PM PDT 23
Peak memory 201320 kb
Host smart-d0313be1-522e-49bb-b86a-9a72e8149c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112253285831252468344169947617095763282006362854580439224954610261528228247077 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.112253285831252468344169947617095763282006362854580439224954610261528228247077
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.52247491293700103891629722713496412508298772969873669772909908520294512222851
Short name T601
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Nov 01 12:34:42 PM PDT 23
Finished Nov 01 12:34:49 PM PDT 23
Peak memory 201172 kb
Host smart-8db49b81-9c58-46d8-a926-64d98d5312f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52247491293700103891629722713496412508298772969873669772909908520294512222851 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.5224749129370010389162972271349641250829877296987366977290990
8520294512222851
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.74293211910972004724145314488269619697526163769893481425551635126454058672889
Short name T424
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Nov 01 12:34:57 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 201072 kb
Host smart-be9ca149-ae36-4c30-8982-ab9c41ed8ab6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74293211910972004724145314488269619697526163769893481425551635126454058672889 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.74293211910972004724145314488269619697526163769893481425551635126454058672889
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.52563670907952041398715072302958655280319078072939780464512308800761483119138
Short name T229
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 01 12:34:55 PM PDT 23
Finished Nov 01 12:35:09 PM PDT 23
Peak memory 201136 kb
Host smart-893ecdf9-139a-4690-a38b-edab6d1815cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52563670907952041398715072302958655280319078072939780464512308800761483119138 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.52563670907952041398715072302958655280319078072939780464512308800761483119138
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.39339640321201586015744216539854981892458693393390243883946660504641507745909
Short name T544
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.09 seconds
Started Nov 01 12:34:53 PM PDT 23
Finished Nov 01 12:38:04 PM PDT 23
Peak memory 201596 kb
Host smart-654e0801-ee90-4372-971c-350aed9df7fe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39339640321201586015744216539854981892458693393390243883946660504641507745909 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.39339640321201586015744216539854981892458693393390243883946660
504641507745909
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3654950563720542532988630230955836692626267981561356906282217233282625244879
Short name T468
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Nov 01 12:34:53 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 201060 kb
Host smart-abe95cf5-0a81-447b-8ad2-6df8cb31e375
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654950563720542532988630230955836692626267981561356906282217233282625244879 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.3654950563720542532988630230955836692626267981561356906282217
233282625244879
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.82651432970773214895953717174765283757660362097016636685749237713851491895429
Short name T560
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Nov 01 12:34:57 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 201052 kb
Host smart-0d0eb0e6-6c7e-46cc-976d-51cb1ba9a7f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82651432970773214895953717174765283757660362097016636685749237713851491895429 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.8265143297077321489595371717476528375766036209701663668574923771
3851491895429
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.57163900759285340014358481968591987735410061025598769533237685290100679597096
Short name T470
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:35:13 PM PDT 23
Peak memory 200944 kb
Host smart-9371e6a5-9eea-4d6c-942e-70a2b3f01ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57163900759285340014358481968591987735410061025598769533237685290100679597096 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.57163900759285340014358481968591987735410061025598769533237685290100679597096
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.75783628642896837214856602410329796821651265944878585233807192120553868896543
Short name T652
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Nov 01 12:34:52 PM PDT 23
Finished Nov 01 12:34:59 PM PDT 23
Peak memory 200976 kb
Host smart-794d188d-d7c1-40ee-8b22-91fec3c01dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75783628642896837214856602410329796821651265944878585233807192120553868896543 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.75783628642896837214856602410329796821651265944878585233807192120553868896543
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.46729789970887407078067559667680428840644606930234075248153382165638184436903
Short name T612
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 01 12:34:51 PM PDT 23
Finished Nov 01 12:34:57 PM PDT 23
Peak memory 200960 kb
Host smart-84480d18-10cd-43d9-a8a2-db44371f855e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46729789970887407078067559667680428840644606930234075248153382165638184436903 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.46729789970887407078067559667680428840644606930234075248153382165638184436903
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.6365728603474099581148630820864063701474739114405926118409136813665707890701
Short name T507
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Nov 01 12:34:50 PM PDT 23
Finished Nov 01 12:34:56 PM PDT 23
Peak memory 201052 kb
Host smart-c5854a42-d68c-45c1-b184-300184b2fa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6365728603474099581148630820864063701474739114405926118409136813665707890701 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.6365728603474099581148630820864063701474739114405926118409136813665707890701
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.21780780016401229693303006814310414645851080241532481148306609166317632640805
Short name T651
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Nov 01 12:34:55 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 200972 kb
Host smart-acd7f9d2-1043-4c0c-92a4-cdfd4dfc7d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21780780016401229693303006814310414645851080241532481148306609166317632640805 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_smoke.21780780016401229693303006814310414645851080241532481148306609166317632640805
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.68240621385113737120535276859441989364470447302891986291926930885557625836635
Short name T498
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 01 12:34:53 PM PDT 23
Finished Nov 01 12:35:04 PM PDT 23
Peak memory 201040 kb
Host smart-8088e159-4bc7-44b0-a839-b871da0c3e3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68240621385113737120535276859441989364470447302891986291926930885557625836635 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.682406213851137371205352768594419893644704473028919862919269
30885557625836635
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.15217013425024563219320677235213497622400191634039587557492731712245402867029
Short name T508
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.81 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:15 PM PDT 23
Peak memory 201060 kb
Host smart-272c1d2e-6816-471c-8761-b003f64f8a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15217013425024563219320677235213497622400191634039587557492731712245402867029 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.15217013425024563219320677235213497622400191634039587557492731712245402867029
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.61332028298330481866428887495620713314892598556540633820847857788918493992490
Short name T304
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Nov 01 12:34:57 PM PDT 23
Finished Nov 01 12:35:09 PM PDT 23
Peak memory 201028 kb
Host smart-2a96aba5-71a4-43ad-8c44-57a5ac0e72b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61332028298330481866428887495620713314892598556540633820847857788918493992490 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.61332028298330481866428887495620713314892598556540633820847857788918493992490
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.6606770681519945451922902306471515600343731538068308834930933558949984886327
Short name T249
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.02 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:38:06 PM PDT 23
Peak memory 201300 kb
Host smart-d63b999f-859d-4d72-8b0a-cdb028997040
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6606770681519945451922902306471515600343731538068308834930933558949984886327 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.660677068151994545192290230647151560034373153806830883493093355
8949984886327
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.56523811344574145340545513997252274766768793694274755738972646286942972309096
Short name T227
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.31 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:35:11 PM PDT 23
Peak memory 201196 kb
Host smart-f2caecac-868a-42fe-8a71-215a520673fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56523811344574145340545513997252274766768793694274755738972646286942972309096 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.565238113445741453405455139972522747667687936942747557389726
46286942972309096
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.20177895168087279624469680975939149126378680866370047136384796120433979218298
Short name T541
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Nov 01 12:34:55 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 201068 kb
Host smart-bd854b1f-48de-4880-9138-b1ed3d797f7d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20177895168087279624469680975939149126378680866370047136384796120433979218298 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.2017789516808727962446968097593914912637868086637004713638479612
0433979218298
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.53539441675279196905922728459256399157353022954029157405313324864066058444638
Short name T355
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.78 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 201232 kb
Host smart-cec8b982-f1ac-4d45-99e7-2436fc529711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53539441675279196905922728459256399157353022954029157405313324864066058444638 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.53539441675279196905922728459256399157353022954029157405313324864066058444638
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.46955408873900775050734753048670714138294331840696728492881366735134871816983
Short name T469
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Nov 01 12:35:03 PM PDT 23
Finished Nov 01 12:35:14 PM PDT 23
Peak memory 201068 kb
Host smart-bcac5ae0-d1ed-4479-9dd2-166cc5555e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46955408873900775050734753048670714138294331840696728492881366735134871816983 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.46955408873900775050734753048670714138294331840696728492881366735134871816983
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.11149629265141758441542627178257988572203414832187491235948159828709085198465
Short name T347
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:35:12 PM PDT 23
Peak memory 201140 kb
Host smart-7c5f7e21-af3c-4da2-8771-3e1b5138bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11149629265141758441542627178257988572203414832187491235948159828709085198465 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.11149629265141758441542627178257988572203414832187491235948159828709085198465
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.25893468685398622025018030361848234022376226247301016194533078802841515315055
Short name T546
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.67 seconds
Started Nov 01 12:34:57 PM PDT 23
Finished Nov 01 12:35:08 PM PDT 23
Peak memory 201060 kb
Host smart-0ecbbd5e-d7bd-4316-9063-2fe30e438d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25893468685398622025018030361848234022376226247301016194533078802841515315055 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.25893468685398622025018030361848234022376226247301016194533078802841515315055
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.45721607830508880817597743331629788908158041191000503764211974540990909001988
Short name T194
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 01 12:34:53 PM PDT 23
Finished Nov 01 12:35:03 PM PDT 23
Peak memory 200924 kb
Host smart-36a16434-6dcc-485e-b4f1-ab56dbe77e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45721607830508880817597743331629788908158041191000503764211974540990909001988 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_smoke.45721607830508880817597743331629788908158041191000503764211974540990909001988
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.90449364673621977938693475209920941031585461374001192750079751892296377116015
Short name T323
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.07 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:37:28 PM PDT 23
Peak memory 201216 kb
Host smart-f378cafb-a566-4586-a3bb-2f764fe0918d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90449364673621977938693475209920941031585461374001192750079751892296377116015 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.90449364673621977938693475209920941031585461374001192750079751892296377116015
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.20186187487959433997892387353320983147674090035581210919705894291955565542098
Short name T308
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.87 seconds
Started Nov 01 12:34:59 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 201184 kb
Host smart-1dde5564-de48-4a13-b90e-df40b5cc8b44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20186187487959433997892387353320983147674090035581210919705894291955565542098 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.201861874879594339978923873533209831476740900355812109197058
94291955565542098
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.105504825951627276497077115758314213917965838808120259760979181627176612103884
Short name T206
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 200784 kb
Host smart-14c30e3a-e9be-4864-952f-45bdc324c063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105504825951627276497077115758314213917965838808120259760979181627176612103884 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.105504825951627276497077115758314213917965838808120259760979181627176612103884
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.97584370492938538401654395680863409785868217116829563520333274730543015849105
Short name T172
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.57 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201192 kb
Host smart-965866aa-c70d-480b-a569-50b841ac9862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97584370492938538401654395680863409785868217116829563520333274730543015849105 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.97584370492938538401654395680863409785868217116829563520333274730543015849105
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.16696986236013003491092912415445743564267181531691724043938107670079912720533
Short name T540
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.93 seconds
Started Nov 01 12:35:09 PM PDT 23
Finished Nov 01 12:38:19 PM PDT 23
Peak memory 201236 kb
Host smart-d89f1243-0bd7-4420-951d-33674e64ff17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16696986236013003491092912415445743564267181531691724043938107670079912720533 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.16696986236013003491092912415445743564267181531691724043938107
670079912720533
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.105676968809912657414026719020830773133376126647249236684647646197461776593947
Short name T275
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Nov 01 12:35:01 PM PDT 23
Finished Nov 01 12:35:13 PM PDT 23
Peak memory 201004 kb
Host smart-43d54e50-182a-4343-a5ea-b85c1ff4981e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105676968809912657414026719020830773133376126647249236684647646197461776593947 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.105676968809912657414026719020830773133376126647249236684647646
197461776593947
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.24682237704173156085402146609946135628540478098772522033122630950117375531930
Short name T620
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.79 seconds
Started Nov 01 12:35:09 PM PDT 23
Finished Nov 01 12:35:20 PM PDT 23
Peak memory 200984 kb
Host smart-70d7d9f2-3b87-444c-b8b2-00c3232131a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24682237704173156085402146609946135628540478098772522033122630950117375531930 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.24682237704173156085402146609946135628540478098772522033122630950117375531930
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.79426152312202314640523763947276328310412358830086682130819088736833551133152
Short name T231
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 201056 kb
Host smart-4aeb6de8-e08d-431a-8612-0e7981b65e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79426152312202314640523763947276328310412358830086682130819088736833551133152 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.79426152312202314640523763947276328310412358830086682130819088736833551133152
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.53358100306953817630753552180214508344327988275493425611973695788169778263273
Short name T271
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 201140 kb
Host smart-3d79b796-7ae2-47eb-80cf-efd6e5019174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53358100306953817630753552180214508344327988275493425611973695788169778263273 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.53358100306953817630753552180214508344327988275493425611973695788169778263273
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.25409668854265907509746038502845913186904916780045515033319692981814754323475
Short name T387
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 200784 kb
Host smart-addd0aef-b11c-4ebc-ad87-5f1fdfa2a144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25409668854265907509746038502845913186904916780045515033319692981814754323475 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.25409668854265907509746038502845913186904916780045515033319692981814754323475
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.9884484987515124944212053830929900239129602765917060055459654038590164456582
Short name T503
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 200948 kb
Host smart-9dcbf35d-873a-44c1-811b-ded32fe307a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9884484987515124944212053830929900239129602765917060055459654038590164456582 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sysrst_ctrl_smoke.9884484987515124944212053830929900239129602765917060055459654038590164456582
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.4098942408157678669519427385120422737844479648004725031439817275679783385886
Short name T263
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.36 seconds
Started Nov 01 12:35:09 PM PDT 23
Finished Nov 01 12:37:32 PM PDT 23
Peak memory 201272 kb
Host smart-d20b3809-3868-4612-93c0-df155db8a396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098942408157678669519427385120422737844479648004725031439817275679783385886 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.4098942408157678669519427385120422737844479648004725031439817275679783385886
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.50307026541451915198708799744095710885200058370097663108460105355292857059394
Short name T622
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201056 kb
Host smart-b8191699-649b-4e2e-8b12-b91aefab1ae8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50307026541451915198708799744095710885200058370097663108460105355292857059394 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.503070265414519151987087997440957108852000583700976631084601
05355292857059394
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.60039092878569671495985545145375877606693110397622444694275679338267750905971
Short name T565
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 201168 kb
Host smart-c6a05fcf-29b7-447b-a9e8-886db164d516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60039092878569671495985545145375877606693110397622444694275679338267750905971 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.60039092878569671495985545145375877606693110397622444694275679338267750905971
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.30781540014766305817520398184265264124946493396386197546183569292563203530584
Short name T533
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:20 PM PDT 23
Peak memory 201208 kb
Host smart-3f708fec-a6bb-4883-bac5-e75a68df3c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30781540014766305817520398184265264124946493396386197546183569292563203530584 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.30781540014766305817520398184265264124946493396386197546183569292563203530584
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.3589621245264330445776089850236421811317448964824306039757576464118536778996
Short name T638
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.23 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:38:10 PM PDT 23
Peak memory 201336 kb
Host smart-ff0dcc57-2f11-4b88-a50e-17a46f2a74e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589621245264330445776089850236421811317448964824306039757576464118536778996 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.358962124526433044577608985023642181131744896482430603975757646
4118536778996
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3934870111910350929451987024122392944317332618581891365884147991073830576530
Short name T166
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:22 PM PDT 23
Peak memory 201192 kb
Host smart-b999bc8f-7659-43b4-a25c-27b12c0a63b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934870111910350929451987024122392944317332618581891365884147991073830576530 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.3934870111910350929451987024122392944317332618581891365884147
991073830576530
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.33834181798113204910777274192079507613840596817067349351979935605290818821839
Short name T34
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.37 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:21 PM PDT 23
Peak memory 201156 kb
Host smart-a478a690-2efe-45ce-8b3c-67f96e6d160b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33834181798113204910777274192079507613840596817067349351979935605290818821839 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.3383418179811320491077727419207950761384059681706734935197993560
5290818821839
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.113576378029309779197832285382716710399177882688157222297610732618517272315056
Short name T471
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.77 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:35:13 PM PDT 23
Peak memory 201072 kb
Host smart-92d96824-69f1-4a1f-8ca2-f16cbe3b229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113576378029309779197832285382716710399177882688157222297610732618517272315056 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.113576378029309779197832285382716710399177882688157222297610732618517272315056
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.51094186876749209011260543781745044379188490338750867026161506317732858255415
Short name T617
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 200836 kb
Host smart-d489c51d-121a-46d7-8b66-f039d93df2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51094186876749209011260543781745044379188490338750867026161506317732858255415 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.51094186876749209011260543781745044379188490338750867026161506317732858255415
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.56952346978267200253818514465076747244581670431861120078546485001160369857413
Short name T581
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 201140 kb
Host smart-754de18c-d0fd-4ac6-bb4f-de10763bcaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56952346978267200253818514465076747244581670431861120078546485001160369857413 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.56952346978267200253818514465076747244581670431861120078546485001160369857413
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.12893947810331196898665044476445572918086874659904932334613795934774419408931
Short name T293
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 200960 kb
Host smart-b5ee7c08-43b4-435c-92a7-b25f5958c055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12893947810331196898665044476445572918086874659904932334613795934774419408931 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.12893947810331196898665044476445572918086874659904932334613795934774419408931
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.30002114355868792929538129599365314184158894637015930987487856892947045174100
Short name T656
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:15 PM PDT 23
Peak memory 201156 kb
Host smart-af144165-9523-496d-aa90-9cb5cd46470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30002114355868792929538129599365314184158894637015930987487856892947045174100 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sysrst_ctrl_smoke.30002114355868792929538129599365314184158894637015930987487856892947045174100
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.72878005027829574133110437235815710165232483976579203049804531671669647935915
Short name T456
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.75 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:37:32 PM PDT 23
Peak memory 201444 kb
Host smart-54d5ee62-f032-49d0-8c5f-6f71dbf730c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72878005027829574133110437235815710165232483976579203049804531671669647935915 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.72878005027829574133110437235815710165232483976579203049804531671669647935915
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.91828900929407050519173036569264948361447116732569752980874532011833559853820
Short name T482
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 201000 kb
Host smart-2e903061-9e21-47da-9d47-2afd76515c90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91828900929407050519173036569264948361447116732569752980874532011833559853820 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.918289009294070505191730365692649483614471167325697529808745
32011833559853820
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.74757316418780804544371122119613168209437458829553785725346626759180887680278
Short name T624
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 01 12:35:21 PM PDT 23
Finished Nov 01 12:35:26 PM PDT 23
Peak memory 201072 kb
Host smart-e13dcd08-c1ee-4278-83bf-84e736efa916
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74757316418780804544371122119613168209437458829553785725346626759180887680278 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.74757316418780804544371122119613168209437458829553785725346626759180887680278
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.44785315129061532504239176869502535594242067926554824615193396698382365354256
Short name T665
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.76 seconds
Started Nov 01 12:35:03 PM PDT 23
Finished Nov 01 12:35:15 PM PDT 23
Peak memory 201180 kb
Host smart-389d6952-80ba-49e7-aad4-08b45e378ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44785315129061532504239176869502535594242067926554824615193396698382365354256 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.44785315129061532504239176869502535594242067926554824615193396698382365354256
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.74662496978384890259425871842201210918732490569970339704148999621501685855834
Short name T467
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.59 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:38:10 PM PDT 23
Peak memory 201260 kb
Host smart-0348e6d8-3e22-4661-8ab5-71a6e5e59745
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74662496978384890259425871842201210918732490569970339704148999621501685855834 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.74662496978384890259425871842201210918732490569970339704148999
621501685855834
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.100443081524785014528100239034718027214982036140812007158937885027760479708990
Short name T260
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.46 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 201276 kb
Host smart-2f1e26cf-c305-45e4-8e41-ecbf65e0f82f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100443081524785014528100239034718027214982036140812007158937885027760479708990 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.10044308152478501452810023903471802721498203614081200715893
7885027760479708990
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.54565459124604822275505828206858067114123511268728344082527731885978949960157
Short name T545
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 201140 kb
Host smart-9510f92b-9d1f-41ae-83ea-a8e23015bf7b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54565459124604822275505828206858067114123511268728344082527731885978949960157 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.5456545912460482227550582820685806711412351126872834408252773188
5978949960157
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.47726633882867464612306830429951553606089747543462470001673958371950052551458
Short name T288
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.6 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201052 kb
Host smart-0a907322-90f5-4ae2-8401-79a024e27a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47726633882867464612306830429951553606089747543462470001673958371950052551458 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.47726633882867464612306830429951553606089747543462470001673958371950052551458
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.20458005822336786907722683550327416552811804144195859930538387602698524029145
Short name T42
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 201120 kb
Host smart-c3107503-d9f4-42bb-bc5a-ed4df3bb2c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20458005822336786907722683550327416552811804144195859930538387602698524029145 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.20458005822336786907722683550327416552811804144195859930538387602698524029145
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.86811005405803122482276806812564430305531618494283431961228432258714042507394
Short name T259
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.82 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 200992 kb
Host smart-a8669674-7fc7-493a-b753-4af54a6cbdd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86811005405803122482276806812564430305531618494283431961228432258714042507394 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.86811005405803122482276806812564430305531618494283431961228432258714042507394
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.101158682137726283486029031732770715004000443967797012361516838371387781103329
Short name T613
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 200980 kb
Host smart-dba4acfa-3ece-411b-b18b-62efe50af98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101158682137726283486029031732770715004000443967797012361516838371387781103329 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.101158682137726283486029031732770715004000443967797012361516838371387781103329
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.60453583766405828062595439733904940282971564513353056238866858178174287064641
Short name T404
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 01 12:35:03 PM PDT 23
Finished Nov 01 12:35:13 PM PDT 23
Peak memory 200964 kb
Host smart-b0a28926-a920-4b34-be54-fc6ac8c4ce61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60453583766405828062595439733904940282971564513353056238866858178174287064641 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sysrst_ctrl_smoke.60453583766405828062595439733904940282971564513353056238866858178174287064641
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.85775445640876668438455857631379559400021998545018814258886927418536469567236
Short name T600
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.57 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:37:25 PM PDT 23
Peak memory 201308 kb
Host smart-1316206a-7da9-408a-946f-26819e00020e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85775445640876668438455857631379559400021998545018814258886927418536469567236 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.85775445640876668438455857631379559400021998545018814258886927418536469567236
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.54393584178155600657679170315367423033596073049906522960313951162765035338977
Short name T300
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.7 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201056 kb
Host smart-ef72c001-1919-4621-b1f2-ec3a9e5d0047
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54393584178155600657679170315367423033596073049906522960313951162765035338977 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.543935841781556006576791703153674230335960730499065229603139
51162765035338977
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.72865997895989914778188432109481218989538772402624804762811380976632697734191
Short name T381
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.73 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 201140 kb
Host smart-e7b84f29-443d-4f9a-a633-f601fe9a6e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72865997895989914778188432109481218989538772402624804762811380976632697734191 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.72865997895989914778188432109481218989538772402624804762811380976632697734191
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.114716118894073073518676732230050785441343531342546367212052805963699000059555
Short name T479
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.56 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 200996 kb
Host smart-bae03cdc-04fa-4d14-82cd-c102dd3f91eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114716118894073073518676732230050785441343531342546367212052805963699000059555 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.114716118894073073518676732230050785441343531342546367212052805963699000059555
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.4685333094513473124199906164215207379354355449589011384457001955885459237085
Short name T392
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.05 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:38:17 PM PDT 23
Peak memory 201276 kb
Host smart-a17dab4a-1267-4eba-8a6d-57292fec8b75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4685333094513473124199906164215207379354355449589011384457001955885459237085 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.468533309451347312419990616421520737935435544958901138445700195
5885459237085
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.40343798803165765262959049394074065098387143367406167963784043258332995943565
Short name T183
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.59 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 201160 kb
Host smart-ec4c2f7f-e22f-4fdb-bd8a-d02b13026693
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343798803165765262959049394074065098387143367406167963784043258332995943565 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.403437988031657652629590493940740650983871433674061679637840
43258332995943565
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.52170270321658189864619699582179210242713533755278437539916370816771128642425
Short name T567
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Nov 01 12:35:09 PM PDT 23
Finished Nov 01 12:35:21 PM PDT 23
Peak memory 201008 kb
Host smart-8784be9a-6b81-49ed-a0f1-57d26751f392
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52170270321658189864619699582179210242713533755278437539916370816771128642425 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.5217027032165818986461969958217921024271353375527843753991637081
6771128642425
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.111576126672566563043726675378623554334807520776412198195410928683179490465187
Short name T378
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.56 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:36 PM PDT 23
Peak memory 200940 kb
Host smart-1164a3e0-4000-4e54-bd7b-831f4ddb75ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111576126672566563043726675378623554334807520776412198195410928683179490465187 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.111576126672566563043726675378623554334807520776412198195410928683179490465187
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.86936926229056940858827334894725667845568006134843166129502292086856527770418
Short name T401
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:19 PM PDT 23
Peak memory 201056 kb
Host smart-d6f31aad-c49d-472f-b8c5-c4dfdd7f7bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86936926229056940858827334894725667845568006134843166129502292086856527770418 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.86936926229056940858827334894725667845568006134843166129502292086856527770418
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.80938635348743879989932572306490785698088304769168377664491457004012539976127
Short name T228
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 200996 kb
Host smart-165fce31-34d6-4640-8dfb-9b2788c895a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80938635348743879989932572306490785698088304769168377664491457004012539976127 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.80938635348743879989932572306490785698088304769168377664491457004012539976127
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.76651482905995776433846851648749070230070969872663449834532705122964333248744
Short name T320
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 201180 kb
Host smart-60e4c4cb-fa56-4ecc-93f2-c9f11ca03c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76651482905995776433846851648749070230070969872663449834532705122964333248744 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.76651482905995776433846851648749070230070969872663449834532705122964333248744
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.90979407583436875340857674150891643817049018686556588323531463349081094264956
Short name T473
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 01 12:35:03 PM PDT 23
Finished Nov 01 12:35:13 PM PDT 23
Peak memory 201004 kb
Host smart-e8c585aa-3c9f-4207-9ccb-9e472b0fae9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90979407583436875340857674150891643817049018686556588323531463349081094264956 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sysrst_ctrl_smoke.90979407583436875340857674150891643817049018686556588323531463349081094264956
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.90409978664527841579868156854548594077898650485637244345376144316139571927994
Short name T425
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.23 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:37:28 PM PDT 23
Peak memory 201344 kb
Host smart-b5d69683-7ecb-4c24-8d2e-b0285c23a7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90409978664527841579868156854548594077898650485637244345376144316139571927994 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.90409978664527841579868156854548594077898650485637244345376144316139571927994
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.21391688883402835013330272062606485359249708294645445386975711569168663556776
Short name T138
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.79 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:35:15 PM PDT 23
Peak memory 201004 kb
Host smart-cf74c9ac-1e44-43ab-9742-7c0e50363377
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21391688883402835013330272062606485359249708294645445386975711569168663556776 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.213916888834028350133302720626064853592497082946454453869757
11569168663556776
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.107076632820994760593406358381690254605021078584604261957196515022134091719653
Short name T386
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201080 kb
Host smart-39c9066c-423d-4e46-b642-862f724ed83e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107076632820994760593406358381690254605021078584604261957196515022134091719653 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.107076632820994760593406358381690254605021078584604261957196515022134091719653
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.72636997238643596081192677524466612966729397567402910080341020444334668233579
Short name T513
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.45 seconds
Started Nov 01 12:35:09 PM PDT 23
Finished Nov 01 12:35:23 PM PDT 23
Peak memory 201096 kb
Host smart-2ec9f569-5e0d-400d-ba34-8cfe0e600090
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72636997238643596081192677524466612966729397567402910080341020444334668233579 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.726369972386435960811926775244666129667293975674029100803410
20444334668233579
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.72289783707821038490497396903656011389645410591673139880961972548616538227474
Short name T457
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.47 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:20 PM PDT 23
Peak memory 200968 kb
Host smart-1909b621-428e-4b99-bd08-130871bbbe08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72289783707821038490497396903656011389645410591673139880961972548616538227474 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.7228978370782103849049739690365601138964541059167313988096197254
8616538227474
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.59565408040631402912199368018803023369207103684382070040249239692535466110396
Short name T594
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 01 12:35:07 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 201088 kb
Host smart-70a237cf-57c1-4605-bfb9-6d2d64c7fa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59565408040631402912199368018803023369207103684382070040249239692535466110396 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.59565408040631402912199368018803023369207103684382070040249239692535466110396
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.110142124710287301493876643336668755906832926130703250297954775872641692945124
Short name T147
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:35:14 PM PDT 23
Peak memory 201056 kb
Host smart-aaa19a81-17b3-4a7f-85e0-5d7954f2241f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110142124710287301493876643336668755906832926130703250297954775872641692945124 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.110142124710287301493876643336668755906832926130703250297954775872641692945124
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.9506875471290364200591935597059482818855314155862115835755868272061113503919
Short name T216
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:15 PM PDT 23
Peak memory 201016 kb
Host smart-b3b8936e-a4b9-45ac-9b98-8ee58a4bd160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9506875471290364200591935597059482818855314155862115835755868272061113503919 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.9506875471290364200591935597059482818855314155862115835755868272061113503919
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.59298838014999037316742452948207246603599402203993890107651959153931015557197
Short name T426
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Nov 01 12:35:09 PM PDT 23
Finished Nov 01 12:35:20 PM PDT 23
Peak memory 201040 kb
Host smart-fad430ae-36f4-4b2a-9880-5a816db847c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59298838014999037316742452948207246603599402203993890107651959153931015557197 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.59298838014999037316742452948207246603599402203993890107651959153931015557197
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.10658850259769976216765471827814145247541092085112420923456122626674688773231
Short name T447
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.95 seconds
Started Nov 01 12:35:08 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 200992 kb
Host smart-c255defe-10b0-459d-80f8-5b4d3393b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10658850259769976216765471827814145247541092085112420923456122626674688773231 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_smoke.10658850259769976216765471827814145247541092085112420923456122626674688773231
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.78230083840623482572191481370455044829601289804048069185368243192689558291576
Short name T266
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.11 seconds
Started Nov 01 12:35:13 PM PDT 23
Finished Nov 01 12:37:34 PM PDT 23
Peak memory 201212 kb
Host smart-58f2bb70-54f1-4793-a5b2-bc97ba979d9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78230083840623482572191481370455044829601289804048069185368243192689558291576 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.78230083840623482572191481370455044829601289804048069185368243192689558291576
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.79994206307538554338286132228630976115887696958675535402948887738909133850715
Short name T204
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201004 kb
Host smart-33ff07de-1424-47d3-996b-94b9a4890c43
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79994206307538554338286132228630976115887696958675535402948887738909133850715 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.799942063075385543382861322286309761158876969586755354029488
87738909133850715
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.24825603268036851302364569031001025567055917404667960916374351458630805800380
Short name T621
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:31 PM PDT 23
Peak memory 201080 kb
Host smart-7bdf3082-62e5-4539-9b8c-e90d4040babe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24825603268036851302364569031001025567055917404667960916374351458630805800380 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.24825603268036851302364569031001025567055917404667960916374351458630805800380
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.10172340966795379588379387255176949407973298260883984787401521474559820251278
Short name T655
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 01 12:35:24 PM PDT 23
Finished Nov 01 12:35:30 PM PDT 23
Peak memory 201100 kb
Host smart-fec680f6-4285-4eaa-86aa-523afc5b3e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10172340966795379588379387255176949407973298260883984787401521474559820251278 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.10172340966795379588379387255176949407973298260883984787401521474559820251278
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.84557263477176477585953425351532736663146180989106013402310452786786696506456
Short name T495
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.25 seconds
Started Nov 01 12:35:28 PM PDT 23
Finished Nov 01 12:38:31 PM PDT 23
Peak memory 201196 kb
Host smart-7489603c-66a6-4d29-a8fd-4bd2f6a8113b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84557263477176477585953425351532736663146180989106013402310452786786696506456 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.84557263477176477585953425351532736663146180989106013402310452
786786696506456
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.77473749617707508080518102814878023156945067759338420934144603045626742488177
Short name T235
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.42 seconds
Started Nov 01 12:35:25 PM PDT 23
Finished Nov 01 12:35:34 PM PDT 23
Peak memory 201144 kb
Host smart-b538df25-17d0-4268-88ce-0ac75ef7421a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77473749617707508080518102814878023156945067759338420934144603045626742488177 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.774737496177075080805181028148780231569450677593384209341446
03045626742488177
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.15600280430413320668244935230207242397731933836002918040533614904841642865615
Short name T30
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.39 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:35 PM PDT 23
Peak memory 200984 kb
Host smart-3c05b1b2-7b92-492b-a201-c12199db360c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15600280430413320668244935230207242397731933836002918040533614904841642865615 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.1560028043041332066824493523020724239773193383600291804053361490
4841642865615
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.84131104839222198673079772316900372506963681147080216854868603548662383466182
Short name T254
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 01 12:35:21 PM PDT 23
Finished Nov 01 12:35:26 PM PDT 23
Peak memory 201044 kb
Host smart-27c8d54c-6247-4a3b-824e-5a51e831c424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84131104839222198673079772316900372506963681147080216854868603548662383466182 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.84131104839222198673079772316900372506963681147080216854868603548662383466182
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.94396152638003613436690566293125467455493332629014968547760855466964134878581
Short name T371
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.9 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:35:11 PM PDT 23
Peak memory 201048 kb
Host smart-991d0579-d014-495b-8ae8-361f1130c4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94396152638003613436690566293125467455493332629014968547760855466964134878581 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.94396152638003613436690566293125467455493332629014968547760855466964134878581
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.88649531185884627602156650537535161089874707711432126427105601642688025178109
Short name T449
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:31 PM PDT 23
Peak memory 201052 kb
Host smart-145787c4-84f1-48e4-b149-9446a583cf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88649531185884627602156650537535161089874707711432126427105601642688025178109 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.88649531185884627602156650537535161089874707711432126427105601642688025178109
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.64464211383313386762104812349084868401252177913858599145666393271899326412114
Short name T451
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:32 PM PDT 23
Peak memory 201048 kb
Host smart-8d2241fc-dcc8-4fd1-8350-0cd43474400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64464211383313386762104812349084868401252177913858599145666393271899326412114 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.64464211383313386762104812349084868401252177913858599145666393271899326412114
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.30316734909998092086069713337818000846175200493451892933223745436900156168701
Short name T606
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.75 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 200972 kb
Host smart-aefe8c57-63db-4c8c-8ad3-3c2c9ceabfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30316734909998092086069713337818000846175200493451892933223745436900156168701 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_smoke.30316734909998092086069713337818000846175200493451892933223745436900156168701
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.75357800320685150610050273020652337565195273332966850201081872087972698919076
Short name T152
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.24 seconds
Started Nov 01 12:35:25 PM PDT 23
Finished Nov 01 12:37:42 PM PDT 23
Peak memory 201348 kb
Host smart-63cd5778-e286-45b0-bc49-6daaf6726fed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75357800320685150610050273020652337565195273332966850201081872087972698919076 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.75357800320685150610050273020652337565195273332966850201081872087972698919076
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.72672417326799355990259989965527388059911024136297903177704435806383026315491
Short name T309
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Nov 01 12:35:23 PM PDT 23
Finished Nov 01 12:35:29 PM PDT 23
Peak memory 201144 kb
Host smart-8fb765bd-456a-4af5-b79d-30a80d597c95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72672417326799355990259989965527388059911024136297903177704435806383026315491 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.726724173267993559902599899655273880599110241362979031777044
35806383026315491
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.114266369413993338439612995568321061253514828088750013728389359092310609561076
Short name T291
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 01 12:35:22 PM PDT 23
Finished Nov 01 12:35:28 PM PDT 23
Peak memory 201376 kb
Host smart-e4db6e33-0ab2-4fd7-9def-7e8878fc1e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114266369413993338439612995568321061253514828088750013728389359092310609561076 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.114266369413993338439612995568321061253514828088750013728389359092310609561076
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.111603766391265045674849677056457407935156336144248864957841539825524369782112
Short name T577
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.58 seconds
Started Nov 01 12:35:31 PM PDT 23
Finished Nov 01 12:35:40 PM PDT 23
Peak memory 201284 kb
Host smart-f7618316-9db4-4a05-9204-aa68a3bd8907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111603766391265045674849677056457407935156336144248864957841539825524369782112 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.111603766391265045674849677056457407935156336144248864957841539825524369782112
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.11296470806167626818787473931501219475462402921190646016680476424562603541646
Short name T561
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.84 seconds
Started Nov 01 12:35:19 PM PDT 23
Finished Nov 01 12:38:24 PM PDT 23
Peak memory 201272 kb
Host smart-661ea371-668a-40e9-9854-f48c85093e19
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296470806167626818787473931501219475462402921190646016680476424562603541646 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.11296470806167626818787473931501219475462402921190646016680476
424562603541646
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.88471224330837079671363839065586808385850368412848795444656304594556961083809
Short name T199
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Nov 01 12:35:33 PM PDT 23
Finished Nov 01 12:35:43 PM PDT 23
Peak memory 201176 kb
Host smart-733c27ca-452e-4d6a-8134-a3da584c628f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88471224330837079671363839065586808385850368412848795444656304594556961083809 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.884712243308370796713638390655868083858503684128487954446563
04594556961083809
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.70502355018496819573765164333447507948513070438372715023428624885876975280605
Short name T474
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:40 PM PDT 23
Peak memory 201160 kb
Host smart-80d900e2-c85e-4d6c-8dcd-7c4c9e5d5ed2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70502355018496819573765164333447507948513070438372715023428624885876975280605 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.7050235501849681957376516433344750794851307043837271502342862488
5876975280605
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.28061959481826429907387358121618496349704142504624830972439165334705930884235
Short name T625
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.56 seconds
Started Nov 01 12:35:24 PM PDT 23
Finished Nov 01 12:35:30 PM PDT 23
Peak memory 201180 kb
Host smart-b5877b56-3b7d-4d06-ad99-b5b878c70e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28061959481826429907387358121618496349704142504624830972439165334705930884235 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.28061959481826429907387358121618496349704142504624830972439165334705930884235
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.92915680353916387279591082626964318665624708993007533261920977300898345191392
Short name T407
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:37 PM PDT 23
Peak memory 201092 kb
Host smart-dca71c42-960f-4738-b38a-7e2cb6d86eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92915680353916387279591082626964318665624708993007533261920977300898345191392 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.92915680353916387279591082626964318665624708993007533261920977300898345191392
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.59175960042001166529376562842508638390890933520471033718768131406916991319772
Short name T647
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 01 12:35:27 PM PDT 23
Finished Nov 01 12:35:33 PM PDT 23
Peak memory 201024 kb
Host smart-0ea36f10-8ebb-4dca-8fb8-96d721cce8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59175960042001166529376562842508638390890933520471033718768131406916991319772 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.59175960042001166529376562842508638390890933520471033718768131406916991319772
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.40629445584473671017433008953677793707371943604573572178472615810201187586749
Short name T177
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:32 PM PDT 23
Peak memory 200916 kb
Host smart-2d946bbf-ba6b-42a0-8757-4b92db4a8a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40629445584473671017433008953677793707371943604573572178472615810201187586749 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sysrst_ctrl_smoke.40629445584473671017433008953677793707371943604573572178472615810201187586749
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.16451717110324897472558089988741488683969051839990759739412393761330025733296
Short name T462
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.26 seconds
Started Nov 01 12:35:23 PM PDT 23
Finished Nov 01 12:37:41 PM PDT 23
Peak memory 201300 kb
Host smart-2ea942cc-3bca-44ff-a674-16a038df8e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16451717110324897472558089988741488683969051839990759739412393761330025733296 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.16451717110324897472558089988741488683969051839990759739412393761330025733296
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.37296140774934595169390838088380640975154382151946421575468487545884763706464
Short name T273
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Nov 01 12:35:29 PM PDT 23
Finished Nov 01 12:35:34 PM PDT 23
Peak memory 201336 kb
Host smart-f5a60df2-e3df-4952-83ae-659ef11087f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37296140774934595169390838088380640975154382151946421575468487545884763706464 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.372961407749345951693908380883806409751543821519464215754684
87545884763706464
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.8802104316744575633665858687441722310650566646954952654747502458602338211050
Short name T146
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.81 seconds
Started Nov 01 12:35:28 PM PDT 23
Finished Nov 01 12:35:33 PM PDT 23
Peak memory 200980 kb
Host smart-bec79537-8ebb-418e-98bd-410af6c4ea97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8802104316744575633665858687441722310650566646954952654747502458602338211050 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.8802104316744575633665858687441722310650566646954952654747502458602338211050
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.70569335789460911871375330402307226982557180745799871414980119157487303467136
Short name T454
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 01 12:35:21 PM PDT 23
Finished Nov 01 12:35:27 PM PDT 23
Peak memory 201108 kb
Host smart-bc398dd9-e177-4e21-9fb1-8e5860390e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70569335789460911871375330402307226982557180745799871414980119157487303467136 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.70569335789460911871375330402307226982557180745799871414980119157487303467136
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.83136051432858687160382221889510911859538368522404492368654238915129930004567
Short name T167
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.61 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:38:37 PM PDT 23
Peak memory 201312 kb
Host smart-7ea13c89-b34b-48f6-b11c-3f58bde68330
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83136051432858687160382221889510911859538368522404492368654238915129930004567 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.83136051432858687160382221889510911859538368522404492368654238
915129930004567
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.31107889648608017691373666197550944186879014186569036401371403223032108389190
Short name T518
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 01 12:35:23 PM PDT 23
Finished Nov 01 12:35:32 PM PDT 23
Peak memory 201088 kb
Host smart-86d6a678-bcea-4a6a-9b1d-72bb5ca750ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31107889648608017691373666197550944186879014186569036401371403223032108389190 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.311078896486080176913736661975509441868790141865690364013714
03223032108389190
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.32820603815320650122020249503898558675997638697437112199160369684246283794374
Short name T609
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.37 seconds
Started Nov 01 12:35:31 PM PDT 23
Finished Nov 01 12:35:41 PM PDT 23
Peak memory 201152 kb
Host smart-1f0818b3-2c0f-41fa-9956-cd460216d198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820603815320650122020249503898558675997638697437112199160369684246283794374 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.3282060381532065012202024950389855867599763869743711219916036968
4246283794374
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.97673492839398072260006195199525584506891517961579416551266146423939541036530
Short name T405
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:32 PM PDT 23
Peak memory 201036 kb
Host smart-35e0bfae-cd23-4086-88ca-dd708ae44a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97673492839398072260006195199525584506891517961579416551266146423939541036530 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.97673492839398072260006195199525584506891517961579416551266146423939541036530
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.73693652126391653667993748529630938762808452426198758213372331748333950316767
Short name T377
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.7 seconds
Started Nov 01 12:35:34 PM PDT 23
Finished Nov 01 12:35:40 PM PDT 23
Peak memory 201032 kb
Host smart-eec8965f-cbe5-4689-92a2-65460639b3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73693652126391653667993748529630938762808452426198758213372331748333950316767 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.73693652126391653667993748529630938762808452426198758213372331748333950316767
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.62171144474016668160381578867392450629752660377300934000613145705458999240172
Short name T445
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 01 12:35:25 PM PDT 23
Finished Nov 01 12:35:30 PM PDT 23
Peak memory 200984 kb
Host smart-178f9823-dc0d-440c-91b5-da02e6df3719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62171144474016668160381578867392450629752660377300934000613145705458999240172 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.62171144474016668160381578867392450629752660377300934000613145705458999240172
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.94034436220406931916788196326815351537984167504581871665258702876174172510731
Short name T667
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.48 seconds
Started Nov 01 12:35:34 PM PDT 23
Finished Nov 01 12:35:40 PM PDT 23
Peak memory 201020 kb
Host smart-111a85f4-b39a-41a6-9d86-3bc00aef7f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94034436220406931916788196326815351537984167504581871665258702876174172510731 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.94034436220406931916788196326815351537984167504581871665258702876174172510731
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.648881685243816870917335764979400734950962969843462133171469773715076976622
Short name T328
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Nov 01 12:35:33 PM PDT 23
Finished Nov 01 12:35:39 PM PDT 23
Peak memory 201096 kb
Host smart-02dbc765-4ee3-4393-a4e9-61079ed48212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648881685243816870917335764979400734950962969843462133171469773715076976622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.sysrst_ctrl_smoke.648881685243816870917335764979400734950962969843462133171469773715076976622
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.101413398105730146651525667112596355607969216124745741500608935093206542171313
Short name T571
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.28 seconds
Started Nov 01 12:35:31 PM PDT 23
Finished Nov 01 12:37:52 PM PDT 23
Peak memory 201432 kb
Host smart-24117c3d-c06c-4c5a-b548-b3346f335ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101413398105730146651525667112596355607969216124745741500608935093206542171313 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.101413398105730146651525667112596355607969216124745741500608935093206542171313
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.76803653675881954532826357903200098373220170531715410651171291178799182543141
Short name T236
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Nov 01 12:35:19 PM PDT 23
Finished Nov 01 12:35:26 PM PDT 23
Peak memory 201096 kb
Host smart-781234e4-b1be-457b-99a3-1800ca492088
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76803653675881954532826357903200098373220170531715410651171291178799182543141 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.768036536758819545328263579032000983732201705317154106511712
91178799182543141
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.43583740357758018319061711806380830255576826147435066308356496674370174452497
Short name T635
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 01 12:34:06 PM PDT 23
Finished Nov 01 12:34:11 PM PDT 23
Peak memory 201064 kb
Host smart-ef9395aa-a447-45e9-a304-ac6c8240617f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43583740357758018319061711806380830255576826147435066308356496674370174452497 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.43583740357758018319061711806380830255576826147435066308356496674370174452497
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.102072455843075724898780445378001919168397155598773801850737876324706771575112
Short name T438
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 01 12:33:55 PM PDT 23
Finished Nov 01 12:34:02 PM PDT 23
Peak memory 201120 kb
Host smart-a53e20e0-ac3d-4de0-a41f-e3d8366a13a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102072455843075724898780445378001919168397155598773801850737876324706771575112 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.102072455843075724898780445378001919168397155598773801850737876324706771575112
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.80739880654867487050393186061092780812482847688044097461252155200292292135153
Short name T464
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.78 seconds
Started Nov 01 12:34:08 PM PDT 23
Finished Nov 01 12:37:15 PM PDT 23
Peak memory 201292 kb
Host smart-eaa8cb10-8b1f-448d-9ade-53f1418e1201
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80739880654867487050393186061092780812482847688044097461252155200292292135153 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.807398806548674870503931860610927808124828476880440974612521552
00292292135153
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.48379393893356777289380878181754910986412773234227561394919168453302141295199
Short name T139
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.22 seconds
Started Nov 01 12:34:02 PM PDT 23
Finished Nov 01 12:34:09 PM PDT 23
Peak memory 200988 kb
Host smart-37981813-35bb-4445-9a36-2c51b2813a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48379393893356777289380878181754910986412773234227561394919168453302141295199 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.48379393893356777289380878181754910986412773234227561394919168453302141295199
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.95117846407700433485732008328841836573847250078607966922291475991024155246164
Short name T128
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.4 seconds
Started Nov 01 12:33:56 PM PDT 23
Finished Nov 01 12:34:01 PM PDT 23
Peak memory 201084 kb
Host smart-5c47cc65-c26a-464b-8790-620ab53f9c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95117846407700433485732008328841836573847250078607966922291475991024155246164 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.95117846407700433485732008328841836573847250078607966
922291475991024155246164
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.114867464164995417197386921256841110829674672588128202656493159825742034877756
Short name T360
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Nov 01 12:33:55 PM PDT 23
Finished Nov 01 12:34:04 PM PDT 23
Peak memory 201100 kb
Host smart-28d3f7ee-32fb-48b2-bf07-3fb7a8840cc0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114867464164995417197386921256841110829674672588128202656493159825742034877756 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.114867464164995417197386921256841110829674672588128202656493
159825742034877756
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.5311797566298178764325771138691964785484800670188699576030002968483392107919
Short name T535
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:06 PM PDT 23
Peak memory 201036 kb
Host smart-56e1dbb6-08d5-48e0-8452-4de3f2e215a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5311797566298178764325771138691964785484800670188699576030002968483392107919 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.5311797566298178764325771138691964785484800670188699576030002968483392107919
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.72063465269026592042883423664429219984554511253096605239100709489889915415228
Short name T349
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.59 seconds
Started Nov 01 12:34:08 PM PDT 23
Finished Nov 01 12:34:17 PM PDT 23
Peak memory 201140 kb
Host smart-96b33eb4-98cd-48ac-b098-fe992782033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72063465269026592042883423664429219984554511253096605239100709489889915415228 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.72063465269026592042883423664429219984554511253096605239100709489889915415228
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.24559631593873777585708850825184481964889129841348978258695083634977318911309
Short name T43
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:34:08 PM PDT 23
Peak memory 201028 kb
Host smart-51a102b1-f9e1-4f09-9222-e3cc2fd75c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24559631593873777585708850825184481964889129841348978258695083634977318911309 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.24559631593873777585708850825184481964889129841348978258695083634977318911309
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.43804096215386261747464648750433566992465787152330875582564226045896981742642
Short name T40
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.71 seconds
Started Nov 01 12:33:57 PM PDT 23
Finished Nov 01 12:34:01 PM PDT 23
Peak memory 201028 kb
Host smart-4bf2f0a2-5f2a-4324-a3ec-b002d874b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43804096215386261747464648750433566992465787152330875582564226045896981742642 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.43804096215386261747464648750433566992465787152330875582564226045896981742642
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.12128769605456458955484767904900574565320089346829455725457972088264262489589
Short name T644
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:04 PM PDT 23
Peak memory 201040 kb
Host smart-4235cf27-0e5d-4003-ad4e-8aca0a2a2382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12128769605456458955484767904900574565320089346829455725457972088264262489589 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.12128769605456458955484767904900574565320089346829455725457972088264262489589
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.30675007270251058129069746543160407012533256188271876149413740437545079358776
Short name T140
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.86 seconds
Started Nov 01 12:34:04 PM PDT 23
Finished Nov 01 12:35:12 PM PDT 23
Peak memory 221432 kb
Host smart-1e769dac-648f-4942-bd00-5690773ed67a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675007270251058129069746543160407012533256188271876149413740437545079358776 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.30675007270251058129069746543160407012533256188271876149413740437545079358776
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.95748680851115257757324325131682669731310083505304460643844505964870290671749
Short name T306
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 01 12:34:07 PM PDT 23
Finished Nov 01 12:34:12 PM PDT 23
Peak memory 201008 kb
Host smart-ca89bfb4-fa02-4012-bb44-465c7faf4966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95748680851115257757324325131682669731310083505304460643844505964870290671749 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_smoke.95748680851115257757324325131682669731310083505304460643844505964870290671749
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.92014049305666886087705507974615700397001911248151618545300466753301388144455
Short name T399
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.98 seconds
Started Nov 01 12:34:00 PM PDT 23
Finished Nov 01 12:36:20 PM PDT 23
Peak memory 201348 kb
Host smart-f62d6bcf-b8b0-40fc-8b52-925f623df2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92014049305666886087705507974615700397001911248151618545300466753301388144455 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.92014049305666886087705507974615700397001911248151618545300466753301388144455
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.15125049166029694004461885696500177215386447582752046952419833762022698385347
Short name T145
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.64 seconds
Started Nov 01 12:34:05 PM PDT 23
Finished Nov 01 12:34:11 PM PDT 23
Peak memory 201040 kb
Host smart-914d9f14-3c57-4f5e-8429-c1be86ba187f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15125049166029694004461885696500177215386447582752046952419833762022698385347 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.1512504916602969400446188569650017721538644758275204695241983
3762022698385347
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.45497530398932359139072326681680340502573378743506288576702908896708276961023
Short name T294
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Nov 01 12:35:27 PM PDT 23
Finished Nov 01 12:35:32 PM PDT 23
Peak memory 201032 kb
Host smart-bd08a3a0-7b4f-4410-8742-bbb6ddceb346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45497530398932359139072326681680340502573378743506288576702908896708276961023 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.45497530398932359139072326681680340502573378743506288576702908896708276961023
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.9855111402009842507766922002229717885766625816192548404902741756821716417583
Short name T307
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.57 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:38 PM PDT 23
Peak memory 201192 kb
Host smart-15ba9e8c-098a-4cb1-9df5-4aa59ebbd98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9855111402009842507766922002229717885766625816192548404902741756821716417583 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.9855111402009842507766922002229717885766625816192548404902741756821716417583
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.30929422629564123847071251786765900277303866942471249351909584628717909445208
Short name T29
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.51 seconds
Started Nov 01 12:35:33 PM PDT 23
Finished Nov 01 12:38:38 PM PDT 23
Peak memory 201312 kb
Host smart-5790e1dc-7253-4a76-992d-cc86a4b1edcc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30929422629564123847071251786765900277303866942471249351909584628717909445208 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.30929422629564123847071251786765900277303866942471249351909584
628717909445208
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.104827609215446670565265096671473754450656801816056009842350537041359791071681
Short name T267
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.44 seconds
Started Nov 01 12:35:28 PM PDT 23
Finished Nov 01 12:35:37 PM PDT 23
Peak memory 201176 kb
Host smart-b83cec43-ceeb-4b7b-9ed8-eeca0ff75b9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104827609215446670565265096671473754450656801816056009842350537041359791071681 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.10482760921544667056526509667147375445065680181605600984235
0537041359791071681
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.8341484444193466673693867919944690096296141504361460836867178282304414285898
Short name T423
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.25 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:40 PM PDT 23
Peak memory 201064 kb
Host smart-61645550-9610-44a5-988e-7135c943c074
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8341484444193466673693867919944690096296141504361460836867178282304414285898 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.8341484444193466673693867919944690096296141504361460836867178282304414285898
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.103107800992780179097962993852202764381689170339873106046889597988698380758764
Short name T472
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.75 seconds
Started Nov 01 12:35:31 PM PDT 23
Finished Nov 01 12:35:38 PM PDT 23
Peak memory 201048 kb
Host smart-a9d84c44-f575-4fba-83e2-cc9a41276caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103107800992780179097962993852202764381689170339873106046889597988698380758764 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.103107800992780179097962993852202764381689170339873106046889597988698380758764
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.22930160248278657233886331898261904197692606204788691578828321139500990542350
Short name T421
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.7 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:33 PM PDT 23
Peak memory 201072 kb
Host smart-a6e06011-f593-4184-9821-d2e3bc1cec1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22930160248278657233886331898261904197692606204788691578828321139500990542350 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.22930160248278657233886331898261904197692606204788691578828321139500990542350
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.51348155406379955929767622608856404489842003407357598410611617339008455144448
Short name T570
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 01 12:35:21 PM PDT 23
Finished Nov 01 12:35:26 PM PDT 23
Peak memory 201016 kb
Host smart-810c0be3-c17a-483c-87e5-d50bb9314b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51348155406379955929767622608856404489842003407357598410611617339008455144448 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.51348155406379955929767622608856404489842003407357598410611617339008455144448
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.18197978944165283175543142624638840612366382000414038711701645617681609392502
Short name T591
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.84 seconds
Started Nov 01 12:35:31 PM PDT 23
Finished Nov 01 12:35:39 PM PDT 23
Peak memory 201032 kb
Host smart-36b46e24-cf10-46ee-9b7f-304815c2fea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18197978944165283175543142624638840612366382000414038711701645617681609392502 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.18197978944165283175543142624638840612366382000414038711701645617681609392502
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.76553249884670636345964917560589684768789649494603795771706131587276098035725
Short name T494
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Nov 01 12:35:31 PM PDT 23
Finished Nov 01 12:35:38 PM PDT 23
Peak memory 200980 kb
Host smart-38fa512d-c49d-4ac7-9ca3-ebce5ef5c030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76553249884670636345964917560589684768789649494603795771706131587276098035725 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_smoke.76553249884670636345964917560589684768789649494603795771706131587276098035725
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.4299363952603055903128839204397018855459475985570021508565905518989902919658
Short name T120
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.12 seconds
Started Nov 01 12:35:32 PM PDT 23
Finished Nov 01 12:37:52 PM PDT 23
Peak memory 201312 kb
Host smart-11e39fb5-ed98-430f-84c4-0bd493662a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4299363952603055903128839204397018855459475985570021508565905518989902919658 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.4299363952603055903128839204397018855459475985570021508565905518989902919658
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.50709997953599727972144450716709416644461330939374639829474865329408784472755
Short name T211
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 01 12:35:29 PM PDT 23
Finished Nov 01 12:35:34 PM PDT 23
Peak memory 200932 kb
Host smart-90b744ce-caa7-4c1c-b986-b9fbd21ba5bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50709997953599727972144450716709416644461330939374639829474865329408784472755 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.507099979535997279721444507167094166444613309393746398294748
65329408784472755
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.649128176943207526760390931698998018120376942978794573472793992052719236980
Short name T340
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.77 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:36 PM PDT 23
Peak memory 201000 kb
Host smart-7a1d3404-b6b3-4b56-a682-c26730d80c99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649128176943207526760390931698998018120376942978794573472793992052719236980 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.649128176943207526760390931698998018120376942978794573472793992052719236980
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.21495873962545696819375139599139307554718260750069195340656580495649318257067
Short name T238
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 01 12:35:35 PM PDT 23
Finished Nov 01 12:35:41 PM PDT 23
Peak memory 201140 kb
Host smart-64cda251-1f64-43dc-8e10-96be8bd03685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21495873962545696819375139599139307554718260750069195340656580495649318257067 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.21495873962545696819375139599139307554718260750069195340656580495649318257067
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.114763566392247490412597018480176697708405971750475166561298021429198632852401
Short name T289
Test name
Test status
Simulation time 118289458206 ps
CPU time 186.92 seconds
Started Nov 01 12:35:34 PM PDT 23
Finished Nov 01 12:38:42 PM PDT 23
Peak memory 201312 kb
Host smart-e3640817-aff9-43eb-8420-b4fb078b331c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114763566392247490412597018480176697708405971750475166561298021429198632852401 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.1147635663922474904125970184801766977084059717504751665612980
21429198632852401
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.48899959136959116424668158151415266915083877929906636129670654498590978524525
Short name T556
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 01 12:35:35 PM PDT 23
Finished Nov 01 12:35:43 PM PDT 23
Peak memory 201192 kb
Host smart-29dfc1e3-d471-4459-948b-b5e60e5a956a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48899959136959116424668158151415266915083877929906636129670654498590978524525 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.488999591369591164246681581514152669150838779299066361296706
54498590978524525
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.51583311960814197053771707290231816322366046394073537176785045131837730814918
Short name T327
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.19 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:39 PM PDT 23
Peak memory 201056 kb
Host smart-deeb3867-788d-4f12-b163-c4c7ff2dfe0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51583311960814197053771707290231816322366046394073537176785045131837730814918 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.5158331196081419705377170729023181632236604639407353717678504513
1837730814918
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.26420095461525945784634184949139761108450612638545413252362248184764035070309
Short name T554
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 01 12:35:38 PM PDT 23
Finished Nov 01 12:35:43 PM PDT 23
Peak memory 201016 kb
Host smart-edb8f77e-a765-47fe-8be3-d29569fc2f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26420095461525945784634184949139761108450612638545413252362248184764035070309 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.26420095461525945784634184949139761108450612638545413252362248184764035070309
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.70381175098098791062515547716035950061617577092950834263742340796502608516694
Short name T118
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.85 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:33 PM PDT 23
Peak memory 201068 kb
Host smart-489b3c62-ce36-462b-a3cd-00cf170c8eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70381175098098791062515547716035950061617577092950834263742340796502608516694 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.70381175098098791062515547716035950061617577092950834263742340796502608516694
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.110363239131967008180258226129883180629903469991856936238395942281864802687459
Short name T436
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Nov 01 12:35:32 PM PDT 23
Finished Nov 01 12:35:39 PM PDT 23
Peak memory 201016 kb
Host smart-dd6aa4fe-542f-4293-97da-6d9931ae9b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110363239131967008180258226129883180629903469991856936238395942281864802687459 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.110363239131967008180258226129883180629903469991856936238395942281864802687459
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.81332845849199027228158318742573888734244400469015082882960420721079764765865
Short name T389
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.47 seconds
Started Nov 01 12:35:34 PM PDT 23
Finished Nov 01 12:35:40 PM PDT 23
Peak memory 201176 kb
Host smart-1d9fc498-9b11-47bc-acf5-9530ba74ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81332845849199027228158318742573888734244400469015082882960420721079764765865 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.81332845849199027228158318742573888734244400469015082882960420721079764765865
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.2805350834568222784614851541266798792556740354388283620204589860776566347022
Short name T178
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Nov 01 12:35:32 PM PDT 23
Finished Nov 01 12:35:39 PM PDT 23
Peak memory 200980 kb
Host smart-e46b1000-f6f0-4f2e-b14b-16a2c9161720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805350834568222784614851541266798792556740354388283620204589860776566347022 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sysrst_ctrl_smoke.2805350834568222784614851541266798792556740354388283620204589860776566347022
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.37932052334298491651962893855490634089801215218111824616803581523774700681940
Short name T452
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.09 seconds
Started Nov 01 12:35:44 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201272 kb
Host smart-46128bff-33e7-4b06-ab1c-043334df9e65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37932052334298491651962893855490634089801215218111824616803581523774700681940 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.37932052334298491651962893855490634089801215218111824616803581523774700681940
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.19486996212142998487460886949845791758975272577441253243874266086654362522944
Short name T302
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.93 seconds
Started Nov 01 12:35:36 PM PDT 23
Finished Nov 01 12:35:43 PM PDT 23
Peak memory 201028 kb
Host smart-a61dc0b4-5515-43f0-9ca2-db9d5c7c22a3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19486996212142998487460886949845791758975272577441253243874266086654362522944 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.194869962121429984874608869498457917589752725774412532438742
66086654362522944
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.94950040455254801059588378468980828591664775734535491307244599248491983240251
Short name T607
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:35:31 PM PDT 23
Peak memory 201080 kb
Host smart-a9f6e10a-ea5f-4a58-b856-4342540db2ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94950040455254801059588378468980828591664775734535491307244599248491983240251 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.94950040455254801059588378468980828591664775734535491307244599248491983240251
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.87304596610035326960598770228141191578559886181271274898154423402751476177012
Short name T241
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Nov 01 12:35:44 PM PDT 23
Finished Nov 01 12:35:51 PM PDT 23
Peak memory 201108 kb
Host smart-bb008d29-7837-46ef-8bf3-ca52834c5f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87304596610035326960598770228141191578559886181271274898154423402751476177012 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.87304596610035326960598770228141191578559886181271274898154423402751476177012
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.20694115159665597206572980127955407285522204982297443333384420827807452474862
Short name T313
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.15 seconds
Started Nov 01 12:35:26 PM PDT 23
Finished Nov 01 12:38:31 PM PDT 23
Peak memory 201364 kb
Host smart-3accc702-c686-4ef3-840f-3d2551e9230b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20694115159665597206572980127955407285522204982297443333384420827807452474862 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.20694115159665597206572980127955407285522204982297443333384420
827807452474862
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.29272446436528934411283924852848366957772259182756652750733132392134913359425
Short name T517
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Nov 01 12:35:55 PM PDT 23
Finished Nov 01 12:36:03 PM PDT 23
Peak memory 201060 kb
Host smart-71ef37f3-a19f-40f0-a9d3-2b9218a43069
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29272446436528934411283924852848366957772259182756652750733132392134913359425 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.292724464365289344112839248528483669577722591827566527507331
32392134913359425
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.41893748400760113557917475323043244772897254400199742337089040068071631418913
Short name T322
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Nov 01 12:35:37 PM PDT 23
Finished Nov 01 12:35:45 PM PDT 23
Peak memory 201028 kb
Host smart-ee8ca191-61c9-4a80-96e8-5305fb6a14ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41893748400760113557917475323043244772897254400199742337089040068071631418913 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.4189374840076011355791747532304324477289725440019974233708904006
8071631418913
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.83924001767746472067896080977248009316811624690779923325496252966596417717742
Short name T574
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.58 seconds
Started Nov 01 12:35:18 PM PDT 23
Finished Nov 01 12:35:26 PM PDT 23
Peak memory 201008 kb
Host smart-ca955663-46a2-4eb4-9d4b-946d0ce89dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83924001767746472067896080977248009316811624690779923325496252966596417717742 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.83924001767746472067896080977248009316811624690779923325496252966596417717742
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.115711842676542281905119345259346716864145682272276970403015298607286414165983
Short name T420
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.9 seconds
Started Nov 01 12:35:36 PM PDT 23
Finished Nov 01 12:35:43 PM PDT 23
Peak memory 201056 kb
Host smart-2f4b1d84-320e-463a-9b6a-0839ef5fb381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115711842676542281905119345259346716864145682272276970403015298607286414165983 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.115711842676542281905119345259346716864145682272276970403015298607286414165983
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.57495206431452815217171737682150407430495322303181175617131579973213094018699
Short name T428
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 01 12:35:36 PM PDT 23
Finished Nov 01 12:35:42 PM PDT 23
Peak memory 201012 kb
Host smart-f2b5de47-3dea-4bbc-b940-fe1595d91084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57495206431452815217171737682150407430495322303181175617131579973213094018699 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.57495206431452815217171737682150407430495322303181175617131579973213094018699
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.106891782116421817108209970897533786017317908840880663746555594714572147796334
Short name T212
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Nov 01 12:35:39 PM PDT 23
Finished Nov 01 12:35:46 PM PDT 23
Peak memory 201048 kb
Host smart-7b3991ce-8c27-4eb3-9edb-9aebb902a3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106891782116421817108209970897533786017317908840880663746555594714572147796334 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.106891782116421817108209970897533786017317908840880663746555594714572147796334
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.76561733377004912104841110719124241437140077405527433587894344798474330273353
Short name T504
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.91 seconds
Started Nov 01 12:35:34 PM PDT 23
Finished Nov 01 12:35:39 PM PDT 23
Peak memory 201076 kb
Host smart-ac3f101a-676d-48f2-af95-2abb29965244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76561733377004912104841110719124241437140077405527433587894344798474330273353 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_smoke.76561733377004912104841110719124241437140077405527433587894344798474330273353
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.91724651899793123232262455106723988209618504973874510956719381601549094337546
Short name T265
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.91 seconds
Started Nov 01 12:35:23 PM PDT 23
Finished Nov 01 12:37:40 PM PDT 23
Peak memory 201308 kb
Host smart-60097814-217e-4d9f-9c2d-f739e1a1c34a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91724651899793123232262455106723988209618504973874510956719381601549094337546 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.91724651899793123232262455106723988209618504973874510956719381601549094337546
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.98659248106967177108428024660322279063326772484532495552128455055392739150801
Short name T286
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 01 12:35:30 PM PDT 23
Finished Nov 01 12:35:38 PM PDT 23
Peak memory 201152 kb
Host smart-0ebcfbc5-7418-4ee8-ab3c-ea7c0c66b3ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98659248106967177108428024660322279063326772484532495552128455055392739150801 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.986592481069671771084280246603222790633267724845324955521284
55055392739150801
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.33138727642587817851186934686241976569390706377602332655026353748703875274502
Short name T431
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 01 12:36:11 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 201068 kb
Host smart-67411a62-24f0-43e9-aaa6-a76e9de42f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33138727642587817851186934686241976569390706377602332655026353748703875274502 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.33138727642587817851186934686241976569390706377602332655026353748703875274502
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.59184696679514256352463841832938358260426842160706257028758279888908126024636
Short name T406
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.57 seconds
Started Nov 01 12:36:10 PM PDT 23
Finished Nov 01 12:39:16 PM PDT 23
Peak memory 201292 kb
Host smart-ae0230f0-5c36-4f29-baeb-6e157dd6fdbd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59184696679514256352463841832938358260426842160706257028758279888908126024636 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.59184696679514256352463841832938358260426842160706257028758279
888908126024636
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.57727400195540280945183766945661264520531778521908449921248380845898748809648
Short name T526
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.46 seconds
Started Nov 01 12:36:08 PM PDT 23
Finished Nov 01 12:36:16 PM PDT 23
Peak memory 201040 kb
Host smart-1bf19f5d-65bc-4004-8801-82e2bf549722
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57727400195540280945183766945661264520531778521908449921248380845898748809648 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.577274001955402809451837669456612645205317785219084499212483
80845898748809648
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.79958400802139821835249209404093732386168002538014225010045805684669176227340
Short name T510
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 01 12:36:12 PM PDT 23
Finished Nov 01 12:36:24 PM PDT 23
Peak memory 201020 kb
Host smart-aff26d01-34e1-400a-acab-160722556dce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79958400802139821835249209404093732386168002538014225010045805684669176227340 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.7995840080213982183524920940409373238616800253801422501004580568
4669176227340
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.13594370227217050839397885951133864725489086778333356768651220822823387409408
Short name T460
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 01 12:36:13 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 201088 kb
Host smart-3f3b8ddd-0be9-40f7-890d-15e46454afb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13594370227217050839397885951133864725489086778333356768651220822823387409408 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.13594370227217050839397885951133864725489086778333356768651220822823387409408
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.84034484254311226162251205345323379411811685212119199743528954422937603094534
Short name T344
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 01 12:35:24 PM PDT 23
Finished Nov 01 12:35:30 PM PDT 23
Peak memory 201108 kb
Host smart-e31c707a-099d-4fd0-ad39-d28812a78946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84034484254311226162251205345323379411811685212119199743528954422937603094534 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.84034484254311226162251205345323379411811685212119199743528954422937603094534
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.6679697019612299089520213540889277383042444840097346364490534336303406996525
Short name T326
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 01 12:35:25 PM PDT 23
Finished Nov 01 12:35:29 PM PDT 23
Peak memory 200996 kb
Host smart-1db301cd-5019-4535-ba57-645ba3b3eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6679697019612299089520213540889277383042444840097346364490534336303406996525 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.6679697019612299089520213540889277383042444840097346364490534336303406996525
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.9606236797440245712673905349264349759533374332683213128274947259608904105169
Short name T41
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 01 12:36:12 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 201000 kb
Host smart-45856071-f31c-4965-befa-141242fec1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9606236797440245712673905349264349759533374332683213128274947259608904105169 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.9606236797440245712673905349264349759533374332683213128274947259608904105169
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.6337501267495025887559226345666584108253399820655701852649046220472750446851
Short name T439
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.79 seconds
Started Nov 01 12:35:29 PM PDT 23
Finished Nov 01 12:35:34 PM PDT 23
Peak memory 201012 kb
Host smart-176fb6eb-285a-4be0-a42b-e5726ba300bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6337501267495025887559226345666584108253399820655701852649046220472750446851 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sysrst_ctrl_smoke.6337501267495025887559226345666584108253399820655701852649046220472750446851
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.4030228492980735040391825490231301865809893301928718305985586413969663489530
Short name T480
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.66 seconds
Started Nov 01 12:36:01 PM PDT 23
Finished Nov 01 12:38:18 PM PDT 23
Peak memory 201388 kb
Host smart-217639d6-b630-4fb6-acb9-b1a903f17e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030228492980735040391825490231301865809893301928718305985586413969663489530 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.4030228492980735040391825490231301865809893301928718305985586413969663489530
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.56056308212008921502637147204102974593869248191156704666116172323858521005335
Short name T595
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 01 12:35:59 PM PDT 23
Finished Nov 01 12:36:05 PM PDT 23
Peak memory 201032 kb
Host smart-d4686e7d-e6a0-4b2d-ab92-0d1a437f3f51
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56056308212008921502637147204102974593869248191156704666116172323858521005335 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.560563082120089215026371472041029745938692481911567046661161
72323858521005335
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.40353019879509919925443058568930128841265946364356669866643619331848096552282
Short name T182
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 01 12:36:13 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 201044 kb
Host smart-7c63465a-5cdf-4075-9e19-df62e0ad7d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40353019879509919925443058568930128841265946364356669866643619331848096552282 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.40353019879509919925443058568930128841265946364356669866643619331848096552282
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.82821889391613593777682944652258294046066725841259015956312335279583976717300
Short name T358
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 01 12:36:15 PM PDT 23
Finished Nov 01 12:36:24 PM PDT 23
Peak memory 201092 kb
Host smart-d1901c4e-dd90-49f7-b3f5-72b9355fec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82821889391613593777682944652258294046066725841259015956312335279583976717300 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.82821889391613593777682944652258294046066725841259015956312335279583976717300
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.61833474315642695698685751443879530791135789375420746272081384871922915147143
Short name T314
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.84 seconds
Started Nov 01 12:36:16 PM PDT 23
Finished Nov 01 12:39:22 PM PDT 23
Peak memory 201364 kb
Host smart-1503520b-0ee7-4127-ba10-b346e4221fb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61833474315642695698685751443879530791135789375420746272081384871922915147143 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.61833474315642695698685751443879530791135789375420746272081384
871922915147143
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.107831042201213358655615679296196664026639680362430890038641532098084095885912
Short name T297
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.56 seconds
Started Nov 01 12:36:10 PM PDT 23
Finished Nov 01 12:36:19 PM PDT 23
Peak memory 201056 kb
Host smart-ce91b726-6e07-4ad8-8875-6776483beabb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107831042201213358655615679296196664026639680362430890038641532098084095885912 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.10783104220121335865561567929619666402663968036243089003864
1532098084095885912
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.57980837521873760298951180477603048748113479216748257673483086511853774939740
Short name T354
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 01 12:36:06 PM PDT 23
Finished Nov 01 12:36:13 PM PDT 23
Peak memory 201216 kb
Host smart-15dffc32-bd28-4108-bdf9-291932fe70dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57980837521873760298951180477603048748113479216748257673483086511853774939740 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.5798083752187376029895118047760304874811347921674825767348308651
1853774939740
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.73586067616020928332657329335421634470678734749388343344067887544499206134733
Short name T522
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.76 seconds
Started Nov 01 12:36:09 PM PDT 23
Finished Nov 01 12:36:15 PM PDT 23
Peak memory 201036 kb
Host smart-d1bf39d3-d87b-49fb-9b3d-8fec6c5faf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73586067616020928332657329335421634470678734749388343344067887544499206134733 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.73586067616020928332657329335421634470678734749388343344067887544499206134733
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.81056882927613456374378821330546299056127318381672982470126238805758837807809
Short name T489
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 01 12:36:09 PM PDT 23
Finished Nov 01 12:36:16 PM PDT 23
Peak memory 201076 kb
Host smart-163ae956-d830-4720-aa24-846c93fa3e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81056882927613456374378821330546299056127318381672982470126238805758837807809 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.81056882927613456374378821330546299056127318381672982470126238805758837807809
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.65752566790033524631150140069487809899280522007564482680799429398860628891941
Short name T509
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Nov 01 12:36:12 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 200996 kb
Host smart-6001739e-63e7-4dec-985c-419476c66c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65752566790033524631150140069487809899280522007564482680799429398860628891941 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.65752566790033524631150140069487809899280522007564482680799429398860628891941
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.93896411140241430231029557089265838107038885511317373798483531401516872460791
Short name T137
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.66 seconds
Started Nov 01 12:36:09 PM PDT 23
Finished Nov 01 12:36:15 PM PDT 23
Peak memory 201144 kb
Host smart-3bdb613d-02ab-4000-9387-cca0695f1b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93896411140241430231029557089265838107038885511317373798483531401516872460791 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.93896411140241430231029557089265838107038885511317373798483531401516872460791
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.78070953695590970582798836098775472428050310239354498646530825996790266760729
Short name T16
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Nov 01 12:36:10 PM PDT 23
Finished Nov 01 12:36:16 PM PDT 23
Peak memory 201076 kb
Host smart-4a6a20fe-2c2d-4f92-a299-74fedec2b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78070953695590970582798836098775472428050310239354498646530825996790266760729 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_smoke.78070953695590970582798836098775472428050310239354498646530825996790266760729
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.114861511423577215287191227331947528374678736123693514861328797683879193967181
Short name T36
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.6 seconds
Started Nov 01 12:36:12 PM PDT 23
Finished Nov 01 12:38:34 PM PDT 23
Peak memory 201340 kb
Host smart-1df8cdc5-5e82-4f2c-a82f-9c069dfbcc01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114861511423577215287191227331947528374678736123693514861328797683879193967181 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.114861511423577215287191227331947528374678736123693514861328797683879193967181
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.70165610621011117969565364429547693093048540664141946898981008920839907484824
Short name T660
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Nov 01 12:36:16 PM PDT 23
Finished Nov 01 12:36:24 PM PDT 23
Peak memory 201028 kb
Host smart-9d85a189-6974-4c31-9c88-0a345ac3ba09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70165610621011117969565364429547693093048540664141946898981008920839907484824 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.701656106210111179695653644295476930930485406641419468989810
08920839907484824
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.15222046223047145582007968788710563316212647761702758132809977502930192760832
Short name T444
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.64 seconds
Started Nov 01 12:36:16 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 201056 kb
Host smart-1bc7e23c-6021-48da-9798-1533b43ac23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15222046223047145582007968788710563316212647761702758132809977502930192760832 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.15222046223047145582007968788710563316212647761702758132809977502930192760832
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.92060582686981426145014478881041293674646338610266111566535050453742800742074
Short name T379
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 01 12:36:10 PM PDT 23
Finished Nov 01 12:36:17 PM PDT 23
Peak memory 201144 kb
Host smart-19f6b883-f650-4fe0-a819-16630c631105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92060582686981426145014478881041293674646338610266111566535050453742800742074 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.92060582686981426145014478881041293674646338610266111566535050453742800742074
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.96119904321133534133278889592242055539378601298695497016357101687715151264832
Short name T321
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.38 seconds
Started Nov 01 12:36:18 PM PDT 23
Finished Nov 01 12:39:26 PM PDT 23
Peak memory 201280 kb
Host smart-3e6ca154-b199-4394-8ef5-12f55ef33c0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96119904321133534133278889592242055539378601298695497016357101687715151264832 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.96119904321133534133278889592242055539378601298695497016357101
687715151264832
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.84646204043146927853682715354261359171640123261795598368034324793272685589077
Short name T672
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Nov 01 12:36:11 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 201368 kb
Host smart-ad0fcdb1-7a31-48ef-bc63-c4c6ff3603b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84646204043146927853682715354261359171640123261795598368034324793272685589077 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.846462040431469278536827153542613591716401232617955983680343
24793272685589077
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.89678720217856481348287745999901513257434834203433520610100992017834047682358
Short name T38
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Nov 01 12:36:21 PM PDT 23
Finished Nov 01 12:36:29 PM PDT 23
Peak memory 201028 kb
Host smart-f3bcbe08-01fe-457d-999b-5d7bb5e2e3c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89678720217856481348287745999901513257434834203433520610100992017834047682358 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.8967872021785648134828774599990151325743483420343352061010099201
7834047682358
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.10441324509489351251845704632916036183685535886132194927015003949847508242211
Short name T346
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.64 seconds
Started Nov 01 12:36:12 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 200984 kb
Host smart-c451952d-8480-461c-bd54-4af4c960c3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10441324509489351251845704632916036183685535886132194927015003949847508242211 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.10441324509489351251845704632916036183685535886132194927015003949847508242211
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.73639347773368475310874577571150487913873852118454116762258988845506821211749
Short name T240
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.73 seconds
Started Nov 01 12:36:10 PM PDT 23
Finished Nov 01 12:36:16 PM PDT 23
Peak memory 201076 kb
Host smart-6781998d-db04-40fa-8981-1e04f18aedad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73639347773368475310874577571150487913873852118454116762258988845506821211749 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.73639347773368475310874577571150487913873852118454116762258988845506821211749
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.114446509549050562594513703421225708459381318875269089327207647174658460835618
Short name T324
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.81 seconds
Started Nov 01 12:36:12 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 200992 kb
Host smart-72e3a8ac-cd4b-41aa-8ecb-76c7ccd1f27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114446509549050562594513703421225708459381318875269089327207647174658460835618 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.114446509549050562594513703421225708459381318875269089327207647174658460835618
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.17472604702974433183483874962961959640421702172141814343879938220312250565504
Short name T476
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.62 seconds
Started Nov 01 12:36:02 PM PDT 23
Finished Nov 01 12:36:07 PM PDT 23
Peak memory 201024 kb
Host smart-8379212d-370a-4c2c-b83d-4e06cd64d25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17472604702974433183483874962961959640421702172141814343879938220312250565504 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.17472604702974433183483874962961959640421702172141814343879938220312250565504
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.100916285425431224099046954902876687877300079963237568764244903496569504045891
Short name T417
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.89 seconds
Started Nov 01 12:36:15 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 200976 kb
Host smart-9960f9d8-647b-4578-9459-8b41ffa9750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100916285425431224099046954902876687877300079963237568764244903496569504045891 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.sysrst_ctrl_smoke.100916285425431224099046954902876687877300079963237568764244903496569504045891
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.8332767674594140652090316185069371709150209813641788441155826249929989728285
Short name T525
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.07 seconds
Started Nov 01 12:36:16 PM PDT 23
Finished Nov 01 12:38:36 PM PDT 23
Peak memory 201344 kb
Host smart-ff4fe921-d201-437d-b778-6d0d2e096cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8332767674594140652090316185069371709150209813641788441155826249929989728285 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.8332767674594140652090316185069371709150209813641788441155826249929989728285
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.24057886822049225878173001488400705097833803571320655074826544800254009305481
Short name T153
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 01 12:36:25 PM PDT 23
Finished Nov 01 12:36:30 PM PDT 23
Peak memory 201156 kb
Host smart-5ca8fd00-fc75-4f59-ba46-3004db3ddda6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24057886822049225878173001488400705097833803571320655074826544800254009305481 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.24057886822049225878173001488400705097833803571320655074826544800254009305481
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.110155611724441200397101362417456058042214601800500801415581275714784821721377
Short name T171
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Nov 01 12:36:17 PM PDT 23
Finished Nov 01 12:36:25 PM PDT 23
Peak memory 201148 kb
Host smart-f40f20d0-b2e9-46fd-af7b-ceaf47a37918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110155611724441200397101362417456058042214601800500801415581275714784821721377 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.110155611724441200397101362417456058042214601800500801415581275714784821721377
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.11831960718539588025871415273690166096811518970274306975165958297931885444756
Short name T180
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.31 seconds
Started Nov 01 12:36:26 PM PDT 23
Finished Nov 01 12:39:30 PM PDT 23
Peak memory 201280 kb
Host smart-4465b76b-4ae3-47ce-a06e-cabdd5ea4099
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11831960718539588025871415273690166096811518970274306975165958297931885444756 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.11831960718539588025871415273690166096811518970274306975165958
297931885444756
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.82008040513947683370753229824527940440041988487623271696795894347558317544923
Short name T252
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.66 seconds
Started Nov 01 12:36:20 PM PDT 23
Finished Nov 01 12:36:30 PM PDT 23
Peak memory 201184 kb
Host smart-1c36ac0d-7fbc-45a8-b0ee-97b7b71eef4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82008040513947683370753229824527940440041988487623271696795894347558317544923 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.820080405139476833707532298245279404400419884876232716967958
94347558317544923
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.89571372312252112487187044353829019289514180021060750494720950919199009025068
Short name T357
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.47 seconds
Started Nov 01 12:36:14 PM PDT 23
Finished Nov 01 12:36:24 PM PDT 23
Peak memory 200968 kb
Host smart-04ce61b7-01a0-4103-a099-c1ff5a53b2db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89571372312252112487187044353829019289514180021060750494720950919199009025068 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.8957137231225211248718704435382901928951418002106075049472095091
9199009025068
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.36562378169820060949492295320525973559195548198985811459107284014482383645520
Short name T536
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 01 12:36:19 PM PDT 23
Finished Nov 01 12:36:26 PM PDT 23
Peak memory 201168 kb
Host smart-f27e7c50-a8b4-4c25-a76c-71393a482e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36562378169820060949492295320525973559195548198985811459107284014482383645520 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.36562378169820060949492295320525973559195548198985811459107284014482383645520
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.17659711805479722930137422784059868125964523028592704264820452318211131445234
Short name T393
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Nov 01 12:36:16 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 201060 kb
Host smart-b3f139e2-e980-4602-a7af-ecfa634b6e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17659711805479722930137422784059868125964523028592704264820452318211131445234 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.17659711805479722930137422784059868125964523028592704264820452318211131445234
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.96499974665769428898272130082452199713588765680127341605318318910290304708557
Short name T144
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Nov 01 12:36:12 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 200964 kb
Host smart-491a113f-04f7-4175-b857-d3f2de947843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96499974665769428898272130082452199713588765680127341605318318910290304708557 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.96499974665769428898272130082452199713588765680127341605318318910290304708557
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.39600949743463361844249475172032206327142909174273491043359208194114712815212
Short name T125
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 01 12:36:18 PM PDT 23
Finished Nov 01 12:36:26 PM PDT 23
Peak memory 201060 kb
Host smart-ea560c17-9705-42a8-93f1-9f8a8676050b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39600949743463361844249475172032206327142909174273491043359208194114712815212 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.39600949743463361844249475172032206327142909174273491043359208194114712815212
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.52022052304769291388191585540762742106607842711885878692314670973435436042455
Short name T341
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.9 seconds
Started Nov 01 12:36:17 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 200944 kb
Host smart-1dc13752-a0af-4814-9f81-2d3c8ab2bedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52022052304769291388191585540762742106607842711885878692314670973435436042455 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_smoke.52022052304769291388191585540762742106607842711885878692314670973435436042455
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.76583365392319643473438886919330915248105459654832004550307721412561519255100
Short name T232
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.23 seconds
Started Nov 01 12:36:19 PM PDT 23
Finished Nov 01 12:38:38 PM PDT 23
Peak memory 201348 kb
Host smart-3119a4e6-1ca3-4ad2-8e22-638af4b8c4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76583365392319643473438886919330915248105459654832004550307721412561519255100 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.76583365392319643473438886919330915248105459654832004550307721412561519255100
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.54071132231958505311080923010658013569466098832015980247692667283235804288397
Short name T674
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.63 seconds
Started Nov 01 12:36:16 PM PDT 23
Finished Nov 01 12:36:23 PM PDT 23
Peak memory 201008 kb
Host smart-1813ba5e-68f0-4bca-96fe-0100c9297263
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54071132231958505311080923010658013569466098832015980247692667283235804288397 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.540711322319585053110809230106580135694660988320159802476926
67283235804288397
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.33743963819321619088543308281791185018142875283472815323311484484228192689654
Short name T411
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 01 12:36:32 PM PDT 23
Finished Nov 01 12:36:36 PM PDT 23
Peak memory 201012 kb
Host smart-34a820e8-51f1-499b-80f4-a6c593cba884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33743963819321619088543308281791185018142875283472815323311484484228192689654 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.33743963819321619088543308281791185018142875283472815323311484484228192689654
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.43590144670950328321372445860338575688862305181127046427064974047578794801896
Short name T97
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.63 seconds
Started Nov 01 12:36:10 PM PDT 23
Finished Nov 01 12:36:17 PM PDT 23
Peak memory 201112 kb
Host smart-8b9b5df2-9841-4331-95e5-286d8f8044f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43590144670950328321372445860338575688862305181127046427064974047578794801896 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.43590144670950328321372445860338575688862305181127046427064974047578794801896
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.5412080595160413558472563892237906127001128780615195704754794490560843746749
Short name T659
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.98 seconds
Started Nov 01 12:36:17 PM PDT 23
Finished Nov 01 12:39:25 PM PDT 23
Peak memory 201256 kb
Host smart-517536ee-b96a-4796-9d02-8799ccdf2af0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5412080595160413558472563892237906127001128780615195704754794490560843746749 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.541208059516041355847256389223790612700112878061519570475479449
0560843746749
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.96080804002315043598346048332378992998811266924798392260103156874546658701160
Short name T658
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.52 seconds
Started Nov 01 12:35:59 PM PDT 23
Finished Nov 01 12:36:07 PM PDT 23
Peak memory 201040 kb
Host smart-176ea959-9c83-476f-a301-c0dbc347639b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96080804002315043598346048332378992998811266924798392260103156874546658701160 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.960808040023150435983460483323789929988112669247983922601031
56874546658701160
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.16329181116543080351865027517324438773246630574340494628591997878738556292972
Short name T395
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.34 seconds
Started Nov 01 12:36:20 PM PDT 23
Finished Nov 01 12:36:29 PM PDT 23
Peak memory 201332 kb
Host smart-3da75049-0557-46a3-9dcb-9452302aff7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16329181116543080351865027517324438773246630574340494628591997878738556292972 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.1632918111654308035186502751732443877324663057434049462859199787
8738556292972
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.51865765612692564886789580888537885071185073934635155347346966617893123024742
Short name T116
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.79 seconds
Started Nov 01 12:36:04 PM PDT 23
Finished Nov 01 12:36:09 PM PDT 23
Peak memory 201120 kb
Host smart-a306e011-d23a-4ad7-a1d4-b61428229416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51865765612692564886789580888537885071185073934635155347346966617893123024742 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.51865765612692564886789580888537885071185073934635155347346966617893123024742
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.62967520841141054807843011515874798062809306333830746248879929087178321318244
Short name T132
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.91 seconds
Started Nov 01 12:36:21 PM PDT 23
Finished Nov 01 12:36:27 PM PDT 23
Peak memory 201360 kb
Host smart-2aa089e4-7169-455a-b9f0-52b8face1dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62967520841141054807843011515874798062809306333830746248879929087178321318244 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.62967520841141054807843011515874798062809306333830746248879929087178321318244
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.74628698282398570598239485271674433241279820118588857216815203339351857458865
Short name T270
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.85 seconds
Started Nov 01 12:36:01 PM PDT 23
Finished Nov 01 12:36:05 PM PDT 23
Peak memory 201052 kb
Host smart-eba097c5-3b4f-4633-80f3-3577701f9789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74628698282398570598239485271674433241279820118588857216815203339351857458865 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.74628698282398570598239485271674433241279820118588857216815203339351857458865
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.26606195160467505141265489316157428593283304122336315698100921542311057337652
Short name T246
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 01 12:36:10 PM PDT 23
Finished Nov 01 12:36:16 PM PDT 23
Peak memory 201120 kb
Host smart-a8072cfe-abec-4cd6-85e5-eec4f0e85d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26606195160467505141265489316157428593283304122336315698100921542311057337652 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.26606195160467505141265489316157428593283304122336315698100921542311057337652
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.112600877671766503635833626597625881095023621504916317312814383767748552787919
Short name T669
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.85 seconds
Started Nov 01 12:36:15 PM PDT 23
Finished Nov 01 12:36:22 PM PDT 23
Peak memory 200944 kb
Host smart-33bf7ca4-38b3-4a18-9e51-2591f7269f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112600877671766503635833626597625881095023621504916317312814383767748552787919 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 27.sysrst_ctrl_smoke.112600877671766503635833626597625881095023621504916317312814383767748552787919
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.88238190604182661142507848425210065761991920524443120529071566402835940361741
Short name T414
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.16 seconds
Started Nov 01 12:36:17 PM PDT 23
Finished Nov 01 12:38:36 PM PDT 23
Peak memory 201300 kb
Host smart-80dbd21a-65cd-40ae-8aaf-e348dcb6ee8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88238190604182661142507848425210065761991920524443120529071566402835940361741 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.88238190604182661142507848425210065761991920524443120529071566402835940361741
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.55467764438213196905281365453359781235768638310906794143055425940714123379423
Short name T634
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 01 12:36:09 PM PDT 23
Finished Nov 01 12:36:16 PM PDT 23
Peak memory 201064 kb
Host smart-bfad9d27-9ba9-4a47-a6be-de33cb847378
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55467764438213196905281365453359781235768638310906794143055425940714123379423 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.554677644382131969052813654533597812357686383109067941430554
25940714123379423
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.97079763595568154396921946426516231461036773754992939950087325799880696845471
Short name T499
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 01 12:36:35 PM PDT 23
Finished Nov 01 12:36:39 PM PDT 23
Peak memory 201236 kb
Host smart-59037d8d-3be6-45db-a96d-844c4ddb4e1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97079763595568154396921946426516231461036773754992939950087325799880696845471 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.97079763595568154396921946426516231461036773754992939950087325799880696845471
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.747653493888425875612765667877763830493796435510725084024365974578580095044
Short name T630
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Nov 01 12:36:34 PM PDT 23
Finished Nov 01 12:36:41 PM PDT 23
Peak memory 201176 kb
Host smart-41cd44dd-47bd-47a2-bc12-84dcd27495d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747653493888425875612765667877763830493796435510725084024365974578580095044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl
_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.747653493888425875612765667877763830493796435510725084024365974578580095044
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.108025760871648028736782338194542705175984955986204312242058606130775526178983
Short name T203
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.11 seconds
Started Nov 01 12:36:32 PM PDT 23
Finished Nov 01 12:39:36 PM PDT 23
Peak memory 201268 kb
Host smart-e4e86b64-0f7b-41fb-95b2-af75b326f435
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108025760871648028736782338194542705175984955986204312242058606130775526178983 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.1080257608716480287367823381945427051759849559862043122420586
06130775526178983
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.8645559041467034619080797739771615598214154485932098985887611706874218936095
Short name T333
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.43 seconds
Started Nov 01 12:36:25 PM PDT 23
Finished Nov 01 12:36:34 PM PDT 23
Peak memory 201064 kb
Host smart-19a95b5b-bb18-4628-a8e5-9ece8842e409
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8645559041467034619080797739771615598214154485932098985887611706874218936095 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.8645559041467034619080797739771615598214154485932098985887611
706874218936095
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.50369418967158711043745973906590793186978991571961466570863290332079426337702
Short name T157
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.26 seconds
Started Nov 01 12:36:27 PM PDT 23
Finished Nov 01 12:36:34 PM PDT 23
Peak memory 201060 kb
Host smart-10eb9fe1-361c-49d2-8742-ee628dfe3667
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50369418967158711043745973906590793186978991571961466570863290332079426337702 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.5036941896715871104374597390659079318697899157196146657086329033
2079426337702
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.14954034486552421383149150143671234714940916499775939035819731429644720783693
Short name T527
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 01 12:36:31 PM PDT 23
Finished Nov 01 12:36:37 PM PDT 23
Peak memory 201028 kb
Host smart-ff58e849-5015-45cf-ae44-c8ce7ebe4792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14954034486552421383149150143671234714940916499775939035819731429644720783693 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.14954034486552421383149150143671234714940916499775939035819731429644720783693
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.15685420694728398056862703262608571743830228020108335225607368844097089746394
Short name T299
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Nov 01 12:36:31 PM PDT 23
Finished Nov 01 12:36:37 PM PDT 23
Peak memory 201108 kb
Host smart-1d1c9fc0-a30f-4010-9e98-b95e653461c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15685420694728398056862703262608571743830228020108335225607368844097089746394 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.15685420694728398056862703262608571743830228020108335225607368844097089746394
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.24058991433035496261039288027529481863807116723331947046585182400108705357835
Short name T367
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.86 seconds
Started Nov 01 12:36:25 PM PDT 23
Finished Nov 01 12:36:30 PM PDT 23
Peak memory 201140 kb
Host smart-e2c4ca8a-21c0-4768-8820-fe99e940c23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24058991433035496261039288027529481863807116723331947046585182400108705357835 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.24058991433035496261039288027529481863807116723331947046585182400108705357835
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.93763617535914323413295206290636914715775729122699755000059873065614571797678
Short name T515
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.92 seconds
Started Nov 01 12:36:33 PM PDT 23
Finished Nov 01 12:36:40 PM PDT 23
Peak memory 200964 kb
Host smart-eba80aed-ef49-4d9d-91e5-82396e6f6318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93763617535914323413295206290636914715775729122699755000059873065614571797678 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.93763617535914323413295206290636914715775729122699755000059873065614571797678
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.74099422340008871349722181524719593698982507262471170408557684416500142391449
Short name T427
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.95 seconds
Started Nov 01 12:36:18 PM PDT 23
Finished Nov 01 12:36:25 PM PDT 23
Peak memory 201004 kb
Host smart-67f3b215-86a1-433f-82b8-85de8a350cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74099422340008871349722181524719593698982507262471170408557684416500142391449 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_smoke.74099422340008871349722181524719593698982507262471170408557684416500142391449
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.33095026854533748444405327310640537071987155763174986060125884056794554981604
Short name T296
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.63 seconds
Started Nov 01 12:36:34 PM PDT 23
Finished Nov 01 12:38:53 PM PDT 23
Peak memory 201412 kb
Host smart-01f7740d-5910-4d63-af01-671b7494fe34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33095026854533748444405327310640537071987155763174986060125884056794554981604 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.33095026854533748444405327310640537071987155763174986060125884056794554981604
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2577978606910673723332371080758098317564336890551047490830304591478657795629
Short name T20
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Nov 01 12:36:31 PM PDT 23
Finished Nov 01 12:36:37 PM PDT 23
Peak memory 201128 kb
Host smart-ee00561d-89ef-4fc9-9c51-08f60069db94
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577978606910673723332371080758098317564336890551047490830304591478657795629 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.2577978606910673723332371080758098317564336890551047490830304
591478657795629
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.82499175449119532924596539841133652854378373323606578176331739083535874714970
Short name T331
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 01 12:36:40 PM PDT 23
Finished Nov 01 12:36:47 PM PDT 23
Peak memory 201056 kb
Host smart-ec218227-d1cb-40ae-acc8-8990e54ad2b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82499175449119532924596539841133652854378373323606578176331739083535874714970 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.82499175449119532924596539841133652854378373323606578176331739083535874714970
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.97523948922548135525679586710233656243594788679045534769081100979256604420717
Short name T332
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Nov 01 12:36:36 PM PDT 23
Finished Nov 01 12:36:45 PM PDT 23
Peak memory 200604 kb
Host smart-65a27ac3-fe6a-4242-a0cc-8ef6884c3258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97523948922548135525679586710233656243594788679045534769081100979256604420717 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.97523948922548135525679586710233656243594788679045534769081100979256604420717
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.99625160933081067704372690413109635496595107151605606669335677500717431933724
Short name T579
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.88 seconds
Started Nov 01 12:36:35 PM PDT 23
Finished Nov 01 12:39:38 PM PDT 23
Peak memory 201280 kb
Host smart-dbc87997-5bcc-47dc-abf7-36cea12f9953
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99625160933081067704372690413109635496595107151605606669335677500717431933724 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.99625160933081067704372690413109635496595107151605606669335677
500717431933724
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.69869382436060410275175497563323138470105614749811549129661381394398855901753
Short name T170
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.36 seconds
Started Nov 01 12:36:31 PM PDT 23
Finished Nov 01 12:36:40 PM PDT 23
Peak memory 201056 kb
Host smart-f9356c09-0c0c-433e-9298-4b7a1144cace
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69869382436060410275175497563323138470105614749811549129661381394398855901753 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.698693824360604102751754975633231384701056147498115491296613
81394398855901753
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.61907195389131326102471167068602321659503094867641260605285407433659414762560
Short name T597
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.65 seconds
Started Nov 01 12:36:39 PM PDT 23
Finished Nov 01 12:36:49 PM PDT 23
Peak memory 201028 kb
Host smart-50bde7a4-602c-4413-8c97-4ff579354ddc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61907195389131326102471167068602321659503094867641260605285407433659414762560 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.6190719538913132610247116706860232165950309486764126060528540743
3659414762560
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.31781634812199136982744308115628116211433906155360422649062427315945393444138
Short name T603
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 01 12:36:36 PM PDT 23
Finished Nov 01 12:36:44 PM PDT 23
Peak memory 201028 kb
Host smart-120149ed-e195-41f0-8515-db09b26e1247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31781634812199136982744308115628116211433906155360422649062427315945393444138 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.31781634812199136982744308115628116211433906155360422649062427315945393444138
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.57481315776065096387032926257875817774008254628340752005403326919225747994649
Short name T596
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.88 seconds
Started Nov 01 12:36:32 PM PDT 23
Finished Nov 01 12:36:38 PM PDT 23
Peak memory 201088 kb
Host smart-1cd19eaf-121a-4a02-ba93-3e60a81de283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57481315776065096387032926257875817774008254628340752005403326919225747994649 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.57481315776065096387032926257875817774008254628340752005403326919225747994649
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.10861185703372241735659632052896078398938677571558085162273078458069020914328
Short name T173
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 01 12:36:24 PM PDT 23
Finished Nov 01 12:36:29 PM PDT 23
Peak memory 201032 kb
Host smart-299d1fcf-7714-472b-be64-daf325f1ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10861185703372241735659632052896078398938677571558085162273078458069020914328 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.10861185703372241735659632052896078398938677571558085162273078458069020914328
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.88199787045187972502792868160761489713055885980654508880303768249793390819066
Short name T670
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.58 seconds
Started Nov 01 12:36:31 PM PDT 23
Finished Nov 01 12:36:37 PM PDT 23
Peak memory 201144 kb
Host smart-4db20201-33e4-424f-a453-a82c87546d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88199787045187972502792868160761489713055885980654508880303768249793390819066 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.88199787045187972502792868160761489713055885980654508880303768249793390819066
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.53884374761641479163427967169266106707617581244967494308910979947334106335666
Short name T277
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Nov 01 12:36:32 PM PDT 23
Finished Nov 01 12:36:37 PM PDT 23
Peak memory 201076 kb
Host smart-ec0edace-735c-4219-8341-4e31dccb9ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53884374761641479163427967169266106707617581244967494308910979947334106335666 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_smoke.53884374761641479163427967169266106707617581244967494308910979947334106335666
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.111039078584765675182449789128326373518747372179523413841762789698859047372778
Short name T37
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.15 seconds
Started Nov 01 12:36:32 PM PDT 23
Finished Nov 01 12:38:51 PM PDT 23
Peak memory 201296 kb
Host smart-271b907a-8e0b-4dca-801c-e1f260c6c18f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111039078584765675182449789128326373518747372179523413841762789698859047372778 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.111039078584765675182449789128326373518747372179523413841762789698859047372778
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.15951761539680365041122691585468011216853990565029159470693975151223824367937
Short name T45
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.89 seconds
Started Nov 01 12:36:34 PM PDT 23
Finished Nov 01 12:36:40 PM PDT 23
Peak memory 201124 kb
Host smart-abcdbba6-a1ac-4bd7-a698-34545e78084c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15951761539680365041122691585468011216853990565029159470693975151223824367937 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.159517615396803650411226915854680112168539905650291594706939
75151223824367937
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.59844648950972178193810935603490434180990993252875830520386184171190243292087
Short name T491
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:34:25 PM PDT 23
Peak memory 200932 kb
Host smart-e4fa94ac-8daa-4d9b-904c-a0a844d78a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59844648950972178193810935603490434180990993252875830520386184171190243292087 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.59844648950972178193810935603490434180990993252875830520386184171190243292087
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.75533128470200938647831681933375338383553541549464486924021232708956557314045
Short name T429
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.44 seconds
Started Nov 01 12:34:07 PM PDT 23
Finished Nov 01 12:34:14 PM PDT 23
Peak memory 201132 kb
Host smart-2938b8fb-c6a2-400e-8cca-3f2e7509caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75533128470200938647831681933375338383553541549464486924021232708956557314045 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.75533128470200938647831681933375338383553541549464486924021232708956557314045
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.36525763432884864996519571815683757308954166678353600236437772810777488019700
Short name T440
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.95 seconds
Started Nov 01 12:34:32 PM PDT 23
Finished Nov 01 12:37:41 PM PDT 23
Peak memory 201276 kb
Host smart-d66bedcb-5e32-47be-a71f-6094156fef9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36525763432884864996519571815683757308954166678353600236437772810777488019700 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.365257634328848649965195718156837573089541666783536002364377728
10777488019700
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.16891099534501208896889472018011401453233051698777344462756506891555677396028
Short name T24
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.28 seconds
Started Nov 01 12:34:15 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 201056 kb
Host smart-9c07e364-8174-407b-bfd5-c014f4c83bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16891099534501208896889472018011401453233051698777344462756506891555677396028 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.16891099534501208896889472018011401453233051698777344462756506891555677396028
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.57821375608171292158994879853057959103968321582476060022677174563635091785976
Short name T100
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.47 seconds
Started Nov 01 12:34:12 PM PDT 23
Finished Nov 01 12:34:22 PM PDT 23
Peak memory 201016 kb
Host smart-80d32388-3845-4299-a65e-2fa4f2d3445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57821375608171292158994879853057959103968321582476060022677174563635091785976 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.57821375608171292158994879853057959103968321582476060
022677174563635091785976
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.30492648051893482052481647669490553454122767709914891099315576689745226972905
Short name T264
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.45 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:34 PM PDT 23
Peak memory 200928 kb
Host smart-c729c224-33e2-48ec-89b7-bece4120021a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30492648051893482052481647669490553454122767709914891099315576689745226972905 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.3049264805189348205248164766949055345412276770991489109931557
6689745226972905
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.76368393239206529175598890716580829294612629875056066505475092991386098149088
Short name T352
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.62 seconds
Started Nov 01 12:34:12 PM PDT 23
Finished Nov 01 12:34:34 PM PDT 23
Peak memory 201036 kb
Host smart-98357489-949c-44df-b326-fc1270a7c1bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76368393239206529175598890716580829294612629875056066505475092991386098149088 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.76368393239206529175598890716580829294612629875056066505475092991386098149088
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.19435729325049877467662711018269441819773325152515574123475756744456226149046
Short name T285
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:34:33 PM PDT 23
Peak memory 201172 kb
Host smart-9dec675b-5533-4d01-9742-3d7822b467d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19435729325049877467662711018269441819773325152515574123475756744456226149046 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.19435729325049877467662711018269441819773325152515574123475756744456226149046
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.89897409606901270594562047511737671099973502528737553883860665326823801411370
Short name T532
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Nov 01 12:33:58 PM PDT 23
Finished Nov 01 12:34:04 PM PDT 23
Peak memory 201004 kb
Host smart-3c456ec5-bd44-450e-b7ce-c8db4a15d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89897409606901270594562047511737671099973502528737553883860665326823801411370 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.89897409606901270594562047511737671099973502528737553883860665326823801411370
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.11987133753258985183622213203731438786832495291571400662288929057846296159337
Short name T486
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 01 12:34:10 PM PDT 23
Finished Nov 01 12:34:21 PM PDT 23
Peak memory 201196 kb
Host smart-34efdd36-748a-4cbd-bfec-03d8dfd42655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11987133753258985183622213203731438786832495291571400662288929057846296159337 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.11987133753258985183622213203731438786832495291571400662288929057846296159337
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.12350684762550800174997132184244343917457774040811444577008763925408883130710
Short name T542
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Nov 01 12:34:18 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 200920 kb
Host smart-ce423792-8b0e-4323-a763-76e07976cc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12350684762550800174997132184244343917457774040811444577008763925408883130710 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.12350684762550800174997132184244343917457774040811444577008763925408883130710
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.23119130085456715202660047183892349359647506680976605507349792227402962750420
Short name T163
Test name
Test status
Simulation time 42018621949 ps
CPU time 65.87 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:35:34 PM PDT 23
Peak memory 221420 kb
Host smart-17ac31cf-3413-4d47-8182-c24c986d266c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23119130085456715202660047183892349359647506680976605507349792227402962750420 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.23119130085456715202660047183892349359647506680976605507349792227402962750420
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.68495082701867121984467552951236345542039312977791322687780414222590107194386
Short name T184
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.9 seconds
Started Nov 01 12:34:10 PM PDT 23
Finished Nov 01 12:34:21 PM PDT 23
Peak memory 200964 kb
Host smart-9c0b72c4-75a8-4055-b807-60456a4978b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68495082701867121984467552951236345542039312977791322687780414222590107194386 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sysrst_ctrl_smoke.68495082701867121984467552951236345542039312977791322687780414222590107194386
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.94627523013460725801449052076796523215534784024361852355176492512937306942679
Short name T150
Test name
Test status
Simulation time 87228974549 ps
CPU time 138.8 seconds
Started Nov 01 12:34:18 PM PDT 23
Finished Nov 01 12:36:44 PM PDT 23
Peak memory 201252 kb
Host smart-1f132cfa-4e60-4fee-9042-6f6f45a94b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94627523013460725801449052076796523215534784024361852355176492512937306942679 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.94627523013460725801449052076796523215534784024361852355176492512937306942679
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.105539040465465035563061694481959697231859317732981189971473749358250388162158
Short name T130
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Nov 01 12:34:09 PM PDT 23
Finished Nov 01 12:34:18 PM PDT 23
Peak memory 201052 kb
Host smart-fe083a96-84ba-4e6b-90fd-c1dd2b269c6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105539040465465035563061694481959697231859317732981189971473749358250388162158 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.105539040465465035563061694481959697231859317732981189971473
749358250388162158
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.52934252098827852864740124712835636862008039767181217701347090963376301840147
Short name T248
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 01 12:36:39 PM PDT 23
Finished Nov 01 12:36:46 PM PDT 23
Peak memory 201012 kb
Host smart-52cf1a28-b45c-4f09-ada7-df58e17a5328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52934252098827852864740124712835636862008039767181217701347090963376301840147 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.52934252098827852864740124712835636862008039767181217701347090963376301840147
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.39834808006834820177623055603860572414086684388470971331912595875297419341073
Short name T233
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Nov 01 12:36:38 PM PDT 23
Finished Nov 01 12:36:47 PM PDT 23
Peak memory 201112 kb
Host smart-5af8eb5f-a23b-4a10-9353-6138ac1b09ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39834808006834820177623055603860572414086684388470971331912595875297419341073 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.39834808006834820177623055603860572414086684388470971331912595875297419341073
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.114170420834863492711897386074661327189935987821965745690557834450981110816856
Short name T262
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.83 seconds
Started Nov 01 12:36:43 PM PDT 23
Finished Nov 01 12:39:49 PM PDT 23
Peak memory 201340 kb
Host smart-fd5acea2-cd12-4669-8eb5-e66e01581dd5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114170420834863492711897386074661327189935987821965745690557834450981110816856 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.1141704208348634927118973860746613271899359878219657456905578
34450981110816856
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.53138157237459607385653733535933021195798012760002460028033081295637936209210
Short name T413
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.63 seconds
Started Nov 01 12:36:39 PM PDT 23
Finished Nov 01 12:36:50 PM PDT 23
Peak memory 201144 kb
Host smart-217e01ca-721b-4b1c-8d67-e6c0be8387dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53138157237459607385653733535933021195798012760002460028033081295637936209210 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.531381572374596073856537335359330211957980127600024600280330
81295637936209210
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.32533097494859000327692981427076995087117985904319342317800717306350798383001
Short name T627
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.17 seconds
Started Nov 01 12:36:43 PM PDT 23
Finished Nov 01 12:36:51 PM PDT 23
Peak memory 201068 kb
Host smart-03f434c6-1839-4562-8d2c-a44cccd35c14
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32533097494859000327692981427076995087117985904319342317800717306350798383001 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.3253309749485900032769298142707699508711798590431934231780071730
6350798383001
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.15153910363567055234088597368732387921007964528987003276066716554048812543885
Short name T572
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Nov 01 12:36:44 PM PDT 23
Finished Nov 01 12:36:50 PM PDT 23
Peak memory 201160 kb
Host smart-588dcae7-1a7d-4cef-9239-3bc75b5d0fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15153910363567055234088597368732387921007964528987003276066716554048812543885 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.15153910363567055234088597368732387921007964528987003276066716554048812543885
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.66267024017098183121294520130498981324737169702642627018731018061637238343924
Short name T441
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 01 12:36:38 PM PDT 23
Finished Nov 01 12:36:47 PM PDT 23
Peak memory 201204 kb
Host smart-ed24524e-7ed9-4472-8c54-e1898e96d120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66267024017098183121294520130498981324737169702642627018731018061637238343924 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.66267024017098183121294520130498981324737169702642627018731018061637238343924
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.50299377284230610923654643065826631579056114630935160526951851672806108538090
Short name T412
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Nov 01 12:36:36 PM PDT 23
Finished Nov 01 12:36:44 PM PDT 23
Peak memory 201124 kb
Host smart-565bc933-06e6-4975-afb3-bd960c0c2d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50299377284230610923654643065826631579056114630935160526951851672806108538090 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.50299377284230610923654643065826631579056114630935160526951851672806108538090
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.15588737607774889409088949646932481108266083231622825977737146325118004313915
Short name T511
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.67 seconds
Started Nov 01 12:36:41 PM PDT 23
Finished Nov 01 12:36:48 PM PDT 23
Peak memory 201036 kb
Host smart-85daf7c9-7144-4c51-af1a-6a5e14b1fdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15588737607774889409088949646932481108266083231622825977737146325118004313915 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.15588737607774889409088949646932481108266083231622825977737146325118004313915
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.79354210268462209435617381837801014144422049013190261857292574685302920765917
Short name T283
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.74 seconds
Started Nov 01 12:36:35 PM PDT 23
Finished Nov 01 12:36:39 PM PDT 23
Peak memory 200904 kb
Host smart-28aa19a9-c7f7-415e-8ba6-b049f9ff9970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79354210268462209435617381837801014144422049013190261857292574685302920765917 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sysrst_ctrl_smoke.79354210268462209435617381837801014144422049013190261857292574685302920765917
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.6424852494812704461559179522422049230788472259182048197782894879866995552712
Short name T335
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.29 seconds
Started Nov 01 12:36:56 PM PDT 23
Finished Nov 01 12:39:14 PM PDT 23
Peak memory 201316 kb
Host smart-642d2d75-6fd3-4113-b779-79f6d73f70dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6424852494812704461559179522422049230788472259182048197782894879866995552712 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.6424852494812704461559179522422049230788472259182048197782894879866995552712
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2351014310856559702306659440844157731369281671479525595665121025270766672574
Short name T21
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Nov 01 12:36:54 PM PDT 23
Finished Nov 01 12:36:59 PM PDT 23
Peak memory 200948 kb
Host smart-e0d109e2-cc66-4b2d-81e9-b05e2d19bc18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351014310856559702306659440844157731369281671479525595665121025270766672574 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.2351014310856559702306659440844157731369281671479525595665121
025270766672574
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.15083935202402134191565203786997729777199938841193924296300990965678787854190
Short name T664
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.73 seconds
Started Nov 01 12:36:26 PM PDT 23
Finished Nov 01 12:36:31 PM PDT 23
Peak memory 201116 kb
Host smart-68393f91-8f5b-4e6d-b7b7-558a6ac8bd54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15083935202402134191565203786997729777199938841193924296300990965678787854190 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.15083935202402134191565203786997729777199938841193924296300990965678787854190
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.99748109522331387308286449649515642044518002598797169909196053106562106612061
Short name T564
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 01 12:36:43 PM PDT 23
Finished Nov 01 12:36:50 PM PDT 23
Peak memory 201176 kb
Host smart-d5b3ae0e-2f5c-47fa-9cc4-4ac9a7e46080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99748109522331387308286449649515642044518002598797169909196053106562106612061 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.99748109522331387308286449649515642044518002598797169909196053106562106612061
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.29090766185719796187887721855458796086892161878788742480487855752411290134830
Short name T27
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.96 seconds
Started Nov 01 12:36:35 PM PDT 23
Finished Nov 01 12:39:39 PM PDT 23
Peak memory 201376 kb
Host smart-f668f0fa-0286-4b1c-8790-2fa330fb67c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29090766185719796187887721855458796086892161878788742480487855752411290134830 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.29090766185719796187887721855458796086892161878788742480487855
752411290134830
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.23401527961710071510793828479324628495270962398066981697218965253788517773070
Short name T133
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Nov 01 12:36:59 PM PDT 23
Finished Nov 01 12:37:07 PM PDT 23
Peak memory 201052 kb
Host smart-7dcd12a3-a3f7-4b7b-87b3-1727b1219dc3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23401527961710071510793828479324628495270962398066981697218965253788517773070 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.234015279617100715107938284793246284952709623980669816972189
65253788517773070
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.65305539977217561565473963958579698028270016014076991923176533852714801484862
Short name T650
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Nov 01 12:36:48 PM PDT 23
Finished Nov 01 12:36:55 PM PDT 23
Peak memory 201056 kb
Host smart-df7b2ce8-9287-4e5d-823f-90e3200de917
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65305539977217561565473963958579698028270016014076991923176533852714801484862 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.6530553997721756156547396395857969802827001601407699192317653385
2714801484862
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.97656213829950322814283450077347687208869286954747564058806687065705386712825
Short name T217
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.83 seconds
Started Nov 01 12:36:49 PM PDT 23
Finished Nov 01 12:36:55 PM PDT 23
Peak memory 201032 kb
Host smart-da023ff4-3a86-4c41-b1fb-a4b2fd9916fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97656213829950322814283450077347687208869286954747564058806687065705386712825 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.97656213829950322814283450077347687208869286954747564058806687065705386712825
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.99454160955924684064525770870899160250252177752919298765736949491042471761751
Short name T165
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.9 seconds
Started Nov 01 12:36:51 PM PDT 23
Finished Nov 01 12:36:57 PM PDT 23
Peak memory 201064 kb
Host smart-2f26db46-5ae3-4306-a0a4-b3ea2dfbcfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99454160955924684064525770870899160250252177752919298765736949491042471761751 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.99454160955924684064525770870899160250252177752919298765736949491042471761751
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.34020822901867746493757742875488801195555659609219283110385651433907142322547
Short name T496
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.84 seconds
Started Nov 01 12:36:49 PM PDT 23
Finished Nov 01 12:36:54 PM PDT 23
Peak memory 201148 kb
Host smart-b39873a9-a583-4f3e-b0f7-9a8d8415b5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34020822901867746493757742875488801195555659609219283110385651433907142322547 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.34020822901867746493757742875488801195555659609219283110385651433907142322547
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.46853755190730045110817918645818342828660881535035466308362543092442250461367
Short name T586
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.59 seconds
Started Nov 01 12:37:02 PM PDT 23
Finished Nov 01 12:37:08 PM PDT 23
Peak memory 201032 kb
Host smart-1fc90f0d-0c58-4db0-9563-361071270761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46853755190730045110817918645818342828660881535035466308362543092442250461367 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.46853755190730045110817918645818342828660881535035466308362543092442250461367
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.65693592177984235782247296404918736457849368796076472851370615506500519155947
Short name T408
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 01 12:36:38 PM PDT 23
Finished Nov 01 12:36:45 PM PDT 23
Peak memory 200968 kb
Host smart-afb7880d-e3ec-471f-9685-f82d9216c275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65693592177984235782247296404918736457849368796076472851370615506500519155947 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_smoke.65693592177984235782247296404918736457849368796076472851370615506500519155947
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.65324586232827703561922015205145835209202984466112921021204683793263415811496
Short name T141
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.48 seconds
Started Nov 01 12:36:30 PM PDT 23
Finished Nov 01 12:38:46 PM PDT 23
Peak memory 201312 kb
Host smart-c9afdcb4-a3e1-4d81-a880-93fee9ea5e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65324586232827703561922015205145835209202984466112921021204683793263415811496 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.65324586232827703561922015205145835209202984466112921021204683793263415811496
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.77351028463873008711885415880076982331530082294502902470640898428475378687825
Short name T131
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Nov 01 12:36:59 PM PDT 23
Finished Nov 01 12:37:05 PM PDT 23
Peak memory 201020 kb
Host smart-d260308a-7ca6-4840-861f-90ccd292b5ad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77351028463873008711885415880076982331530082294502902470640898428475378687825 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.773510284638730087118854158800769823315300822945029024706408
98428475378687825
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.293240020666088817225992194652030122696421914392409865760043225802281384938
Short name T181
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 01 12:36:44 PM PDT 23
Finished Nov 01 12:36:49 PM PDT 23
Peak memory 201172 kb
Host smart-0dc78ea3-607b-47b8-b41c-282ecaafe4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293240020666088817225992194652030122696421914392409865760043225802281384938 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.293240020666088817225992194652030122696421914392409865760043225802281384938
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.49514657859344030554515691386837854822654987387798629077649517354415843604015
Short name T485
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 01 12:36:36 PM PDT 23
Finished Nov 01 12:36:45 PM PDT 23
Peak memory 200636 kb
Host smart-710f21fa-fa8a-4a8d-b696-88aafc413e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49514657859344030554515691386837854822654987387798629077649517354415843604015 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.49514657859344030554515691386837854822654987387798629077649517354415843604015
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.73847242537524874971455029195608473621825691328952200947979100003029394117124
Short name T569
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.98 seconds
Started Nov 01 12:36:31 PM PDT 23
Finished Nov 01 12:39:34 PM PDT 23
Peak memory 201276 kb
Host smart-4090b789-7eff-43a5-8e5f-611881a5a224
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73847242537524874971455029195608473621825691328952200947979100003029394117124 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.73847242537524874971455029195608473621825691328952200947979100
003029394117124
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.38819667638051483091558070377681808683875235921784931939661921105110583911026
Short name T384
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.51 seconds
Started Nov 01 12:36:42 PM PDT 23
Finished Nov 01 12:36:51 PM PDT 23
Peak memory 201060 kb
Host smart-ab52cd11-d72f-4931-b42f-d6e5ea340c48
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38819667638051483091558070377681808683875235921784931939661921105110583911026 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.388196676380514830915580703776818086838752359217849319396619
21105110583911026
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.101898794480470641153406743041082301879474573093052005202273467167612867536255
Short name T453
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.18 seconds
Started Nov 01 12:36:32 PM PDT 23
Finished Nov 01 12:36:40 PM PDT 23
Peak memory 200996 kb
Host smart-61372c16-1856-4855-8726-be48131e9da7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101898794480470641153406743041082301879474573093052005202273467167612867536255 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.101898794480470641153406743041082301879474573093052005202273467
167612867536255
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.97369770480903824763749600573477776983418119497834395901638431131721465020333
Short name T258
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Nov 01 12:36:44 PM PDT 23
Finished Nov 01 12:36:50 PM PDT 23
Peak memory 201160 kb
Host smart-7dfe49bd-383e-47b7-bd2a-cd32ad8c50cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97369770480903824763749600573477776983418119497834395901638431131721465020333 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.97369770480903824763749600573477776983418119497834395901638431131721465020333
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.52063316968352734016623983637791565115094787440469971907017814644660915428934
Short name T388
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.84 seconds
Started Nov 01 12:36:28 PM PDT 23
Finished Nov 01 12:36:34 PM PDT 23
Peak memory 201056 kb
Host smart-f462a851-8525-48cf-acc1-e170aefdf7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52063316968352734016623983637791565115094787440469971907017814644660915428934 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.52063316968352734016623983637791565115094787440469971907017814644660915428934
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.58892177591501373008204060188822850246711060955321965625632548756663925245306
Short name T390
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.83 seconds
Started Nov 01 12:36:44 PM PDT 23
Finished Nov 01 12:36:49 PM PDT 23
Peak memory 201112 kb
Host smart-aa93e77d-7929-4979-9304-5526afe13185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58892177591501373008204060188822850246711060955321965625632548756663925245306 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.58892177591501373008204060188822850246711060955321965625632548756663925245306
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.44787138723989119775997855353466930419769808230252309911971491258485801228790
Short name T268
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.52 seconds
Started Nov 01 12:36:32 PM PDT 23
Finished Nov 01 12:36:38 PM PDT 23
Peak memory 201036 kb
Host smart-05436e46-5c67-4621-af81-1df0b08ead80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44787138723989119775997855353466930419769808230252309911971491258485801228790 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.44787138723989119775997855353466930419769808230252309911971491258485801228790
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.64700884259297562052592792589457883728120332287988915389742510499264470695239
Short name T433
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.94 seconds
Started Nov 01 12:36:31 PM PDT 23
Finished Nov 01 12:36:36 PM PDT 23
Peak memory 201004 kb
Host smart-c68b868e-7a08-420c-9969-5c3efd2ba597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64700884259297562052592792589457883728120332287988915389742510499264470695239 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sysrst_ctrl_smoke.64700884259297562052592792589457883728120332287988915389742510499264470695239
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.34772607979713991093191620654342506041578857328708943305110208380531638263703
Short name T336
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.38 seconds
Started Nov 01 12:36:41 PM PDT 23
Finished Nov 01 12:39:01 PM PDT 23
Peak memory 201328 kb
Host smart-8eb19bea-c316-475c-bc08-a25034d28f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34772607979713991093191620654342506041578857328708943305110208380531638263703 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.34772607979713991093191620654342506041578857328708943305110208380531638263703
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.42588320614656812387178129702745707973650175511004319491474050079175482989274
Short name T202
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 01 12:36:39 PM PDT 23
Finished Nov 01 12:36:47 PM PDT 23
Peak memory 201000 kb
Host smart-3f4b469b-7c08-4891-8bad-de8fe7ae4980
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42588320614656812387178129702745707973650175511004319491474050079175482989274 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.425883206146568123871781297027457079736501755110043194914740
50079175482989274
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.114167538793225444500237489344568238760421831312420461678387528717391345830137
Short name T523
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Nov 01 12:36:48 PM PDT 23
Finished Nov 01 12:36:53 PM PDT 23
Peak memory 201168 kb
Host smart-24cddf3f-1a93-4501-b91f-be96895b8a27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114167538793225444500237489344568238760421831312420461678387528717391345830137 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.114167538793225444500237489344568238760421831312420461678387528717391345830137
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.38299375694055371460583701312169679608492540894435055213195637488737820759446
Short name T110
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 01 12:36:44 PM PDT 23
Finished Nov 01 12:36:51 PM PDT 23
Peak memory 200996 kb
Host smart-f26994e5-a7e6-4120-a241-2efb9195b992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38299375694055371460583701312169679608492540894435055213195637488737820759446 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.38299375694055371460583701312169679608492540894435055213195637488737820759446
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.43466563293081416869178180936266154848859406842163080424525925881104115868474
Short name T432
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.52 seconds
Started Nov 01 12:36:49 PM PDT 23
Finished Nov 01 12:39:52 PM PDT 23
Peak memory 201280 kb
Host smart-f63ab62c-eb7d-465a-8903-240718421769
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43466563293081416869178180936266154848859406842163080424525925881104115868474 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.43466563293081416869178180936266154848859406842163080424525925
881104115868474
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.71512727104563068618785667098071711233195903422671117282358689032232435833268
Short name T608
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.63 seconds
Started Nov 01 12:36:43 PM PDT 23
Finished Nov 01 12:36:52 PM PDT 23
Peak memory 201064 kb
Host smart-3f7e34c8-13f5-48ab-ba0f-6c0d65694974
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71512727104563068618785667098071711233195903422671117282358689032232435833268 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.715127271045630686187856670980717112331959034226711172823586
89032232435833268
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.59569726923961546782175781632470651101447166332604902699747413171397238613223
Short name T253
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 01 12:36:44 PM PDT 23
Finished Nov 01 12:36:52 PM PDT 23
Peak memory 201008 kb
Host smart-5bc8040e-59f9-4773-bee8-64c86c997baa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59569726923961546782175781632470651101447166332604902699747413171397238613223 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.5956972692396154678217578163247065110144716633260490269974741317
1397238613223
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.44816553823172745402509534311053306915445262518913320428126366323819171217872
Short name T448
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 01 12:36:57 PM PDT 23
Finished Nov 01 12:37:03 PM PDT 23
Peak memory 201028 kb
Host smart-a1e715ab-a6e5-4af0-b1a5-76fa22aea828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44816553823172745402509534311053306915445262518913320428126366323819171217872 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.44816553823172745402509534311053306915445262518913320428126366323819171217872
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.75870191460527420402527603995233460413227487395484230851523802834865506819923
Short name T359
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.93 seconds
Started Nov 01 12:36:40 PM PDT 23
Finished Nov 01 12:36:48 PM PDT 23
Peak memory 201188 kb
Host smart-f97e61bd-9d09-488f-b5aa-10d1edc5664a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75870191460527420402527603995233460413227487395484230851523802834865506819923 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.75870191460527420402527603995233460413227487395484230851523802834865506819923
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.5864069179605041446443410869870305337883373908491581037882261893204312074616
Short name T589
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 01 12:36:42 PM PDT 23
Finished Nov 01 12:36:48 PM PDT 23
Peak memory 200928 kb
Host smart-05c20925-44d6-47b0-8078-a402fca7ed41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5864069179605041446443410869870305337883373908491581037882261893204312074616 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.5864069179605041446443410869870305337883373908491581037882261893204312074616
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.111220557567676797265940945222326859605027327569351382722576201658529017074256
Short name T127
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.81 seconds
Started Nov 01 12:36:42 PM PDT 23
Finished Nov 01 12:36:49 PM PDT 23
Peak memory 201024 kb
Host smart-5da5fec6-6378-4013-a06f-1403d15da827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111220557567676797265940945222326859605027327569351382722576201658529017074256 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.111220557567676797265940945222326859605027327569351382722576201658529017074256
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.26146581374646687469499846444564796495962028136798641179480058529453583069705
Short name T403
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Nov 01 12:36:39 PM PDT 23
Finished Nov 01 12:36:46 PM PDT 23
Peak memory 201064 kb
Host smart-cb66e14d-d001-4b99-964f-e7fa8b3f40d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26146581374646687469499846444564796495962028136798641179480058529453583069705 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_smoke.26146581374646687469499846444564796495962028136798641179480058529453583069705
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.56618461737297839056114345228057924447548179375340449903162081936793305076686
Short name T501
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.04 seconds
Started Nov 01 12:37:00 PM PDT 23
Finished Nov 01 12:39:18 PM PDT 23
Peak memory 201312 kb
Host smart-eabb732c-177e-4958-97e3-a990239bae1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56618461737297839056114345228057924447548179375340449903162081936793305076686 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.56618461737297839056114345228057924447548179375340449903162081936793305076686
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.24690809203459231131824485078090218817236650258020345724244741002774856122161
Short name T49
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 01 12:36:43 PM PDT 23
Finished Nov 01 12:36:49 PM PDT 23
Peak memory 200948 kb
Host smart-9640a31f-43cb-4ac1-83e8-35233999e33c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24690809203459231131824485078090218817236650258020345724244741002774856122161 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.246908092034592311318244850780902188172366502580203457242447
41002774856122161
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.53370930276672383385671175592529904316647299044351697991591407784249189043781
Short name T383
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 01 12:37:06 PM PDT 23
Finished Nov 01 12:37:10 PM PDT 23
Peak memory 201024 kb
Host smart-cb78b2ed-5631-4de8-a21e-8645ebd3885e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53370930276672383385671175592529904316647299044351697991591407784249189043781 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.53370930276672383385671175592529904316647299044351697991591407784249189043781
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.51609705729445973517599873185878867763138396218923775158802814388359943434496
Short name T443
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.46 seconds
Started Nov 01 12:36:49 PM PDT 23
Finished Nov 01 12:36:56 PM PDT 23
Peak memory 201004 kb
Host smart-ff315e25-d134-4f64-b434-caf1de634658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51609705729445973517599873185878867763138396218923775158802814388359943434496 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.51609705729445973517599873185878867763138396218923775158802814388359943434496
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.38866425586716713531117827829712162488232661072229342511368372340129825332705
Short name T215
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.97 seconds
Started Nov 01 12:36:52 PM PDT 23
Finished Nov 01 12:39:57 PM PDT 23
Peak memory 201248 kb
Host smart-ff4e664c-3c9d-49d6-8036-b712f9986197
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38866425586716713531117827829712162488232661072229342511368372340129825332705 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.38866425586716713531117827829712162488232661072229342511368372
340129825332705
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.63386492562788191640180596239759049330500706166559754162936956580728139231897
Short name T555
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.61 seconds
Started Nov 01 12:36:45 PM PDT 23
Finished Nov 01 12:36:54 PM PDT 23
Peak memory 201040 kb
Host smart-46389c5e-6160-4638-9fd1-0781ea3e59d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63386492562788191640180596239759049330500706166559754162936956580728139231897 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.633864925627881916401805962397590493305007061665597541629369
56580728139231897
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.82848600399635877260811742401738589520853048448490228416692533267772676668984
Short name T311
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.3 seconds
Started Nov 01 12:36:53 PM PDT 23
Finished Nov 01 12:37:01 PM PDT 23
Peak memory 201028 kb
Host smart-269b86eb-3ae2-4d0f-9c18-6032e157051f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82848600399635877260811742401738589520853048448490228416692533267772676668984 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.8284860039963587726081174240173858952085304844849022841669253326
7772676668984
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.115656075084992318339574916483514563041960385827790059103978011672794958109978
Short name T465
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.99 seconds
Started Nov 01 12:37:02 PM PDT 23
Finished Nov 01 12:37:08 PM PDT 23
Peak memory 200940 kb
Host smart-79114f1c-5a44-4233-9bd8-e6b68d0cee38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115656075084992318339574916483514563041960385827790059103978011672794958109978 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.115656075084992318339574916483514563041960385827790059103978011672794958109978
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.34986577681317279477700705690960656296151372339928963129750141296102686976633
Short name T580
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Nov 01 12:36:43 PM PDT 23
Finished Nov 01 12:36:50 PM PDT 23
Peak memory 201060 kb
Host smart-e01577d9-5990-4e22-994f-46c991906067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34986577681317279477700705690960656296151372339928963129750141296102686976633 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.34986577681317279477700705690960656296151372339928963129750141296102686976633
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.59635949256205705577152550329441842680785385825305732025567029725304952271974
Short name T458
Test name
Test status
Simulation time 2074566504 ps
CPU time 4.15 seconds
Started Nov 01 12:36:56 PM PDT 23
Finished Nov 01 12:37:02 PM PDT 23
Peak memory 200952 kb
Host smart-801c52ea-aeb7-479a-ba2f-9e051c2a697d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59635949256205705577152550329441842680785385825305732025567029725304952271974 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.59635949256205705577152550329441842680785385825305732025567029725304952271974
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.74941854949179126497393321808241893979485185642136956967558972115702293888329
Short name T143
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.56 seconds
Started Nov 01 12:36:50 PM PDT 23
Finished Nov 01 12:36:55 PM PDT 23
Peak memory 200992 kb
Host smart-8b9e3239-4b85-46c9-8ad0-0fb95f58d402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74941854949179126497393321808241893979485185642136956967558972115702293888329 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.74941854949179126497393321808241893979485185642136956967558972115702293888329
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.82161459082770796905742986742422582231937395414137932569781441078104472157782
Short name T663
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 01 12:36:39 PM PDT 23
Finished Nov 01 12:36:46 PM PDT 23
Peak memory 200976 kb
Host smart-fecc0132-3fd9-4806-8baa-cb030de1ad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82161459082770796905742986742422582231937395414137932569781441078104472157782 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sysrst_ctrl_smoke.82161459082770796905742986742422582231937395414137932569781441078104472157782
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.87216494792817645056225774908741549828762593958604015578802581351503120193031
Short name T151
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.16 seconds
Started Nov 01 12:36:52 PM PDT 23
Finished Nov 01 12:39:11 PM PDT 23
Peak memory 201212 kb
Host smart-d05d2c7c-470e-4174-b4ef-9cb9171a4aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87216494792817645056225774908741549828762593958604015578802581351503120193031 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.87216494792817645056225774908741549828762593958604015578802581351503120193031
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.92870633494460946685443733545386289935429400255365118135659675625687092627776
Short name T582
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.85 seconds
Started Nov 01 12:36:57 PM PDT 23
Finished Nov 01 12:37:03 PM PDT 23
Peak memory 200932 kb
Host smart-7ff15015-cc2a-4c25-b6e8-993be8409565
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92870633494460946685443733545386289935429400255365118135659675625687092627776 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.928706334944609466854437335453862899354294002553651181356596
75625687092627776
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.28247220369107173733002691477781410118659762116063543504977620186013960815555
Short name T221
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.68 seconds
Started Nov 01 12:37:15 PM PDT 23
Finished Nov 01 12:37:19 PM PDT 23
Peak memory 201032 kb
Host smart-8be5d66f-9e0a-4fda-9041-298dbbb7a628
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28247220369107173733002691477781410118659762116063543504977620186013960815555 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.28247220369107173733002691477781410118659762116063543504977620186013960815555
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.14968901789074128395930215658340188050165134490285881401172073658737189261209
Short name T505
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.48 seconds
Started Nov 01 12:37:14 PM PDT 23
Finished Nov 01 12:37:21 PM PDT 23
Peak memory 201112 kb
Host smart-66a335d7-722b-4b65-b79d-e471cda23fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14968901789074128395930215658340188050165134490285881401172073658737189261209 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.14968901789074128395930215658340188050165134490285881401172073658737189261209
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.75665259177751659945745274320752761306850601892339332231033777744306502895972
Short name T31
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.25 seconds
Started Nov 01 12:37:18 PM PDT 23
Finished Nov 01 12:40:24 PM PDT 23
Peak memory 201248 kb
Host smart-00f772a8-b577-4521-b0bb-237f1720fb53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75665259177751659945745274320752761306850601892339332231033777744306502895972 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.75665259177751659945745274320752761306850601892339332231033777
744306502895972
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.45976254916251415368853445071950955061279402116401888479387130211171649628801
Short name T643
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.49 seconds
Started Nov 01 12:37:21 PM PDT 23
Finished Nov 01 12:37:38 PM PDT 23
Peak memory 201072 kb
Host smart-e2992dd9-da06-4931-859c-ea19a2f70211
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45976254916251415368853445071950955061279402116401888479387130211171649628801 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.459762549162514153688534450719509550612794021164018884793871
30211171649628801
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.82599365503774753756040972091283555335082255770131861526733088925873577177222
Short name T272
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Nov 01 12:37:26 PM PDT 23
Finished Nov 01 12:37:37 PM PDT 23
Peak memory 201008 kb
Host smart-04abf2de-b322-40c3-a2b3-a19bab3068cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82599365503774753756040972091283555335082255770131861526733088925873577177222 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.8259936550377475375604097209128355533508225577013186152673308892
5873577177222
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.31288994292723374326501394935295905042481951508271292207997156894355466291931
Short name T539
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Nov 01 12:37:13 PM PDT 23
Finished Nov 01 12:37:19 PM PDT 23
Peak memory 201164 kb
Host smart-458bdbd6-2510-4371-8eff-101e361ef427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31288994292723374326501394935295905042481951508271292207997156894355466291931 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.31288994292723374326501394935295905042481951508271292207997156894355466291931
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.39417389360329090369191068657310905478728595669802540737225763181273481733330
Short name T653
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.75 seconds
Started Nov 01 12:37:11 PM PDT 23
Finished Nov 01 12:37:17 PM PDT 23
Peak memory 201112 kb
Host smart-d453a0bc-a822-4f3f-8308-b15bac83d11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39417389360329090369191068657310905478728595669802540737225763181273481733330 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.39417389360329090369191068657310905478728595669802540737225763181273481733330
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.87507266872670020245204519700066845425540857238594685861398353521024732053028
Short name T430
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 01 12:37:15 PM PDT 23
Finished Nov 01 12:37:20 PM PDT 23
Peak memory 201004 kb
Host smart-51c840c9-88c1-418e-882d-ff2b3bb68474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87507266872670020245204519700066845425540857238594685861398353521024732053028 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.87507266872670020245204519700066845425540857238594685861398353521024732053028
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.113516403965635569682784285005513058433863823814834650135422512877659469169477
Short name T245
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.53 seconds
Started Nov 01 12:37:16 PM PDT 23
Finished Nov 01 12:37:22 PM PDT 23
Peak memory 201012 kb
Host smart-e537b15b-6dbd-46af-8599-f703b5a1dfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113516403965635569682784285005513058433863823814834650135422512877659469169477 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.113516403965635569682784285005513058433863823814834650135422512877659469169477
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.74832050467214849424948897791190296257547356210492349391159763053277306351290
Short name T189
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 01 12:36:47 PM PDT 23
Finished Nov 01 12:36:52 PM PDT 23
Peak memory 200980 kb
Host smart-65c2b666-1b63-4a12-9304-5f93395fea4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74832050467214849424948897791190296257547356210492349391159763053277306351290 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_smoke.74832050467214849424948897791190296257547356210492349391159763053277306351290
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.109738941525361506509370191871389217892235972424487191047479407904755239260198
Short name T391
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.13 seconds
Started Nov 01 12:37:16 PM PDT 23
Finished Nov 01 12:39:32 PM PDT 23
Peak memory 201292 kb
Host smart-f6577654-592a-46e3-8967-a6731ef2ab45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109738941525361506509370191871389217892235972424487191047479407904755239260198 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.109738941525361506509370191871389217892235972424487191047479407904755239260198
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.10502025764680958302541341434145375741955121415435419598889122479138403413035
Short name T380
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.73 seconds
Started Nov 01 12:37:18 PM PDT 23
Finished Nov 01 12:37:25 PM PDT 23
Peak memory 201044 kb
Host smart-3f283dc7-4bdd-4ea2-9a09-aed1c3048a32
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502025764680958302541341434145375741955121415435419598889122479138403413035 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.105020257646809583025413414341453757419551214154354195988891
22479138403413035
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.35525219123734672928925290687940406486038417916222739491589507437636108540765
Short name T175
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 01 12:37:13 PM PDT 23
Finished Nov 01 12:37:18 PM PDT 23
Peak memory 201044 kb
Host smart-14ab3f3c-9bcb-47e8-aa3a-a5e32ccceeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35525219123734672928925290687940406486038417916222739491589507437636108540765 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.35525219123734672928925290687940406486038417916222739491589507437636108540765
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.2950971135772425615555790047232836466632888761932513390350424157550922462388
Short name T396
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 01 12:37:14 PM PDT 23
Finished Nov 01 12:37:20 PM PDT 23
Peak memory 201108 kb
Host smart-63befeb4-e7e5-4d35-93e5-49fd2a4aa1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950971135772425615555790047232836466632888761932513390350424157550922462388 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.2950971135772425615555790047232836466632888761932513390350424157550922462388
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.94785298605000733465968914139745506500226575570817404853550883735022800983994
Short name T256
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.39 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:40:25 PM PDT 23
Peak memory 201296 kb
Host smart-e6982ba2-105f-4722-9069-3f3c40c61cd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94785298605000733465968914139745506500226575570817404853550883735022800983994 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.94785298605000733465968914139745506500226575570817404853550883
735022800983994
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.53612899844214354699320966708236614513124880748508930759045983825196914292869
Short name T279
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.6 seconds
Started Nov 01 12:37:19 PM PDT 23
Finished Nov 01 12:37:30 PM PDT 23
Peak memory 201252 kb
Host smart-a4a37910-3427-4ec5-9dd4-f862473db61a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53612899844214354699320966708236614513124880748508930759045983825196914292869 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.536128998442143546993209667082366145131248807485089307590459
83825196914292869
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.17862293598557201302063374510710460179871213800923070118863141026174227124831
Short name T154
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Nov 01 12:37:12 PM PDT 23
Finished Nov 01 12:37:19 PM PDT 23
Peak memory 201168 kb
Host smart-fa36f98e-10b4-4615-9ed1-8fb5ae3ed080
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17862293598557201302063374510710460179871213800923070118863141026174227124831 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.1786229359855720130206337451071046017987121380092307011886314102
6174227124831
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.63191020741339894765929093538015189183089361293243689726502452491718527946094
Short name T375
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.71 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:37:28 PM PDT 23
Peak memory 201120 kb
Host smart-c324ff2b-f23d-439e-ac4e-72f971615027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63191020741339894765929093538015189183089361293243689726502452491718527946094 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.63191020741339894765929093538015189183089361293243689726502452491718527946094
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.32941689593172252646180894512286899900610750916289910672670945708005332029675
Short name T169
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 01 12:37:15 PM PDT 23
Finished Nov 01 12:37:21 PM PDT 23
Peak memory 201056 kb
Host smart-884d50c4-6299-400a-b26e-c59c19ad5c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32941689593172252646180894512286899900610750916289910672670945708005332029675 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.32941689593172252646180894512286899900610750916289910672670945708005332029675
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.91541924939306681440582774082963034083691270989983187533189530427893873035716
Short name T481
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.78 seconds
Started Nov 01 12:37:11 PM PDT 23
Finished Nov 01 12:37:16 PM PDT 23
Peak memory 201048 kb
Host smart-7078e46c-8800-49ef-a0ad-d8332a509aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91541924939306681440582774082963034083691270989983187533189530427893873035716 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.91541924939306681440582774082963034083691270989983187533189530427893873035716
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.45643260718814250952579767789972329129225825076343447259925056493177659331879
Short name T551
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.66 seconds
Started Nov 01 12:37:13 PM PDT 23
Finished Nov 01 12:37:19 PM PDT 23
Peak memory 201060 kb
Host smart-76f7e34a-4583-464c-8e21-b6a630753401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45643260718814250952579767789972329129225825076343447259925056493177659331879 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.45643260718814250952579767789972329129225825076343447259925056493177659331879
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.29244821183686191432643608091134269395368674004598432169005234869801250082530
Short name T490
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.74 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:37:27 PM PDT 23
Peak memory 200980 kb
Host smart-60efa933-c36b-4fa6-9753-dfc89e480475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29244821183686191432643608091134269395368674004598432169005234869801250082530 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sysrst_ctrl_smoke.29244821183686191432643608091134269395368674004598432169005234869801250082530
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.66754887486759491920910882454412672394952276613046870220081870887367578567671
Short name T602
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.21 seconds
Started Nov 01 12:37:17 PM PDT 23
Finished Nov 01 12:39:34 PM PDT 23
Peak memory 201316 kb
Host smart-14166496-d7c3-412e-b16f-80df7cb5467c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66754887486759491920910882454412672394952276613046870220081870887367578567671 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.66754887486759491920910882454412672394952276613046870220081870887367578567671
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.76839168196448165165977706419076558106912336896954502501859332833312745548947
Short name T576
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Nov 01 12:37:09 PM PDT 23
Finished Nov 01 12:37:15 PM PDT 23
Peak memory 201152 kb
Host smart-1f5face6-9736-440c-bb79-2c650d3b8a69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76839168196448165165977706419076558106912336896954502501859332833312745548947 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.768391681964481651659777064190765581069123368969545025018593
32833312745548947
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.28402370298608899545681218848465335502851589876191774803876906873146535987704
Short name T329
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.78 seconds
Started Nov 01 12:37:17 PM PDT 23
Finished Nov 01 12:37:23 PM PDT 23
Peak memory 201024 kb
Host smart-cc7fb7d2-6998-4d4d-b165-c8ab131b9d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28402370298608899545681218848465335502851589876191774803876906873146535987704 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.28402370298608899545681218848465335502851589876191774803876906873146535987704
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.33600386294219467204252902133363641227568729799142997343823301928144068514214
Short name T109
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.37 seconds
Started Nov 01 12:37:11 PM PDT 23
Finished Nov 01 12:37:18 PM PDT 23
Peak memory 201080 kb
Host smart-76ba107a-c669-4098-b7ea-7dfb1b592268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33600386294219467204252902133363641227568729799142997343823301928144068514214 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.33600386294219467204252902133363641227568729799142997343823301928144068514214
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.42084944159670609935341130005068558190965353365249219151677520800766180766111
Short name T210
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.31 seconds
Started Nov 01 12:37:13 PM PDT 23
Finished Nov 01 12:40:15 PM PDT 23
Peak memory 201236 kb
Host smart-d6441266-f916-4e1c-af1e-9d880bf45f1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42084944159670609935341130005068558190965353365249219151677520800766180766111 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.42084944159670609935341130005068558190965353365249219151677520
800766180766111
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.113794188693561531713376496051013986389540179216326160149215160997847813128621
Short name T168
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.38 seconds
Started Nov 01 12:37:14 PM PDT 23
Finished Nov 01 12:37:23 PM PDT 23
Peak memory 201012 kb
Host smart-276e2e24-6c85-4d59-bfb3-aa3a7831d8d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113794188693561531713376496051013986389540179216326160149215160997847813128621 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.11379418869356153171337649605101398638954017921632616014921
5160997847813128621
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.41411078581186521881072502250347399133107580889683612847668589659909739826303
Short name T506
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Nov 01 12:37:19 PM PDT 23
Finished Nov 01 12:37:37 PM PDT 23
Peak memory 201028 kb
Host smart-cc9e1ca4-d088-488d-909f-bd0225ac2daf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41411078581186521881072502250347399133107580889683612847668589659909739826303 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.4141107858118652188107250225034739913310758088968361284766858965
9909739826303
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.104418541169594907586578636873001566493203031035067766076401452784141149845771
Short name T675
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 01 12:37:12 PM PDT 23
Finished Nov 01 12:37:18 PM PDT 23
Peak memory 201048 kb
Host smart-4073996e-b9c0-4415-9ce2-223726a0c41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104418541169594907586578636873001566493203031035067766076401452784141149845771 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.104418541169594907586578636873001566493203031035067766076401452784141149845771
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.17061465299105766815626170933431070142376010783092892125389168304439036813417
Short name T493
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.94 seconds
Started Nov 01 12:37:22 PM PDT 23
Finished Nov 01 12:37:33 PM PDT 23
Peak memory 201000 kb
Host smart-d3e2ab86-9bd4-4b81-9e19-b6c8a940f244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17061465299105766815626170933431070142376010783092892125389168304439036813417 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.17061465299105766815626170933431070142376010783092892125389168304439036813417
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.21846777283592432647714066373843964412235144475812214692649916935786308312198
Short name T230
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 01 12:37:13 PM PDT 23
Finished Nov 01 12:37:18 PM PDT 23
Peak memory 201008 kb
Host smart-90efca07-4b3a-4257-b620-ad5b7620fad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21846777283592432647714066373843964412235144475812214692649916935786308312198 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.21846777283592432647714066373843964412235144475812214692649916935786308312198
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.31659751149073086405091163770788124194003640485640391099304159759422134603259
Short name T548
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.92 seconds
Started Nov 01 12:37:15 PM PDT 23
Finished Nov 01 12:37:21 PM PDT 23
Peak memory 201048 kb
Host smart-5d0bd0a6-05ec-49b2-bbea-a882ef46ce0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31659751149073086405091163770788124194003640485640391099304159759422134603259 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.31659751149073086405091163770788124194003640485640391099304159759422134603259
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.66934580791789789542787057799239280955056712072519538368402177336587232713295
Short name T394
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 01 12:37:16 PM PDT 23
Finished Nov 01 12:37:21 PM PDT 23
Peak memory 201088 kb
Host smart-6442fc2e-5404-4ef9-a645-95a07a9f8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66934580791789789542787057799239280955056712072519538368402177336587232713295 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_smoke.66934580791789789542787057799239280955056712072519538368402177336587232713295
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.65095402368595052422814251939248985399777711723493428752258692990168205167715
Short name T524
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.57 seconds
Started Nov 01 12:37:14 PM PDT 23
Finished Nov 01 12:39:32 PM PDT 23
Peak memory 201656 kb
Host smart-ca255416-4bbb-48c0-8052-0efee2ede7db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65095402368595052422814251939248985399777711723493428752258692990168205167715 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.65095402368595052422814251939248985399777711723493428752258692990168205167715
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.104619244448647009372213910585008150552643924004731109193585441408266232468974
Short name T343
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.64 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:37:27 PM PDT 23
Peak memory 201056 kb
Host smart-1c584a44-a32f-4a2e-b79d-0a50edb173fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104619244448647009372213910585008150552643924004731109193585441408266232468974 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.10461924444864700937221391058500815055264392400473110919358
5441408266232468974
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.65973129200818453664923305972440771069930650349399442736403312882157183575004
Short name T135
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.77 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:37:27 PM PDT 23
Peak memory 201020 kb
Host smart-2dd208e5-a3ac-4431-b0d2-f4d4ad67d923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65973129200818453664923305972440771069930650349399442736403312882157183575004 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.65973129200818453664923305972440771069930650349399442736403312882157183575004
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.35016524151984967651795507918525965779488527507283374306178242589418999848371
Short name T105
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:37:29 PM PDT 23
Peak memory 201088 kb
Host smart-6960d0b7-6197-4b5d-a492-05eab6c375bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35016524151984967651795507918525965779488527507283374306178242589418999848371 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.35016524151984967651795507918525965779488527507283374306178242589418999848371
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.24436782347916967090818672645349634824064275393550771383260050534581299754351
Short name T563
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.35 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:40:25 PM PDT 23
Peak memory 201256 kb
Host smart-11fa9fcf-a34a-44e8-9373-2a587964ae5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24436782347916967090818672645349634824064275393550771383260050534581299754351 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.24436782347916967090818672645349634824064275393550771383260050
534581299754351
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.47608684590644500905890111288751467717356896129306028674399690324545205017033
Short name T599
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.32 seconds
Started Nov 01 12:37:13 PM PDT 23
Finished Nov 01 12:37:22 PM PDT 23
Peak memory 201072 kb
Host smart-dd4f3654-a695-425a-8704-704e8cd8419b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47608684590644500905890111288751467717356896129306028674399690324545205017033 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.476086845906445009058901112887514677173568961293060286743996
90324545205017033
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.40535584902462186189336942468776531121251393444056748720037919570680840781954
Short name T623
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.37 seconds
Started Nov 01 12:37:19 PM PDT 23
Finished Nov 01 12:37:29 PM PDT 23
Peak memory 201160 kb
Host smart-658f9058-7353-4118-ba2d-4c58a4ce7065
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40535584902462186189336942468776531121251393444056748720037919570680840781954 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.4053558490246218618933694246877653112125139344405674872003791957
0680840781954
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.70362280971981363951282744603915717578930588869424313173227244128461188187875
Short name T626
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.72 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:37:27 PM PDT 23
Peak memory 201024 kb
Host smart-8e643e17-0099-4a75-a489-3bb12bb4fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70362280971981363951282744603915717578930588869424313173227244128461188187875 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.70362280971981363951282744603915717578930588869424313173227244128461188187875
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.84173324978852391335187360428823586293867252141600942868640946444029561908250
Short name T234
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Nov 01 12:37:16 PM PDT 23
Finished Nov 01 12:37:23 PM PDT 23
Peak memory 201068 kb
Host smart-73d53a37-1ecf-4713-876c-3b5119e5aa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84173324978852391335187360428823586293867252141600942868640946444029561908250 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.84173324978852391335187360428823586293867252141600942868640946444029561908250
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.32663664667166327288585210525170722585639259375206595355528190686051587500641
Short name T364
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 01 12:37:14 PM PDT 23
Finished Nov 01 12:37:19 PM PDT 23
Peak memory 201016 kb
Host smart-038fc417-e4bc-49b5-89cb-547644964058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32663664667166327288585210525170722585639259375206595355528190686051587500641 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.32663664667166327288585210525170722585639259375206595355528190686051587500641
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.98770203184676982255091770719155660257082497132126214706773019948083980707589
Short name T562
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.45 seconds
Started Nov 01 12:37:12 PM PDT 23
Finished Nov 01 12:37:18 PM PDT 23
Peak memory 201032 kb
Host smart-6f6b9b59-094a-4a1c-90c2-d7e649f4f584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98770203184676982255091770719155660257082497132126214706773019948083980707589 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.98770203184676982255091770719155660257082497132126214706773019948083980707589
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.63764826818910504278394233742183926295986348571411746764063046503575090890813
Short name T188
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Nov 01 12:37:18 PM PDT 23
Finished Nov 01 12:37:24 PM PDT 23
Peak memory 200944 kb
Host smart-26f17e47-b898-47d6-8ec0-e4224daf7e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63764826818910504278394233742183926295986348571411746764063046503575090890813 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_smoke.63764826818910504278394233742183926295986348571411746764063046503575090890813
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.47667292105411124327483582480470646857963011711131952807760961362486094096077
Short name T148
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.02 seconds
Started Nov 01 12:37:13 PM PDT 23
Finished Nov 01 12:39:30 PM PDT 23
Peak memory 201376 kb
Host smart-ef4f0c8c-24b2-4412-8900-6025b0456f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47667292105411124327483582480470646857963011711131952807760961362486094096077 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.47667292105411124327483582480470646857963011711131952807760961362486094096077
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.58987345726018669272916321792004079988870503064124881198075630133671374213486
Short name T46
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 01 12:37:19 PM PDT 23
Finished Nov 01 12:37:27 PM PDT 23
Peak memory 201160 kb
Host smart-ef7c4d67-751f-4a77-8c4a-e8f66ede73f9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58987345726018669272916321792004079988870503064124881198075630133671374213486 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.589873457260186692729163217920040799888705030641248811980756
30133671374213486
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.175444118643110165106024513892097894558614758505839257551934699544468298802
Short name T592
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Nov 01 12:37:19 PM PDT 23
Finished Nov 01 12:37:26 PM PDT 23
Peak memory 201240 kb
Host smart-07b90521-f278-48e6-9b58-168d26461c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175444118643110165106024513892097894558614758505839257551934699544468298802 -assert nopostproc
+UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.175444118643110165106024513892097894558614758505839257551934699544468298802
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.20336862124691696105316827050609456530300577671072506613313497797579837765239
Short name T298
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.67 seconds
Started Nov 01 12:37:15 PM PDT 23
Finished Nov 01 12:37:22 PM PDT 23
Peak memory 201112 kb
Host smart-0b2f3b60-8b91-4c11-9131-ff8061d2805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20336862124691696105316827050609456530300577671072506613313497797579837765239 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.20336862124691696105316827050609456530300577671072506613313497797579837765239
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.75831234352132647671960149148866844613635014474047965403755998846256295492465
Short name T319
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.56 seconds
Started Nov 01 12:37:19 PM PDT 23
Finished Nov 01 12:40:24 PM PDT 23
Peak memory 201280 kb
Host smart-a2912632-a67a-4e9a-bc2c-0749780ac1fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75831234352132647671960149148866844613635014474047965403755998846256295492465 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.75831234352132647671960149148866844613635014474047965403755998
846256295492465
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.111822396713415797704822851373323828707411453678160227713460459139920457726970
Short name T461
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.49 seconds
Started Nov 01 12:37:15 PM PDT 23
Finished Nov 01 12:37:24 PM PDT 23
Peak memory 201052 kb
Host smart-52cdfbf2-46c6-49c2-b28b-e577ce53eb89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111822396713415797704822851373323828707411453678160227713460459139920457726970 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.11182239671341579770482285137332382870741145367816022771346
0459139920457726970
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.12654477466833319237545414141618182178473921514633289679089521510318921349015
Short name T32
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.24 seconds
Started Nov 01 12:37:17 PM PDT 23
Finished Nov 01 12:37:25 PM PDT 23
Peak memory 201056 kb
Host smart-b8eb4167-8acd-4582-8f2c-eb278ad61d50
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654477466833319237545414141618182178473921514633289679089521510318921349015 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.1265447746683331923754541414161818217847392151463328967908952151
0318921349015
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.45540362175756280806036944428124912393165384874635065037725474528433697371776
Short name T247
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 01 12:37:16 PM PDT 23
Finished Nov 01 12:37:22 PM PDT 23
Peak memory 201028 kb
Host smart-a11016ed-c50b-4a10-962d-f575c1f55c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45540362175756280806036944428124912393165384874635065037725474528433697371776 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.45540362175756280806036944428124912393165384874635065037725474528433697371776
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.37930035035513375367435412687477921159658673928112457584148411510925611231132
Short name T588
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.87 seconds
Started Nov 01 12:37:14 PM PDT 23
Finished Nov 01 12:37:20 PM PDT 23
Peak memory 201204 kb
Host smart-838e9d2b-7617-4bbb-8575-7e846cfded21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37930035035513375367435412687477921159658673928112457584148411510925611231132 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.37930035035513375367435412687477921159658673928112457584148411510925611231132
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.68036907271107711800666969839306736787475259145901054091343206277631037027686
Short name T195
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.83 seconds
Started Nov 01 12:37:17 PM PDT 23
Finished Nov 01 12:37:23 PM PDT 23
Peak memory 201016 kb
Host smart-fbdd5c4d-65f9-42a0-bb90-984160bd3497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68036907271107711800666969839306736787475259145901054091343206277631037027686 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.68036907271107711800666969839306736787475259145901054091343206277631037027686
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.95556857797255140441247226686986222060038558572208603046270388099184279048690
Short name T261
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.5 seconds
Started Nov 01 12:37:14 PM PDT 23
Finished Nov 01 12:37:20 PM PDT 23
Peak memory 201172 kb
Host smart-b231444f-79a9-4a65-b5eb-de8f2898a89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95556857797255140441247226686986222060038558572208603046270388099184279048690 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.95556857797255140441247226686986222060038558572208603046270388099184279048690
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.20819741700676173863787682378527909152911713725704352597080102669068402023907
Short name T197
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.84 seconds
Started Nov 01 12:37:22 PM PDT 23
Finished Nov 01 12:37:34 PM PDT 23
Peak memory 200948 kb
Host smart-cccf3973-5862-47ce-807c-fe1b76a12360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20819741700676173863787682378527909152911713725704352597080102669068402023907 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sysrst_ctrl_smoke.20819741700676173863787682378527909152911713725704352597080102669068402023907
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.18018743419585979861251064599542406326845499480258458137554754748475537978525
Short name T543
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.62 seconds
Started Nov 01 12:37:20 PM PDT 23
Finished Nov 01 12:39:39 PM PDT 23
Peak memory 201332 kb
Host smart-0a5bb2ee-091d-467f-9141-f8f454de8a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18018743419585979861251064599542406326845499480258458137554754748475537978525 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.18018743419585979861251064599542406326845499480258458137554754748475537978525
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.96505971248670655410710169067777509679818656053595455402394682250084094203565
Short name T385
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Nov 01 12:37:16 PM PDT 23
Finished Nov 01 12:37:22 PM PDT 23
Peak memory 201040 kb
Host smart-435b8e6f-9180-4696-a1ca-21f4fe287bc8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96505971248670655410710169067777509679818656053595455402394682250084094203565 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.965059712486706554107101690677775096798186560535954554023946
82250084094203565
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.104979309142008126290663424824921714511688180209413342122871903504491730684116
Short name T187
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 01 12:34:34 PM PDT 23
Finished Nov 01 12:34:41 PM PDT 23
Peak memory 201052 kb
Host smart-530c1700-377e-4a8a-bc6e-11123a60be78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104979309142008126290663424824921714511688180209413342122871903504491730684116 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.104979309142008126290663424824921714511688180209413342122871903504491730684116
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.74728029783614207654893229966928971883360469714846672502475778698459325725244
Short name T237
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 01 12:34:24 PM PDT 23
Finished Nov 01 12:34:34 PM PDT 23
Peak memory 200996 kb
Host smart-6d230b88-994e-4880-a7f6-8768c4ed39ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74728029783614207654893229966928971883360469714846672502475778698459325725244 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.74728029783614207654893229966928971883360469714846672502475778698459325725244
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.63931952671694979258717179535868812431461191625331646554608695933829066575175
Short name T641
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.24 seconds
Started Nov 01 12:34:41 PM PDT 23
Finished Nov 01 12:37:49 PM PDT 23
Peak memory 201416 kb
Host smart-d1fd296c-d0be-48d7-ab1a-64ff16a88d1e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63931952671694979258717179535868812431461191625331646554608695933829066575175 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.639319526716949792587171795358688124314611916253316465546086959
33829066575175
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.67440313124000491549950443524683444741508493273517942289541969318210883452504
Short name T446
Test name
Test status
Simulation time 2398742482 ps
CPU time 4.84 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:27 PM PDT 23
Peak memory 201132 kb
Host smart-00c5fb1f-e46d-44e7-b98f-ac4e41491b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67440313124000491549950443524683444741508493273517942289541969318210883452504 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.67440313124000491549950443524683444741508493273517942289541969318210883452504
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.16177011713568220769106771226944060392140275319754426238033772505294219065882
Short name T129
Test name
Test status
Simulation time 2534562824 ps
CPU time 4.52 seconds
Started Nov 01 12:34:17 PM PDT 23
Finished Nov 01 12:34:26 PM PDT 23
Peak memory 201012 kb
Host smart-5f429402-4129-4a6c-bd57-1d374968bff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16177011713568220769106771226944060392140275319754426238033772505294219065882 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.16177011713568220769106771226944060392140275319754426
238033772505294219065882
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.33155950779189795255485811514965598392473163305773082710810069156475596966139
Short name T338
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.68 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:34:35 PM PDT 23
Peak memory 201196 kb
Host smart-2bd83508-5ca9-4668-b5e9-a9f8c14cbc68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33155950779189795255485811514965598392473163305773082710810069156475596966139 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.3315595077918979525548581151496559839247316330577308271081006
9156475596966139
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.77437596633363273620497543203388034349863914914412061247921329323801815437688
Short name T637
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Nov 01 12:34:37 PM PDT 23
Finished Nov 01 12:34:47 PM PDT 23
Peak memory 201152 kb
Host smart-b55fbfd6-3d45-4614-8ae5-cbb15d3feb8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77437596633363273620497543203388034349863914914412061247921329323801815437688 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.77437596633363273620497543203388034349863914914412061247921329323801815437688
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.69694801665039098329062834845975098595619088735539553657946809559528298748569
Short name T537
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Nov 01 12:34:18 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 201144 kb
Host smart-69b1b7f9-3644-44f7-883f-f3ce9f5d3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69694801665039098329062834845975098595619088735539553657946809559528298748569 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.69694801665039098329062834845975098595619088735539553657946809559528298748569
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.63468493758572628564518759445115974308474634559394150092456719388756098358954
Short name T636
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Nov 01 12:34:24 PM PDT 23
Finished Nov 01 12:34:34 PM PDT 23
Peak memory 201176 kb
Host smart-8c2874f8-59b1-485b-8800-2e0ff5788574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63468493758572628564518759445115974308474634559394150092456719388756098358954 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.63468493758572628564518759445115974308474634559394150092456719388756098358954
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.33521956171934896256153011335601088514884586628276413528337312903319358028661
Short name T282
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 01 12:34:19 PM PDT 23
Finished Nov 01 12:34:30 PM PDT 23
Peak memory 201012 kb
Host smart-ea275608-ac37-42cd-b7de-fe71b39b3a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33521956171934896256153011335601088514884586628276413528337312903319358028661 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.33521956171934896256153011335601088514884586628276413528337312903319358028661
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.35058005934730086674198166662238266126955008144742714684828698132884698377814
Short name T222
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.8 seconds
Started Nov 01 12:34:21 PM PDT 23
Finished Nov 01 12:34:33 PM PDT 23
Peak memory 201152 kb
Host smart-1b2f07e7-f7ea-4b07-8727-42c7b0b34433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35058005934730086674198166662238266126955008144742714684828698132884698377814 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.35058005934730086674198166662238266126955008144742714684828698132884698377814
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.28661966876613182556387448972347908000796996442164347871065786956136323854579
Short name T159
Test name
Test status
Simulation time 42018621949 ps
CPU time 64.83 seconds
Started Nov 01 12:34:03 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 221408 kb
Host smart-34f71beb-e09a-4c70-a85b-d3f8d73fe8b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28661966876613182556387448972347908000796996442164347871065786956136323854579 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.28661966876613182556387448972347908000796996442164347871065786956136323854579
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.89479686196647593730437113916839434047397366623972653384028877623051426843371
Short name T224
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.82 seconds
Started Nov 01 12:34:20 PM PDT 23
Finished Nov 01 12:34:31 PM PDT 23
Peak memory 201076 kb
Host smart-43f27a27-0b20-4621-9f09-324d0d7766ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89479686196647593730437113916839434047397366623972653384028877623051426843371 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_smoke.89479686196647593730437113916839434047397366623972653384028877623051426843371
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.61535857579640961970043414093521894751090912228186565849534162060018788309868
Short name T305
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.43 seconds
Started Nov 01 12:34:25 PM PDT 23
Finished Nov 01 12:36:45 PM PDT 23
Peak memory 201316 kb
Host smart-693a37fe-51c1-4165-9b8f-0f3f9edde693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61535857579640961970043414093521894751090912228186565849534162060018788309868 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.61535857579640961970043414093521894751090912228186565849534162060018788309868
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.77485692064177467854757863818635192610981520202478097038203614479276043865067
Short name T585
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.75 seconds
Started Nov 01 12:34:20 PM PDT 23
Finished Nov 01 12:34:32 PM PDT 23
Peak memory 201128 kb
Host smart-c00c3057-f418-4ebd-b297-bb6b6dc15bd4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77485692064177467854757863818635192610981520202478097038203614479276043865067 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.7748569206417746785475786381863519261098152020247809703820361
4479276043865067
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.87556136064303612721261754451451657465452409714957039453333020359668211091351
Short name T410
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.61 seconds
Started Nov 01 12:37:41 PM PDT 23
Finished Nov 01 12:37:52 PM PDT 23
Peak memory 201076 kb
Host smart-44254fb0-cba0-43d1-89f2-17fe9fc1e985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87556136064303612721261754451451657465452409714957039453333020359668211091351 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.87556136064303612721261754451451657465452409714957039453333020359668211091351
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4784011524034201039083987939035495317594717440144976784992139036066015432321
Short name T559
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Nov 01 12:37:42 PM PDT 23
Finished Nov 01 12:37:58 PM PDT 23
Peak memory 201088 kb
Host smart-0f5ff16e-0d45-4c7e-a92b-db1d915efc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4784011524034201039083987939035495317594717440144976784992139036066015432321 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.4784011524034201039083987939035495317594717440144976784992139036066015432321
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.28367698377801628846006911785767493005914144960462075170872720247672577923593
Short name T317
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.54 seconds
Started Nov 01 12:37:44 PM PDT 23
Finished Nov 01 12:40:57 PM PDT 23
Peak memory 201376 kb
Host smart-0bec5fdf-a7b8-4ba1-9a97-b06e7a50bb2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28367698377801628846006911785767493005914144960462075170872720247672577923593 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.28367698377801628846006911785767493005914144960462075170872720
247672577923593
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.41715691813610075084631790382315132397334317976374261673485782560724328749275
Short name T196
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.43 seconds
Started Nov 01 12:37:36 PM PDT 23
Finished Nov 01 12:37:46 PM PDT 23
Peak memory 201092 kb
Host smart-21c402dd-676f-4ad0-97cf-a0fc2c7d180f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41715691813610075084631790382315132397334317976374261673485782560724328749275 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.417156918136100750846317903823151323973343179763742616734857
82560724328749275
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.107551695990026037845853493863607054858333011811465674203126596809238757906502
Short name T566
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.2 seconds
Started Nov 01 12:37:49 PM PDT 23
Finished Nov 01 12:38:02 PM PDT 23
Peak memory 201156 kb
Host smart-397dea84-43df-4182-bbc5-1ee2a47d9eaf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107551695990026037845853493863607054858333011811465674203126596809238757906502 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.107551695990026037845853493863607054858333011811465674203126596
809238757906502
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.76226718318149737133144405476673137531279127728541554416637992301031359571697
Short name T631
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Nov 01 12:37:34 PM PDT 23
Finished Nov 01 12:37:41 PM PDT 23
Peak memory 201028 kb
Host smart-4fa632de-648c-4213-b4ed-6d56769dc0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76226718318149737133144405476673137531279127728541554416637992301031359571697 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.76226718318149737133144405476673137531279127728541554416637992301031359571697
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.93944598232687056489852247669056972421721261538029917092163952119512956481645
Short name T402
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.93 seconds
Started Nov 01 12:37:17 PM PDT 23
Finished Nov 01 12:37:24 PM PDT 23
Peak memory 201068 kb
Host smart-d41c0e82-bf18-405a-875d-b892e61e82f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93944598232687056489852247669056972421721261538029917092163952119512956481645 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.93944598232687056489852247669056972421721261538029917092163952119512956481645
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.97901273894850942884782799393908648618563936508385789425801611405812312282419
Short name T201
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 01 12:37:35 PM PDT 23
Finished Nov 01 12:37:40 PM PDT 23
Peak memory 201016 kb
Host smart-3524cd90-09c8-413e-99a1-38016fbb9ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97901273894850942884782799393908648618563936508385789425801611405812312282419 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.97901273894850942884782799393908648618563936508385789425801611405812312282419
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.55698684146375498821863402720583840548671263569814460332731116805391160062440
Short name T615
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.79 seconds
Started Nov 01 12:37:44 PM PDT 23
Finished Nov 01 12:37:57 PM PDT 23
Peak memory 201024 kb
Host smart-92819d90-214c-4419-aa21-b9ad98b93e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55698684146375498821863402720583840548671263569814460332731116805391160062440 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.55698684146375498821863402720583840548671263569814460332731116805391160062440
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.55850560637525081769182355686159222965591052636468077057259019062183649195312
Short name T310
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.74 seconds
Started Nov 01 12:37:24 PM PDT 23
Finished Nov 01 12:37:35 PM PDT 23
Peak memory 200908 kb
Host smart-6b170425-ba0e-413b-b529-936506d9b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55850560637525081769182355686159222965591052636468077057259019062183649195312 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sysrst_ctrl_smoke.55850560637525081769182355686159222965591052636468077057259019062183649195312
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.93830169117524460601976189425214085865500123508551639614942103596210355555961
Short name T661
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.4 seconds
Started Nov 01 12:37:46 PM PDT 23
Finished Nov 01 12:40:10 PM PDT 23
Peak memory 201444 kb
Host smart-9509ef19-08f5-4d8c-8402-044c3442293a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93830169117524460601976189425214085865500123508551639614942103596210355555961 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.93830169117524460601976189425214085865500123508551639614942103596210355555961
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.87863811523978768064500668237150187930534874284735335327593670913371910684355
Short name T662
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.74 seconds
Started Nov 01 12:37:40 PM PDT 23
Finished Nov 01 12:37:52 PM PDT 23
Peak memory 201040 kb
Host smart-c0ea8fbb-cfd8-407f-8da5-82d414b14d54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87863811523978768064500668237150187930534874284735335327593670913371910684355 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.878638115239787680645006682371501879305348742847353353275936
70913371910684355
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.26166742597818656441928564893892096751552541730453443623055743693651359409358
Short name T190
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 01 12:37:36 PM PDT 23
Finished Nov 01 12:37:42 PM PDT 23
Peak memory 201000 kb
Host smart-ffa74088-0723-4e62-9de3-0ce21feda8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26166742597818656441928564893892096751552541730453443623055743693651359409358 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.26166742597818656441928564893892096751552541730453443623055743693651359409358
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.52278983155395606466494353138604635965476165314304066873927680215497901615149
Short name T290
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.78 seconds
Started Nov 01 12:37:36 PM PDT 23
Finished Nov 01 12:37:44 PM PDT 23
Peak memory 201104 kb
Host smart-c0c3e2f0-4b2d-4104-a1f3-78e0aab1e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52278983155395606466494353138604635965476165314304066873927680215497901615149 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.52278983155395606466494353138604635965476165314304066873927680215497901615149
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.76766072437388157521796242688827952094415722168500142571443245716443858470171
Short name T220
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.3 seconds
Started Nov 01 12:37:40 PM PDT 23
Finished Nov 01 12:40:50 PM PDT 23
Peak memory 201256 kb
Host smart-a332c623-a6d5-4676-bbbe-7e09d9f8dc80
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76766072437388157521796242688827952094415722168500142571443245716443858470171 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.76766072437388157521796242688827952094415722168500142571443245
716443858470171
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.5911734817809381217990634730782865553427540818953703687406963014234962209011
Short name T350
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.43 seconds
Started Nov 01 12:37:40 PM PDT 23
Finished Nov 01 12:37:53 PM PDT 23
Peak memory 201204 kb
Host smart-864348c6-b0ec-4513-951f-46255bd5a253
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5911734817809381217990634730782865553427540818953703687406963014234962209011 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.5911734817809381217990634730782865553427540818953703687406963
014234962209011
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.99196357912520962632907984332194294440281376832945891975044181350348448891058
Short name T455
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.27 seconds
Started Nov 01 12:37:37 PM PDT 23
Finished Nov 01 12:37:45 PM PDT 23
Peak memory 201028 kb
Host smart-7438dc91-8851-4327-98bf-4c7c6c187dfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99196357912520962632907984332194294440281376832945891975044181350348448891058 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.9919635791252096263290798433219429444028137683294589197504418135
0348448891058
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.44404661328268381320041960148822319710842745628369942270872975757904734005800
Short name T123
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.69 seconds
Started Nov 01 12:37:37 PM PDT 23
Finished Nov 01 12:37:44 PM PDT 23
Peak memory 200940 kb
Host smart-5ba2543d-7d3e-4c67-94b0-71c9d4d226c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44404661328268381320041960148822319710842745628369942270872975757904734005800 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.44404661328268381320041960148822319710842745628369942270872975757904734005800
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.4937507974718529253579650715931991047497950087010867603657983721339954102470
Short name T345
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.78 seconds
Started Nov 01 12:37:34 PM PDT 23
Finished Nov 01 12:37:41 PM PDT 23
Peak memory 201196 kb
Host smart-fa6d12bc-1d42-4bf9-987b-663a812008fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4937507974718529253579650715931991047497950087010867603657983721339954102470 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.4937507974718529253579650715931991047497950087010867603657983721339954102470
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.24988326470973044917611805052985797946109722159884591694155028396757053957580
Short name T409
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.69 seconds
Started Nov 01 12:37:42 PM PDT 23
Finished Nov 01 12:37:54 PM PDT 23
Peak memory 200964 kb
Host smart-7344180a-94a5-429c-887a-56b9e8483983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24988326470973044917611805052985797946109722159884591694155028396757053957580 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.24988326470973044917611805052985797946109722159884591694155028396757053957580
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.82163831661238315198889182406610846616898673780514288843097591755004390791971
Short name T611
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Nov 01 12:37:48 PM PDT 23
Finished Nov 01 12:38:00 PM PDT 23
Peak memory 201024 kb
Host smart-8388e8e3-0b99-40c7-af6a-35300f35d471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82163831661238315198889182406610846616898673780514288843097591755004390791971 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.82163831661238315198889182406610846616898673780514288843097591755004390791971
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.54238768316213387646795977020849646916123780685066266307274914807801029587476
Short name T575
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Nov 01 12:37:45 PM PDT 23
Finished Nov 01 12:37:56 PM PDT 23
Peak memory 200912 kb
Host smart-a5410864-e7bb-4fb1-8d7a-1cd9558dc794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54238768316213387646795977020849646916123780685066266307274914807801029587476 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_smoke.54238768316213387646795977020849646916123780685066266307274914807801029587476
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.23752128858726312707207858194137829267719065428827061593940774865556133417341
Short name T312
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.05 seconds
Started Nov 01 12:37:38 PM PDT 23
Finished Nov 01 12:39:56 PM PDT 23
Peak memory 201252 kb
Host smart-68006785-0778-454b-89b9-e9bfdd400846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23752128858726312707207858194137829267719065428827061593940774865556133417341 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.23752128858726312707207858194137829267719065428827061593940774865556133417341
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.58560292693930803559642816905080057016724439672706235075202631240441496553138
Short name T516
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.86 seconds
Started Nov 01 12:37:36 PM PDT 23
Finished Nov 01 12:37:44 PM PDT 23
Peak memory 201020 kb
Host smart-e27304aa-c3c3-4669-8a57-e078b1da2a09
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58560292693930803559642816905080057016724439672706235075202631240441496553138 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.585602926939308035596428169050800570167244396727062350752026
31240441496553138
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.34922862844338352391044147718871178465734517552456746141088121954330441228804
Short name T633
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:38:02 PM PDT 23
Peak memory 201088 kb
Host smart-f9e3b516-1f2d-4450-a393-d1dc0b793394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34922862844338352391044147718871178465734517552456746141088121954330441228804 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.34922862844338352391044147718871178465734517552456746141088121954330441228804
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.85189048344248735924643155047634690993566532315417137767482260084533935701160
Short name T558
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 01 12:37:48 PM PDT 23
Finished Nov 01 12:37:59 PM PDT 23
Peak memory 201176 kb
Host smart-4d94c9de-2147-4b20-8b4c-9b7cdeebfc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85189048344248735924643155047634690993566532315417137767482260084533935701160 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.85189048344248735924643155047634690993566532315417137767482260084533935701160
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.4360447057522695037545595784861943562361913061557755995045967856663695705938
Short name T553
Test name
Test status
Simulation time 118289458206 ps
CPU time 186.51 seconds
Started Nov 01 12:37:45 PM PDT 23
Finished Nov 01 12:40:59 PM PDT 23
Peak memory 201304 kb
Host smart-f7b85f65-6b1a-4d3d-9ca0-60dbca6e4d2f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4360447057522695037545595784861943562361913061557755995045967856663695705938 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.436044705752269503754559578486194356236191306155775599504596785
6663695705938
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.34312983349280947191946560416231597574337112950142978276151848488567767631496
Short name T583
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.37 seconds
Started Nov 01 12:37:37 PM PDT 23
Finished Nov 01 12:37:47 PM PDT 23
Peak memory 200952 kb
Host smart-ffdd49bb-f225-4ed9-8da6-02cbb94ccfea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34312983349280947191946560416231597574337112950142978276151848488567767631496 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.343129833492809471919465604162315975743371129501429782761518
48488567767631496
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.10053382283531772948716307128353989993452300178967442133040913598987208985442
Short name T519
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.21 seconds
Started Nov 01 12:37:48 PM PDT 23
Finished Nov 01 12:38:01 PM PDT 23
Peak memory 201016 kb
Host smart-a3b9d7cf-0ff1-4d4a-956f-682b8e346d67
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053382283531772948716307128353989993452300178967442133040913598987208985442 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.1005338228353177294871630712835398999345230017896744213304091359
8987208985442
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.28862458133704663774386031688421925497492181437447688135392929431978433137209
Short name T618
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 01 12:37:45 PM PDT 23
Finished Nov 01 12:37:57 PM PDT 23
Peak memory 200996 kb
Host smart-8b9f9f9f-a037-4960-9dd6-3c42014af408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28862458133704663774386031688421925497492181437447688135392929431978433137209 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.28862458133704663774386031688421925497492181437447688135392929431978433137209
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.79951932147184353051722202312191818440439400306000958029860099382735640549898
Short name T398
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.74 seconds
Started Nov 01 12:37:46 PM PDT 23
Finished Nov 01 12:37:57 PM PDT 23
Peak memory 201008 kb
Host smart-e8dd65a1-3212-4bb8-afaa-116d190d8b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79951932147184353051722202312191818440439400306000958029860099382735640549898 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.79951932147184353051722202312191818440439400306000958029860099382735640549898
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.52341224225722218271394476257185920413100074655309230118188101147336060586097
Short name T200
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.76 seconds
Started Nov 01 12:37:41 PM PDT 23
Finished Nov 01 12:37:54 PM PDT 23
Peak memory 200908 kb
Host smart-c00e9a26-f3e3-4d46-9cc7-e8829b845c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52341224225722218271394476257185920413100074655309230118188101147336060586097 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.52341224225722218271394476257185920413100074655309230118188101147336060586097
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.5634485140754888826080006022497454885236917135416440080360916069956909954290
Short name T287
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Nov 01 12:37:37 PM PDT 23
Finished Nov 01 12:37:45 PM PDT 23
Peak memory 201052 kb
Host smart-0835e118-e556-4d65-b62c-67a5b2bc1ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5634485140754888826080006022497454885236917135416440080360916069956909954290 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.5634485140754888826080006022497454885236917135416440080360916069956909954290
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.109016545088840094355081317972645340350479071467333621878124609174950841132070
Short name T422
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.81 seconds
Started Nov 01 12:37:33 PM PDT 23
Finished Nov 01 12:37:40 PM PDT 23
Peak memory 200928 kb
Host smart-d21921ea-875b-4576-bf02-101af213e2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109016545088840094355081317972645340350479071467333621878124609174950841132070 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 42.sysrst_ctrl_smoke.109016545088840094355081317972645340350479071467333621878124609174950841132070
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.78428389749467814109325592320871241520532381018268563845930200200499338860815
Short name T477
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.95 seconds
Started Nov 01 12:37:35 PM PDT 23
Finished Nov 01 12:39:52 PM PDT 23
Peak memory 201320 kb
Host smart-2579f94d-e901-4403-af79-453c0f5d5557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78428389749467814109325592320871241520532381018268563845930200200499338860815 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.78428389749467814109325592320871241520532381018268563845930200200499338860815
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.39214423142725589671247630556628588289298585723519794530455489572297050439738
Short name T318
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Nov 01 12:37:42 PM PDT 23
Finished Nov 01 12:37:57 PM PDT 23
Peak memory 201172 kb
Host smart-277a5235-ef66-431f-a58a-fd20d5f01541
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39214423142725589671247630556628588289298585723519794530455489572297050439738 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.392144231427255896712476305566285882892985857235197945304554
89572297050439738
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.45808124609026426644688208077223567453377199136741271826876289532180192755725
Short name T628
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.6 seconds
Started Nov 01 12:37:52 PM PDT 23
Finished Nov 01 12:38:02 PM PDT 23
Peak memory 201080 kb
Host smart-bdf90556-23b3-4d1d-b1b5-2d0b43acf452
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45808124609026426644688208077223567453377199136741271826876289532180192755725 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.45808124609026426644688208077223567453377199136741271826876289532180192755725
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.13307134348979392067187000064535990709779234459466176508473462716963673342937
Short name T98
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Nov 01 12:37:43 PM PDT 23
Finished Nov 01 12:37:58 PM PDT 23
Peak memory 201120 kb
Host smart-874d4fd2-d13b-4383-bab5-b1300f34bd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13307134348979392067187000064535990709779234459466176508473462716963673342937 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.13307134348979392067187000064535990709779234459466176508473462716963673342937
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.105807912803379014102122461213220545331486124074686749728875355249078865950694
Short name T646
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.42 seconds
Started Nov 01 12:37:47 PM PDT 23
Finished Nov 01 12:40:58 PM PDT 23
Peak memory 201292 kb
Host smart-595d4c4b-a25d-4c06-9e4d-fe6107783210
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105807912803379014102122461213220545331486124074686749728875355249078865950694 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.1058079128033790141021224612132205453314861240746867497288753
55249078865950694
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.8151040509683469919719872479859374695470479689599984327327451205495162679561
Short name T257
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.43 seconds
Started Nov 01 12:37:37 PM PDT 23
Finished Nov 01 12:37:47 PM PDT 23
Peak memory 201196 kb
Host smart-e1456008-6a94-43d4-b917-f78eb5270dd2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8151040509683469919719872479859374695470479689599984327327451205495162679561 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.8151040509683469919719872479859374695470479689599984327327451
205495162679561
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.91424103539495411977996925161870217824946869206835759673950035178374564421146
Short name T26
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Nov 01 12:37:38 PM PDT 23
Finished Nov 01 12:37:47 PM PDT 23
Peak memory 201028 kb
Host smart-d277cee5-5f49-4e93-9723-0be946aacf78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91424103539495411977996925161870217824946869206835759673950035178374564421146 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.9142410353949541197799692516187021782494686920683575967395003517
8374564421146
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.18491990413956709112983035304833009921987879629469654268591645371925590171158
Short name T678
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 01 12:37:58 PM PDT 23
Finished Nov 01 12:38:06 PM PDT 23
Peak memory 200928 kb
Host smart-1f98060c-8d3f-40f0-86d0-d8160ab9d369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18491990413956709112983035304833009921987879629469654268591645371925590171158 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.18491990413956709112983035304833009921987879629469654268591645371925590171158
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.61271449940034070974509521811490360797755111499871401054315734520236582414743
Short name T366
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Nov 01 12:37:40 PM PDT 23
Finished Nov 01 12:37:51 PM PDT 23
Peak memory 201048 kb
Host smart-f64f7149-8aa8-4bcb-a77c-c2dde1dd8b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61271449940034070974509521811490360797755111499871401054315734520236582414743 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.61271449940034070974509521811490360797755111499871401054315734520236582414743
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.48184093783398187279813066106606607582883407753988487860267593395404341563585
Short name T368
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.69 seconds
Started Nov 01 12:37:43 PM PDT 23
Finished Nov 01 12:37:56 PM PDT 23
Peak memory 200984 kb
Host smart-e22adc2d-a711-45ac-ba29-491c7bbbce48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48184093783398187279813066106606607582883407753988487860267593395404341563585 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.48184093783398187279813066106606607582883407753988487860267593395404341563585
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.80102523833827060007823072793577663226165290141429857920413799983997921705030
Short name T475
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.66 seconds
Started Nov 01 12:37:41 PM PDT 23
Finished Nov 01 12:37:55 PM PDT 23
Peak memory 201032 kb
Host smart-b39cd9cc-272c-4836-b6a9-432cf338c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80102523833827060007823072793577663226165290141429857920413799983997921705030 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.80102523833827060007823072793577663226165290141429857920413799983997921705030
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.7228336853879325492390492436365810191666339968114257424441696549202994044471
Short name T337
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Nov 01 12:37:48 PM PDT 23
Finished Nov 01 12:37:57 PM PDT 23
Peak memory 200984 kb
Host smart-ec51c719-68d1-4449-81bf-81064bd7814e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7228336853879325492390492436365810191666339968114257424441696549202994044471 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sysrst_ctrl_smoke.7228336853879325492390492436365810191666339968114257424441696549202994044471
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.111970245495797554006840407251972685121718319595793864889764566331970690441517
Short name T276
Test name
Test status
Simulation time 87228974549 ps
CPU time 137.06 seconds
Started Nov 01 12:37:55 PM PDT 23
Finished Nov 01 12:40:16 PM PDT 23
Peak memory 201616 kb
Host smart-dae2cc63-a891-4bef-9a5d-57270f0b01a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111970245495797554006840407251972685121718319595793864889764566331970690441517 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.111970245495797554006840407251972685121718319595793864889764566331970690441517
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.31587030763599958724096802689195646856438864269731924754470343233891769692307
Short name T295
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.76 seconds
Started Nov 01 12:37:58 PM PDT 23
Finished Nov 01 12:38:07 PM PDT 23
Peak memory 200932 kb
Host smart-eff0fd98-3ce8-4710-823f-acb28ea6b4ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31587030763599958724096802689195646856438864269731924754470343233891769692307 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.315870307635999587240968026891956468564388642697319247544703
43233891769692307
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.64504524640812024832788289492000221570565110444621228090358099034463852025795
Short name T435
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 01 12:37:50 PM PDT 23
Finished Nov 01 12:38:00 PM PDT 23
Peak memory 200936 kb
Host smart-cf1f3b39-34e0-4332-85c2-452a8b7516a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64504524640812024832788289492000221570565110444621228090358099034463852025795 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.64504524640812024832788289492000221570565110444621228090358099034463852025795
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.48813045491297431560925831738461785581590641148089300563550312049971656963747
Short name T108
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201088 kb
Host smart-b596d452-bcba-413c-a13e-fc3df2a7c19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48813045491297431560925831738461785581590641148089300563550312049971656963747 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.48813045491297431560925831738461785581590641148089300563550312049971656963747
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.104339243901218575971636126796902538364064386710970669165671907113517582964443
Short name T550
Test name
Test status
Simulation time 118289458206 ps
CPU time 180.21 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:40:58 PM PDT 23
Peak memory 201276 kb
Host smart-20bdd2d2-4ab9-440a-87cf-6cbb66b6017b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104339243901218575971636126796902538364064386710970669165671907113517582964443 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.1043392439012185759716361267969025383640643867109706691656719
07113517582964443
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.95244793782752160015833395118894581711241546000505830533566931089417108886259
Short name T115
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.28 seconds
Started Nov 01 12:37:52 PM PDT 23
Finished Nov 01 12:38:05 PM PDT 23
Peak memory 201008 kb
Host smart-a1b1a464-ec6f-4d7e-9021-459b1f49acfb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95244793782752160015833395118894581711241546000505830533566931089417108886259 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.952447937827521600158333951188945817112415460005058305335669
31089417108886259
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.59430562968655399072145475936665911557598111837663515699533704193560848476750
Short name T528
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.28 seconds
Started Nov 01 12:37:50 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201196 kb
Host smart-32c545d9-4aa6-46af-887c-52437a2fd82f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59430562968655399072145475936665911557598111837663515699533704193560848476750 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.5943056296865539907214547593666591155759811183766351569953370419
3560848476750
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.10905843244317049026240896163800403695298892700309620387163664309990421710728
Short name T645
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.58 seconds
Started Nov 01 12:37:50 PM PDT 23
Finished Nov 01 12:38:01 PM PDT 23
Peak memory 201080 kb
Host smart-a63399fb-0e20-435b-9503-576f16e14e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10905843244317049026240896163800403695298892700309620387163664309990421710728 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.10905843244317049026240896163800403695298892700309620387163664309990421710728
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.53580665024959129635643665180653467399097596099185618683536083503977703482312
Short name T372
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.86 seconds
Started Nov 01 12:37:53 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201212 kb
Host smart-72447036-acbb-4034-9c7b-b65e04ccc2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53580665024959129635643665180653467399097596099185618683536083503977703482312 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.53580665024959129635643665180653467399097596099185618683536083503977703482312
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.82788057793230057471699542160225328321253723676071934002020744443449416154402
Short name T639
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.74 seconds
Started Nov 01 12:37:55 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201008 kb
Host smart-94e3fe6b-ae1d-442f-a884-cde4636d7fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82788057793230057471699542160225328321253723676071934002020744443449416154402 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.82788057793230057471699542160225328321253723676071934002020744443449416154402
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.56222411238815679911639974548746690860601283896914038923218196791729526184233
Short name T604
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.57 seconds
Started Nov 01 12:37:49 PM PDT 23
Finished Nov 01 12:38:00 PM PDT 23
Peak memory 201152 kb
Host smart-7fff5ff9-ca36-44e9-aee4-cfa47f94c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56222411238815679911639974548746690860601283896914038923218196791729526184233 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.56222411238815679911639974548746690860601283896914038923218196791729526184233
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.66129507509386290398802917629697148993238697845692145419210417829968523399793
Short name T610
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:38:01 PM PDT 23
Peak memory 200992 kb
Host smart-0669a15f-4e47-49dc-a6bb-28246bbde77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66129507509386290398802917629697148993238697845692145419210417829968523399793 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sysrst_ctrl_smoke.66129507509386290398802917629697148993238697845692145419210417829968523399793
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.45651374897369507406943270706102041718190784508573513969495006969494949517901
Short name T250
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.92 seconds
Started Nov 01 12:37:47 PM PDT 23
Finished Nov 01 12:40:09 PM PDT 23
Peak memory 201312 kb
Host smart-6ca791db-833d-4d48-9efc-f074cad13194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45651374897369507406943270706102041718190784508573513969495006969494949517901 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.45651374897369507406943270706102041718190784508573513969495006969494949517901
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.57615042107322561605574760305372455783806207583592025020508111912214496435342
Short name T573
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.71 seconds
Started Nov 01 12:37:52 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201064 kb
Host smart-7068b7eb-ee03-46eb-b151-6edc3768512c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57615042107322561605574760305372455783806207583592025020508111912214496435342 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.576150421073225616055747603053724557838062075835920250205081
11912214496435342
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.85110074349889773507379597723181349764113171893711033603065200280726986955573
Short name T122
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.72 seconds
Started Nov 01 12:38:01 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 201056 kb
Host smart-c664630a-e1f2-4d7c-96e7-823e0ac1c359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85110074349889773507379597723181349764113171893711033603065200280726986955573 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.85110074349889773507379597723181349764113171893711033603065200280726986955573
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.47123065760261204256692386704108020264402157736365976672368358549000523868544
Short name T419
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 200980 kb
Host smart-3bd8e3bf-bca3-4cd8-925e-fbbcb5a03ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47123065760261204256692386704108020264402157736365976672368358549000523868544 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.47123065760261204256692386704108020264402157736365976672368358549000523868544
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.50217463783664256495623391443123031467965466969997650687412262055965901379608
Short name T209
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.63 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:41:00 PM PDT 23
Peak memory 201144 kb
Host smart-891251da-a172-4e11-9853-317547e9ff34
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50217463783664256495623391443123031467965466969997650687412262055965901379608 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.50217463783664256495623391443123031467965466969997650687412262
055965901379608
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.99269980460281662804972623433016067653151822376119870009062223859791466615553
Short name T17
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.41 seconds
Started Nov 01 12:37:45 PM PDT 23
Finished Nov 01 12:38:00 PM PDT 23
Peak memory 201064 kb
Host smart-03cd1e1b-2fd5-46da-bfb5-2bf9356ead12
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99269980460281662804972623433016067653151822376119870009062223859791466615553 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.992699804602816628049726234330160676531518223761198700090622
23859791466615553
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3081979786064781399101487407270565877870451769559276912273999432302328448915
Short name T512
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.23 seconds
Started Nov 01 12:37:57 PM PDT 23
Finished Nov 01 12:38:07 PM PDT 23
Peak memory 200484 kb
Host smart-2b7f0abf-24fe-414a-baf4-0202f7046bc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081979786064781399101487407270565877870451769559276912273999432302328448915 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.3081979786064781399101487407270565877870451769559276912273999432302328448915
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.12612043491089794841210492144947886066448639936208640436322466769327434956188
Short name T207
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 01 12:37:54 PM PDT 23
Finished Nov 01 12:38:04 PM PDT 23
Peak memory 201084 kb
Host smart-b41328b0-4564-4ea7-a178-b6d670479253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12612043491089794841210492144947886066448639936208640436322466769327434956188 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.12612043491089794841210492144947886066448639936208640436322466769327434956188
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.23093852207424344596502858412225929083071055862576964796522389064632603600187
Short name T590
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.81 seconds
Started Nov 01 12:37:54 PM PDT 23
Finished Nov 01 12:38:04 PM PDT 23
Peak memory 201028 kb
Host smart-d23df6ca-0a4d-4b41-b3c3-bde2b60d33f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23093852207424344596502858412225929083071055862576964796522389064632603600187 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.23093852207424344596502858412225929083071055862576964796522389064632603600187
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.85321701603167472877764352820629938216854442691261458423900789680077405422346
Short name T113
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 01 12:37:52 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201052 kb
Host smart-866a6083-b02d-418d-afb1-ffdd5eb2196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85321701603167472877764352820629938216854442691261458423900789680077405422346 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.85321701603167472877764352820629938216854442691261458423900789680077405422346
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.76985014235092974653445245999393707089657293427851716852421544093435347633590
Short name T325
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.51 seconds
Started Nov 01 12:37:56 PM PDT 23
Finished Nov 01 12:38:05 PM PDT 23
Peak memory 201040 kb
Host smart-a3b18fe0-69d8-4bd7-83f0-3b86547b2269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76985014235092974653445245999393707089657293427851716852421544093435347633590 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.76985014235092974653445245999393707089657293427851716852421544093435347633590
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.25412835754321035374477023520603024637483577539957820829237083693316923855532
Short name T244
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.76 seconds
Started Nov 01 12:37:52 PM PDT 23
Finished Nov 01 12:38:02 PM PDT 23
Peak memory 201016 kb
Host smart-effe07ce-3c74-4192-bf54-c2c2b444db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25412835754321035374477023520603024637483577539957820829237083693316923855532 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_smoke.25412835754321035374477023520603024637483577539957820829237083693316923855532
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.22021546288883447599931734284238272156240133680107669957677502422180188487273
Short name T142
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.27 seconds
Started Nov 01 12:37:50 PM PDT 23
Finished Nov 01 12:40:12 PM PDT 23
Peak memory 201300 kb
Host smart-6ce9b583-2f61-48f8-be01-bd332be0d917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22021546288883447599931734284238272156240133680107669957677502422180188487273 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.22021546288883447599931734284238272156240133680107669957677502422180188487273
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.85257517431167222178678672811614151213122723814521207969813624978518270881829
Short name T339
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 01 12:37:57 PM PDT 23
Finished Nov 01 12:38:10 PM PDT 23
Peak memory 201044 kb
Host smart-1b0223b6-ec0e-460f-a10c-84ed8afbb2f4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85257517431167222178678672811614151213122723814521207969813624978518270881829 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.852575174311672221786786728116141512131227238145212079698136
24978518270881829
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.114577585659559607312358972169237560296657877938106895631817578705074572404721
Short name T251
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:38:07 PM PDT 23
Peak memory 201028 kb
Host smart-f55912d6-7b2f-4313-bc1c-d593a2d00ad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114577585659559607312358972169237560296657877938106895631817578705074572404721 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.114577585659559607312358972169237560296657877938106895631817578705074572404721
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.95699532030154918726635990112260330929767595020403012646517876293496928455234
Short name T274
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.49 seconds
Started Nov 01 12:37:57 PM PDT 23
Finished Nov 01 12:38:06 PM PDT 23
Peak memory 200376 kb
Host smart-a2da2038-9cc9-4179-b08d-a079df85988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95699532030154918726635990112260330929767595020403012646517876293496928455234 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.95699532030154918726635990112260330929767595020403012646517876293496928455234
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.83289169237636891387731185395231545440621003683239639296453067112011952842190
Short name T35
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.14 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:41:00 PM PDT 23
Peak memory 201276 kb
Host smart-01c40d9a-cc9c-4cba-9909-12108eb13acd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83289169237636891387731185395231545440621003683239639296453067112011952842190 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.83289169237636891387731185395231545440621003683239639296453067
112011952842190
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.34491600229724351864514918193177059732622890190818624277980951930351843453776
Short name T676
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.5 seconds
Started Nov 01 12:37:53 PM PDT 23
Finished Nov 01 12:38:06 PM PDT 23
Peak memory 201096 kb
Host smart-d8c4914e-732e-4d9d-a205-a57df319fa1c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34491600229724351864514918193177059732622890190818624277980951930351843453776 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.344916002297243518645149181931770597326228901908186242779809
51930351843453776
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.25059369115757437820069318682853805978926267803824307216967275966374241104536
Short name T373
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Nov 01 12:37:54 PM PDT 23
Finished Nov 01 12:38:05 PM PDT 23
Peak memory 201020 kb
Host smart-69ca1391-4607-4183-9671-27e5f996c489
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25059369115757437820069318682853805978926267803824307216967275966374241104536 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.2505936911575743782006931868285380597892626780382430721696727596
6374241104536
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.33734041669669614443257252994995508783851457669669037520155662953919390005972
Short name T330
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.62 seconds
Started Nov 01 12:37:54 PM PDT 23
Finished Nov 01 12:38:04 PM PDT 23
Peak memory 201028 kb
Host smart-d86c9c9d-661b-4841-a7bb-5c54a78e3823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33734041669669614443257252994995508783851457669669037520155662953919390005972 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.33734041669669614443257252994995508783851457669669037520155662953919390005972
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.46038428728563545000055506840023223403990998174286982459906821007879595862699
Short name T219
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.72 seconds
Started Nov 01 12:37:50 PM PDT 23
Finished Nov 01 12:38:01 PM PDT 23
Peak memory 201056 kb
Host smart-9e78d4b8-ee69-44b7-b71f-8ee0afb0b277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46038428728563545000055506840023223403990998174286982459906821007879595862699 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.46038428728563545000055506840023223403990998174286982459906821007879595862699
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.71838430093514706738488482185176827628970556401433555481178434256166434829026
Short name T185
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.72 seconds
Started Nov 01 12:37:54 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 200932 kb
Host smart-6e3189b6-701a-423d-8368-31b9451ecb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71838430093514706738488482185176827628970556401433555481178434256166434829026 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.71838430093514706738488482185176827628970556401433555481178434256166434829026
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.22048966933127974626638848938870740474228436666189831530467266541517657670833
Short name T605
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.51 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:38:07 PM PDT 23
Peak memory 200868 kb
Host smart-738f7ab9-d2f3-4121-b524-c66af5332f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22048966933127974626638848938870740474228436666189831530467266541517657670833 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.22048966933127974626638848938870740474228436666189831530467266541517657670833
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.74688145988590062225265984409431691188607955837964696924600718673628961051597
Short name T239
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.77 seconds
Started Nov 01 12:37:50 PM PDT 23
Finished Nov 01 12:38:00 PM PDT 23
Peak memory 201144 kb
Host smart-54e7c92a-cc07-4998-9305-e87f7db1738c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74688145988590062225265984409431691188607955837964696924600718673628961051597 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_smoke.74688145988590062225265984409431691188607955837964696924600718673628961051597
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.19104905045710314036138015812396371399167512140710518550555512075266188141487
Short name T502
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.52 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:40:19 PM PDT 23
Peak memory 201268 kb
Host smart-dc297cd5-a33f-4466-aaca-1893b342ca83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104905045710314036138015812396371399167512140710518550555512075266188141487 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.19104905045710314036138015812396371399167512140710518550555512075266188141487
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.29520858283561813994640963545560685017778631010968602482506651797333527732564
Short name T351
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.72 seconds
Started Nov 01 12:37:56 PM PDT 23
Finished Nov 01 12:38:05 PM PDT 23
Peak memory 201024 kb
Host smart-dd9da41d-3f26-4d1d-8fff-582dfbdf5b08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29520858283561813994640963545560685017778631010968602482506651797333527732564 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.295208582835618139946409635455606850177786310109686024825066
51797333527732564
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.60425589555645250105165752654838027318814772926300481626114165829202218505826
Short name T214
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.63 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:38:06 PM PDT 23
Peak memory 200944 kb
Host smart-7be11bb8-7fe5-43ff-b5eb-a61c8aa4b5fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60425589555645250105165752654838027318814772926300481626114165829202218505826 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.60425589555645250105165752654838027318814772926300481626114165829202218505826
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.12340883782559324176210919390945960284771960180962956476229804835171521664950
Short name T353
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Nov 01 12:38:01 PM PDT 23
Finished Nov 01 12:38:10 PM PDT 23
Peak memory 201048 kb
Host smart-187c8a62-137c-4a5f-959e-b490ff86a990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12340883782559324176210919390945960284771960180962956476229804835171521664950 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.12340883782559324176210919390945960284771960180962956476229804835171521664950
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.41392174158708050571856234325851670146157944072105997253607975789445681497856
Short name T218
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.4 seconds
Started Nov 01 12:38:04 PM PDT 23
Finished Nov 01 12:41:13 PM PDT 23
Peak memory 201376 kb
Host smart-679d2c81-33d6-4067-a3ee-f80465e9c54b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41392174158708050571856234325851670146157944072105997253607975789445681497856 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.41392174158708050571856234325851670146157944072105997253607975
789445681497856
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.75150488842881413832375773182526849479209931060388023830576350284282072252887
Short name T208
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.34 seconds
Started Nov 01 12:37:55 PM PDT 23
Finished Nov 01 12:38:07 PM PDT 23
Peak memory 200980 kb
Host smart-22edc788-6909-41b5-8a8b-c6622b571535
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75150488842881413832375773182526849479209931060388023830576350284282072252887 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.751504888428814138323757731825268494792099310603880238305763
50284282072252887
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.97151979519878699951060739915950722373914481896181140508752739772517881678099
Short name T255
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Nov 01 12:37:55 PM PDT 23
Finished Nov 01 12:38:06 PM PDT 23
Peak memory 200944 kb
Host smart-561171a1-fcca-4678-8df4-95227a851e6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97151979519878699951060739915950722373914481896181140508752739772517881678099 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.9715197951987869995106073991595072237391448189618114050875273977
2517881678099
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.96766393996965041078806659241491280398910418524480178860518304162516108387229
Short name T278
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.61 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 201088 kb
Host smart-55c06dc6-b738-40a6-8dd3-eaa496080cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96766393996965041078806659241491280398910418524480178860518304162516108387229 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.96766393996965041078806659241491280398910418524480178860518304162516108387229
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.13485293216063033264661538437461893217596740550754388691944802440712470878040
Short name T134
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.73 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 200960 kb
Host smart-850803da-c05b-4981-bbd1-998ce0726512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13485293216063033264661538437461893217596740550754388691944802440712470878040 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.13485293216063033264661538437461893217596740550754388691944802440712470878040
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.40334385028681803769751628180610702920569754896899277991994204481721070768663
Short name T483
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.82 seconds
Started Nov 01 12:38:00 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 201140 kb
Host smart-cf4b8e20-9fd5-41dd-b780-6e31a620c078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40334385028681803769751628180610702920569754896899277991994204481721070768663 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.40334385028681803769751628180610702920569754896899277991994204481721070768663
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.94291704303944267374489084458736947666576560466484001134854271673508519684520
Short name T280
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.6 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:38:01 PM PDT 23
Peak memory 200912 kb
Host smart-54bff9e6-9fac-4a87-a89e-006dfcaea7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94291704303944267374489084458736947666576560466484001134854271673508519684520 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.94291704303944267374489084458736947666576560466484001134854271673508519684520
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.92055258533700168806861680662698644217399225191659434758265621452508235429470
Short name T415
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.93 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:38:01 PM PDT 23
Peak memory 200976 kb
Host smart-8510fc4a-9ce1-4bc6-bf44-c22f12114ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92055258533700168806861680662698644217399225191659434758265621452508235429470 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_smoke.92055258533700168806861680662698644217399225191659434758265621452508235429470
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.20850993894619544708517620353855564471425082937864531049730521692983445992901
Short name T629
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.85 seconds
Started Nov 01 12:37:51 PM PDT 23
Finished Nov 01 12:40:13 PM PDT 23
Peak memory 201212 kb
Host smart-4faa9c77-f70d-47a5-92d4-723185c95296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20850993894619544708517620353855564471425082937864531049730521692983445992901 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.20850993894619544708517620353855564471425082937864531049730521692983445992901
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.45545837109103061314840989929842541715319554478603324126874525382244046634405
Short name T374
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.85 seconds
Started Nov 01 12:38:01 PM PDT 23
Finished Nov 01 12:38:10 PM PDT 23
Peak memory 200872 kb
Host smart-5b05cc1e-de18-4dd4-89d6-b317e11db2f0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45545837109103061314840989929842541715319554478603324126874525382244046634405 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.455458371091030613148409899298425417153195544786033241268745
25382244046634405
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.80591983654813686654327100746195148304512562888846064991767205574042480674710
Short name T671
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.66 seconds
Started Nov 01 12:38:13 PM PDT 23
Finished Nov 01 12:38:20 PM PDT 23
Peak memory 200988 kb
Host smart-cd190c0a-20e7-4533-a601-1cea55eceb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80591983654813686654327100746195148304512562888846064991767205574042480674710 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.80591983654813686654327100746195148304512562888846064991767205574042480674710
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.77815621264441516260004534555770069216026270159140188534455245260277125078452
Short name T520
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.47 seconds
Started Nov 01 12:37:54 PM PDT 23
Finished Nov 01 12:38:05 PM PDT 23
Peak memory 201232 kb
Host smart-cebe34f4-eace-4026-b309-179156b566f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77815621264441516260004534555770069216026270159140188534455245260277125078452 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.77815621264441516260004534555770069216026270159140188534455245260277125078452
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.79792130793393888149198394032825821416696685747548324369938553882808969955883
Short name T442
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.38 seconds
Started Nov 01 12:37:54 PM PDT 23
Finished Nov 01 12:41:04 PM PDT 23
Peak memory 201280 kb
Host smart-31737725-04f8-435f-8d44-a09d98fa5661
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79792130793393888149198394032825821416696685747548324369938553882808969955883 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.79792130793393888149198394032825821416696685747548324369938553
882808969955883
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.59029951155971398240805551710804439303368368223367214082404542019908367313421
Short name T376
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Nov 01 12:38:03 PM PDT 23
Finished Nov 01 12:38:14 PM PDT 23
Peak memory 201096 kb
Host smart-08f22850-a279-402d-9639-2ac60e505b31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59029951155971398240805551710804439303368368223367214082404542019908367313421 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.590299511559713982408055517108044393033683682233672140824045
42019908367313421
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.10507440871443799809408657228740699244186632984923380666565467436461223801360
Short name T156
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.31 seconds
Started Nov 01 12:37:50 PM PDT 23
Finished Nov 01 12:38:03 PM PDT 23
Peak memory 201216 kb
Host smart-31af4cac-2a19-4b02-a379-ca1d05791c60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10507440871443799809408657228740699244186632984923380666565467436461223801360 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.1050744087144379980940865722874069924418663298492338066656546743
6461223801360
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.19963671283741494502089492620015767468548869959749415304172952037042724329360
Short name T198
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Nov 01 12:37:55 PM PDT 23
Finished Nov 01 12:38:04 PM PDT 23
Peak memory 201036 kb
Host smart-d569f9b6-aa0d-4701-817c-eeafa4c4492d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19963671283741494502089492620015767468548869959749415304172952037042724329360 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.19963671283741494502089492620015767468548869959749415304172952037042724329360
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.107575520556747944910422079522027531037921911758298153320721222547824745913341
Short name T500
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.9 seconds
Started Nov 01 12:38:04 PM PDT 23
Finished Nov 01 12:38:12 PM PDT 23
Peak memory 201176 kb
Host smart-cef5176b-38d8-4b13-acb6-817e3e8682ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107575520556747944910422079522027531037921911758298153320721222547824745913341 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.107575520556747944910422079522027531037921911758298153320721222547824745913341
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.42419117106076562355090171535599996548505217073644090011157969643731171147719
Short name T673
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.83 seconds
Started Nov 01 12:38:04 PM PDT 23
Finished Nov 01 12:38:11 PM PDT 23
Peak memory 201112 kb
Host smart-c43f2ec9-7b2a-4444-b64d-b5529774d529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42419117106076562355090171535599996548505217073644090011157969643731171147719 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.42419117106076562355090171535599996548505217073644090011157969643731171147719
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.58177256612573687429903005026259112680374165660185146337102385282613239298085
Short name T382
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Nov 01 12:38:03 PM PDT 23
Finished Nov 01 12:38:11 PM PDT 23
Peak memory 201056 kb
Host smart-1ccfa635-47f3-4616-9880-98bd63c3b6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58177256612573687429903005026259112680374165660185146337102385282613239298085 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.58177256612573687429903005026259112680374165660185146337102385282613239298085
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.28712400446870828811238336146331870536887798955537981620677234455327541966438
Short name T44
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Nov 01 12:37:59 PM PDT 23
Finished Nov 01 12:38:07 PM PDT 23
Peak memory 200512 kb
Host smart-4f57cdfe-b008-4e56-addc-936843f5fbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28712400446870828811238336146331870536887798955537981620677234455327541966438 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_smoke.28712400446870828811238336146331870536887798955537981620677234455327541966438
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.74910201019186938099232820408222024298882107979363149739341022238410898053347
Short name T584
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.02 seconds
Started Nov 01 12:37:55 PM PDT 23
Finished Nov 01 12:40:15 PM PDT 23
Peak memory 201304 kb
Host smart-a9cedfe9-c5d9-4034-aab7-f5ff8b3e0465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74910201019186938099232820408222024298882107979363149739341022238410898053347 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.74910201019186938099232820408222024298882107979363149739341022238410898053347
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.31831063123125616904854389338169482190927795133580013381334611513389464327515
Short name T530
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.82 seconds
Started Nov 01 12:38:05 PM PDT 23
Finished Nov 01 12:38:14 PM PDT 23
Peak memory 201124 kb
Host smart-4ab74c93-c2aa-4767-8882-0c0bdb5dc75f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31831063123125616904854389338169482190927795133580013381334611513389464327515 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.318310631231256169048543893381694821909277951335800133813346
11513389464327515
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.63886014752770142690429539734000390628872740391435889994824307014374642292174
Short name T39
Test name
Test status
Simulation time 2015424120 ps
CPU time 4.04 seconds
Started Nov 01 12:38:41 PM PDT 23
Finished Nov 01 12:38:46 PM PDT 23
Peak memory 200956 kb
Host smart-4c787572-e52b-4543-a5eb-ff2cb5b4902d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63886014752770142690429539734000390628872740391435889994824307014374642292174 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.63886014752770142690429539734000390628872740391435889994824307014374642292174
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.98960934516596491777131893487537066832856492099919635608601198049032154888946
Short name T107
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.45 seconds
Started Nov 01 12:38:45 PM PDT 23
Finished Nov 01 12:38:51 PM PDT 23
Peak memory 201108 kb
Host smart-bf35354f-476f-419a-86c9-98ef074f57da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98960934516596491777131893487537066832856492099919635608601198049032154888946 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.98960934516596491777131893487537066832856492099919635608601198049032154888946
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.110325633044569445617147716029831840036317250948441615678137260966344510530880
Short name T25
Test name
Test status
Simulation time 118289458206 ps
CPU time 183.29 seconds
Started Nov 01 12:38:44 PM PDT 23
Finished Nov 01 12:41:49 PM PDT 23
Peak memory 201300 kb
Host smart-1dbfa9ee-230f-41ff-9e9a-9f14628899ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110325633044569445617147716029831840036317250948441615678137260966344510530880 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.1103256330445694456171477160298318400363172509484416156781372
60966344510530880
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.18843652262279738472321257240866008726311045432579902058102787735097803121490
Short name T361
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.39 seconds
Started Nov 01 12:38:54 PM PDT 23
Finished Nov 01 12:39:03 PM PDT 23
Peak memory 201184 kb
Host smart-5021b826-0def-4326-a060-3403c2feaba1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18843652262279738472321257240866008726311045432579902058102787735097803121490 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.188436522622797384723212572408660087263110454325799020581027
87735097803121490
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.30739794340322423864675329271681851914545513469322573033150360491111268727100
Short name T492
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.8 seconds
Started Nov 01 12:38:41 PM PDT 23
Finished Nov 01 12:38:49 PM PDT 23
Peak memory 200928 kb
Host smart-e01bac32-e625-413c-8f30-72081fbd8934
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30739794340322423864675329271681851914545513469322573033150360491111268727100 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.3073979434032242386467532927168185191454551346932257303315036049
1111268727100
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.91807002265715081035987051209665629267263277002192919880035749627971020651613
Short name T478
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.68 seconds
Started Nov 01 12:38:41 PM PDT 23
Finished Nov 01 12:38:46 PM PDT 23
Peak memory 201088 kb
Host smart-54e534b0-e773-488d-962f-57412bb0eca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91807002265715081035987051209665629267263277002192919880035749627971020651613 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.91807002265715081035987051209665629267263277002192919880035749627971020651613
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.101433830295142314750131635368506102674129665420733436030014811561056500258948
Short name T521
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.83 seconds
Started Nov 01 12:38:41 PM PDT 23
Finished Nov 01 12:38:46 PM PDT 23
Peak memory 201056 kb
Host smart-9fd762d0-0b94-467d-b40e-63f90c7e110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101433830295142314750131635368506102674129665420733436030014811561056500258948 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.101433830295142314750131635368506102674129665420733436030014811561056500258948
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1516054628217475555842375564770996553660998737949654612299605934413670939075
Short name T497
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.73 seconds
Started Nov 01 12:38:47 PM PDT 23
Finished Nov 01 12:38:51 PM PDT 23
Peak memory 200776 kb
Host smart-02dfc1e9-6d10-49d8-a66a-f4ed75aef44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516054628217475555842375564770996553660998737949654612299605934413670939075 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1516054628217475555842375564770996553660998737949654612299605934413670939075
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.104428162801457104057568070167399316993807615296961234270659244047902141829008
Short name T365
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.67 seconds
Started Nov 01 12:38:48 PM PDT 23
Finished Nov 01 12:38:53 PM PDT 23
Peak memory 201120 kb
Host smart-7ebdbf1d-65c6-49d8-b641-e8523c9cdc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104428162801457104057568070167399316993807615296961234270659244047902141829008 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.104428162801457104057568070167399316993807615296961234270659244047902141829008
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.36798787780859868869019429331056674904205801278865935297177969091639838077651
Short name T416
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.87 seconds
Started Nov 01 12:38:41 PM PDT 23
Finished Nov 01 12:38:45 PM PDT 23
Peak memory 201088 kb
Host smart-780e3871-e0af-4a6a-b8c8-1693d78515be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36798787780859868869019429331056674904205801278865935297177969091639838077651 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sysrst_ctrl_smoke.36798787780859868869019429331056674904205801278865935297177969091639838077651
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.2142939778579121774871623742614207479138926949022023847843834228667874464214
Short name T568
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.37 seconds
Started Nov 01 12:38:41 PM PDT 23
Finished Nov 01 12:40:58 PM PDT 23
Peak memory 201300 kb
Host smart-e8f5538d-22af-407c-af6e-21f705074825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142939778579121774871623742614207479138926949022023847843834228667874464214 -assert nopost
proc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.2142939778579121774871623742614207479138926949022023847843834228667874464214
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.10370369190603915839534586874834085461819932301890516980529743349979328999582
Short name T47
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.77 seconds
Started Nov 01 12:38:44 PM PDT 23
Finished Nov 01 12:38:50 PM PDT 23
Peak memory 201052 kb
Host smart-30cc9107-86d4-458f-90c1-e4ddb337ed3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370369190603915839534586874834085461819932301890516980529743349979328999582 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.103703691906039158395345868748340854618199323018905169805297
43349979328999582
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.58799814979085714665249795011310629092587089598757062652321035917665717968591
Short name T642
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.7 seconds
Started Nov 01 12:34:50 PM PDT 23
Finished Nov 01 12:34:56 PM PDT 23
Peak memory 200996 kb
Host smart-1e48fb5e-399e-49fd-a44f-618c60611cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58799814979085714665249795011310629092587089598757062652321035917665717968591 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.58799814979085714665249795011310629092587089598757062652321035917665717968591
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.10095298943665618419712981554068903951360555303323562759565953435728071556222
Short name T362
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.53 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:35:09 PM PDT 23
Peak memory 201108 kb
Host smart-2b59e14c-6f7a-409f-a19d-ce4bad40aacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10095298943665618419712981554068903951360555303323562759565953435728071556222 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.10095298943665618419712981554068903951360555303323562759565953435728071556222
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.21609057443625013270384891416717281595321622164669823578941264821662246392015
Short name T22
Test name
Test status
Simulation time 118289458206 ps
CPU time 182.49 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:38:14 PM PDT 23
Peak memory 201264 kb
Host smart-fb57a9fe-06dc-4aba-a0d1-f5ef00a5ac66
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609057443625013270384891416717281595321622164669823578941264821662246392015 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.216090574436250132703848914167172815953216221646698235789412648
21662246392015
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.68865828010803058182991069829228447582029746492907814421837289302512433225537
Short name T557
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.31 seconds
Started Nov 01 12:34:50 PM PDT 23
Finished Nov 01 12:34:59 PM PDT 23
Peak memory 201076 kb
Host smart-1b52bc8e-3b43-41c6-96a6-cfe3c9a62dcf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68865828010803058182991069829228447582029746492907814421837289302512433225537 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.6886582801080305818299106982922844758202974649290781442183728
9302512433225537
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1799354365030219731182580673761151046059695263565016884339521193359720883482
Short name T666
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.54 seconds
Started Nov 01 12:34:50 PM PDT 23
Finished Nov 01 12:34:59 PM PDT 23
Peak memory 200972 kb
Host smart-5be133be-1a63-490a-a051-0e5681a2dd5d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799354365030219731182580673761151046059695263565016884339521193359720883482 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.1799354365030219731182580673761151046059695263565016884339521193359720883482
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.14509897345799878500719449195398110417325505224477776173020471588761678038422
Short name T619
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Nov 01 12:34:58 PM PDT 23
Finished Nov 01 12:35:09 PM PDT 23
Peak memory 201024 kb
Host smart-352f600b-c840-42c0-99e0-6ffd8a8be386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14509897345799878500719449195398110417325505224477776173020471588761678038422 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.14509897345799878500719449195398110417325505224477776173020471588761678038422
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.93336198536383302108492098507857416071922670425312754456654682495662881822653
Short name T269
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.82 seconds
Started Nov 01 12:34:02 PM PDT 23
Finished Nov 01 12:34:10 PM PDT 23
Peak memory 201172 kb
Host smart-b3d815a3-31b5-451b-b351-e043399befe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93336198536383302108492098507857416071922670425312754456654682495662881822653 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.93336198536383302108492098507857416071922670425312754456654682495662881822653
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.85411071476549182981392332825509164783426864004107831556487190060873413208499
Short name T114
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.75 seconds
Started Nov 01 12:34:49 PM PDT 23
Finished Nov 01 12:34:54 PM PDT 23
Peak memory 201016 kb
Host smart-5e48049e-8971-4aa3-bfe8-675918fccf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85411071476549182981392332825509164783426864004107831556487190060873413208499 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.85411071476549182981392332825509164783426864004107831556487190060873413208499
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.106018354709669015032674125637587362348615634524349020725702433400751303939708
Short name T303
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.74 seconds
Started Nov 01 12:34:49 PM PDT 23
Finished Nov 01 12:34:56 PM PDT 23
Peak memory 201028 kb
Host smart-2e717a98-2308-40e1-8160-0636ef3a323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106018354709669015032674125637587362348615634524349020725702433400751303939708 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.106018354709669015032674125637587362348615634524349020725702433400751303939708
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.108167034280016400594795584169149070238440424899720672685913470303262165353115
Short name T136
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 01 12:34:02 PM PDT 23
Finished Nov 01 12:34:09 PM PDT 23
Peak memory 201104 kb
Host smart-05cf75af-6a48-4d49-8d0f-93c3c4c802e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108167034280016400594795584169149070238440424899720672685913470303262165353115 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.sysrst_ctrl_smoke.108167034280016400594795584169149070238440424899720672685913470303262165353115
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.37002590216007168381875805174266391583856962980633553038412171052849944228700
Short name T538
Test name
Test status
Simulation time 87228974549 ps
CPU time 135.5 seconds
Started Nov 01 12:34:54 PM PDT 23
Finished Nov 01 12:37:17 PM PDT 23
Peak memory 201320 kb
Host smart-860924ea-9481-426f-899a-490943469381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37002590216007168381875805174266391583856962980633553038412171052849944228700 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.37002590216007168381875805174266391583856962980633553038412171052849944228700
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.63178622432799532205406352793469684596489745256396962580371367503037090460453
Short name T213
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.83 seconds
Started Nov 01 12:34:50 PM PDT 23
Finished Nov 01 12:34:57 PM PDT 23
Peak memory 201012 kb
Host smart-817d8d7b-1529-4d44-90d3-428197f4d30e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63178622432799532205406352793469684596489745256396962580371367503037090460453 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.6317862243279953220540635279346968459648974525639696258037136
7503037090460453
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.111422786995485129067701074091947031637715526968622256363922512699913155685060
Short name T640
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.75 seconds
Started Nov 01 12:34:53 PM PDT 23
Finished Nov 01 12:35:03 PM PDT 23
Peak memory 201348 kb
Host smart-2cb598d0-537a-41df-a8a9-cf88808a86c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111422786995485129067701074091947031637715526968622256363922512699913155685060 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.111422786995485129067701074091947031637715526968622256363922512699913155685060
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.11178836654436209002466661060365762915926532547484532160002300065947771967562
Short name T111
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.5 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:35:14 PM PDT 23
Peak memory 201076 kb
Host smart-24b0f3ba-8c86-49cd-94a7-6d14f9b08155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11178836654436209002466661060365762915926532547484532160002300065947771967562 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.11178836654436209002466661060365762915926532547484532160002300065947771967562
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.43331291027714232718936277352348918564244096701087130217790697120383952378136
Short name T434
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.29 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 201272 kb
Host smart-52a1b307-9680-435f-bcc4-c5f4d016ea53
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43331291027714232718936277352348918564244096701087130217790697120383952378136 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.433312910277142327189362773523489185642440967010871302177906971
20383952378136
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1631057642337357721378992518795492891726006512811132047707858760637596120796
Short name T193
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.3 seconds
Started Nov 01 12:34:57 PM PDT 23
Finished Nov 01 12:35:11 PM PDT 23
Peak memory 201040 kb
Host smart-a573a6ac-554f-484c-9a7f-8e3968e75d18
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631057642337357721378992518795492891726006512811132047707858760637596120796 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.16310576423373577213789925187954928917260065128111320477078587
60637596120796
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.16445640117162330284812689988078282868552373926690125390684331743442001764910
Short name T547
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.19 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 201064 kb
Host smart-99e32618-21a8-4848-9a83-cf650d3b16a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16445640117162330284812689988078282868552373926690125390684331743442001764910 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.16445640117162330284812689988078282868552373926690125390684331743442001764910
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.26903460155662324077126026134812807385977198066254635844286417961439297139035
Short name T370
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.65 seconds
Started Nov 01 12:34:53 PM PDT 23
Finished Nov 01 12:35:06 PM PDT 23
Peak memory 201064 kb
Host smart-83d7a34c-afdb-46ca-9465-4ed162f519c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26903460155662324077126026134812807385977198066254635844286417961439297139035 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.26903460155662324077126026134812807385977198066254635844286417961439297139035
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.45586237612840809317551342578758949456963258912753866426493286602874893249185
Short name T119
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.79 seconds
Started Nov 01 12:34:50 PM PDT 23
Finished Nov 01 12:34:57 PM PDT 23
Peak memory 201048 kb
Host smart-ec52b49c-ef18-4231-bdcf-b7ea3d2b464a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45586237612840809317551342578758949456963258912753866426493286602874893249185 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.45586237612840809317551342578758949456963258912753866426493286602874893249185
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3966242886812716796383192912455764554693008177434292419472867643758368632480
Short name T649
Test name
Test status
Simulation time 2074566504 ps
CPU time 4.24 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:35:08 PM PDT 23
Peak memory 201004 kb
Host smart-5bd5d68c-8365-4595-aa92-90744aeeadc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966242886812716796383192912455764554693008177434292419472867643758368632480 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3966242886812716796383192912455764554693008177434292419472867643758368632480
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.75178447465144345994646047276235132731766341173198296059808867360131159704372
Short name T632
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.63 seconds
Started Nov 01 12:34:49 PM PDT 23
Finished Nov 01 12:34:56 PM PDT 23
Peak memory 201124 kb
Host smart-860dd030-5c44-4d35-afa5-41631ba2f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75178447465144345994646047276235132731766341173198296059808867360131159704372 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.75178447465144345994646047276235132731766341173198296059808867360131159704372
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.45983038775400199647905019789607006171014800972447723653474850773339714604569
Short name T223
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.89 seconds
Started Nov 01 12:34:51 PM PDT 23
Finished Nov 01 12:34:57 PM PDT 23
Peak memory 200972 kb
Host smart-71d0daad-1bdd-4f58-b934-2f28e345b0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45983038775400199647905019789607006171014800972447723653474850773339714604569 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_smoke.45983038775400199647905019789607006171014800972447723653474850773339714604569
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.21671284644160493830900053292900943196398936851948886608568480044104096004097
Short name T225
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.28 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:37:18 PM PDT 23
Peak memory 201308 kb
Host smart-aa4c2bcc-ccf4-47f7-b344-bf6f1b69ee0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21671284644160493830900053292900943196398936851948886608568480044104096004097 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.21671284644160493830900053292900943196398936851948886608568480044104096004097
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1251788972693755660354089018511628934536678625849360929409643952408248247131
Short name T51
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.81 seconds
Started Nov 01 12:34:55 PM PDT 23
Finished Nov 01 12:35:08 PM PDT 23
Peak memory 201056 kb
Host smart-793003b1-4d97-4147-aeab-39cc3ba4b22d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251788972693755660354089018511628934536678625849360929409643952408248247131 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.12517889726937556603540890185116289345366786258493609294096439
52408248247131
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.37286739605729095067391462545182233628991085001089733374721200704441552351420
Short name T668
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.71 seconds
Started Nov 01 12:34:55 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 201080 kb
Host smart-2eb6d10e-4811-4a74-a2e4-c870827c7c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286739605729095067391462545182233628991085001089733374721200704441552351420 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.37286739605729095067391462545182233628991085001089733374721200704441552351420
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.85952868764142230914112535720516877041808014016188475297037696676789575923619
Short name T356
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.41 seconds
Started Nov 01 12:35:01 PM PDT 23
Finished Nov 01 12:35:12 PM PDT 23
Peak memory 201232 kb
Host smart-b39689d7-cf8e-4237-a1e7-b3e6bdb6ab0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85952868764142230914112535720516877041808014016188475297037696676789575923619 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.85952868764142230914112535720516877041808014016188475297037696676789575923619
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.33313456971381510648089908728729976849116314777499365292348889998605213894553
Short name T226
Test name
Test status
Simulation time 118289458206 ps
CPU time 185.06 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:38:17 PM PDT 23
Peak memory 201464 kb
Host smart-3df558c1-223f-423a-ac0e-b3e02cb73c8d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33313456971381510648089908728729976849116314777499365292348889998605213894553 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.333134569713815106480899087287299768491163147774993652923488899
98605213894553
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.68074993718377696562864890368373262298242125130121372785495292122360559404344
Short name T450
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201088 kb
Host smart-36a8954c-7278-4929-b36d-d8bb5ae56682
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68074993718377696562864890368373262298242125130121372785495292122360559404344 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.6807499371837769656286489036837326229824212513012137278549529
2122360559404344
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.32487657493569297984491204731281399571775669937536901171160886100087780949418
Short name T18
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.32 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:18 PM PDT 23
Peak memory 201000 kb
Host smart-719c1b8a-1ff6-4ba2-9cb6-2f4dca03d4b4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32487657493569297984491204731281399571775669937536901171160886100087780949418 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.32487657493569297984491204731281399571775669937536901171160886100087780949418
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.36293074612858039018498963074896408496030552227472742100588809259524744675062
Short name T534
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.67 seconds
Started Nov 01 12:35:02 PM PDT 23
Finished Nov 01 12:35:13 PM PDT 23
Peak memory 201152 kb
Host smart-b00dada9-d6b4-40f0-830b-52315ed246a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36293074612858039018498963074896408496030552227472742100588809259524744675062 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.36293074612858039018498963074896408496030552227472742100588809259524744675062
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.9038569542078318456229685802150911077718412318702614015325744280910535639281
Short name T514
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.99 seconds
Started Nov 01 12:34:50 PM PDT 23
Finished Nov 01 12:34:58 PM PDT 23
Peak memory 201072 kb
Host smart-cccf6308-a6a7-41d1-ae64-8c15e96edd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9038569542078318456229685802150911077718412318702614015325744280910535639281 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.9038569542078318456229685802150911077718412318702614015325744280910535639281
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.114454473803766288053076166652883558816998065942783983205471828602767897779007
Short name T418
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.8 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 201044 kb
Host smart-4331c6e4-75d3-484e-9f22-2edf73e53425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114454473803766288053076166652883558816998065942783983205471828602767897779007 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.114454473803766288053076166652883558816998065942783983205471828602767897779007
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.23710590822667388773083458064934472587440899847512599856037062565691279688068
Short name T459
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.61 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 200988 kb
Host smart-bae68ad3-26a7-4494-9ad9-f06e465f74d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23710590822667388773083458064934472587440899847512599856037062565691279688068 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.23710590822667388773083458064934472587440899847512599856037062565691279688068
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.96148117840701035822692868664170457504786282256957877124496685938130465270581
Short name T179
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.78 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 200952 kb
Host smart-45ec85d8-ddb9-4443-87d6-26b7e3dc51b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96148117840701035822692868664170457504786282256957877124496685938130465270581 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_smoke.96148117840701035822692868664170457504786282256957877124496685938130465270581
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.32333462888006184986751885406037282445929768114606272482396185219011973519615
Short name T243
Test name
Test status
Simulation time 87228974549 ps
CPU time 133.6 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:37:26 PM PDT 23
Peak memory 201312 kb
Host smart-a4997211-89de-4c0d-8c45-91654b6e4a79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32333462888006184986751885406037282445929768114606272482396185219011973519615 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.32333462888006184986751885406037282445929768114606272482396185219011973519615
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.115048155304410006610644455180431570530330365383414546492059287377994662322799
Short name T463
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.68 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 201056 kb
Host smart-54484060-aeb7-4456-bd3c-ba2fec32c1a5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115048155304410006610644455180431570530330365383414546492059287377994662322799 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.115048155304410006610644455180431570530330365383414546492059
287377994662322799
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.76798753016307940957791072546613846368279234568917040180981180732958480968129
Short name T164
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.65 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 201016 kb
Host smart-07c93e15-4213-41de-8ddf-5c14eff702c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76798753016307940957791072546613846368279234568917040180981180732958480968129 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.76798753016307940957791072546613846368279234568917040180981180732958480968129
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.56968704641368529144995489725131054294046466433427176294038193909621556817653
Short name T99
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.55 seconds
Started Nov 01 12:34:52 PM PDT 23
Finished Nov 01 12:34:59 PM PDT 23
Peak memory 201100 kb
Host smart-0c30e75b-4807-4b5a-8758-3192cb1a4724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56968704641368529144995489725131054294046466433427176294038193909621556817653 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.56968704641368529144995489725131054294046466433427176294038193909621556817653
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.90163642445897448743180219588537429849220926278379143439131312872627708283314
Short name T466
Test name
Test status
Simulation time 118289458206 ps
CPU time 181.73 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 201252 kb
Host smart-711621de-4a94-405a-b278-c3187d0da072
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90163642445897448743180219588537429849220926278379143439131312872627708283314 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.901636424458974487431802195885374298492209262783791434391313128
72627708283314
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.56558230742221901605352084297308066577516378570874880450123912931557796429761
Short name T488
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.33 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:35:11 PM PDT 23
Peak memory 201196 kb
Host smart-be033353-f062-4b7d-96b6-80083d9b195e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56558230742221901605352084297308066577516378570874880450123912931557796429761 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.5655823074222190160535208429730806657751637857087488045012391
2931557796429761
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.6406976784569743148137012601509577929456687165169598451037115240125968964212
Short name T242
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.29 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:35:12 PM PDT 23
Peak memory 201068 kb
Host smart-80d40575-7bf1-4d78-9619-ef8901b624ec
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6406976784569743148137012601509577929456687165169598451037115240125968964212 -assert nop
ostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.6406976784569743148137012601509577929456687165169598451037115240125968964212
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.101628188312032823182833399713096179017060148981357147988876193494189939074559
Short name T124
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.66 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:35:11 PM PDT 23
Peak memory 201072 kb
Host smart-2c256051-a412-4913-bd85-39691e56ce86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101628188312032823182833399713096179017060148981357147988876193494189939074559 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.101628188312032823182833399713096179017060148981357147988876193494189939074559
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.14614972010312097269984064829213661924221631922729157010489694927123503188185
Short name T281
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.8 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 200948 kb
Host smart-f0a864ff-accc-487a-9311-3ce52ce8476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14614972010312097269984064829213661924221631922729157010489694927123503188185 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.14614972010312097269984064829213661924221631922729157010489694927123503188185
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.110291498435233873535213030552644468745183269746707047204007437606159344937077
Short name T614
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.79 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 200888 kb
Host smart-36334f88-d0b2-4df9-8056-024bd9956bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110291498435233873535213030552644468745183269746707047204007437606159344937077 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.110291498435233873535213030552644468745183269746707047204007437606159344937077
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.24038803389504920397135256439680731434906015322434147863343472614541188027921
Short name T126
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.54 seconds
Started Nov 01 12:34:54 PM PDT 23
Finished Nov 01 12:35:08 PM PDT 23
Peak memory 201068 kb
Host smart-98b872c2-5776-4ab5-b960-8e97d6d92e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24038803389504920397135256439680731434906015322434147863343472614541188027921 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm
_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.24038803389504920397135256439680731434906015322434147863343472614541188027921
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.5024457720897732932038330244466364267063482826228288606737306157463272134446
Short name T529
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.83 seconds
Started Nov 01 12:34:57 PM PDT 23
Finished Nov 01 12:35:07 PM PDT 23
Peak memory 200848 kb
Host smart-095e75c0-60a9-4fc9-a8cf-4def3ab9a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5024457720897732932038330244466364267063482826228288606737306157463272134446 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 8.sysrst_ctrl_smoke.5024457720897732932038330244466364267063482826228288606737306157463272134446
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.114500717474323799371582721739714638416299850740339426918046928614134819826105
Short name T677
Test name
Test status
Simulation time 87228974549 ps
CPU time 134.16 seconds
Started Nov 01 12:34:58 PM PDT 23
Finished Nov 01 12:37:18 PM PDT 23
Peak memory 201356 kb
Host smart-2287a0e7-438c-4e2c-9209-46fb60cfbc21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114500717474323799371582721739714638416299850740339426918046928614134819826105 -assert nopo
stproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.114500717474323799371582721739714638416299850740339426918046928614134819826105
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.12932110389800044190120850101152217059768501421322430431970881233087400814299
Short name T48
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.78 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:17 PM PDT 23
Peak memory 201000 kb
Host smart-d1e323fe-522e-4421-9947-99ce84120bda
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12932110389800044190120850101152217059768501421322430431970881233087400814299 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.1293211038980004419012085010115221705976850142132243043197088
1233087400814299
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.28583422448094564168510613047157404584875021826706710733804513916884837904641
Short name T112
Test name
Test status
Simulation time 2015424120 ps
CPU time 3.67 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 201088 kb
Host smart-a42548b9-1e87-4783-bfb4-2f14e04cca9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28583422448094564168510613047157404584875021826706710733804513916884837904641 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.28583422448094564168510613047157404584875021826706710733804513916884837904641
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.8409671363132677617488087202463096646537073960639942906651075234806113957820
Short name T657
Test name
Test status
Simulation time 3138968703 ps
CPU time 5.43 seconds
Started Nov 01 12:35:03 PM PDT 23
Finished Nov 01 12:35:15 PM PDT 23
Peak memory 201068 kb
Host smart-c5f07bf2-26e7-4c69-9141-9138638e0211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8409671363132677617488087202463096646537073960639942906651075234806113957820 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.8409671363132677617488087202463096646537073960639942906651075234806113957820
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.21827960012967448051217538676385227989259006624585023952354857003496117055219
Short name T578
Test name
Test status
Simulation time 118289458206 ps
CPU time 184.03 seconds
Started Nov 01 12:34:56 PM PDT 23
Finished Nov 01 12:38:08 PM PDT 23
Peak memory 201304 kb
Host smart-b781cdc3-2bd2-4d65-acfd-b1de536d775a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21827960012967448051217538676385227989259006624585023952354857003496117055219 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.218279600129674480512175386763852279892590066245850239523548570
03496117055219
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.57542231959030659608963660826562089062381248661336892533400633953104208610087
Short name T72
Test name
Test status
Simulation time 4425119128 ps
CPU time 7.46 seconds
Started Nov 01 12:35:06 PM PDT 23
Finished Nov 01 12:35:20 PM PDT 23
Peak memory 201032 kb
Host smart-c86c72a2-3277-4168-b1e5-ec9558a9a144
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57542231959030659608963660826562089062381248661336892533400633953104208610087 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.5754223195903065960896366082656208906238124866133689253340063
3953104208610087
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.92502412032710048713637657706999653406124215022761308671815860199406245493162
Short name T587
Test name
Test status
Simulation time 4089103959 ps
CPU time 6.33 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 199928 kb
Host smart-a81c40ff-a70f-496b-b57a-6ae72a4806c2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92502412032710048713637657706999653406124215022761308671815860199406245493162 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.92502412032710048713637657706999653406124215022761308671815860199406245493162
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.63246981943078113141659832273826855417875915934534786054567054154337341860646
Short name T292
Test name
Test status
Simulation time 2619740714 ps
CPU time 4.56 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:35:14 PM PDT 23
Peak memory 201036 kb
Host smart-dcd6ba36-6c8c-4cca-848e-1cf5bb39ceb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63246981943078113141659832273826855417875915934534786054567054154337341860646 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.63246981943078113141659832273826855417875915934534786054567054154337341860646
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.95544031383277518670585197717168575548156284818488222217848077712354175014948
Short name T552
Test name
Test status
Simulation time 2470384766 ps
CPU time 4.77 seconds
Started Nov 01 12:35:03 PM PDT 23
Finished Nov 01 12:35:14 PM PDT 23
Peak memory 201080 kb
Host smart-c7a79fb1-5266-4931-8cb7-773ca7877a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95544031383277518670585197717168575548156284818488222217848077712354175014948 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.95544031383277518670585197717168575548156284818488222217848077712354175014948
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.109328745338234939823168898203818027340721986248515214569328415395914540573697
Short name T192
Test name
Test status
Simulation time 2074566504 ps
CPU time 3.77 seconds
Started Nov 01 12:35:04 PM PDT 23
Finished Nov 01 12:35:14 PM PDT 23
Peak memory 200128 kb
Host smart-cdaa3316-baaa-4ea5-9aed-101218488885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109328745338234939823168898203818027340721986248515214569328415395914540573697 -assert nopostproc +UVM_TESTNAME=sysrst_c
trl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.109328745338234939823168898203818027340721986248515214569328415395914540573697
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.9846240425317258315945529981962477477904711877808039094420508663083562926159
Short name T334
Test name
Test status
Simulation time 2515402263 ps
CPU time 4.55 seconds
Started Nov 01 12:35:03 PM PDT 23
Finished Nov 01 12:35:14 PM PDT 23
Peak memory 201052 kb
Host smart-681ff710-f199-48e3-a04f-975036062c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9846240425317258315945529981962477477904711877808039094420508663083562926159 -assert nopostproc +UVM_TESTNAME=sysrst_ctr
l_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.9846240425317258315945529981962477477904711877808039094420508663083562926159
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.81347692878025404611779809578591622686141576674671411530121604822303642343793
Short name T484
Test name
Test status
Simulation time 2116887594 ps
CPU time 3.8 seconds
Started Nov 01 12:35:00 PM PDT 23
Finished Nov 01 12:35:10 PM PDT 23
Peak memory 201096 kb
Host smart-b48f649c-dbbb-4642-b4e0-ca0ed31d8fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81347692878025404611779809578591622686141576674671411530121604822303642343793 -assert nopostproc +UVM_TESTNAME=sysrst_ct
rl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_smoke.81347692878025404611779809578591622686141576674671411530121604822303642343793
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.13359803432318916970083615825404925140772680352171395407848891064361107236163
Short name T149
Test name
Test status
Simulation time 87228974549 ps
CPU time 136.03 seconds
Started Nov 01 12:34:57 PM PDT 23
Finished Nov 01 12:37:20 PM PDT 23
Peak memory 201348 kb
Host smart-3d829998-1593-4206-9488-51d778e8eb6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359803432318916970083615825404925140772680352171395407848891064361107236163 -assert nopos
tproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.13359803432318916970083615825404925140772680352171395407848891064361107236163
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.103396002941042664682899318256500949274732594308708515030919446845366223080113
Short name T654
Test name
Test status
Simulation time 5189470156 ps
CPU time 4.69 seconds
Started Nov 01 12:35:05 PM PDT 23
Finished Nov 01 12:35:16 PM PDT 23
Peak memory 201064 kb
Host smart-e4ec2c76-2a5a-480d-bce3-7de35f06c58b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103396002941042664682899318256500949274732594308708515030919446845366223080113 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.103396002941042664682899318256500949274732594308708515030919
446845366223080113
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest
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