Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T79 |
8 |
|
T69 |
13 |
|
T80 |
12 |
| auto[1] |
880 |
1 |
|
|
T79 |
12 |
|
T69 |
7 |
|
T80 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T79 |
8 |
|
T69 |
10 |
|
T80 |
8 |
| auto[1] |
892 |
1 |
|
|
T79 |
12 |
|
T69 |
10 |
|
T80 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T79 |
10 |
|
T69 |
8 |
|
T80 |
11 |
| auto[1] |
899 |
1 |
|
|
T79 |
10 |
|
T69 |
12 |
|
T80 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
864 |
1 |
|
|
T79 |
9 |
|
T69 |
6 |
|
T80 |
9 |
| auto[1] |
869 |
1 |
|
|
T79 |
11 |
|
T69 |
14 |
|
T80 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T79 |
11 |
|
T69 |
12 |
|
T80 |
13 |
| auto[1] |
848 |
1 |
|
|
T79 |
9 |
|
T69 |
8 |
|
T80 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T79 |
12 |
|
T69 |
7 |
|
T80 |
8 |
| auto[1] |
901 |
1 |
|
|
T79 |
8 |
|
T69 |
13 |
|
T80 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
881 |
1 |
|
|
T79 |
12 |
|
T69 |
10 |
|
T80 |
7 |
| auto[1] |
852 |
1 |
|
|
T79 |
8 |
|
T69 |
10 |
|
T80 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T79 |
12 |
|
T69 |
6 |
|
T80 |
7 |
| auto[1] |
845 |
1 |
|
|
T79 |
8 |
|
T69 |
14 |
|
T80 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T79 |
8 |
|
T69 |
14 |
|
T80 |
6 |
| auto[1] |
919 |
1 |
|
|
T79 |
12 |
|
T69 |
6 |
|
T80 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T79 |
16 |
|
T69 |
12 |
|
T80 |
10 |
| auto[1] |
875 |
1 |
|
|
T79 |
4 |
|
T69 |
8 |
|
T80 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T79 |
13 |
|
T69 |
9 |
|
T80 |
12 |
| auto[1] |
901 |
1 |
|
|
T79 |
7 |
|
T69 |
11 |
|
T80 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T79 |
10 |
|
T69 |
14 |
|
T80 |
8 |
| auto[1] |
885 |
1 |
|
|
T79 |
10 |
|
T69 |
6 |
|
T80 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T79 |
11 |
|
T69 |
10 |
|
T80 |
11 |
| auto[1] |
834 |
1 |
|
|
T79 |
9 |
|
T69 |
10 |
|
T80 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T79 |
8 |
|
T69 |
10 |
|
T80 |
8 |
| auto[1] |
892 |
1 |
|
|
T79 |
12 |
|
T69 |
10 |
|
T80 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T79 |
12 |
|
T69 |
11 |
|
T80 |
7 |
| auto[1] |
840 |
1 |
|
|
T79 |
8 |
|
T69 |
9 |
|
T80 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T79 |
9 |
|
T69 |
11 |
|
T80 |
7 |
| auto[1] |
842 |
1 |
|
|
T79 |
11 |
|
T69 |
9 |
|
T80 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T79 |
8 |
|
T69 |
7 |
|
T80 |
10 |
| auto[1] |
875 |
1 |
|
|
T79 |
12 |
|
T69 |
13 |
|
T80 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T79 |
9 |
|
T69 |
10 |
|
T80 |
11 |
| auto[1] |
880 |
1 |
|
|
T79 |
11 |
|
T69 |
10 |
|
T80 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
874 |
1 |
|
|
T79 |
9 |
|
T69 |
11 |
|
T80 |
9 |
| auto[1] |
859 |
1 |
|
|
T79 |
11 |
|
T69 |
9 |
|
T80 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
827 |
1 |
|
|
T79 |
5 |
|
T69 |
7 |
|
T80 |
11 |
| auto[1] |
906 |
1 |
|
|
T79 |
15 |
|
T69 |
13 |
|
T80 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
899 |
1 |
|
|
T79 |
13 |
|
T69 |
12 |
|
T80 |
14 |
| auto[1] |
834 |
1 |
|
|
T79 |
7 |
|
T69 |
8 |
|
T80 |
6 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
873 |
1 |
|
|
T79 |
6 |
|
T69 |
9 |
|
T80 |
12 |
| auto[1] |
860 |
1 |
|
|
T79 |
14 |
|
T69 |
11 |
|
T80 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
847 |
1 |
|
|
T79 |
3 |
|
T69 |
8 |
|
T80 |
8 |
| auto[1] |
886 |
1 |
|
|
T79 |
17 |
|
T69 |
12 |
|
T80 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
848 |
1 |
|
|
T79 |
10 |
|
T69 |
14 |
|
T80 |
8 |
| auto[1] |
885 |
1 |
|
|
T79 |
10 |
|
T69 |
6 |
|
T80 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
440 |
1 |
|
|
T79 |
6 |
|
T69 |
4 |
|
T80 |
4 |
| auto[0] |
auto[1] |
453 |
1 |
|
|
T79 |
6 |
|
T69 |
7 |
|
T80 |
3 |
| auto[1] |
auto[0] |
394 |
1 |
|
|
T79 |
4 |
|
T69 |
4 |
|
T80 |
7 |
| auto[1] |
auto[1] |
446 |
1 |
|
|
T79 |
4 |
|
T69 |
5 |
|
T80 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
454 |
1 |
|
|
T79 |
4 |
|
T69 |
3 |
|
T80 |
3 |
| auto[0] |
auto[1] |
437 |
1 |
|
|
T79 |
5 |
|
T69 |
8 |
|
T80 |
4 |
| auto[1] |
auto[0] |
410 |
1 |
|
|
T79 |
5 |
|
T69 |
3 |
|
T80 |
6 |
| auto[1] |
auto[1] |
432 |
1 |
|
|
T79 |
6 |
|
T69 |
6 |
|
T80 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T79 |
4 |
|
T69 |
2 |
|
T80 |
7 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T79 |
4 |
|
T69 |
5 |
|
T80 |
3 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T79 |
7 |
|
T69 |
10 |
|
T80 |
6 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T79 |
5 |
|
T69 |
3 |
|
T80 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
410 |
1 |
|
|
T79 |
5 |
|
T69 |
1 |
|
T80 |
5 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T79 |
4 |
|
T69 |
9 |
|
T80 |
6 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T79 |
7 |
|
T69 |
6 |
|
T80 |
3 |
| auto[1] |
auto[1] |
458 |
1 |
|
|
T79 |
4 |
|
T69 |
4 |
|
T80 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
451 |
1 |
|
|
T79 |
5 |
|
T69 |
5 |
|
T80 |
2 |
| auto[0] |
auto[1] |
423 |
1 |
|
|
T79 |
4 |
|
T69 |
6 |
|
T80 |
7 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T79 |
7 |
|
T69 |
5 |
|
T80 |
5 |
| auto[1] |
auto[1] |
429 |
1 |
|
|
T79 |
4 |
|
T69 |
4 |
|
T80 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T79 |
3 |
|
T69 |
1 |
|
T80 |
3 |
| auto[0] |
auto[1] |
396 |
1 |
|
|
T79 |
2 |
|
T69 |
6 |
|
T80 |
8 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T79 |
9 |
|
T69 |
5 |
|
T80 |
4 |
| auto[1] |
auto[1] |
449 |
1 |
|
|
T79 |
6 |
|
T69 |
8 |
|
T80 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
429 |
1 |
|
|
T79 |
5 |
|
T69 |
6 |
|
T80 |
6 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T79 |
1 |
|
T69 |
3 |
|
T80 |
6 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T79 |
11 |
|
T69 |
6 |
|
T80 |
4 |
| auto[1] |
auto[1] |
431 |
1 |
|
|
T79 |
3 |
|
T69 |
5 |
|
T80 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
403 |
1 |
|
|
T79 |
2 |
|
T69 |
4 |
|
T80 |
5 |
| auto[0] |
auto[1] |
444 |
1 |
|
|
T79 |
1 |
|
T69 |
4 |
|
T80 |
3 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T79 |
11 |
|
T69 |
5 |
|
T80 |
7 |
| auto[1] |
auto[1] |
457 |
1 |
|
|
T79 |
6 |
|
T69 |
7 |
|
T80 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T79 |
4 |
|
T69 |
7 |
|
T80 |
6 |
| auto[0] |
auto[1] |
457 |
1 |
|
|
T79 |
7 |
|
T69 |
3 |
|
T80 |
5 |
| auto[1] |
auto[0] |
411 |
1 |
|
|
T79 |
4 |
|
T69 |
6 |
|
T80 |
6 |
| auto[1] |
auto[1] |
423 |
1 |
|
|
T79 |
5 |
|
T69 |
4 |
|
T80 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
841 |
1 |
|
|
T79 |
8 |
|
T69 |
10 |
|
T80 |
8 |
| auto[1] |
auto[1] |
892 |
1 |
|
|
T79 |
12 |
|
T69 |
10 |
|
T80 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T79 |
6 |
|
T69 |
9 |
|
T80 |
5 |
| auto[0] |
auto[1] |
465 |
1 |
|
|
T79 |
7 |
|
T69 |
3 |
|
T80 |
9 |
| auto[1] |
auto[0] |
380 |
1 |
|
|
T79 |
2 |
|
T69 |
5 |
|
T80 |
1 |
| auto[1] |
auto[1] |
454 |
1 |
|
|
T79 |
5 |
|
T69 |
3 |
|
T80 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
848 |
1 |
|
|
T79 |
10 |
|
T69 |
14 |
|
T80 |
8 |
| auto[1] |
auto[1] |
885 |
1 |
|
|
T79 |
10 |
|
T69 |
6 |
|
T80 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T45 |
12 |
|
T98 |
8 |
|
T188 |
9 |
| auto[1] |
131 |
1 |
|
|
T45 |
8 |
|
T98 |
12 |
|
T188 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T45 |
10 |
|
T98 |
10 |
|
T188 |
7 |
| auto[1] |
139 |
1 |
|
|
T45 |
10 |
|
T98 |
10 |
|
T188 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T45 |
9 |
|
T98 |
11 |
|
T188 |
9 |
| auto[1] |
129 |
1 |
|
|
T45 |
11 |
|
T98 |
9 |
|
T188 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T45 |
11 |
|
T98 |
12 |
|
T188 |
12 |
| auto[1] |
124 |
1 |
|
|
T45 |
9 |
|
T98 |
8 |
|
T188 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
139 |
1 |
|
|
T45 |
10 |
|
T98 |
13 |
|
T188 |
10 |
| auto[1] |
121 |
1 |
|
|
T45 |
10 |
|
T98 |
7 |
|
T188 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T45 |
6 |
|
T98 |
8 |
|
T188 |
11 |
| auto[1] |
130 |
1 |
|
|
T45 |
14 |
|
T98 |
12 |
|
T188 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
133 |
1 |
|
|
T45 |
11 |
|
T98 |
11 |
|
T188 |
11 |
| auto[1] |
127 |
1 |
|
|
T45 |
9 |
|
T98 |
9 |
|
T188 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T45 |
11 |
|
T98 |
14 |
|
T188 |
15 |
| auto[1] |
113 |
1 |
|
|
T45 |
9 |
|
T98 |
6 |
|
T188 |
5 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T45 |
11 |
|
T98 |
14 |
|
T188 |
13 |
| auto[1] |
129 |
1 |
|
|
T45 |
9 |
|
T98 |
6 |
|
T188 |
7 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T45 |
9 |
|
T98 |
12 |
|
T188 |
10 |
| auto[1] |
134 |
1 |
|
|
T45 |
11 |
|
T98 |
8 |
|
T188 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T45 |
15 |
|
T98 |
8 |
|
T188 |
10 |
| auto[1] |
129 |
1 |
|
|
T45 |
5 |
|
T98 |
12 |
|
T188 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T45 |
7 |
|
T98 |
12 |
|
T188 |
12 |
| auto[1] |
118 |
1 |
|
|
T45 |
13 |
|
T98 |
8 |
|
T188 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T45 |
5 |
|
T98 |
8 |
|
T188 |
10 |
| auto[1] |
139 |
1 |
|
|
T45 |
15 |
|
T98 |
12 |
|
T188 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
121 |
1 |
|
|
T45 |
10 |
|
T98 |
10 |
|
T188 |
7 |
| auto[1] |
139 |
1 |
|
|
T45 |
10 |
|
T98 |
10 |
|
T188 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
116 |
1 |
|
|
T45 |
8 |
|
T98 |
8 |
|
T188 |
8 |
| auto[1] |
144 |
1 |
|
|
T45 |
12 |
|
T98 |
12 |
|
T188 |
12 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T45 |
10 |
|
T98 |
9 |
|
T188 |
11 |
| auto[1] |
123 |
1 |
|
|
T45 |
10 |
|
T98 |
11 |
|
T188 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
126 |
1 |
|
|
T45 |
6 |
|
T98 |
10 |
|
T188 |
9 |
| auto[1] |
134 |
1 |
|
|
T45 |
14 |
|
T98 |
10 |
|
T188 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T45 |
8 |
|
T98 |
11 |
|
T188 |
10 |
| auto[1] |
125 |
1 |
|
|
T45 |
12 |
|
T98 |
9 |
|
T188 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T45 |
10 |
|
T98 |
11 |
|
T188 |
10 |
| auto[1] |
133 |
1 |
|
|
T45 |
10 |
|
T98 |
9 |
|
T188 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T45 |
12 |
|
T98 |
12 |
|
T188 |
10 |
| auto[1] |
123 |
1 |
|
|
T45 |
8 |
|
T98 |
8 |
|
T188 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T45 |
8 |
|
T98 |
10 |
|
T188 |
8 |
| auto[1] |
123 |
1 |
|
|
T45 |
12 |
|
T98 |
10 |
|
T188 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T45 |
8 |
|
T98 |
9 |
|
T188 |
11 |
| auto[1] |
122 |
1 |
|
|
T45 |
12 |
|
T98 |
11 |
|
T188 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T45 |
8 |
|
T98 |
11 |
|
T188 |
11 |
| auto[1] |
129 |
1 |
|
|
T45 |
12 |
|
T98 |
9 |
|
T188 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T45 |
7 |
|
T98 |
12 |
|
T188 |
12 |
| auto[1] |
118 |
1 |
|
|
T45 |
13 |
|
T98 |
8 |
|
T188 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
59 |
1 |
|
|
T45 |
5 |
|
T98 |
4 |
|
T188 |
4 |
| auto[0] |
auto[1] |
57 |
1 |
|
|
T45 |
3 |
|
T98 |
4 |
|
T188 |
4 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T45 |
4 |
|
T98 |
7 |
|
T188 |
5 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T45 |
8 |
|
T98 |
5 |
|
T188 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T45 |
7 |
|
T98 |
5 |
|
T188 |
7 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T45 |
3 |
|
T98 |
4 |
|
T188 |
4 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T45 |
4 |
|
T98 |
7 |
|
T188 |
5 |
| auto[1] |
auto[1] |
59 |
1 |
|
|
T45 |
6 |
|
T98 |
4 |
|
T188 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T45 |
3 |
|
T98 |
8 |
|
T188 |
7 |
| auto[0] |
auto[1] |
60 |
1 |
|
|
T45 |
3 |
|
T98 |
2 |
|
T188 |
2 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T45 |
7 |
|
T98 |
5 |
|
T188 |
3 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T45 |
7 |
|
T98 |
5 |
|
T188 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T45 |
2 |
|
T98 |
6 |
|
T188 |
8 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T45 |
6 |
|
T98 |
5 |
|
T188 |
2 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T45 |
4 |
|
T98 |
2 |
|
T188 |
3 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T45 |
8 |
|
T98 |
7 |
|
T188 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T45 |
6 |
|
T98 |
7 |
|
T188 |
4 |
| auto[0] |
auto[1] |
64 |
1 |
|
|
T45 |
4 |
|
T98 |
4 |
|
T188 |
6 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T45 |
5 |
|
T98 |
4 |
|
T188 |
7 |
| auto[1] |
auto[1] |
63 |
1 |
|
|
T45 |
5 |
|
T98 |
5 |
|
T188 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T45 |
7 |
|
T98 |
9 |
|
T188 |
6 |
| auto[0] |
auto[1] |
62 |
1 |
|
|
T45 |
5 |
|
T98 |
3 |
|
T188 |
4 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T45 |
4 |
|
T98 |
5 |
|
T188 |
9 |
| auto[1] |
auto[1] |
51 |
1 |
|
|
T45 |
4 |
|
T98 |
3 |
|
T188 |
1 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T45 |
4 |
|
T98 |
6 |
|
T188 |
7 |
| auto[0] |
auto[1] |
73 |
1 |
|
|
T45 |
4 |
|
T98 |
3 |
|
T188 |
4 |
| auto[1] |
auto[0] |
61 |
1 |
|
|
T45 |
5 |
|
T98 |
6 |
|
T188 |
3 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T45 |
7 |
|
T98 |
5 |
|
T188 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
64 |
1 |
|
|
T45 |
7 |
|
T98 |
5 |
|
T188 |
7 |
| auto[0] |
auto[1] |
67 |
1 |
|
|
T45 |
1 |
|
T98 |
6 |
|
T188 |
4 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T45 |
8 |
|
T98 |
3 |
|
T188 |
3 |
| auto[1] |
auto[1] |
62 |
1 |
|
|
T45 |
4 |
|
T98 |
6 |
|
T188 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
63 |
1 |
|
|
T45 |
2 |
|
T98 |
4 |
|
T188 |
5 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T45 |
3 |
|
T98 |
4 |
|
T188 |
5 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T45 |
10 |
|
T98 |
4 |
|
T188 |
4 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T45 |
5 |
|
T98 |
8 |
|
T188 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
121 |
1 |
|
|
T45 |
10 |
|
T98 |
10 |
|
T188 |
7 |
| auto[1] |
auto[1] |
139 |
1 |
|
|
T45 |
10 |
|
T98 |
10 |
|
T188 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T45 |
5 |
|
T98 |
8 |
|
T188 |
5 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T45 |
3 |
|
T98 |
2 |
|
T188 |
3 |
| auto[1] |
auto[0] |
62 |
1 |
|
|
T45 |
6 |
|
T98 |
6 |
|
T188 |
8 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T45 |
6 |
|
T98 |
4 |
|
T188 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
142 |
1 |
|
|
T45 |
7 |
|
T98 |
12 |
|
T188 |
12 |
| auto[1] |
auto[1] |
118 |
1 |
|
|
T45 |
13 |
|
T98 |
8 |
|
T188 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T45 |
11 |
|
T98 |
8 |
|
T96 |
11 |
| auto[1] |
75 |
1 |
|
|
T45 |
9 |
|
T98 |
12 |
|
T96 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T45 |
11 |
|
T98 |
9 |
|
T96 |
11 |
| auto[1] |
79 |
1 |
|
|
T45 |
9 |
|
T98 |
11 |
|
T96 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T45 |
15 |
|
T98 |
7 |
|
T96 |
16 |
| auto[1] |
69 |
1 |
|
|
T45 |
5 |
|
T98 |
13 |
|
T96 |
4 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T45 |
9 |
|
T98 |
11 |
|
T96 |
12 |
| auto[1] |
80 |
1 |
|
|
T45 |
11 |
|
T98 |
9 |
|
T96 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T45 |
13 |
|
T98 |
11 |
|
T96 |
10 |
| auto[1] |
73 |
1 |
|
|
T45 |
7 |
|
T98 |
9 |
|
T96 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T45 |
12 |
|
T98 |
12 |
|
T96 |
13 |
| auto[1] |
71 |
1 |
|
|
T45 |
8 |
|
T98 |
8 |
|
T96 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T45 |
4 |
|
T98 |
11 |
|
T96 |
11 |
| auto[1] |
86 |
1 |
|
|
T45 |
16 |
|
T98 |
9 |
|
T96 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
78 |
1 |
|
|
T45 |
8 |
|
T98 |
10 |
|
T96 |
6 |
| auto[1] |
82 |
1 |
|
|
T45 |
12 |
|
T98 |
10 |
|
T96 |
14 |