Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T59 |
6 |
|
T70 |
9 |
|
T64 |
7 |
| auto[1] |
930 |
1 |
|
|
T59 |
14 |
|
T70 |
11 |
|
T64 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T59 |
11 |
|
T70 |
10 |
|
T64 |
11 |
| auto[1] |
891 |
1 |
|
|
T59 |
9 |
|
T70 |
10 |
|
T64 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T59 |
9 |
|
T70 |
14 |
|
T64 |
9 |
| auto[1] |
896 |
1 |
|
|
T59 |
11 |
|
T70 |
6 |
|
T64 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
911 |
1 |
|
|
T59 |
10 |
|
T70 |
10 |
|
T64 |
9 |
| auto[1] |
886 |
1 |
|
|
T59 |
10 |
|
T70 |
10 |
|
T64 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
850 |
1 |
|
|
T59 |
10 |
|
T70 |
7 |
|
T64 |
9 |
| auto[1] |
947 |
1 |
|
|
T59 |
10 |
|
T70 |
13 |
|
T64 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
915 |
1 |
|
|
T59 |
11 |
|
T70 |
15 |
|
T64 |
10 |
| auto[1] |
882 |
1 |
|
|
T59 |
9 |
|
T70 |
5 |
|
T64 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
936 |
1 |
|
|
T59 |
13 |
|
T70 |
10 |
|
T64 |
7 |
| auto[1] |
861 |
1 |
|
|
T59 |
7 |
|
T70 |
10 |
|
T64 |
13 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
917 |
1 |
|
|
T59 |
5 |
|
T70 |
15 |
|
T64 |
10 |
| auto[1] |
880 |
1 |
|
|
T59 |
15 |
|
T70 |
5 |
|
T64 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
931 |
1 |
|
|
T59 |
10 |
|
T70 |
7 |
|
T64 |
11 |
| auto[1] |
866 |
1 |
|
|
T59 |
10 |
|
T70 |
13 |
|
T64 |
9 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T59 |
13 |
|
T70 |
10 |
|
T64 |
10 |
| auto[1] |
893 |
1 |
|
|
T59 |
7 |
|
T70 |
10 |
|
T64 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T59 |
7 |
|
T70 |
12 |
|
T64 |
12 |
| auto[1] |
895 |
1 |
|
|
T59 |
13 |
|
T70 |
8 |
|
T64 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
905 |
1 |
|
|
T59 |
11 |
|
T70 |
12 |
|
T64 |
9 |
| auto[1] |
892 |
1 |
|
|
T59 |
9 |
|
T70 |
8 |
|
T64 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
886 |
1 |
|
|
T59 |
13 |
|
T70 |
10 |
|
T64 |
9 |
| auto[1] |
911 |
1 |
|
|
T59 |
7 |
|
T70 |
10 |
|
T64 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T59 |
11 |
|
T70 |
10 |
|
T64 |
11 |
| auto[1] |
891 |
1 |
|
|
T59 |
9 |
|
T70 |
10 |
|
T64 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T59 |
9 |
|
T70 |
9 |
|
T64 |
7 |
| auto[1] |
907 |
1 |
|
|
T59 |
11 |
|
T70 |
11 |
|
T64 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T59 |
14 |
|
T70 |
9 |
|
T64 |
9 |
| auto[1] |
891 |
1 |
|
|
T59 |
6 |
|
T70 |
11 |
|
T64 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
890 |
1 |
|
|
T59 |
8 |
|
T70 |
13 |
|
T64 |
9 |
| auto[1] |
907 |
1 |
|
|
T59 |
12 |
|
T70 |
7 |
|
T64 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
905 |
1 |
|
|
T59 |
11 |
|
T70 |
11 |
|
T64 |
12 |
| auto[1] |
892 |
1 |
|
|
T59 |
9 |
|
T70 |
9 |
|
T64 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
920 |
1 |
|
|
T59 |
13 |
|
T70 |
14 |
|
T64 |
12 |
| auto[1] |
877 |
1 |
|
|
T59 |
7 |
|
T70 |
6 |
|
T64 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
881 |
1 |
|
|
T59 |
9 |
|
T70 |
7 |
|
T64 |
11 |
| auto[1] |
916 |
1 |
|
|
T59 |
11 |
|
T70 |
13 |
|
T64 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
924 |
1 |
|
|
T59 |
10 |
|
T70 |
9 |
|
T64 |
11 |
| auto[1] |
873 |
1 |
|
|
T59 |
10 |
|
T70 |
11 |
|
T64 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T59 |
9 |
|
T70 |
10 |
|
T64 |
9 |
| auto[1] |
915 |
1 |
|
|
T59 |
11 |
|
T70 |
10 |
|
T64 |
11 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
912 |
1 |
|
|
T59 |
13 |
|
T70 |
6 |
|
T64 |
11 |
| auto[1] |
885 |
1 |
|
|
T59 |
7 |
|
T70 |
14 |
|
T64 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
905 |
1 |
|
|
T59 |
11 |
|
T70 |
12 |
|
T64 |
9 |
| auto[1] |
892 |
1 |
|
|
T59 |
9 |
|
T70 |
8 |
|
T64 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T59 |
4 |
|
T70 |
8 |
|
T64 |
4 |
| auto[0] |
auto[1] |
460 |
1 |
|
|
T59 |
5 |
|
T70 |
1 |
|
T64 |
3 |
| auto[1] |
auto[0] |
471 |
1 |
|
|
T59 |
5 |
|
T70 |
6 |
|
T64 |
5 |
| auto[1] |
auto[1] |
436 |
1 |
|
|
T59 |
6 |
|
T70 |
5 |
|
T64 |
8 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
443 |
1 |
|
|
T59 |
7 |
|
T70 |
6 |
|
T64 |
5 |
| auto[0] |
auto[1] |
463 |
1 |
|
|
T59 |
7 |
|
T70 |
3 |
|
T64 |
4 |
| auto[1] |
auto[0] |
468 |
1 |
|
|
T59 |
3 |
|
T70 |
4 |
|
T64 |
4 |
| auto[1] |
auto[1] |
423 |
1 |
|
|
T59 |
3 |
|
T70 |
7 |
|
T64 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T59 |
1 |
|
T70 |
6 |
|
T64 |
4 |
| auto[0] |
auto[1] |
463 |
1 |
|
|
T59 |
7 |
|
T70 |
7 |
|
T64 |
5 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T59 |
9 |
|
T70 |
1 |
|
T64 |
5 |
| auto[1] |
auto[1] |
484 |
1 |
|
|
T59 |
3 |
|
T70 |
6 |
|
T64 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
467 |
1 |
|
|
T59 |
3 |
|
T70 |
9 |
|
T64 |
6 |
| auto[0] |
auto[1] |
438 |
1 |
|
|
T59 |
8 |
|
T70 |
2 |
|
T64 |
6 |
| auto[1] |
auto[0] |
448 |
1 |
|
|
T59 |
8 |
|
T70 |
6 |
|
T64 |
4 |
| auto[1] |
auto[1] |
444 |
1 |
|
|
T59 |
1 |
|
T70 |
3 |
|
T64 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
469 |
1 |
|
|
T59 |
8 |
|
T70 |
6 |
|
T64 |
4 |
| auto[0] |
auto[1] |
451 |
1 |
|
|
T59 |
5 |
|
T70 |
8 |
|
T64 |
8 |
| auto[1] |
auto[0] |
467 |
1 |
|
|
T59 |
5 |
|
T70 |
4 |
|
T64 |
3 |
| auto[1] |
auto[1] |
410 |
1 |
|
|
T59 |
2 |
|
T70 |
2 |
|
T64 |
5 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
440 |
1 |
|
|
T59 |
2 |
|
T70 |
5 |
|
T64 |
5 |
| auto[0] |
auto[1] |
441 |
1 |
|
|
T59 |
7 |
|
T70 |
2 |
|
T64 |
6 |
| auto[1] |
auto[0] |
477 |
1 |
|
|
T59 |
3 |
|
T70 |
10 |
|
T64 |
5 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T59 |
8 |
|
T70 |
3 |
|
T64 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T59 |
5 |
|
T70 |
3 |
|
T64 |
5 |
| auto[0] |
auto[1] |
451 |
1 |
|
|
T59 |
4 |
|
T70 |
7 |
|
T64 |
4 |
| auto[1] |
auto[0] |
473 |
1 |
|
|
T59 |
8 |
|
T70 |
7 |
|
T64 |
5 |
| auto[1] |
auto[1] |
442 |
1 |
|
|
T59 |
3 |
|
T70 |
3 |
|
T64 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
445 |
1 |
|
|
T59 |
4 |
|
T70 |
2 |
|
T64 |
7 |
| auto[0] |
auto[1] |
467 |
1 |
|
|
T59 |
9 |
|
T70 |
4 |
|
T64 |
4 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T59 |
3 |
|
T70 |
10 |
|
T64 |
5 |
| auto[1] |
auto[1] |
428 |
1 |
|
|
T59 |
4 |
|
T70 |
4 |
|
T64 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
427 |
1 |
|
|
T59 |
5 |
|
T70 |
4 |
|
T64 |
3 |
| auto[0] |
auto[1] |
459 |
1 |
|
|
T59 |
8 |
|
T70 |
6 |
|
T64 |
6 |
| auto[1] |
auto[0] |
440 |
1 |
|
|
T59 |
1 |
|
T70 |
5 |
|
T64 |
4 |
| auto[1] |
auto[1] |
471 |
1 |
|
|
T59 |
6 |
|
T70 |
5 |
|
T64 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
906 |
1 |
|
|
T59 |
11 |
|
T70 |
10 |
|
T64 |
11 |
| auto[1] |
auto[1] |
891 |
1 |
|
|
T59 |
9 |
|
T70 |
10 |
|
T64 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
479 |
1 |
|
|
T59 |
4 |
|
T70 |
4 |
|
T64 |
5 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T59 |
6 |
|
T70 |
5 |
|
T64 |
6 |
| auto[1] |
auto[0] |
452 |
1 |
|
|
T59 |
6 |
|
T70 |
3 |
|
T64 |
6 |
| auto[1] |
auto[1] |
421 |
1 |
|
|
T59 |
4 |
|
T70 |
8 |
|
T64 |
3 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
905 |
1 |
|
|
T59 |
11 |
|
T70 |
12 |
|
T64 |
9 |
| auto[1] |
auto[1] |
892 |
1 |
|
|
T59 |
9 |
|
T70 |
8 |
|
T64 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
180 |
1 |
|
|
T67 |
11 |
|
T48 |
10 |
|
T44 |
10 |
| auto[1] |
180 |
1 |
|
|
T67 |
9 |
|
T48 |
10 |
|
T44 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
166 |
1 |
|
|
T67 |
9 |
|
T48 |
12 |
|
T44 |
7 |
| auto[1] |
194 |
1 |
|
|
T67 |
11 |
|
T48 |
8 |
|
T44 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
186 |
1 |
|
|
T67 |
8 |
|
T48 |
12 |
|
T44 |
12 |
| auto[1] |
174 |
1 |
|
|
T67 |
12 |
|
T48 |
8 |
|
T44 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T67 |
10 |
|
T48 |
13 |
|
T44 |
9 |
| auto[1] |
179 |
1 |
|
|
T67 |
10 |
|
T48 |
7 |
|
T44 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
170 |
1 |
|
|
T67 |
8 |
|
T48 |
8 |
|
T44 |
11 |
| auto[1] |
190 |
1 |
|
|
T67 |
12 |
|
T48 |
12 |
|
T44 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
200 |
1 |
|
|
T67 |
14 |
|
T48 |
11 |
|
T44 |
13 |
| auto[1] |
160 |
1 |
|
|
T67 |
6 |
|
T48 |
9 |
|
T44 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
170 |
1 |
|
|
T67 |
6 |
|
T48 |
6 |
|
T44 |
11 |
| auto[1] |
190 |
1 |
|
|
T67 |
14 |
|
T48 |
14 |
|
T44 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T67 |
9 |
|
T48 |
10 |
|
T44 |
6 |
| auto[1] |
191 |
1 |
|
|
T67 |
11 |
|
T48 |
10 |
|
T44 |
14 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T67 |
7 |
|
T48 |
8 |
|
T44 |
9 |
| auto[1] |
185 |
1 |
|
|
T67 |
13 |
|
T48 |
12 |
|
T44 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T67 |
9 |
|
T48 |
11 |
|
T44 |
11 |
| auto[1] |
185 |
1 |
|
|
T67 |
11 |
|
T48 |
9 |
|
T44 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
180 |
1 |
|
|
T67 |
9 |
|
T48 |
8 |
|
T44 |
9 |
| auto[1] |
180 |
1 |
|
|
T67 |
11 |
|
T48 |
12 |
|
T44 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
191 |
1 |
|
|
T67 |
9 |
|
T48 |
11 |
|
T44 |
11 |
| auto[1] |
169 |
1 |
|
|
T67 |
11 |
|
T48 |
9 |
|
T44 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T67 |
12 |
|
T48 |
8 |
|
T44 |
13 |
| auto[1] |
187 |
1 |
|
|
T67 |
8 |
|
T48 |
12 |
|
T44 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
166 |
1 |
|
|
T67 |
9 |
|
T48 |
12 |
|
T44 |
7 |
| auto[1] |
194 |
1 |
|
|
T67 |
11 |
|
T48 |
8 |
|
T44 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T67 |
10 |
|
T48 |
10 |
|
T44 |
13 |
| auto[1] |
178 |
1 |
|
|
T67 |
10 |
|
T48 |
10 |
|
T44 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T67 |
12 |
|
T48 |
5 |
|
T44 |
12 |
| auto[1] |
181 |
1 |
|
|
T67 |
8 |
|
T48 |
15 |
|
T44 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
191 |
1 |
|
|
T67 |
7 |
|
T48 |
15 |
|
T44 |
8 |
| auto[1] |
169 |
1 |
|
|
T67 |
13 |
|
T48 |
5 |
|
T44 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T67 |
9 |
|
T48 |
16 |
|
T44 |
10 |
| auto[1] |
177 |
1 |
|
|
T67 |
11 |
|
T48 |
4 |
|
T44 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
200 |
1 |
|
|
T67 |
13 |
|
T48 |
11 |
|
T44 |
15 |
| auto[1] |
160 |
1 |
|
|
T67 |
7 |
|
T48 |
9 |
|
T44 |
5 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
187 |
1 |
|
|
T67 |
10 |
|
T48 |
13 |
|
T44 |
10 |
| auto[1] |
173 |
1 |
|
|
T67 |
10 |
|
T48 |
7 |
|
T44 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
187 |
1 |
|
|
T67 |
10 |
|
T48 |
10 |
|
T44 |
13 |
| auto[1] |
173 |
1 |
|
|
T67 |
10 |
|
T48 |
10 |
|
T44 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T67 |
12 |
|
T48 |
11 |
|
T44 |
10 |
| auto[1] |
181 |
1 |
|
|
T67 |
8 |
|
T48 |
9 |
|
T44 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T67 |
12 |
|
T48 |
10 |
|
T44 |
10 |
| auto[1] |
186 |
1 |
|
|
T67 |
8 |
|
T48 |
10 |
|
T44 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
191 |
1 |
|
|
T67 |
9 |
|
T48 |
11 |
|
T44 |
11 |
| auto[1] |
169 |
1 |
|
|
T67 |
11 |
|
T48 |
9 |
|
T44 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
92 |
1 |
|
|
T67 |
5 |
|
T48 |
6 |
|
T44 |
9 |
| auto[0] |
auto[1] |
90 |
1 |
|
|
T67 |
5 |
|
T48 |
4 |
|
T44 |
4 |
| auto[1] |
auto[0] |
94 |
1 |
|
|
T67 |
3 |
|
T48 |
6 |
|
T44 |
3 |
| auto[1] |
auto[1] |
84 |
1 |
|
|
T67 |
7 |
|
T48 |
4 |
|
T44 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
88 |
1 |
|
|
T67 |
7 |
|
T48 |
4 |
|
T44 |
7 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T67 |
5 |
|
T48 |
1 |
|
T44 |
5 |
| auto[1] |
auto[0] |
93 |
1 |
|
|
T67 |
3 |
|
T48 |
9 |
|
T44 |
2 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T67 |
5 |
|
T48 |
6 |
|
T44 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
95 |
1 |
|
|
T67 |
2 |
|
T48 |
5 |
|
T44 |
6 |
| auto[0] |
auto[1] |
96 |
1 |
|
|
T67 |
5 |
|
T48 |
10 |
|
T44 |
2 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T67 |
6 |
|
T48 |
3 |
|
T44 |
5 |
| auto[1] |
auto[1] |
94 |
1 |
|
|
T67 |
7 |
|
T48 |
2 |
|
T44 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
106 |
1 |
|
|
T67 |
6 |
|
T48 |
7 |
|
T44 |
8 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T67 |
3 |
|
T48 |
9 |
|
T44 |
2 |
| auto[1] |
auto[0] |
94 |
1 |
|
|
T67 |
8 |
|
T48 |
4 |
|
T44 |
5 |
| auto[1] |
auto[1] |
83 |
1 |
|
|
T67 |
3 |
|
T44 |
5 |
|
T94 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T67 |
3 |
|
T48 |
2 |
|
T44 |
9 |
| auto[0] |
auto[1] |
110 |
1 |
|
|
T67 |
10 |
|
T48 |
9 |
|
T44 |
6 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T67 |
3 |
|
T48 |
4 |
|
T44 |
2 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T67 |
4 |
|
T48 |
5 |
|
T44 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
83 |
1 |
|
|
T67 |
3 |
|
T48 |
5 |
|
T44 |
4 |
| auto[0] |
auto[1] |
104 |
1 |
|
|
T67 |
7 |
|
T48 |
8 |
|
T44 |
6 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T67 |
6 |
|
T48 |
5 |
|
T44 |
2 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T67 |
4 |
|
T48 |
2 |
|
T44 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T67 |
5 |
|
T48 |
7 |
|
T44 |
3 |
| auto[0] |
auto[1] |
95 |
1 |
|
|
T67 |
7 |
|
T48 |
4 |
|
T44 |
7 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T67 |
4 |
|
T48 |
4 |
|
T44 |
8 |
| auto[1] |
auto[1] |
90 |
1 |
|
|
T67 |
4 |
|
T48 |
5 |
|
T44 |
2 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T67 |
5 |
|
T48 |
5 |
|
T44 |
2 |
| auto[0] |
auto[1] |
90 |
1 |
|
|
T67 |
7 |
|
T48 |
5 |
|
T44 |
8 |
| auto[1] |
auto[0] |
96 |
1 |
|
|
T67 |
4 |
|
T48 |
3 |
|
T44 |
7 |
| auto[1] |
auto[1] |
90 |
1 |
|
|
T67 |
4 |
|
T48 |
7 |
|
T44 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
92 |
1 |
|
|
T67 |
8 |
|
T48 |
6 |
|
T44 |
5 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T67 |
4 |
|
T48 |
2 |
|
T44 |
8 |
| auto[1] |
auto[0] |
88 |
1 |
|
|
T67 |
3 |
|
T48 |
4 |
|
T44 |
5 |
| auto[1] |
auto[1] |
99 |
1 |
|
|
T67 |
5 |
|
T48 |
8 |
|
T44 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
166 |
1 |
|
|
T67 |
9 |
|
T48 |
12 |
|
T44 |
7 |
| auto[1] |
auto[1] |
194 |
1 |
|
|
T67 |
11 |
|
T48 |
8 |
|
T44 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
89 |
1 |
|
|
T67 |
3 |
|
T48 |
4 |
|
T44 |
6 |
| auto[0] |
auto[1] |
98 |
1 |
|
|
T67 |
7 |
|
T48 |
6 |
|
T44 |
7 |
| auto[1] |
auto[0] |
86 |
1 |
|
|
T67 |
4 |
|
T48 |
4 |
|
T44 |
3 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T67 |
6 |
|
T48 |
6 |
|
T44 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
191 |
1 |
|
|
T67 |
9 |
|
T48 |
11 |
|
T44 |
11 |
| auto[1] |
auto[1] |
169 |
1 |
|
|
T67 |
11 |
|
T48 |
9 |
|
T44 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T67 |
11 |
|
T44 |
12 |
|
T88 |
11 |
| auto[1] |
61 |
1 |
|
|
T67 |
9 |
|
T44 |
8 |
|
T88 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
72 |
1 |
|
|
T67 |
13 |
|
T44 |
5 |
|
T88 |
11 |
| auto[1] |
68 |
1 |
|
|
T67 |
7 |
|
T44 |
15 |
|
T88 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T67 |
9 |
|
T44 |
9 |
|
T88 |
9 |
| auto[1] |
72 |
1 |
|
|
T67 |
11 |
|
T44 |
11 |
|
T88 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67 |
1 |
|
|
T67 |
13 |
|
T44 |
11 |
|
T88 |
8 |
| auto[1] |
73 |
1 |
|
|
T67 |
7 |
|
T44 |
9 |
|
T88 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T67 |
8 |
|
T44 |
12 |
|
T88 |
9 |
| auto[1] |
70 |
1 |
|
|
T67 |
12 |
|
T44 |
8 |
|
T88 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T67 |
9 |
|
T44 |
10 |
|
T88 |
11 |
| auto[1] |
69 |
1 |
|
|
T67 |
11 |
|
T44 |
10 |
|
T88 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
74 |
1 |
|
|
T67 |
15 |
|
T44 |
9 |
|
T88 |
11 |
| auto[1] |
66 |
1 |
|
|
T67 |
5 |
|
T44 |
11 |
|
T88 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67 |
1 |
|
|
T67 |
11 |
|
T44 |
11 |
|
T88 |
10 |
| auto[1] |
73 |
1 |
|
|
T67 |
9 |
|
T44 |
9 |
|
T88 |
10 |