Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
872 |
1 |
|
|
T14 |
10 |
|
T33 |
8 |
|
T59 |
6 |
| auto[1] |
888 |
1 |
|
|
T14 |
10 |
|
T33 |
12 |
|
T59 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T14 |
12 |
|
T33 |
9 |
|
T59 |
8 |
| auto[1] |
915 |
1 |
|
|
T14 |
8 |
|
T33 |
11 |
|
T59 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
844 |
1 |
|
|
T14 |
6 |
|
T33 |
5 |
|
T59 |
10 |
| auto[1] |
916 |
1 |
|
|
T14 |
14 |
|
T33 |
15 |
|
T59 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T14 |
10 |
|
T33 |
11 |
|
T59 |
5 |
| auto[1] |
869 |
1 |
|
|
T14 |
10 |
|
T33 |
9 |
|
T59 |
15 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
852 |
1 |
|
|
T14 |
7 |
|
T33 |
9 |
|
T59 |
9 |
| auto[1] |
908 |
1 |
|
|
T14 |
13 |
|
T33 |
11 |
|
T59 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T14 |
11 |
|
T33 |
7 |
|
T59 |
10 |
| auto[1] |
920 |
1 |
|
|
T14 |
9 |
|
T33 |
13 |
|
T59 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
880 |
1 |
|
|
T14 |
9 |
|
T33 |
10 |
|
T59 |
9 |
| auto[1] |
880 |
1 |
|
|
T14 |
11 |
|
T33 |
10 |
|
T59 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
888 |
1 |
|
|
T14 |
8 |
|
T33 |
10 |
|
T59 |
11 |
| auto[1] |
872 |
1 |
|
|
T14 |
12 |
|
T33 |
10 |
|
T59 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
885 |
1 |
|
|
T14 |
8 |
|
T33 |
9 |
|
T59 |
8 |
| auto[1] |
875 |
1 |
|
|
T14 |
12 |
|
T33 |
11 |
|
T59 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
897 |
1 |
|
|
T14 |
10 |
|
T33 |
13 |
|
T59 |
9 |
| auto[1] |
863 |
1 |
|
|
T14 |
10 |
|
T33 |
7 |
|
T59 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T14 |
10 |
|
T33 |
10 |
|
T59 |
10 |
| auto[1] |
883 |
1 |
|
|
T14 |
10 |
|
T33 |
10 |
|
T59 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T14 |
10 |
|
T33 |
8 |
|
T59 |
12 |
| auto[1] |
920 |
1 |
|
|
T14 |
10 |
|
T33 |
12 |
|
T59 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T14 |
13 |
|
T33 |
9 |
|
T59 |
9 |
| auto[1] |
931 |
1 |
|
|
T14 |
7 |
|
T33 |
11 |
|
T59 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T14 |
12 |
|
T33 |
9 |
|
T59 |
8 |
| auto[1] |
915 |
1 |
|
|
T14 |
8 |
|
T33 |
11 |
|
T59 |
12 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
900 |
1 |
|
|
T14 |
10 |
|
T33 |
7 |
|
T59 |
7 |
| auto[1] |
860 |
1 |
|
|
T14 |
10 |
|
T33 |
13 |
|
T59 |
13 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
835 |
1 |
|
|
T14 |
10 |
|
T33 |
11 |
|
T59 |
12 |
| auto[1] |
925 |
1 |
|
|
T14 |
10 |
|
T33 |
9 |
|
T59 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
875 |
1 |
|
|
T14 |
7 |
|
T33 |
11 |
|
T59 |
10 |
| auto[1] |
885 |
1 |
|
|
T14 |
13 |
|
T33 |
9 |
|
T59 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
883 |
1 |
|
|
T14 |
9 |
|
T33 |
11 |
|
T59 |
11 |
| auto[1] |
877 |
1 |
|
|
T14 |
11 |
|
T33 |
9 |
|
T59 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
874 |
1 |
|
|
T14 |
11 |
|
T33 |
9 |
|
T59 |
7 |
| auto[1] |
886 |
1 |
|
|
T14 |
9 |
|
T33 |
11 |
|
T59 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T14 |
16 |
|
T33 |
9 |
|
T59 |
13 |
| auto[1] |
858 |
1 |
|
|
T14 |
4 |
|
T33 |
11 |
|
T59 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
878 |
1 |
|
|
T14 |
13 |
|
T33 |
8 |
|
T59 |
10 |
| auto[1] |
882 |
1 |
|
|
T14 |
7 |
|
T33 |
12 |
|
T59 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T14 |
10 |
|
T33 |
12 |
|
T59 |
14 |
| auto[1] |
856 |
1 |
|
|
T14 |
10 |
|
T33 |
8 |
|
T59 |
6 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
894 |
1 |
|
|
T14 |
12 |
|
T33 |
11 |
|
T59 |
9 |
| auto[1] |
866 |
1 |
|
|
T14 |
8 |
|
T33 |
9 |
|
T59 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
840 |
1 |
|
|
T14 |
10 |
|
T33 |
8 |
|
T59 |
12 |
| auto[1] |
920 |
1 |
|
|
T14 |
10 |
|
T33 |
12 |
|
T59 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T14 |
2 |
|
T33 |
1 |
|
T59 |
5 |
| auto[0] |
auto[1] |
475 |
1 |
|
|
T14 |
8 |
|
T33 |
6 |
|
T59 |
2 |
| auto[1] |
auto[0] |
419 |
1 |
|
|
T14 |
4 |
|
T33 |
4 |
|
T59 |
5 |
| auto[1] |
auto[1] |
441 |
1 |
|
|
T14 |
6 |
|
T33 |
9 |
|
T59 |
8 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T14 |
4 |
|
T33 |
6 |
|
T59 |
5 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T14 |
6 |
|
T33 |
5 |
|
T59 |
7 |
| auto[1] |
auto[0] |
475 |
1 |
|
|
T14 |
6 |
|
T33 |
5 |
|
T174 |
7 |
| auto[1] |
auto[1] |
450 |
1 |
|
|
T14 |
4 |
|
T33 |
4 |
|
T59 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
430 |
1 |
|
|
T14 |
5 |
|
T33 |
6 |
|
T59 |
6 |
| auto[0] |
auto[1] |
445 |
1 |
|
|
T14 |
2 |
|
T33 |
5 |
|
T59 |
4 |
| auto[1] |
auto[0] |
422 |
1 |
|
|
T14 |
2 |
|
T33 |
3 |
|
T59 |
3 |
| auto[1] |
auto[1] |
463 |
1 |
|
|
T14 |
11 |
|
T33 |
6 |
|
T59 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
428 |
1 |
|
|
T14 |
8 |
|
T33 |
5 |
|
T59 |
7 |
| auto[0] |
auto[1] |
455 |
1 |
|
|
T14 |
1 |
|
T33 |
6 |
|
T59 |
4 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T14 |
3 |
|
T33 |
2 |
|
T59 |
3 |
| auto[1] |
auto[1] |
465 |
1 |
|
|
T14 |
8 |
|
T33 |
7 |
|
T59 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
446 |
1 |
|
|
T14 |
5 |
|
T33 |
5 |
|
T59 |
4 |
| auto[0] |
auto[1] |
428 |
1 |
|
|
T14 |
6 |
|
T33 |
4 |
|
T59 |
3 |
| auto[1] |
auto[0] |
434 |
1 |
|
|
T14 |
4 |
|
T33 |
5 |
|
T59 |
5 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T14 |
5 |
|
T33 |
6 |
|
T59 |
8 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
464 |
1 |
|
|
T14 |
7 |
|
T33 |
5 |
|
T59 |
8 |
| auto[0] |
auto[1] |
438 |
1 |
|
|
T14 |
9 |
|
T33 |
4 |
|
T59 |
5 |
| auto[1] |
auto[0] |
424 |
1 |
|
|
T14 |
1 |
|
T33 |
5 |
|
T59 |
3 |
| auto[1] |
auto[1] |
434 |
1 |
|
|
T14 |
3 |
|
T33 |
6 |
|
T59 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
462 |
1 |
|
|
T14 |
5 |
|
T33 |
6 |
|
T59 |
4 |
| auto[0] |
auto[1] |
442 |
1 |
|
|
T14 |
5 |
|
T33 |
6 |
|
T59 |
10 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T14 |
5 |
|
T33 |
7 |
|
T59 |
5 |
| auto[1] |
auto[1] |
421 |
1 |
|
|
T14 |
5 |
|
T33 |
1 |
|
T59 |
1 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
447 |
1 |
|
|
T14 |
6 |
|
T33 |
4 |
|
T59 |
2 |
| auto[0] |
auto[1] |
447 |
1 |
|
|
T14 |
6 |
|
T33 |
7 |
|
T59 |
7 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T14 |
4 |
|
T33 |
6 |
|
T59 |
8 |
| auto[1] |
auto[1] |
436 |
1 |
|
|
T14 |
4 |
|
T33 |
3 |
|
T59 |
3 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
415 |
1 |
|
|
T14 |
6 |
|
T33 |
2 |
|
T59 |
2 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T14 |
7 |
|
T33 |
7 |
|
T59 |
7 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T14 |
4 |
|
T33 |
6 |
|
T59 |
4 |
| auto[1] |
auto[1] |
474 |
1 |
|
|
T14 |
3 |
|
T33 |
5 |
|
T59 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
845 |
1 |
|
|
T14 |
12 |
|
T33 |
9 |
|
T59 |
8 |
| auto[1] |
auto[1] |
915 |
1 |
|
|
T14 |
8 |
|
T33 |
11 |
|
T59 |
12 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
450 |
1 |
|
|
T14 |
6 |
|
T33 |
3 |
|
T59 |
5 |
| auto[0] |
auto[1] |
428 |
1 |
|
|
T14 |
7 |
|
T33 |
5 |
|
T59 |
5 |
| auto[1] |
auto[0] |
435 |
1 |
|
|
T14 |
2 |
|
T33 |
6 |
|
T59 |
3 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T14 |
5 |
|
T33 |
6 |
|
T59 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
840 |
1 |
|
|
T14 |
10 |
|
T33 |
8 |
|
T59 |
12 |
| auto[1] |
auto[1] |
920 |
1 |
|
|
T14 |
10 |
|
T33 |
12 |
|
T59 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T14 |
11 |
|
T43 |
14 |
|
T84 |
7 |
| auto[1] |
161 |
1 |
|
|
T14 |
9 |
|
T43 |
6 |
|
T84 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
172 |
1 |
|
|
T14 |
8 |
|
T43 |
10 |
|
T84 |
13 |
| auto[1] |
148 |
1 |
|
|
T14 |
12 |
|
T43 |
10 |
|
T84 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T14 |
13 |
|
T43 |
13 |
|
T84 |
10 |
| auto[1] |
155 |
1 |
|
|
T14 |
7 |
|
T43 |
7 |
|
T84 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T14 |
13 |
|
T43 |
11 |
|
T84 |
6 |
| auto[1] |
164 |
1 |
|
|
T14 |
7 |
|
T43 |
9 |
|
T84 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T14 |
10 |
|
T43 |
11 |
|
T84 |
9 |
| auto[1] |
160 |
1 |
|
|
T14 |
10 |
|
T43 |
9 |
|
T84 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T14 |
14 |
|
T43 |
11 |
|
T84 |
9 |
| auto[1] |
163 |
1 |
|
|
T14 |
6 |
|
T43 |
9 |
|
T84 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T14 |
10 |
|
T43 |
12 |
|
T84 |
11 |
| auto[1] |
158 |
1 |
|
|
T14 |
10 |
|
T43 |
8 |
|
T84 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
172 |
1 |
|
|
T14 |
8 |
|
T43 |
12 |
|
T84 |
9 |
| auto[1] |
148 |
1 |
|
|
T14 |
12 |
|
T43 |
8 |
|
T84 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
166 |
1 |
|
|
T14 |
12 |
|
T43 |
10 |
|
T84 |
7 |
| auto[1] |
154 |
1 |
|
|
T14 |
8 |
|
T43 |
10 |
|
T84 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T14 |
11 |
|
T43 |
13 |
|
T84 |
9 |
| auto[1] |
157 |
1 |
|
|
T14 |
9 |
|
T43 |
7 |
|
T84 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
168 |
1 |
|
|
T14 |
11 |
|
T43 |
10 |
|
T84 |
11 |
| auto[1] |
152 |
1 |
|
|
T14 |
9 |
|
T43 |
10 |
|
T84 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T14 |
14 |
|
T43 |
11 |
|
T84 |
9 |
| auto[1] |
145 |
1 |
|
|
T14 |
6 |
|
T43 |
9 |
|
T84 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
168 |
1 |
|
|
T14 |
12 |
|
T43 |
11 |
|
T84 |
9 |
| auto[1] |
152 |
1 |
|
|
T14 |
8 |
|
T43 |
9 |
|
T84 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
172 |
1 |
|
|
T14 |
8 |
|
T43 |
10 |
|
T84 |
13 |
| auto[1] |
148 |
1 |
|
|
T14 |
12 |
|
T43 |
10 |
|
T84 |
7 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T14 |
10 |
|
T43 |
10 |
|
T84 |
16 |
| auto[1] |
155 |
1 |
|
|
T14 |
10 |
|
T43 |
10 |
|
T84 |
4 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
178 |
1 |
|
|
T14 |
16 |
|
T43 |
10 |
|
T84 |
10 |
| auto[1] |
142 |
1 |
|
|
T14 |
4 |
|
T43 |
10 |
|
T84 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T14 |
9 |
|
T43 |
9 |
|
T84 |
13 |
| auto[1] |
141 |
1 |
|
|
T14 |
11 |
|
T43 |
11 |
|
T84 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T14 |
7 |
|
T43 |
13 |
|
T84 |
11 |
| auto[1] |
146 |
1 |
|
|
T14 |
13 |
|
T43 |
7 |
|
T84 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
171 |
1 |
|
|
T14 |
9 |
|
T43 |
10 |
|
T84 |
9 |
| auto[1] |
149 |
1 |
|
|
T14 |
11 |
|
T43 |
10 |
|
T84 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T14 |
11 |
|
T43 |
12 |
|
T84 |
11 |
| auto[1] |
151 |
1 |
|
|
T14 |
9 |
|
T43 |
8 |
|
T84 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T14 |
8 |
|
T43 |
7 |
|
T84 |
7 |
| auto[1] |
166 |
1 |
|
|
T14 |
12 |
|
T43 |
13 |
|
T84 |
13 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T14 |
5 |
|
T43 |
9 |
|
T84 |
7 |
| auto[1] |
185 |
1 |
|
|
T14 |
15 |
|
T43 |
11 |
|
T84 |
13 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
160 |
1 |
|
|
T14 |
5 |
|
T43 |
8 |
|
T84 |
13 |
| auto[1] |
160 |
1 |
|
|
T14 |
15 |
|
T43 |
12 |
|
T84 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
175 |
1 |
|
|
T14 |
14 |
|
T43 |
11 |
|
T84 |
9 |
| auto[1] |
145 |
1 |
|
|
T14 |
6 |
|
T43 |
9 |
|
T84 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
88 |
1 |
|
|
T14 |
6 |
|
T43 |
6 |
|
T84 |
9 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T14 |
4 |
|
T43 |
4 |
|
T84 |
7 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T14 |
7 |
|
T43 |
7 |
|
T84 |
1 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T14 |
3 |
|
T43 |
3 |
|
T84 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T14 |
9 |
|
T43 |
5 |
|
T84 |
4 |
| auto[0] |
auto[1] |
88 |
1 |
|
|
T14 |
7 |
|
T43 |
5 |
|
T84 |
6 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T14 |
4 |
|
T43 |
6 |
|
T84 |
2 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T43 |
4 |
|
T84 |
8 |
|
T109 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
88 |
1 |
|
|
T14 |
2 |
|
T43 |
5 |
|
T84 |
6 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T14 |
7 |
|
T43 |
4 |
|
T84 |
7 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T14 |
8 |
|
T43 |
6 |
|
T84 |
3 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T14 |
3 |
|
T43 |
5 |
|
T84 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T14 |
3 |
|
T43 |
7 |
|
T84 |
5 |
| auto[0] |
auto[1] |
90 |
1 |
|
|
T14 |
4 |
|
T43 |
6 |
|
T84 |
6 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T14 |
11 |
|
T43 |
4 |
|
T84 |
4 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T14 |
2 |
|
T43 |
3 |
|
T84 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T14 |
7 |
|
T43 |
8 |
|
T84 |
4 |
| auto[0] |
auto[1] |
85 |
1 |
|
|
T14 |
2 |
|
T43 |
2 |
|
T84 |
5 |
| auto[1] |
auto[0] |
76 |
1 |
|
|
T14 |
3 |
|
T43 |
4 |
|
T84 |
7 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T14 |
8 |
|
T43 |
6 |
|
T84 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T14 |
7 |
|
T43 |
9 |
|
T84 |
4 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T14 |
4 |
|
T43 |
3 |
|
T84 |
7 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T14 |
1 |
|
T43 |
3 |
|
T84 |
5 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T14 |
8 |
|
T43 |
5 |
|
T84 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
78 |
1 |
|
|
T14 |
3 |
|
T43 |
8 |
|
T84 |
4 |
| auto[0] |
auto[1] |
57 |
1 |
|
|
T14 |
2 |
|
T43 |
1 |
|
T84 |
3 |
| auto[1] |
auto[0] |
85 |
1 |
|
|
T14 |
8 |
|
T43 |
5 |
|
T84 |
5 |
| auto[1] |
auto[1] |
100 |
1 |
|
|
T14 |
7 |
|
T43 |
6 |
|
T84 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
93 |
1 |
|
|
T14 |
3 |
|
T43 |
6 |
|
T84 |
8 |
| auto[0] |
auto[1] |
67 |
1 |
|
|
T14 |
2 |
|
T43 |
2 |
|
T84 |
5 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T14 |
8 |
|
T43 |
4 |
|
T84 |
3 |
| auto[1] |
auto[1] |
85 |
1 |
|
|
T14 |
7 |
|
T43 |
8 |
|
T84 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T14 |
6 |
|
T43 |
8 |
|
T84 |
2 |
| auto[0] |
auto[1] |
84 |
1 |
|
|
T14 |
6 |
|
T43 |
3 |
|
T84 |
7 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T14 |
5 |
|
T43 |
6 |
|
T84 |
5 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T14 |
3 |
|
T43 |
3 |
|
T84 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
172 |
1 |
|
|
T14 |
8 |
|
T43 |
10 |
|
T84 |
13 |
| auto[1] |
auto[1] |
148 |
1 |
|
|
T14 |
12 |
|
T43 |
10 |
|
T84 |
7 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
89 |
1 |
|
|
T14 |
6 |
|
T43 |
5 |
|
T84 |
1 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T14 |
2 |
|
T43 |
2 |
|
T84 |
6 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T14 |
6 |
|
T43 |
5 |
|
T84 |
6 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T14 |
6 |
|
T43 |
8 |
|
T84 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
175 |
1 |
|
|
T14 |
14 |
|
T43 |
11 |
|
T84 |
9 |
| auto[1] |
auto[1] |
145 |
1 |
|
|
T14 |
6 |
|
T43 |
9 |
|
T84 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T43 |
9 |
|
T71 |
9 |
|
T110 |
11 |
| auto[1] |
60 |
1 |
|
|
T43 |
11 |
|
T71 |
11 |
|
T110 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
58 |
1 |
|
|
T43 |
8 |
|
T71 |
9 |
|
T110 |
14 |
| auto[1] |
62 |
1 |
|
|
T43 |
12 |
|
T71 |
11 |
|
T110 |
6 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
73 |
1 |
|
|
T43 |
13 |
|
T71 |
11 |
|
T110 |
13 |
| auto[1] |
47 |
1 |
|
|
T43 |
7 |
|
T71 |
9 |
|
T110 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67 |
1 |
|
|
T43 |
11 |
|
T71 |
9 |
|
T110 |
10 |
| auto[1] |
53 |
1 |
|
|
T43 |
9 |
|
T71 |
11 |
|
T110 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T43 |
10 |
|
T71 |
12 |
|
T110 |
12 |
| auto[1] |
54 |
1 |
|
|
T43 |
10 |
|
T71 |
8 |
|
T110 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
61 |
1 |
|
|
T43 |
10 |
|
T71 |
9 |
|
T110 |
9 |
| auto[1] |
59 |
1 |
|
|
T43 |
10 |
|
T71 |
11 |
|
T110 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T43 |
11 |
|
T71 |
12 |
|
T110 |
10 |
| auto[1] |
56 |
1 |
|
|
T43 |
9 |
|
T71 |
8 |
|
T110 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T43 |
10 |
|
T71 |
11 |
|
T110 |
8 |
| auto[1] |
57 |
1 |
|
|
T43 |
10 |
|
T71 |
9 |
|
T110 |
12 |