Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.53 99.32 96.02 100.00 96.79 98.68 99.53 92.36


Total tests in report: 884
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
53.60 53.60 72.27 72.27 66.20 66.20 86.56 86.56 0.00 0.00 75.57 75.57 54.49 54.49 20.13 20.13 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.407617422
70.32 16.72 90.80 18.53 83.67 17.47 96.36 9.79 0.00 0.00 90.43 14.86 80.62 26.12 50.38 30.25 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4190419737
84.49 14.17 90.87 0.07 83.89 0.21 96.58 0.23 96.79 96.79 90.50 0.07 80.71 0.09 52.10 1.72 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2957565385
87.49 3.00 93.44 2.57 86.91 3.03 97.04 0.46 96.79 0.00 92.66 2.16 86.42 5.71 59.15 7.05 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3095613374
90.03 2.54 96.02 2.59 88.89 1.98 98.86 1.82 96.79 0.00 94.50 1.84 91.01 4.59 64.10 4.95 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2738793165
91.53 1.50 96.37 0.35 89.37 0.48 98.86 0.00 96.79 0.00 94.95 0.45 91.95 0.94 72.39 8.29 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.2000549448
92.99 1.47 97.07 0.69 93.04 3.67 98.86 0.00 96.79 0.00 96.07 1.11 95.51 3.56 73.63 1.24 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2475013200
93.77 0.77 97.10 0.03 93.06 0.02 98.86 0.00 96.79 0.00 96.10 0.03 95.60 0.09 78.85 5.22 /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.770742805
94.29 0.52 97.57 0.47 93.47 0.41 98.86 0.00 96.79 0.00 96.52 0.42 97.10 1.50 79.71 0.86 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1202238731
94.77 0.48 97.64 0.07 93.52 0.05 98.86 0.00 96.79 0.00 96.59 0.07 97.28 0.19 82.72 3.01 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1174775780
95.18 0.41 98.75 1.11 93.92 0.41 98.86 0.00 96.79 0.00 97.77 1.18 97.47 0.19 82.72 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.839038968
95.51 0.33 98.75 0.00 94.68 0.76 99.32 0.46 96.79 0.00 97.81 0.03 97.47 0.00 83.75 1.02 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2981375570
95.79 0.28 98.77 0.02 94.76 0.07 99.32 0.00 96.79 0.00 97.84 0.03 97.57 0.09 85.52 1.78 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3119994670
95.97 0.18 98.77 0.00 95.18 0.43 99.32 0.00 96.79 0.00 97.84 0.00 98.22 0.66 85.68 0.16 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4158025307
96.10 0.13 98.77 0.00 95.21 0.02 100.00 0.68 96.79 0.00 97.84 0.00 98.31 0.09 85.79 0.11 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2627281121
96.22 0.12 98.77 0.00 95.26 0.05 100.00 0.00 96.79 0.00 97.84 0.00 98.41 0.09 86.49 0.70 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.4145394850
96.33 0.11 98.77 0.00 95.26 0.00 100.00 0.00 96.79 0.00 97.84 0.00 98.41 0.00 87.24 0.75 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2795683273
96.43 0.10 98.84 0.07 95.33 0.07 100.00 0.00 96.79 0.00 97.95 0.10 98.41 0.00 87.73 0.48 /workspace/coverage/default/47.sysrst_ctrl_stress_all.3366827262
96.53 0.10 98.87 0.03 95.38 0.05 100.00 0.00 96.79 0.00 97.98 0.03 98.60 0.19 88.11 0.38 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.270652555
96.62 0.08 98.87 0.00 95.38 0.00 100.00 0.00 96.79 0.00 97.98 0.00 98.60 0.00 88.70 0.59 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.714454486
96.69 0.07 98.99 0.12 95.42 0.05 100.00 0.00 96.79 0.00 98.22 0.24 98.69 0.09 88.70 0.00 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.678573840
96.76 0.07 98.99 0.00 95.47 0.05 100.00 0.00 96.79 0.00 98.22 0.00 98.88 0.19 88.97 0.27 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2400363614
96.83 0.07 99.06 0.07 95.52 0.05 100.00 0.00 96.79 0.00 98.29 0.07 99.06 0.19 89.07 0.11 /workspace/coverage/default/49.sysrst_ctrl_stress_all.458927277
96.88 0.06 99.06 0.00 95.54 0.02 100.00 0.00 96.79 0.00 98.29 0.00 99.16 0.09 89.34 0.27 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2528651097
96.94 0.05 99.06 0.00 95.54 0.00 100.00 0.00 96.79 0.00 98.29 0.00 99.16 0.00 89.72 0.38 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3504886989
96.99 0.05 99.13 0.07 95.57 0.02 100.00 0.00 96.79 0.00 98.36 0.07 99.25 0.09 89.83 0.11 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.749801748
97.03 0.04 99.13 0.00 95.57 0.00 100.00 0.00 96.79 0.00 98.36 0.00 99.25 0.00 90.10 0.27 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.3343769936
97.07 0.04 99.13 0.00 95.83 0.26 100.00 0.00 96.79 0.00 98.36 0.00 99.25 0.00 90.10 0.00 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.2474505811
97.10 0.03 99.13 0.00 95.83 0.00 100.00 0.00 96.79 0.00 98.36 0.00 99.25 0.00 90.31 0.22 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.372374904
97.13 0.03 99.13 0.00 95.83 0.00 100.00 0.00 96.79 0.00 98.36 0.00 99.25 0.00 90.53 0.22 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.2358121524
97.15 0.03 99.17 0.03 95.85 0.02 100.00 0.00 96.79 0.00 98.40 0.03 99.34 0.09 90.53 0.00 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1277320077
97.18 0.03 99.20 0.03 95.88 0.02 100.00 0.00 96.79 0.00 98.43 0.03 99.44 0.09 90.53 0.00 /workspace/coverage/default/18.sysrst_ctrl_edge_detect.3226274180
97.21 0.03 99.24 0.03 95.90 0.02 100.00 0.00 96.79 0.00 98.47 0.03 99.53 0.09 90.53 0.00 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.554309049
97.23 0.02 99.24 0.00 95.90 0.00 100.00 0.00 96.79 0.00 98.47 0.00 99.53 0.00 90.69 0.16 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.13116673
97.25 0.02 99.24 0.00 95.90 0.00 100.00 0.00 96.79 0.00 98.47 0.00 99.53 0.00 90.85 0.16 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.625182204
97.27 0.02 99.24 0.00 95.92 0.02 100.00 0.00 96.79 0.00 98.47 0.00 99.53 0.00 90.96 0.11 /workspace/coverage/default/40.sysrst_ctrl_stress_all.2025951896
97.29 0.02 99.24 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.47 0.00 99.53 0.00 91.07 0.11 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.922203099
97.30 0.02 99.24 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.47 0.00 99.53 0.00 91.17 0.11 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.762595417
97.32 0.02 99.24 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.47 0.00 99.53 0.00 91.28 0.11 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2818467291
97.33 0.02 99.24 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.47 0.00 99.53 0.00 91.39 0.11 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2802456841
97.35 0.02 99.25 0.02 95.92 0.00 100.00 0.00 96.79 0.00 98.50 0.03 99.53 0.00 91.44 0.05 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.2386688647
97.36 0.01 99.27 0.02 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.07 99.53 0.00 91.44 0.00 /workspace/coverage/default/37.sysrst_ctrl_edge_detect.700584674
97.37 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.50 0.05 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2103298527
97.38 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.55 0.05 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.1098414917
97.39 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.60 0.05 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.659817363
97.39 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.66 0.05 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1582061481
97.40 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.71 0.05 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1134883971
97.41 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.77 0.05 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.3065308976
97.42 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.82 0.05 /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.24574020
97.42 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.87 0.05 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.275602984
97.43 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.93 0.05 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3166054630
97.44 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 91.98 0.05 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3551028114
97.45 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 92.03 0.05 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1822192162
97.45 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 92.09 0.05 /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2722073792
97.46 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 92.14 0.05 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1768888888
97.47 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 92.20 0.05 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2549100559
97.48 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 92.25 0.05 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1391854745
97.49 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 92.30 0.05 /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3925766729
97.49 0.01 99.27 0.00 95.92 0.00 100.00 0.00 96.79 0.00 98.57 0.00 99.53 0.00 92.36 0.05 /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2781139816
97.50 0.01 99.29 0.02 95.92 0.00 100.00 0.00 96.79 0.00 98.61 0.03 99.53 0.00 92.36 0.00 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.3358700757
97.51 0.01 99.31 0.02 95.92 0.00 100.00 0.00 96.79 0.00 98.64 0.03 99.53 0.00 92.36 0.00 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.1423050942
97.52 0.01 99.32 0.02 95.92 0.00 100.00 0.00 96.79 0.00 98.68 0.03 99.53 0.00 92.36 0.00 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.1457231651
97.52 0.01 99.32 0.00 95.97 0.05 100.00 0.00 96.79 0.00 98.68 0.00 99.53 0.00 92.36 0.00 /workspace/coverage/default/0.sysrst_ctrl_alert_test.3580400317
97.53 0.01 99.32 0.00 96.00 0.02 100.00 0.00 96.79 0.00 98.68 0.00 99.53 0.00 92.36 0.00 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1542853543

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2191530689
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2660285061
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2541557520
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.550808064
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3854528564
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.739101333
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.612888671
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3777113186
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.808060910
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2921857786
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1944325584
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1290841979
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1266170787
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1703762017
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.167707879
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1234875614
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.2367824307
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2673701060
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.573994950
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3212350001
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.816795363
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2793986341
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.3800622554
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.864597098
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3713622645
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2932077292
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1793494607
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2116634756
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.633054763
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.966545931
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3458700648
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2946635814
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3172148521
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2439821760
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1054735111
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1371608237
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2962931472
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.994692013
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3116381517
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1199208864
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3910558082
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1876831161
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3926953703
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2681931805
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4239894711
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4063465637
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3579173102
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.1149081706
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3848925984
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1204011583
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3592802524
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3838161178
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3189683509
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4145442899
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3194063819
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.740790689
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1535688778
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3122576588
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1724192410
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.613721552
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.651664008
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3105019856
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.896809490
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.723169444
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1729064921
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.950122818
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.2161127516
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3500175971
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2112393091
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.447750765
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.267726626
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.896035755
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2779728454
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.590609424
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3789717511
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1280372559
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3399133051
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3989157059
/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.869405222
/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2990487809
/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3829061276
/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.337586956
/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.378523532
/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3844662007
/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.1079012221
/workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.295949813
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2512077917
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2966803866
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.40499911
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1482836045
/workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.347205012
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/workspace/coverage/default/44.sysrst_ctrl_alert_test.113113353
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2197098072
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1066517801
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.4084756637
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3111501630
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.130027254
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1907825374
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.4283225030
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.1076831277
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2133047987
/workspace/coverage/default/44.sysrst_ctrl_smoke.3089324597
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2348395027
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.546520238
/workspace/coverage/default/45.sysrst_ctrl_alert_test.2136423530
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2071816325
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1338075271
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2306773157
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3706369539
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3664875054
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1095745289
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.2305979997
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.3984929355
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3198767950
/workspace/coverage/default/45.sysrst_ctrl_smoke.251813929
/workspace/coverage/default/45.sysrst_ctrl_stress_all.4175573383
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2201735546
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2420708072
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1361125172
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.966056133
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.461768672
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1599257445
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1553431714
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2847318401
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.4036224897
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2105883071
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2844212838
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2166513592
/workspace/coverage/default/46.sysrst_ctrl_smoke.2519267008
/workspace/coverage/default/46.sysrst_ctrl_stress_all.3102154062
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2959199348
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2610874855
/workspace/coverage/default/47.sysrst_ctrl_alert_test.59961189
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1452853596
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.3551790890
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.635920842
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1307613445
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3269620865
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.182371560
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2274445332
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.1028494165
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3429935930
/workspace/coverage/default/47.sysrst_ctrl_smoke.433692020
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.515714216
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.4105075049
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2750648139
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3876864575
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2823405214
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1489919547
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1979659538
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2380623684
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2495413281
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3337515202
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3415740387
/workspace/coverage/default/48.sysrst_ctrl_smoke.2735734247
/workspace/coverage/default/48.sysrst_ctrl_stress_all.4275037960
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.40803141
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3083828491
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1148685344
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1887411778
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1989047342
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2925530348
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3642463924
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1691580587
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1477952688
/workspace/coverage/default/49.sysrst_ctrl_smoke.4217708670
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3226672317
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1867437678
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3821792934
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.2165271934
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2015436387
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3556062780
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3486158146
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2034732511
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3666755123
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.193337202
/workspace/coverage/default/5.sysrst_ctrl_smoke.3914950262
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2630540217
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1033111450
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.642912124
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.4126064069
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.649400877
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3347196563
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.4132458917
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3877623376
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3189298749
/workspace/coverage/default/6.sysrst_ctrl_alert_test.405246881
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3516087009
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.906109842
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.3564061057
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.4259831345
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.3056498661
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1497802058
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3625875629
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3454728864
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3847657038
/workspace/coverage/default/6.sysrst_ctrl_smoke.1767476330
/workspace/coverage/default/6.sysrst_ctrl_stress_all.469702178
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1422363311
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3784993279
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3923506068
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.922922280
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1801434375
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1383846628
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.4084034309
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2575726504
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3937881867
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2350405588
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2660757923
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1093080952
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.288040026
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1914933892
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1488418380
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1234162975
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1932659595
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.284062483
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3940249003
/workspace/coverage/default/7.sysrst_ctrl_smoke.3541235579
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1482148033
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.869391676
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3046293782
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.630264472
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.349742144
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1801609265
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3661386135
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.668363344
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2270916530
/workspace/coverage/default/8.sysrst_ctrl_alert_test.1432937113
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1338586693
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1540412526
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.14442663
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3752006201
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2766686139
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.4187915282
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2165779757
/workspace/coverage/default/8.sysrst_ctrl_smoke.2062612006
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3133021757
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.4083629015
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1023788841
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2770760026
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3855156491
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2718691899
/workspace/coverage/default/9.sysrst_ctrl_alert_test.745593667
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1815656479
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2063323855
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2236577771
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.469656853
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3418841014
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2787616414
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3159528689
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.4276586996
/workspace/coverage/default/9.sysrst_ctrl_smoke.3776515731
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1201875343
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2734153889
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.4162345437
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1284121508
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1565711841
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3754997688
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.561326679
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3537066867



Total test records in report: 884
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T7 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2957565385 Jan 07 12:31:43 PM PST 24 Jan 07 12:33:35 PM PST 24 2014427188 ps
T1 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1929242098 Jan 07 12:23:08 PM PST 24 Jan 07 12:24:09 PM PST 24 22199214050 ps
T2 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1944325584 Jan 07 12:29:56 PM PST 24 Jan 07 12:31:54 PM PST 24 2112442067 ps
T24 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.13116673 Jan 07 12:30:20 PM PST 24 Jan 07 12:33:41 PM PST 24 38488721132 ps
T3 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.740790689 Jan 07 12:30:55 PM PST 24 Jan 07 12:33:20 PM PST 24 5280431720 ps
T6 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2541557520 Jan 07 12:26:39 PM PST 24 Jan 07 12:28:13 PM PST 24 6031577366 ps
T4 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.808060910 Jan 07 12:33:15 PM PST 24 Jan 07 12:34:29 PM PST 24 3167047210 ps
T8 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.407617422 Jan 07 12:30:17 PM PST 24 Jan 07 12:33:50 PM PST 24 42390657522 ps
T25 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.350233070 Jan 07 12:37:03 PM PST 24 Jan 07 12:38:15 PM PST 24 2013145312 ps
T5 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2512077917 Jan 07 12:32:32 PM PST 24 Jan 07 12:34:10 PM PST 24 3163619144 ps
T26 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3838161178 Jan 07 12:27:05 PM PST 24 Jan 07 12:28:29 PM PST 24 2013761725 ps
T9 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.395315101 Jan 07 12:25:02 PM PST 24 Jan 07 12:26:14 PM PST 24 2082325126 ps
T37 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2981375570 Jan 07 12:33:55 PM PST 24 Jan 07 12:35:06 PM PST 24 2042270523 ps
T10 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.573994950 Jan 07 12:27:09 PM PST 24 Jan 07 12:28:30 PM PST 24 10967443983 ps
T300 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.2990487809 Jan 07 12:24:10 PM PST 24 Jan 07 12:24:33 PM PST 24 2012059553 ps
T260 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3220712166 Jan 07 12:24:10 PM PST 24 Jan 07 12:24:31 PM PST 24 2524221724 ps
T286 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.896809490 Jan 07 12:31:27 PM PST 24 Jan 07 12:33:29 PM PST 24 2012105980 ps
T11 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.2681931805 Jan 07 12:33:15 PM PST 24 Jan 07 12:34:24 PM PST 24 4719137557 ps
T12 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.809540325 Jan 07 12:28:48 PM PST 24 Jan 07 12:29:59 PM PST 24 2179067119 ps
T264 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.612888671 Jan 07 12:31:36 PM PST 24 Jan 07 12:34:42 PM PST 24 2036893512 ps
T354 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.3500175971 Jan 07 12:27:49 PM PST 24 Jan 07 12:29:06 PM PST 24 2062552633 ps
T367 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2112393091 Jan 07 12:27:22 PM PST 24 Jan 07 12:28:30 PM PST 24 2158686431 ps
T297 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3844662007 Jan 07 12:29:43 PM PST 24 Jan 07 12:31:07 PM PST 24 2127342030 ps
T13 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2475013200 Jan 07 12:30:55 PM PST 24 Jan 07 12:32:59 PM PST 24 4819930193 ps
T34 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2400363614 Jan 07 12:30:03 PM PST 24 Jan 07 12:32:45 PM PST 24 42951430584 ps
T287 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.295949813 Jan 07 12:31:07 PM PST 24 Jan 07 12:32:45 PM PST 24 2035364783 ps
T288 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.3116381517 Jan 07 12:29:09 PM PST 24 Jan 07 12:30:51 PM PST 24 2018443910 ps
T279 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.324405220 Jan 07 12:29:39 PM PST 24 Jan 07 12:31:46 PM PST 24 2111991075 ps
T293 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.1290841979 Jan 07 12:30:27 PM PST 24 Jan 07 12:32:17 PM PST 24 2056438473 ps
T35 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2191530689 Jan 07 12:25:47 PM PST 24 Jan 07 12:26:53 PM PST 24 2128468252 ps
T294 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2875453162 Jan 07 12:27:47 PM PST 24 Jan 07 12:29:29 PM PST 24 2020320813 ps
T280 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4145442899 Jan 07 12:24:44 PM PST 24 Jan 07 12:25:51 PM PST 24 2070503991 ps
T295 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2103298527 Jan 07 12:26:27 PM PST 24 Jan 07 12:27:44 PM PST 24 2011478955 ps
T296 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3172148521 Jan 07 12:30:03 PM PST 24 Jan 07 12:31:57 PM PST 24 2099104912 ps
T36 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4158025307 Jan 07 12:23:49 PM PST 24 Jan 07 12:24:00 PM PST 24 2072793159 ps
T267 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1782384743 Jan 07 12:28:38 PM PST 24 Jan 07 12:29:54 PM PST 24 2128669473 ps
T281 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3077597808 Jan 07 12:28:54 PM PST 24 Jan 07 12:30:17 PM PST 24 2038773029 ps
T310 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.3910558082 Jan 07 12:29:11 PM PST 24 Jan 07 12:32:03 PM PST 24 22199687831 ps
T311 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3854528564 Jan 07 12:26:25 PM PST 24 Jan 07 12:27:36 PM PST 24 2118624168 ps
T368 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.613721552 Jan 07 12:30:17 PM PST 24 Jan 07 12:33:58 PM PST 24 4057141533 ps
T282 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3105019856 Jan 07 12:30:09 PM PST 24 Jan 07 12:31:40 PM PST 24 2080098634 ps
T265 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2617960663 Jan 07 12:26:24 PM PST 24 Jan 07 12:27:35 PM PST 24 2157625991 ps
T283 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1234875614 Jan 07 12:28:01 PM PST 24 Jan 07 12:29:16 PM PST 24 2055927510 ps
T298 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3194063819 Jan 07 12:29:07 PM PST 24 Jan 07 12:30:36 PM PST 24 2038385328 ps
T369 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2779728454 Jan 07 12:27:48 PM PST 24 Jan 07 12:28:52 PM PST 24 2012760977 ps
T370 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1876831161 Jan 07 12:32:38 PM PST 24 Jan 07 12:34:31 PM PST 24 2063015865 ps
T301 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.723169444 Jan 07 12:30:19 PM PST 24 Jan 07 12:32:18 PM PST 24 5284508958 ps
T284 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.235312323 Jan 07 12:36:57 PM PST 24 Jan 07 12:39:42 PM PST 24 22223512341 ps
T268 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2946635814 Jan 07 12:26:23 PM PST 24 Jan 07 12:27:35 PM PST 24 2073063973 ps
T302 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3789717511 Jan 07 12:31:54 PM PST 24 Jan 07 12:33:15 PM PST 24 6072099410 ps
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