Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
800 |
1 |
|
|
T75 |
6 |
|
T25 |
9 |
|
T64 |
8 |
| auto[1] |
820 |
1 |
|
|
T75 |
14 |
|
T25 |
11 |
|
T64 |
12 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
796 |
1 |
|
|
T75 |
11 |
|
T25 |
7 |
|
T64 |
9 |
| auto[1] |
824 |
1 |
|
|
T75 |
9 |
|
T25 |
13 |
|
T64 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
810 |
1 |
|
|
T75 |
13 |
|
T25 |
8 |
|
T64 |
9 |
| auto[1] |
810 |
1 |
|
|
T75 |
7 |
|
T25 |
12 |
|
T64 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T75 |
10 |
|
T25 |
9 |
|
T64 |
7 |
| auto[1] |
792 |
1 |
|
|
T75 |
10 |
|
T25 |
11 |
|
T64 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T75 |
11 |
|
T25 |
8 |
|
T64 |
12 |
| auto[1] |
794 |
1 |
|
|
T75 |
9 |
|
T25 |
12 |
|
T64 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
822 |
1 |
|
|
T75 |
13 |
|
T25 |
10 |
|
T64 |
10 |
| auto[1] |
798 |
1 |
|
|
T75 |
7 |
|
T25 |
10 |
|
T64 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T75 |
11 |
|
T25 |
10 |
|
T64 |
12 |
| auto[1] |
822 |
1 |
|
|
T75 |
9 |
|
T25 |
10 |
|
T64 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
819 |
1 |
|
|
T75 |
13 |
|
T25 |
12 |
|
T64 |
13 |
| auto[1] |
801 |
1 |
|
|
T75 |
7 |
|
T25 |
8 |
|
T64 |
7 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
784 |
1 |
|
|
T75 |
13 |
|
T25 |
5 |
|
T64 |
8 |
| auto[1] |
836 |
1 |
|
|
T75 |
7 |
|
T25 |
15 |
|
T64 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
810 |
1 |
|
|
T75 |
8 |
|
T25 |
13 |
|
T64 |
7 |
| auto[1] |
810 |
1 |
|
|
T75 |
12 |
|
T25 |
7 |
|
T64 |
13 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
796 |
1 |
|
|
T75 |
6 |
|
T25 |
10 |
|
T64 |
10 |
| auto[1] |
824 |
1 |
|
|
T75 |
14 |
|
T25 |
10 |
|
T64 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T75 |
11 |
|
T25 |
11 |
|
T64 |
9 |
| auto[1] |
788 |
1 |
|
|
T75 |
9 |
|
T25 |
9 |
|
T64 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T75 |
11 |
|
T25 |
8 |
|
T64 |
13 |
| auto[1] |
800 |
1 |
|
|
T75 |
9 |
|
T25 |
12 |
|
T64 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
796 |
1 |
|
|
T75 |
11 |
|
T25 |
7 |
|
T64 |
9 |
| auto[1] |
824 |
1 |
|
|
T75 |
9 |
|
T25 |
13 |
|
T64 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T75 |
9 |
|
T25 |
11 |
|
T64 |
6 |
| auto[1] |
806 |
1 |
|
|
T75 |
11 |
|
T25 |
9 |
|
T64 |
14 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
802 |
1 |
|
|
T75 |
10 |
|
T25 |
8 |
|
T64 |
10 |
| auto[1] |
818 |
1 |
|
|
T75 |
10 |
|
T25 |
12 |
|
T64 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T75 |
9 |
|
T25 |
12 |
|
T64 |
7 |
| auto[1] |
799 |
1 |
|
|
T75 |
11 |
|
T25 |
8 |
|
T64 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T75 |
11 |
|
T25 |
10 |
|
T64 |
7 |
| auto[1] |
819 |
1 |
|
|
T75 |
9 |
|
T25 |
10 |
|
T64 |
13 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
796 |
1 |
|
|
T75 |
13 |
|
T25 |
8 |
|
T64 |
10 |
| auto[1] |
824 |
1 |
|
|
T75 |
7 |
|
T25 |
12 |
|
T64 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
809 |
1 |
|
|
T75 |
11 |
|
T25 |
12 |
|
T64 |
9 |
| auto[1] |
811 |
1 |
|
|
T75 |
9 |
|
T25 |
8 |
|
T64 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
791 |
1 |
|
|
T75 |
9 |
|
T25 |
8 |
|
T64 |
9 |
| auto[1] |
829 |
1 |
|
|
T75 |
11 |
|
T25 |
12 |
|
T64 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
809 |
1 |
|
|
T75 |
11 |
|
T25 |
7 |
|
T64 |
6 |
| auto[1] |
811 |
1 |
|
|
T75 |
9 |
|
T25 |
13 |
|
T64 |
14 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
809 |
1 |
|
|
T75 |
13 |
|
T25 |
10 |
|
T64 |
9 |
| auto[1] |
811 |
1 |
|
|
T75 |
7 |
|
T25 |
10 |
|
T64 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T75 |
11 |
|
T25 |
11 |
|
T64 |
9 |
| auto[1] |
788 |
1 |
|
|
T75 |
9 |
|
T25 |
9 |
|
T64 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
413 |
1 |
|
|
T75 |
6 |
|
T25 |
4 |
|
T64 |
2 |
| auto[0] |
auto[1] |
401 |
1 |
|
|
T75 |
3 |
|
T25 |
7 |
|
T64 |
4 |
| auto[1] |
auto[0] |
397 |
1 |
|
|
T75 |
7 |
|
T25 |
4 |
|
T64 |
7 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T75 |
4 |
|
T25 |
5 |
|
T64 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
416 |
1 |
|
|
T75 |
5 |
|
T25 |
3 |
|
T64 |
3 |
| auto[0] |
auto[1] |
386 |
1 |
|
|
T75 |
5 |
|
T25 |
5 |
|
T64 |
7 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T75 |
5 |
|
T25 |
6 |
|
T64 |
4 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T75 |
5 |
|
T25 |
6 |
|
T64 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T75 |
5 |
|
T25 |
4 |
|
T64 |
1 |
| auto[0] |
auto[1] |
413 |
1 |
|
|
T75 |
4 |
|
T25 |
8 |
|
T64 |
6 |
| auto[1] |
auto[0] |
418 |
1 |
|
|
T75 |
6 |
|
T25 |
4 |
|
T64 |
11 |
| auto[1] |
auto[1] |
381 |
1 |
|
|
T75 |
5 |
|
T25 |
4 |
|
T64 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
396 |
1 |
|
|
T75 |
7 |
|
T25 |
4 |
|
T65 |
7 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T75 |
4 |
|
T25 |
6 |
|
T64 |
7 |
| auto[1] |
auto[0] |
426 |
1 |
|
|
T75 |
6 |
|
T25 |
6 |
|
T64 |
10 |
| auto[1] |
auto[1] |
393 |
1 |
|
|
T75 |
3 |
|
T25 |
4 |
|
T64 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
383 |
1 |
|
|
T75 |
7 |
|
T25 |
4 |
|
T64 |
6 |
| auto[0] |
auto[1] |
413 |
1 |
|
|
T75 |
6 |
|
T25 |
4 |
|
T64 |
4 |
| auto[1] |
auto[0] |
415 |
1 |
|
|
T75 |
4 |
|
T25 |
6 |
|
T64 |
6 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T75 |
3 |
|
T25 |
6 |
|
T64 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
400 |
1 |
|
|
T75 |
7 |
|
T25 |
7 |
|
T64 |
6 |
| auto[0] |
auto[1] |
409 |
1 |
|
|
T75 |
4 |
|
T25 |
5 |
|
T64 |
3 |
| auto[1] |
auto[0] |
419 |
1 |
|
|
T75 |
6 |
|
T25 |
5 |
|
T64 |
7 |
| auto[1] |
auto[1] |
392 |
1 |
|
|
T75 |
3 |
|
T25 |
3 |
|
T64 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
389 |
1 |
|
|
T75 |
4 |
|
T25 |
4 |
|
T64 |
1 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T75 |
7 |
|
T25 |
3 |
|
T64 |
5 |
| auto[1] |
auto[0] |
421 |
1 |
|
|
T75 |
4 |
|
T25 |
9 |
|
T64 |
6 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T75 |
5 |
|
T25 |
4 |
|
T64 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
382 |
1 |
|
|
T75 |
4 |
|
T25 |
4 |
|
T64 |
4 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T75 |
9 |
|
T25 |
6 |
|
T64 |
5 |
| auto[1] |
auto[0] |
414 |
1 |
|
|
T75 |
2 |
|
T25 |
6 |
|
T64 |
6 |
| auto[1] |
auto[1] |
397 |
1 |
|
|
T75 |
5 |
|
T25 |
4 |
|
T64 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
395 |
1 |
|
|
T75 |
2 |
|
T25 |
1 |
|
T64 |
5 |
| auto[0] |
auto[1] |
425 |
1 |
|
|
T75 |
9 |
|
T25 |
7 |
|
T64 |
8 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T75 |
4 |
|
T25 |
8 |
|
T64 |
3 |
| auto[1] |
auto[1] |
395 |
1 |
|
|
T75 |
5 |
|
T25 |
4 |
|
T64 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
796 |
1 |
|
|
T75 |
11 |
|
T25 |
7 |
|
T64 |
9 |
| auto[1] |
auto[1] |
824 |
1 |
|
|
T75 |
9 |
|
T25 |
13 |
|
T64 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T75 |
6 |
|
T25 |
2 |
|
T64 |
4 |
| auto[0] |
auto[1] |
397 |
1 |
|
|
T75 |
3 |
|
T25 |
6 |
|
T64 |
5 |
| auto[1] |
auto[0] |
390 |
1 |
|
|
T75 |
7 |
|
T25 |
3 |
|
T64 |
4 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T75 |
4 |
|
T25 |
9 |
|
T64 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
832 |
1 |
|
|
T75 |
11 |
|
T25 |
11 |
|
T64 |
9 |
| auto[1] |
auto[1] |
788 |
1 |
|
|
T75 |
9 |
|
T25 |
9 |
|
T64 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T44 |
11 |
|
T146 |
6 |
|
T105 |
7 |
| auto[1] |
164 |
1 |
|
|
T44 |
9 |
|
T146 |
14 |
|
T105 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T44 |
10 |
|
T146 |
7 |
|
T105 |
9 |
| auto[1] |
147 |
1 |
|
|
T44 |
10 |
|
T146 |
13 |
|
T105 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T44 |
11 |
|
T146 |
8 |
|
T105 |
9 |
| auto[1] |
152 |
1 |
|
|
T44 |
9 |
|
T146 |
12 |
|
T105 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
127 |
1 |
|
|
T44 |
11 |
|
T146 |
8 |
|
T105 |
11 |
| auto[1] |
173 |
1 |
|
|
T44 |
9 |
|
T146 |
12 |
|
T105 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T44 |
8 |
|
T146 |
9 |
|
T105 |
9 |
| auto[1] |
166 |
1 |
|
|
T44 |
12 |
|
T146 |
11 |
|
T105 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T44 |
11 |
|
T146 |
9 |
|
T105 |
11 |
| auto[1] |
143 |
1 |
|
|
T44 |
9 |
|
T146 |
11 |
|
T105 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T44 |
6 |
|
T146 |
8 |
|
T105 |
9 |
| auto[1] |
156 |
1 |
|
|
T44 |
14 |
|
T146 |
12 |
|
T105 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T44 |
12 |
|
T146 |
9 |
|
T105 |
10 |
| auto[1] |
157 |
1 |
|
|
T44 |
8 |
|
T146 |
11 |
|
T105 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T44 |
13 |
|
T146 |
9 |
|
T105 |
12 |
| auto[1] |
131 |
1 |
|
|
T44 |
7 |
|
T146 |
11 |
|
T105 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T44 |
9 |
|
T146 |
10 |
|
T105 |
9 |
| auto[1] |
155 |
1 |
|
|
T44 |
11 |
|
T146 |
10 |
|
T105 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
164 |
1 |
|
|
T44 |
10 |
|
T146 |
12 |
|
T105 |
12 |
| auto[1] |
136 |
1 |
|
|
T44 |
10 |
|
T146 |
8 |
|
T105 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T44 |
8 |
|
T146 |
13 |
|
T105 |
11 |
| auto[1] |
149 |
1 |
|
|
T44 |
12 |
|
T146 |
7 |
|
T105 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
152 |
1 |
|
|
T44 |
9 |
|
T146 |
11 |
|
T105 |
8 |
| auto[1] |
148 |
1 |
|
|
T44 |
11 |
|
T146 |
9 |
|
T105 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T44 |
10 |
|
T146 |
7 |
|
T105 |
9 |
| auto[1] |
147 |
1 |
|
|
T44 |
10 |
|
T146 |
13 |
|
T105 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
152 |
1 |
|
|
T44 |
7 |
|
T146 |
11 |
|
T105 |
9 |
| auto[1] |
148 |
1 |
|
|
T44 |
13 |
|
T146 |
9 |
|
T105 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T44 |
7 |
|
T146 |
11 |
|
T105 |
7 |
| auto[1] |
159 |
1 |
|
|
T44 |
13 |
|
T146 |
9 |
|
T105 |
13 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T44 |
8 |
|
T146 |
12 |
|
T105 |
10 |
| auto[1] |
138 |
1 |
|
|
T44 |
12 |
|
T146 |
8 |
|
T105 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
163 |
1 |
|
|
T44 |
15 |
|
T146 |
12 |
|
T105 |
8 |
| auto[1] |
137 |
1 |
|
|
T44 |
5 |
|
T146 |
8 |
|
T105 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
169 |
1 |
|
|
T44 |
11 |
|
T146 |
10 |
|
T105 |
13 |
| auto[1] |
131 |
1 |
|
|
T44 |
9 |
|
T146 |
10 |
|
T105 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T44 |
15 |
|
T146 |
13 |
|
T105 |
10 |
| auto[1] |
142 |
1 |
|
|
T44 |
5 |
|
T146 |
7 |
|
T105 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T44 |
11 |
|
T146 |
12 |
|
T105 |
12 |
| auto[1] |
144 |
1 |
|
|
T44 |
9 |
|
T146 |
8 |
|
T105 |
8 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T44 |
8 |
|
T146 |
10 |
|
T105 |
8 |
| auto[1] |
138 |
1 |
|
|
T44 |
12 |
|
T146 |
10 |
|
T105 |
12 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T44 |
13 |
|
T146 |
10 |
|
T105 |
11 |
| auto[1] |
139 |
1 |
|
|
T44 |
7 |
|
T146 |
10 |
|
T105 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T44 |
8 |
|
T146 |
13 |
|
T105 |
11 |
| auto[1] |
149 |
1 |
|
|
T44 |
12 |
|
T146 |
7 |
|
T105 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T44 |
4 |
|
T146 |
6 |
|
T105 |
4 |
| auto[0] |
auto[1] |
76 |
1 |
|
|
T44 |
3 |
|
T146 |
5 |
|
T105 |
5 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T44 |
7 |
|
T146 |
2 |
|
T105 |
5 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T44 |
6 |
|
T146 |
7 |
|
T105 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T44 |
4 |
|
T146 |
6 |
|
T105 |
4 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T44 |
3 |
|
T146 |
5 |
|
T105 |
3 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T44 |
7 |
|
T146 |
2 |
|
T105 |
7 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T44 |
6 |
|
T146 |
7 |
|
T105 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T44 |
3 |
|
T146 |
6 |
|
T105 |
3 |
| auto[0] |
auto[1] |
97 |
1 |
|
|
T44 |
5 |
|
T146 |
6 |
|
T105 |
7 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T44 |
5 |
|
T146 |
3 |
|
T105 |
6 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T44 |
7 |
|
T146 |
5 |
|
T105 |
4 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
77 |
1 |
|
|
T44 |
8 |
|
T146 |
6 |
|
T105 |
3 |
| auto[0] |
auto[1] |
86 |
1 |
|
|
T44 |
7 |
|
T146 |
6 |
|
T105 |
5 |
| auto[1] |
auto[0] |
80 |
1 |
|
|
T44 |
3 |
|
T146 |
3 |
|
T105 |
8 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T44 |
2 |
|
T146 |
5 |
|
T105 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T44 |
3 |
|
T146 |
5 |
|
T105 |
8 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T44 |
8 |
|
T146 |
5 |
|
T105 |
5 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T44 |
3 |
|
T146 |
3 |
|
T105 |
1 |
| auto[1] |
auto[1] |
77 |
1 |
|
|
T44 |
6 |
|
T146 |
7 |
|
T105 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T44 |
8 |
|
T146 |
7 |
|
T105 |
7 |
| auto[0] |
auto[1] |
74 |
1 |
|
|
T44 |
7 |
|
T146 |
6 |
|
T105 |
3 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T44 |
4 |
|
T146 |
2 |
|
T105 |
3 |
| auto[1] |
auto[1] |
83 |
1 |
|
|
T44 |
1 |
|
T146 |
5 |
|
T105 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
73 |
1 |
|
|
T44 |
4 |
|
T146 |
4 |
|
T105 |
4 |
| auto[0] |
auto[1] |
89 |
1 |
|
|
T44 |
4 |
|
T146 |
6 |
|
T105 |
4 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T44 |
5 |
|
T146 |
6 |
|
T105 |
5 |
| auto[1] |
auto[1] |
66 |
1 |
|
|
T44 |
7 |
|
T146 |
4 |
|
T105 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
82 |
1 |
|
|
T44 |
7 |
|
T146 |
5 |
|
T105 |
7 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T44 |
6 |
|
T146 |
5 |
|
T105 |
4 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T44 |
3 |
|
T146 |
7 |
|
T105 |
5 |
| auto[1] |
auto[1] |
57 |
1 |
|
|
T44 |
4 |
|
T146 |
3 |
|
T105 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
72 |
1 |
|
|
T44 |
6 |
|
T146 |
4 |
|
T105 |
3 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T44 |
3 |
|
T146 |
7 |
|
T105 |
5 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T44 |
5 |
|
T146 |
2 |
|
T105 |
4 |
| auto[1] |
auto[1] |
84 |
1 |
|
|
T44 |
6 |
|
T146 |
7 |
|
T105 |
8 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
153 |
1 |
|
|
T44 |
10 |
|
T146 |
7 |
|
T105 |
9 |
| auto[1] |
auto[1] |
147 |
1 |
|
|
T44 |
10 |
|
T146 |
13 |
|
T105 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
85 |
1 |
|
|
T44 |
6 |
|
T146 |
4 |
|
T105 |
8 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T44 |
5 |
|
T146 |
8 |
|
T105 |
4 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T44 |
7 |
|
T146 |
5 |
|
T105 |
4 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T44 |
2 |
|
T146 |
3 |
|
T105 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
151 |
1 |
|
|
T44 |
8 |
|
T146 |
13 |
|
T105 |
11 |
| auto[1] |
auto[1] |
149 |
1 |
|
|
T44 |
12 |
|
T146 |
7 |
|
T105 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
59 |
1 |
|
|
T44 |
8 |
|
T207 |
12 |
|
T179 |
9 |
| auto[1] |
61 |
1 |
|
|
T44 |
12 |
|
T207 |
8 |
|
T179 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
68 |
1 |
|
|
T44 |
9 |
|
T207 |
11 |
|
T179 |
12 |
| auto[1] |
52 |
1 |
|
|
T44 |
11 |
|
T207 |
9 |
|
T179 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T44 |
9 |
|
T207 |
10 |
|
T179 |
13 |
| auto[1] |
56 |
1 |
|
|
T44 |
11 |
|
T207 |
10 |
|
T179 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
56 |
1 |
|
|
T44 |
9 |
|
T207 |
9 |
|
T179 |
13 |
| auto[1] |
64 |
1 |
|
|
T44 |
11 |
|
T207 |
11 |
|
T179 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T44 |
11 |
|
T207 |
8 |
|
T179 |
7 |
| auto[1] |
60 |
1 |
|
|
T44 |
9 |
|
T207 |
12 |
|
T179 |
13 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T44 |
12 |
|
T207 |
9 |
|
T179 |
10 |
| auto[1] |
58 |
1 |
|
|
T44 |
8 |
|
T207 |
11 |
|
T179 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T44 |
7 |
|
T207 |
12 |
|
T179 |
12 |
| auto[1] |
58 |
1 |
|
|
T44 |
13 |
|
T207 |
8 |
|
T179 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T44 |
7 |
|
T207 |
12 |
|
T179 |
12 |
| auto[1] |
63 |
1 |
|
|
T44 |
13 |
|
T207 |
8 |
|
T179 |
8 |