Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.73	99.34	96.00	100.00	96.15	98.75	99.44	94.41

Total tests in report: 905

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
67.06	67.06	72.56	72.56	65.94	65.94	80.87	80.87	96.15	96.15	76.12	76.12	57.49	57.49	20.26	20.26	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2947917444
76.60	9.54	86.28	13.72	76.88	10.94	87.47	6.61	96.15	0.00	87.33	11.21	74.34	16.85	27.74	7.49	/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2963550613
83.89	7.29	90.94	4.65	81.76	4.89	89.98	2.51	96.15	0.00	90.67	3.34	83.71	9.36	54.05	26.31	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.754100167
86.36	2.47	93.12	2.19	85.55	3.79	89.98	0.00	96.15	0.00	93.07	2.40	89.04	5.34	57.59	3.54	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3571308367
88.40	2.04	95.45	2.33	87.68	2.12	91.80	1.82	96.15	0.00	94.64	1.57	92.79	3.75	60.26	2.67	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2147268531
90.03	1.63	95.85	0.40	91.82	4.15	97.49	5.69	96.15	0.00	95.20	0.56	93.26	0.47	60.41	0.15	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4176724786
91.43	1.40	95.90	0.05	91.82	0.00	97.49	0.00	96.15	0.00	95.30	0.10	93.26	0.00	70.05	9.64	/workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1980921475
92.66	1.24	96.15	0.24	92.13	0.31	97.49	0.00	96.15	0.00	95.48	0.17	93.91	0.66	77.33	7.28	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.131458418
93.44	0.78	97.15	1.01	93.02	0.88	97.49	0.00	96.15	0.00	96.41	0.94	96.44	2.53	77.44	0.10	/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2437647034
93.90	0.45	98.26	1.11	93.42	0.41	97.49	0.00	96.15	0.00	97.60	1.18	96.91	0.47	77.44	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.1789345510
94.34	0.44	98.32	0.05	94.54	1.12	97.95	0.46	96.15	0.00	97.63	0.03	97.10	0.19	78.67	1.23	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2405655289
94.75	0.41	98.61	0.30	94.73	0.19	99.09	1.14	96.15	0.00	97.74	0.10	97.28	0.19	79.64	0.97	/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2533296213
95.10	0.35	98.63	0.02	94.95	0.21	99.32	0.23	96.15	0.00	97.81	0.07	97.38	0.09	81.49	1.85	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4236073518
95.45	0.35	98.63	0.00	94.95	0.00	99.32	0.00	96.15	0.00	97.81	0.00	97.38	0.00	83.95	2.46	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2449141782
95.78	0.32	98.63	0.00	94.95	0.00	99.32	0.00	96.15	0.00	97.81	0.00	97.38	0.00	86.21	2.26	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.1641618528
95.97	0.19	98.70	0.07	95.02	0.07	99.32	0.00	96.15	0.00	97.95	0.14	97.47	0.09	87.18	0.97	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3530480558
96.12	0.15	98.70	0.00	95.02	0.00	99.32	0.00	96.15	0.00	97.95	0.00	97.47	0.00	88.26	1.08	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3107560231
96.25	0.13	98.70	0.00	95.02	0.00	99.32	0.00	96.15	0.00	97.95	0.00	98.13	0.66	88.51	0.26	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2293199863
96.38	0.13	98.70	0.00	95.04	0.02	100.00	0.68	96.15	0.00	97.95	0.00	98.22	0.09	88.62	0.10	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3143146725
96.50	0.12	98.84	0.14	95.28	0.24	100.00	0.00	96.15	0.00	98.12	0.17	98.50	0.28	88.62	0.00	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1837346912
96.61	0.11	98.84	0.00	95.28	0.00	100.00	0.00	96.15	0.00	98.12	0.00	98.50	0.00	89.38	0.77	/workspace/coverage/default/19.sysrst_ctrl_combo_detect.200800405
96.69	0.08	98.84	0.00	95.28	0.00	100.00	0.00	96.15	0.00	98.12	0.00	98.50	0.00	89.95	0.56	/workspace/coverage/default/8.sysrst_ctrl_combo_detect.477292983
96.77	0.08	98.94	0.10	95.35	0.07	100.00	0.00	96.15	0.00	98.22	0.10	98.78	0.28	89.95	0.00	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1266199418
96.85	0.07	98.94	0.00	95.35	0.00	100.00	0.00	96.15	0.00	98.22	0.00	98.78	0.00	90.46	0.51	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4276081083
96.92	0.07	98.94	0.00	95.40	0.05	100.00	0.00	96.15	0.00	98.22	0.00	98.78	0.00	90.92	0.46	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3093197191
96.98	0.06	99.01	0.07	95.47	0.07	100.00	0.00	96.15	0.00	98.33	0.10	98.78	0.00	91.13	0.21	/workspace/coverage/default/28.sysrst_ctrl_combo_detect.2898413156
97.05	0.06	99.06	0.05	95.49	0.02	100.00	0.00	96.15	0.00	98.40	0.07	98.88	0.09	91.33	0.21	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4236741831
97.10	0.05	99.08	0.02	95.49	0.00	100.00	0.00	96.15	0.00	98.43	0.03	98.88	0.00	91.64	0.31	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2447954723
97.15	0.05	99.08	0.00	95.49	0.00	100.00	0.00	96.15	0.00	98.43	0.00	98.88	0.00	92.00	0.36	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3980787167
97.19	0.04	99.10	0.02	95.49	0.00	100.00	0.00	96.15	0.00	98.47	0.03	98.88	0.00	92.26	0.26	/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2325405603
97.24	0.04	99.10	0.00	95.49	0.00	100.00	0.00	96.15	0.00	98.47	0.00	98.88	0.00	92.56	0.31	/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.83791579
97.27	0.03	99.13	0.03	95.52	0.02	100.00	0.00	96.15	0.00	98.50	0.03	98.97	0.09	92.62	0.05	/workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.864452210
97.30	0.03	99.13	0.00	95.52	0.00	100.00	0.00	96.15	0.00	98.50	0.00	98.97	0.00	92.82	0.21	/workspace/coverage/default/40.sysrst_ctrl_stress_all.3164647586
97.33	0.03	99.17	0.03	95.54	0.02	100.00	0.00	96.15	0.00	98.54	0.03	99.06	0.09	92.82	0.00	/workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3971455685
97.35	0.03	99.20	0.03	95.57	0.02	100.00	0.00	96.15	0.00	98.57	0.03	99.16	0.09	92.82	0.00	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.2637627963
97.38	0.03	99.24	0.03	95.59	0.02	100.00	0.00	96.15	0.00	98.61	0.03	99.25	0.09	92.82	0.00	/workspace/coverage/default/33.sysrst_ctrl_edge_detect.1582318362
97.41	0.03	99.27	0.03	95.61	0.02	100.00	0.00	96.15	0.00	98.64	0.03	99.34	0.09	92.82	0.00	/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3319625776
97.43	0.02	99.27	0.00	95.78	0.17	100.00	0.00	96.15	0.00	98.64	0.00	99.34	0.00	92.82	0.00	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3574299349
97.45	0.02	99.27	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.34	0.00	92.97	0.15	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.395668303
97.47	0.02	99.27	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.34	0.00	93.13	0.15	/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.382061756
97.50	0.02	99.27	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.34	0.00	93.28	0.15	/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2781378255
97.52	0.02	99.27	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.64	0.00	99.34	0.00	93.44	0.15	/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1004330245
97.53	0.01	99.29	0.02	95.78	0.00	100.00	0.00	96.15	0.00	98.68	0.03	99.34	0.00	93.49	0.05	/workspace/coverage/default/10.sysrst_ctrl_stress_all.1266477950
97.55	0.01	99.29	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.34	0.00	93.59	0.10	/workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.916213158
97.56	0.01	99.29	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.34	0.00	93.69	0.10	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.382983921
97.58	0.01	99.29	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.34	0.00	93.79	0.10	/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3640806397
97.59	0.01	99.29	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.34	0.00	93.90	0.10	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4108989362
97.61	0.01	99.29	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.34	0.00	94.00	0.10	/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.21451199
97.62	0.01	99.29	0.00	95.78	0.00	100.00	0.00	96.15	0.00	98.68	0.00	99.44	0.09	94.00	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.140771965
97.63	0.01	99.32	0.03	95.80	0.02	100.00	0.00	96.15	0.00	98.71	0.03	99.44	0.00	94.00	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.1654897302
97.64	0.01	99.34	0.02	95.83	0.02	100.00	0.00	96.15	0.00	98.75	0.03	99.44	0.00	94.00	0.00	/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1611661599
97.65	0.01	99.34	0.00	95.85	0.02	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.05	0.05	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3822143349
97.67	0.01	99.34	0.00	95.88	0.02	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.10	0.05	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.887916407
97.67	0.01	99.34	0.00	95.88	0.00	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.15	0.05	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3930859924
97.68	0.01	99.34	0.00	95.88	0.00	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.21	0.05	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1840362868
97.69	0.01	99.34	0.00	95.88	0.00	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.26	0.05	/workspace/coverage/default/17.sysrst_ctrl_combo_detect.3734691068
97.69	0.01	99.34	0.00	95.88	0.00	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.31	0.05	/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1813809995
97.70	0.01	99.34	0.00	95.88	0.00	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.36	0.05	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2283541373
97.71	0.01	99.34	0.00	95.88	0.00	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.41	0.05	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1238480281
97.72	0.01	99.34	0.00	95.92	0.05	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.41	0.00	/workspace/coverage/default/14.sysrst_ctrl_alert_test.3772727245
97.72	0.01	99.34	0.00	95.97	0.05	100.00	0.00	96.15	0.00	98.75	0.00	99.44	0.00	94.41	0.00	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1498513233

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3735367024
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.957633371
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1157514874
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2204551688
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1518825108
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3578169413
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4123688618
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.103577783
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3321430505
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2968107200
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3694639494
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3538668399
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1902609683
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1693321744
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2601484260
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3375623463
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3812226778
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.588494506
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1780734575
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.527466496
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.615137238
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3125724849
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.461632161
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.431665098
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1040395548
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1358365339
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3105613395
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2626612276
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3690459900
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.765725636
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2840631654
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3392923098
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3232993420
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.52608160
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3238715383
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.436715820
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2535608364
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1877881475
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4026170170
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2693224039
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2474126042
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2942393676
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1284809885
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.329804957
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1768200851
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2642236315
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1149428513
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2127343982
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.23638889
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3852733512
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3927878785
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1345613322
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3344037258
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1574568732
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3347664252
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3182026922
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3388824243
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2739086162
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1004001831
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2697407174
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2964222569
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.610130412
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3960151124
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1959963073
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1185355519
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2404148905
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/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.4217875812
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.352836067
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2868310041
/workspace/coverage/default/4.sysrst_ctrl_smoke.60323083
/workspace/coverage/default/4.sysrst_ctrl_stress_all.1082622899
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3372141395
/workspace/coverage/default/40.sysrst_ctrl_alert_test.1811787242
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1596834524
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.1439239704
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1027809374
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.3455074834
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3502430953
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3567521630
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.676139867
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2392367356
/workspace/coverage/default/40.sysrst_ctrl_smoke.3755804195
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1186058549
/workspace/coverage/default/41.sysrst_ctrl_alert_test.1804570825
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1266961663
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.140378281
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2277461384
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.645806679
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.3420222319
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1050817256
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1152475351
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2642182584
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.498366839
/workspace/coverage/default/41.sysrst_ctrl_smoke.481153823
/workspace/coverage/default/41.sysrst_ctrl_stress_all.2521322825
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2010341869
/workspace/coverage/default/42.sysrst_ctrl_alert_test.911238133
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2130645442
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.2777890732
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3350966465
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3237858318
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.84053044
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1017403191
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.319085562
/workspace/coverage/default/42.sysrst_ctrl_smoke.2395898940
/workspace/coverage/default/42.sysrst_ctrl_stress_all.3098313316
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1597522619
/workspace/coverage/default/43.sysrst_ctrl_alert_test.3629774502
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1381347648
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.4137166658
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.1839474910
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3115160178
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2014092819
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3389944695
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3008546716
/workspace/coverage/default/43.sysrst_ctrl_smoke.2026154437
/workspace/coverage/default/43.sysrst_ctrl_stress_all.544950990
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3686974217
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1762045194
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3827845587
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.366606748
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1340694336
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1780572875
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.3174268586
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2312829811
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.45321829
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4160954861
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1727047599
/workspace/coverage/default/44.sysrst_ctrl_smoke.3032034458
/workspace/coverage/default/44.sysrst_ctrl_stress_all.743874536
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1065246147
/workspace/coverage/default/45.sysrst_ctrl_alert_test.707435307
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1908797841
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.251094946
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.917062054
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2392954009
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4265640249
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2672815291
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3007388308
/workspace/coverage/default/45.sysrst_ctrl_smoke.2351313248
/workspace/coverage/default/45.sysrst_ctrl_stress_all.1887477536
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.910120300
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2739273847
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3590437996
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.441642420
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3947271921
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.578277086
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2942275567
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.739360369
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3574277111
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.773958723
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.4184149517
/workspace/coverage/default/46.sysrst_ctrl_smoke.2325731646
/workspace/coverage/default/46.sysrst_ctrl_stress_all.2814465943
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1617113554
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3368587547
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1053143608
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2728255717
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.230803048
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2095409294
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1547304951
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.992886915
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2034470536
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2160131467
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1665766741
/workspace/coverage/default/47.sysrst_ctrl_smoke.3686856775
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1747312525
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3732757982
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3431707984
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1585472763
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2080652593
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1036672924
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1072972232
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3586453221
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.672020998
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.625021312
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.63097964
/workspace/coverage/default/48.sysrst_ctrl_smoke.2034222859
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3861095538
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3744666158
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2724324994
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2631458211
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1461087463
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.4152611304
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2639059120
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3024231318
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2977013464
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4078844865
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.651507442
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1522130336
/workspace/coverage/default/49.sysrst_ctrl_smoke.1388217281
/workspace/coverage/default/49.sysrst_ctrl_stress_all.4062185984
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2749579966
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1992335921
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2109168525
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3066723124
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.3224867048
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.297959694
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.143127902
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3477238604
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1954548639
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1865172030
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.343324221
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.4111128164
/workspace/coverage/default/5.sysrst_ctrl_smoke.1058006675
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2195146526
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1643294398
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3311001297
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2026610434
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.292072699
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3740116578
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3395706274
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3709665096
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1041850514
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3676100135
/workspace/coverage/default/6.sysrst_ctrl_alert_test.3155539759
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.4227743417
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.409418862
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.37907684
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.884340419
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3954071257
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1011784713
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1290617363
/workspace/coverage/default/6.sysrst_ctrl_smoke.2395621405
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1498081374
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3665895989
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3107177871
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.443005001
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2588445704
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.599748043
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1917288701
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2272758390
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1643220998
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3758125122
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2152060678
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.4009687651
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.554620894
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2323742008
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1537237868
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4085478707
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1139535321
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.556407
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.963388150
/workspace/coverage/default/7.sysrst_ctrl_smoke.1308694954
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3303725324
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2418646815
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2172361867
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1275894026
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2986467498
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2417978259
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2750371696
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3331870279
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.597322140
/workspace/coverage/default/8.sysrst_ctrl_alert_test.3769820101
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.218132148
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2106133321
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2112083624
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3092941211
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3420000292
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1709101924
/workspace/coverage/default/8.sysrst_ctrl_smoke.672253434
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2336590559
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1465544185
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1123951811
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1780820581
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1187457437
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.598465348
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3634504056
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1404001501
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2746065291
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.891666281
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3942207307
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2657491194
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1326972882
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.4250988280
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2079732243
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3564443503
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.722043953
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3526798972
/workspace/coverage/default/9.sysrst_ctrl_smoke.3578842771
/workspace/coverage/default/9.sysrst_ctrl_stress_all.4291754059
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3434904783
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.257189100
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1443284626
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3315520572
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.366427834
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3041542686
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3685630399
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3736405840
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3340195903
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3612808485

Total test records in report: 905

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2947917444	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:44 PM PST 24	22311368741 ps
T6	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.631345024	Jan 10 12:55:58 PM PST 24	Jan 10 12:57:14 PM PST 24	2013405811 ps
T7	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4236073518	Jan 10 12:55:53 PM PST 24	Jan 10 12:57:03 PM PST 24	2046346874 ps
T2	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1358365339	Jan 10 12:56:37 PM PST 24	Jan 10 12:57:48 PM PST 24	2080545318 ps
T23	/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3732331947	Jan 10 12:56:23 PM PST 24	Jan 10 12:57:39 PM PST 24	2016792404 ps
T24	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3125724849	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:19 PM PST 24	2018279159 ps
T3	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2964222569	Jan 10 12:56:24 PM PST 24	Jan 10 12:57:37 PM PST 24	2044068333 ps
T8	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2990851625	Jan 10 12:55:55 PM PST 24	Jan 10 12:57:10 PM PST 24	2038001519 ps
T4	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3960151124	Jan 10 12:56:29 PM PST 24	Jan 10 12:57:43 PM PST 24	5520342937 ps
T9	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3093197191	Jan 10 12:55:50 PM PST 24	Jan 10 12:58:45 PM PST 24	42482898444 ps
T39	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.765725636	Jan 10 12:56:07 PM PST 24	Jan 10 12:57:19 PM PST 24	2141532570 ps
T40	/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3162914662	Jan 10 12:56:29 PM PST 24	Jan 10 12:57:44 PM PST 24	2012263293 ps
T5	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3830492875	Jan 10 12:55:59 PM PST 24	Jan 10 12:57:11 PM PST 24	2094753926 ps
T271	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2405655289	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:17 PM PST 24	2097995405 ps
T10	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.461632161	Jan 10 12:56:26 PM PST 24	Jan 10 12:58:08 PM PST 24	8702772029 ps
T293	/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2220162669	Jan 10 12:56:23 PM PST 24	Jan 10 12:57:36 PM PST 24	2031440917 ps
T57	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.103577783	Jan 10 12:55:50 PM PST 24	Jan 10 12:58:44 PM PST 24	39629435502 ps
T11	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1284809885	Jan 10 12:56:22 PM PST 24	Jan 10 12:57:36 PM PST 24	2063259431 ps
T12	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1840362868	Jan 10 12:56:16 PM PST 24	Jan 10 12:58:31 PM PST 24	22210937122 ps
T283	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.410623334	Jan 10 12:56:15 PM PST 24	Jan 10 12:57:33 PM PST 24	2086973686 ps
T344	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.2831512486	Jan 10 12:56:24 PM PST 24	Jan 10 12:57:37 PM PST 24	2024485521 ps
T33	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3690459900	Jan 10 12:56:06 PM PST 24	Jan 10 12:57:34 PM PST 24	43891442673 ps
T34	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.140771965	Jan 10 12:55:54 PM PST 24	Jan 10 12:57:07 PM PST 24	2037220320 ps
T35	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2756972344	Jan 10 12:55:58 PM PST 24	Jan 10 12:57:12 PM PST 24	2135131706 ps
T36	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4176724786	Jan 10 12:56:23 PM PST 24	Jan 10 12:57:54 PM PST 24	7831608867 ps
T273	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1345613322	Jan 10 12:56:14 PM PST 24	Jan 10 12:57:28 PM PST 24	2206078327 ps
T37	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2293199863	Jan 10 12:55:58 PM PST 24	Jan 10 12:57:10 PM PST 24	2156450442 ps
T38	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1518825108	Jan 10 12:55:49 PM PST 24	Jan 10 12:57:08 PM PST 24	4134557799 ps
T287	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2942393676	Jan 10 12:56:42 PM PST 24	Jan 10 12:57:54 PM PST 24	2108420320 ps
T356	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.588494506	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:29 PM PST 24	5295207919 ps
T274	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1959963073	Jan 10 12:56:27 PM PST 24	Jan 10 12:57:40 PM PST 24	2399062392 ps
T282	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3344037258	Jan 10 12:56:19 PM PST 24	Jan 10 12:58:47 PM PST 24	42467921698 ps
T357	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4244390359	Jan 10 12:56:01 PM PST 24	Jan 10 12:57:17 PM PST 24	2012719779 ps
T278	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.692545483	Jan 10 12:55:58 PM PST 24	Jan 10 12:57:26 PM PST 24	22238133262 ps
T280	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1905670377	Jan 10 12:55:58 PM PST 24	Jan 10 12:58:09 PM PST 24	42407736149 ps
T294	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.468531556	Jan 10 12:56:04 PM PST 24	Jan 10 12:57:16 PM PST 24	2062738961 ps
T275	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3574299349	Jan 10 12:56:22 PM PST 24	Jan 10 12:57:37 PM PST 24	2430642981 ps
T358	/workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1932371922	Jan 10 12:56:24 PM PST 24	Jan 10 12:57:36 PM PST 24	2106357425 ps
T359	/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.828663626	Jan 10 12:56:25 PM PST 24	Jan 10 12:57:41 PM PST 24	2011333113 ps
T291	/workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.987650225	Jan 10 12:56:21 PM PST 24	Jan 10 12:57:34 PM PST 24	2049506613 ps
T288	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2840631654	Jan 10 12:56:03 PM PST 24	Jan 10 12:57:15 PM PST 24	2070896821 ps
T345	/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1765128859	Jan 10 12:56:23 PM PST 24	Jan 10 12:57:35 PM PST 24	2076009476 ps
T295	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2924734650	Jan 10 12:55:57 PM PST 24	Jan 10 12:57:12 PM PST 24	3522477154 ps
T296	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3735367024	Jan 10 12:55:53 PM PST 24	Jan 10 12:57:06 PM PST 24	2740663065 ps
T279	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3790580719	Jan 10 12:56:00 PM PST 24	Jan 10 12:57:13 PM PST 24	2114750517 ps
T277	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1693321744	Jan 10 12:55:52 PM PST 24	Jan 10 12:57:02 PM PST 24	2249681021 ps
T297	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.23638889	Jan 10 12:56:13 PM PST 24	Jan 10 12:57:30 PM PST 24	2036348838 ps
T360	/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1579195947	Jan 10 12:56:32 PM PST 24	Jan 10 12:57:46 PM PST 24	2014695279 ps
T361	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.957633371	Jan 10 12:55:48 PM PST 24	Jan 10 12:59:59 PM PST 24	39471202457 ps
T362	/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.96103909	Jan 10 12:56:22 PM PST 24	Jan 10 12:57:35 PM PST 24	2040659528 ps
T363	/workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3563649904	Jan 10 12:56:25 PM PST 24	Jan 10 12:57:38 PM PST 24	2018795820 ps
T289	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2968107200	Jan 10 12:55:59 PM PST 24	Jan 10 12:57:17 PM PST 24	2060474654 ps
T364	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.587585368	Jan 10 12:56:17 PM PST 24	Jan 10 12:57:56 PM PST 24	22270413927 ps
T320	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3930859924	Jan 10 12:55:57 PM PST 24	Jan 10 12:58:03 PM PST 24	22213022107 ps
T365	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.4184133471	Jan 10 12:56:03 PM PST 24	Jan 10 12:57:47 PM PST 24	7743122720 ps
T366	/workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.701918489	Jan 10 12:56:27 PM PST 24	Jan 10 12:57:37 PM PST 24	2058659578 ps
T355	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2204551688	Jan 10 12:55:49 PM PST 24	Jan 10 12:56:59 PM PST 24	2125303295 ps
T292	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2730172181	Jan 10 12:56:25 PM PST 24	Jan 10 12:57:39 PM PST 24	2043823443 ps
T290	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.615137238	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:21 PM PST 24	2036309122 ps
T281	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1828057477	Jan 10 12:55:58 PM PST 24	Jan 10 12:57:13 PM PST 24	2065611002 ps
T367	/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3128539942	Jan 10 12:56:22 PM PST 24	Jan 10 12:57:38 PM PST 24	2009990534 ps
T368	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1040395548	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:20 PM PST 24	2083920485 ps
T369	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3392923098	Jan 10 12:56:06 PM PST 24	Jan 10 12:57:18 PM PST 24	2041018961 ps
T370	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1877881475	Jan 10 12:56:26 PM PST 24	Jan 10 12:57:38 PM PST 24	2027054557 ps
T371	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1902609683	Jan 10 12:55:57 PM PST 24	Jan 10 12:57:43 PM PST 24	10396434397 ps
T298	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3033328983	Jan 10 12:55:58 PM PST 24	Jan 10 12:57:13 PM PST 24	6046236251 ps
T276	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1185355519	Jan 10 12:56:24 PM PST 24	Jan 10 12:59:24 PM PST 24	42380326483 ps
T372	/workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3135288789	Jan 10 12:56:24 PM PST 24	Jan 10 12:57:37 PM PST 24	2017207318 ps
T373	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1872958898	Jan 10 12:56:19 PM PST 24	Jan 10 12:57:46 PM PST 24	5995150951 ps
T374	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.436715820	Jan 10 12:56:42 PM PST 24	Jan 10 12:57:55 PM PST 24	2050321611 ps
T375	/workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3493457280	Jan 10 12:56:31 PM PST 24	Jan 10 12:57:42 PM PST 24	2039985916 ps
T376	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2511191115	Jan 10 12:55:58 PM PST 24	Jan 10 12:57:14 PM PST 24	5087541905 ps
T299	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3375623463	Jan 10 12:57:14 PM PST 24	Jan 10 12:58:29 PM PST 24	2143217211 ps
T377	/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3496776646	Jan 10 12:56:27 PM PST 24	Jan 10 12:57:39 PM PST 24	2027916587 ps
T378	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.610130412	Jan 10 12:56:21 PM PST 24	Jan 10 12:57:35 PM PST 24	2016064884 ps
T379	/workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.916213158	Jan 10 12:56:24 PM PST 24	Jan 10 12:57:35 PM PST 24	2144785056 ps
T380	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.571108500	Jan 10 12:56:02 PM PST 24	Jan 10 12:57:16 PM PST 24	2142924185 ps
T381	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1574568732	Jan 10 12:56:12 PM PST 24	Jan 10 12:57:26 PM PST 24	2111718847 ps
T382	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3232993420	Jan 10 12:56:07 PM PST 24	Jan 10 12:57:31 PM PST 24	5067427405 ps
T383	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2527870908	Jan 10 12:56:21 PM PST 24	Jan 10 12:58:02 PM PST 24	22263806148 ps
T384	/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2072815688	Jan 10 12:56:25 PM PST 24	Jan 10 12:57:41 PM PST 24	2016365576 ps
T385	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1783211833	Jan 10 12:56:25 PM PST 24	Jan 10 12:58:30 PM PST 24	42561133858 ps
T386	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3182026922	Jan 10 12:56:24 PM PST 24	Jan 10 12:57:40 PM PST 24	2014498642 ps
T387	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4123688618	Jan 10 12:55:57 PM PST 24	Jan 10 12:57:10 PM PST 24	2766438654 ps
T388	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.527466496	Jan 10 12:57:32 PM PST 24	Jan 10 12:58:53 PM PST 24	2064879615 ps
T389	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.417923	Jan 10 12:55:57 PM PST 24	Jan 10 12:57:16 PM PST 24	2511655746 ps
T390	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2574758159	Jan 10 12:56:01 PM PST 24	Jan 10 12:57:17 PM PST 24	2115199661 ps
T391	/workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2200264137	Jan 10 12:56:26 PM PST 24	Jan 10 12:57:38 PM PST 24	2044039555 ps
T392	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1488158404	Jan 10 12:55:57 PM PST 24	Jan 10 12:57:13 PM PST 24	2012038067 ps
T393	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.52608160	Jan 10 12:56:06 PM PST 24	Jan 10 12:57:20 PM PST 24	3166403279 ps
T300	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2504623134	Jan 10 12:55:59 PM PST 24	Jan 10 12:57:14 PM PST 24	2077700316 ps
T394	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1166017745	Jan 10 12:56:26 PM PST 24	Jan 10 12:57:41 PM PST 24	2032437688 ps
T395	/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2701528547	Jan 10 12:56:24 PM PST 24	Jan 10 12:57:40 PM PST 24	2014646459 ps
T396	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1780734575	Jan 10 12:56:02 PM PST 24	Jan 10 12:57:20 PM PST 24	2059659530 ps
T301	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1157514874	Jan 10 12:55:48 PM PST 24	Jan 10 12:57:04 PM PST 24	6037266804 ps
T397	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3951043040	Jan 10 12:56:08 PM PST 24	Jan 10 12:58:16 PM PST 24	39045723821 ps
T398	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.242210350	Jan 10 12:55:56 PM PST 24	Jan 10 12:57:21 PM PST 24	43565570988 ps
T399	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3578169413	Jan 10 12:55:57 PM PST 24	Jan 10 12:57:14 PM PST 24	2031344432 ps
T400	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2626612276	Jan 10 12:56:06 PM PST 24	Jan 10 12:57:31 PM PST 24	9488262761 ps
T401	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.96184052	Jan 10 12:56:16 PM PST 24	Jan 10 12:57:30 PM PST 24	2170004123 ps
T402	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3694639494	Jan 10 12:55:49 PM PST 24	Jan 10 12:56:58 PM PST 24	2098327082 ps
T403	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1149428513	Jan 10 12:56:34 PM PST 24	Jan 10 12:57:59 PM PST 24	22444850979 ps
T404	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2676540268	Jan 10 12:56:09 PM PST 24	Jan 10 12:57:26 PM PST 24	5151823905 ps
T405	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2601484260	Jan 10 12:56:05 PM PST 24	Jan 10 12:57:16 PM PST 24	2114009970 ps
T406	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3812226778	Jan 10 12:56:06 PM PST 24	Jan 10 12:57:23 PM PST 24	2009482584 ps
T41	/workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2222357548	Jan 10 12:31:21 PM PST 24	Jan 10 12:32:10 PM PST 24	3450323882 ps
T42	/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2323742008	Jan 10 12:32:08 PM PST 24	Jan 10 12:42:01 PM PST 24	740710510524 ps
T43	/workspace/coverage/default/4.sysrst_ctrl_sec_cm.3143146725	Jan 10 12:30:53 PM PST 24	Jan 10 12:32:04 PM PST 24	42160766147 ps
T85	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3092941211	Jan 10 12:30:53 PM PST 24	Jan 10 12:31:52 PM PST 24	2609696443 ps
T75	/workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2086586493	Jan 10 12:33:37 PM PST 24	Jan 10 12:33:59 PM PST 24	2483985138 ps
T86	/workspace/coverage/default/13.sysrst_ctrl_pin_override_test.717258116	Jan 10 12:31:37 PM PST 24	Jan 10 12:32:28 PM PST 24	2593578163 ps
T53	/workspace/coverage/default/28.sysrst_ctrl_stress_all.137907720	Jan 10 12:31:48 PM PST 24	Jan 10 12:37:52 PM PST 24	128297178176 ps
T13	/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2963550613	Jan 10 12:30:48 PM PST 24	Jan 10 12:38:25 PM PST 24	156125847375 ps
T14	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3171913373	Jan 10 12:43:58 PM PST 24	Jan 10 12:45:21 PM PST 24	7749078596 ps
T25	/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2014092819	Jan 10 12:47:09 PM PST 24	Jan 10 12:48:46 PM PST 24	2452169264 ps
T26	/workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3926775493	Jan 10 12:30:38 PM PST 24	Jan 10 12:31:25 PM PST 24	2240572602 ps
T27	/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.955793292	Jan 10 12:40:59 PM PST 24	Jan 10 12:43:03 PM PST 24	26079590675 ps
T28	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3311001297	Jan 10 12:44:00 PM PST 24	Jan 10 12:46:48 PM PST 24	36508306457 ps
T29	/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2533296213	Jan 10 12:31:54 PM PST 24	Jan 10 12:32:43 PM PST 24	2532196138 ps
T30	/workspace/coverage/default/27.sysrst_ctrl_smoke.1915947718	Jan 10 12:31:37 PM PST 24	Jan 10 12:32:31 PM PST 24	2118565125 ps
T31	/workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.274416216	Jan 10 12:31:21 PM PST 24	Jan 10 12:32:14 PM PST 24	2613973753 ps
T32	/workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.4115500742	Jan 10 12:31:23 PM PST 24	Jan 10 12:32:13 PM PST 24	7479616943 ps
T15	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2530517141	Jan 10 12:55:42 PM PST 24	Jan 10 12:57:18 PM PST 24	101341258188 ps
T16	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2447954723	Jan 10 12:30:42 PM PST 24	Jan 10 12:33:13 PM PST 24	40201517006 ps
T64	/workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.489640512	Jan 10 12:30:54 PM PST 24	Jan 10 12:31:42 PM PST 24	2482621660 ps
T407	/workspace/coverage/default/1.sysrst_ctrl_smoke.892983673	Jan 10 12:30:35 PM PST 24	Jan 10 12:31:23 PM PST 24	2108299970 ps
T408	/workspace/coverage/default/13.sysrst_ctrl_smoke.962101508	Jan 10 12:31:20 PM PST 24	Jan 10 12:32:09 PM PST 24	2113889354 ps
T17	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1762045194	Jan 10 12:40:55 PM PST 24	Jan 10 12:41:57 PM PST 24	5111619952 ps
T409	/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1551608465	Jan 10 12:31:43 PM PST 24	Jan 10 12:32:33 PM PST 24	2184680844 ps
T18	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.95038426	Jan 10 12:31:28 PM PST 24	Jan 10 12:32:24 PM PST 24	2959176543 ps
T65	/workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3470909010	Jan 10 12:31:12 PM PST 24	Jan 10 12:32:00 PM PST 24	2463914488 ps
T19	/workspace/coverage/default/19.sysrst_ctrl_edge_detect.4013653796	Jan 10 12:31:19 PM PST 24	Jan 10 12:33:44 PM PST 24	492266519436 ps
T20	/workspace/coverage/default/25.sysrst_ctrl_stress_all.2550921895	Jan 10 12:33:13 PM PST 24	Jan 10 12:33:54 PM PST 24	15414660470 ps
T66	/workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2074457968	Jan 10 12:31:54 PM PST 24	Jan 10 12:32:43 PM PST 24	2492905717 ps
T67	/workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3478912754	Jan 10 12:30:47 PM PST 24	Jan 10 12:31:36 PM PST 24	2621655059 ps
T68	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3465931168	Jan 10 12:40:13 PM PST 24	Jan 10 12:41:05 PM PST 24	2619017758 ps
T21	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.3407016797	Jan 10 12:31:07 PM PST 24	Jan 10 12:33:41 PM PST 24	184877499760 ps
T22	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3571308367	Jan 10 12:44:33 PM PST 24	Jan 10 12:46:34 PM PST 24	272645979882 ps
T96	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.891666281	Jan 10 12:31:13 PM PST 24	Jan 10 12:32:04 PM PST 24	3465656923 ps
T52	/workspace/coverage/default/11.sysrst_ctrl_edge_detect.1176903789	Jan 10 12:31:02 PM PST 24	Jan 10 12:36:30 PM PST 24	273998995083 ps
T94	/workspace/coverage/default/7.sysrst_ctrl_stress_all.3303725324	Jan 10 12:31:10 PM PST 24	Jan 10 12:32:16 PM PST 24	7780876767 ps
T171	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3734176803	Jan 10 12:52:55 PM PST 24	Jan 10 12:54:10 PM PST 24	2259690547 ps
T44	/workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.754100167	Jan 10 12:30:17 PM PST 24	Jan 10 12:33:56 PM PST 24	521108923805 ps
T115	/workspace/coverage/default/28.sysrst_ctrl_alert_test.250075244	Jan 10 12:32:01 PM PST 24	Jan 10 12:32:48 PM PST 24	2118680724 ps
T116	/workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1987691389	Jan 10 12:31:33 PM PST 24	Jan 10 12:32:29 PM PST 24	2048144396 ps
T410	/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3917492922	Jan 10 12:31:23 PM PST 24	Jan 10 12:32:16 PM PST 24	2610051859 ps
T354	/workspace/coverage/default/18.sysrst_ctrl_pin_override_test.383960382	Jan 10 12:31:33 PM PST 24	Jan 10 12:32:25 PM PST 24	2519665303 ps
T411	/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2034470536	Jan 10 01:08:19 PM PST 24	Jan 10 01:09:44 PM PST 24	2466713934 ps
T284	/workspace/coverage/default/45.sysrst_ctrl_alert_test.707435307	Jan 10 12:38:12 PM PST 24	Jan 10 12:38:55 PM PST 24	2011113204 ps
T58	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1837346912	Jan 10 12:42:23 PM PST 24	Jan 10 12:44:18 PM PST 24	60569911495 ps
T59	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.4250988280	Jan 10 12:31:22 PM PST 24	Jan 10 12:32:13 PM PST 24	3480078478 ps
T181	/workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2365586336	Jan 10 12:31:46 PM PST 24	Jan 10 12:32:38 PM PST 24	2472477042 ps
T46	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2147268531	Jan 10 01:03:03 PM PST 24	Jan 10 01:11:26 PM PST 24	168556834175 ps
T130	/workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1032228202	Jan 10 12:39:06 PM PST 24	Jan 10 12:39:47 PM PST 24	3217698595 ps
T54	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1389058892	Jan 10 12:31:29 PM PST 24	Jan 10 12:32:53 PM PST 24	137285645403 ps
T182	/workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1619962524	Jan 10 12:57:14 PM PST 24	Jan 10 12:58:35 PM PST 24	2611675629 ps
T45	/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.21451199	Jan 10 12:41:38 PM PST 24	Jan 10 12:43:14 PM PST 24	44085293019 ps
T183	/workspace/coverage/default/14.sysrst_ctrl_alert_test.3772727245	Jan 10 12:31:15 PM PST 24	Jan 10 12:32:05 PM PST 24	2011627660 ps
T49	/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2437647034	Jan 10 12:30:50 PM PST 24	Jan 10 12:31:42 PM PST 24	5699294039 ps
T191	/workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1512553948	Jan 10 12:31:05 PM PST 24	Jan 10 12:31:54 PM PST 24	5533468080 ps
T192	/workspace/coverage/default/23.sysrst_ctrl_pin_override_test.464640185	Jan 10 12:31:49 PM PST 24	Jan 10 12:32:43 PM PST 24	2511222977 ps
T193	/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.773958723	Jan 10 12:45:00 PM PST 24	Jan 10 12:46:31 PM PST 24	2017315532 ps
T194	/workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3135458708	Jan 10 12:31:28 PM PST 24	Jan 10 12:32:20 PM PST 24	4372864345 ps
T195	/workspace/coverage/default/44.sysrst_ctrl_alert_test.3827845587	Jan 10 12:40:34 PM PST 24	Jan 10 12:41:24 PM PST 24	2012239982 ps
T97	/workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3822143349	Jan 10 12:31:59 PM PST 24	Jan 10 12:32:56 PM PST 24	3605931673 ps
T412	/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4265640249	Jan 10 12:46:20 PM PST 24	Jan 10 12:47:43 PM PST 24	2465734061 ps
T102	/workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3825746798	Jan 10 12:31:54 PM PST 24	Jan 10 12:34:07 PM PST 24	32104220140 ps
T413	/workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.4132930884	Jan 10 12:56:33 PM PST 24	Jan 10 12:57:47 PM PST 24	2616058536 ps
T414	/workspace/coverage/default/35.sysrst_ctrl_smoke.3906692277	Jan 10 12:34:35 PM PST 24	Jan 10 12:35:16 PM PST 24	2164759196 ps
T415	/workspace/coverage/default/44.sysrst_ctrl_smoke.3032034458	Jan 10 12:49:42 PM PST 24	Jan 10 12:51:13 PM PST 24	2120137021 ps
T60	/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2172361867	Jan 10 12:37:29 PM PST 24	Jan 10 12:38:32 PM PST 24	39113177261 ps
T353	/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1727047599	Jan 10 12:49:13 PM PST 24	Jan 10 12:50:47 PM PST 24	2518825105 ps
T416	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3586453221	Jan 10 12:38:25 PM PST 24	Jan 10 12:39:01 PM PST 24	2625790357 ps
T417	/workspace/coverage/default/49.sysrst_ctrl_stress_all.4062185984	Jan 10 12:44:10 PM PST 24	Jan 10 12:45:34 PM PST 24	10082105667 ps
T418	/workspace/coverage/default/26.sysrst_ctrl_alert_test.369455573	Jan 10 12:31:42 PM PST 24	Jan 10 12:32:37 PM PST 24	2013322213 ps
T50	/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3477238604	Jan 10 12:30:47 PM PST 24	Jan 10 12:31:33 PM PST 24	2392442260 ps
T243	/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3350966465	Jan 10 01:00:25 PM PST 24	Jan 10 01:02:25 PM PST 24	4338716205 ps
T61	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3851931398	Jan 10 12:30:44 PM PST 24	Jan 10 12:31:35 PM PST 24	2510123294 ps
T419	/workspace/coverage/default/21.sysrst_ctrl_smoke.3387975877	Jan 10 12:31:34 PM PST 24	Jan 10 12:32:26 PM PST 24	2127969682 ps
T51	/workspace/coverage/default/40.sysrst_ctrl_edge_detect.3455074834	Jan 10 12:49:45 PM PST 24	Jan 10 12:51:17 PM PST 24	3322469000 ps
T98	/workspace/coverage/default/48.sysrst_ctrl_stress_all.3861095538	Jan 10 01:10:24 PM PST 24	Jan 10 01:11:52 PM PST 24	7767171694 ps
T420	/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.556407	Jan 10 12:30:38 PM PST 24	Jan 10 12:31:27 PM PST 24	2255537177 ps
T62	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.857904566	Jan 10 12:30:04 PM PST 24	Jan 10 12:30:48 PM PST 24	2531553999 ps
T421	/workspace/coverage/default/2.sysrst_ctrl_pin_access_test.4189083382	Jan 10 12:30:19 PM PST 24	Jan 10 12:31:05 PM PST 24	2125294935 ps
T167	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.1135940098	Jan 10 12:33:32 PM PST 24	Jan 10 12:33:40 PM PST 24	3470742209 ps
T253	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.4152611304	Jan 10 01:05:55 PM PST 24	Jan 10 01:09:57 PM PST 24	60946147763 ps
T264	/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.498366839	Jan 10 12:37:43 PM PST 24	Jan 10 12:38:22 PM PST 24	2516048528 ps
T422	/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1748415829	Jan 10 12:31:41 PM PST 24	Jan 10 12:32:33 PM PST 24	2634630543 ps
T82	/workspace/coverage/default/49.sysrst_ctrl_edge_detect.2977013464	Jan 10 12:44:05 PM PST 24	Jan 10 12:45:22 PM PST 24	3509801684 ps
T196	/workspace/coverage/default/24.sysrst_ctrl_stress_all.475967319	Jan 10 12:33:13 PM PST 24	Jan 10 12:33:28 PM PST 24	9916647353 ps
T197	/workspace/coverage/default/48.sysrst_ctrl_smoke.2034222859	Jan 10 12:46:54 PM PST 24	Jan 10 12:48:13 PM PST 24	2137527353 ps
T55	/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3340195903	Jan 10 12:45:13 PM PST 24	Jan 10 12:48:59 PM PST 24	52982115942 ps
T56	/workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4276081083	Jan 10 12:32:10 PM PST 24	Jan 10 12:37:32 PM PST 24	118465426947 ps
T423	/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1723800396	Jan 10 12:31:41 PM PST 24	Jan 10 12:32:37 PM PST 24	2191630657 ps
T202	/workspace/coverage/default/32.sysrst_ctrl_edge_detect.4149521747	Jan 10 01:04:28 PM PST 24	Jan 10 01:05:48 PM PST 24	2974082865 ps
T95	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3186285082	Jan 10 12:31:16 PM PST 24	Jan 10 12:32:16 PM PST 24	21851382155 ps
T424	/workspace/coverage/default/30.sysrst_ctrl_alert_test.290889371	Jan 10 12:41:38 PM PST 24	Jan 10 12:42:46 PM PST 24	2028380236 ps
T63	/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1336669433	Jan 10 12:31:15 PM PST 24	Jan 10 12:32:06 PM PST 24	6272058143 ps
T135	/workspace/coverage/default/16.sysrst_ctrl_edge_detect.299313133	Jan 10 12:30:52 PM PST 24	Jan 10 12:31:38 PM PST 24	3036046896 ps
T136	/workspace/coverage/default/6.sysrst_ctrl_alert_test.3155539759	Jan 10 12:30:35 PM PST 24	Jan 10 12:31:20 PM PST 24	2028153720 ps
T137	/workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1181669812	Jan 10 12:30:19 PM PST 24	Jan 10 12:31:05 PM PST 24	2476108806 ps
T138	/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3389944695	Jan 10 12:45:40 PM PST 24	Jan 10 12:47:05 PM PST 24	2243228651 ps
T99	/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.218132148	Jan 10 12:30:45 PM PST 24	Jan 10 12:31:32 PM PST 24	3403966834 ps
T117	/workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1609556228	Jan 10 12:40:20 PM PST 24	Jan 10 12:41:13 PM PST 24	2141157013 ps
T118	/workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1678499743	Jan 10 12:45:42 PM PST 24	Jan 10 12:47:06 PM PST 24	2458532796 ps
T352	/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.319085562	Jan 10 12:38:03 PM PST 24	Jan 10 12:38:40 PM PST 24	2516425657 ps
T425	/workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2822198498	Jan 10 12:31:12 PM PST 24	Jan 10 12:32:05 PM PST 24	2459625524 ps
T426	/workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2544516829	Jan 10 12:31:11 PM PST 24	Jan 10 12:31:59 PM PST 24	2631154534 ps
T427	/workspace/coverage/default/38.sysrst_ctrl_alert_test.3275859742	Jan 10 12:35:40 PM PST 24	Jan 10 12:36:11 PM PST 24	2015198069 ps
T100	/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.366606748	Jan 10 01:03:48 PM PST 24	Jan 10 01:05:07 PM PST 24	3326421719 ps
T428	/workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.644217506	Jan 10 12:31:20 PM PST 24	Jan 10 12:32:14 PM PST 24	2926329310 ps
T429	/workspace/coverage/default/42.sysrst_ctrl_alert_test.911238133	Jan 10 12:48:54 PM PST 24	Jan 10 12:50:26 PM PST 24	2027990119 ps
T306	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.3752441444	Jan 10 12:31:25 PM PST 24	Jan 10 12:32:36 PM PST 24	44165267164 ps
T430	/workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3036839567	Jan 10 12:31:03 PM PST 24	Jan 10 12:31:56 PM PST 24	4033308083 ps
T90	/workspace/coverage/default/33.sysrst_ctrl_edge_detect.1582318362	Jan 10 12:36:19 PM PST 24	Jan 10 12:36:58 PM PST 24	3166267560 ps
T176	/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1699927269	Jan 10 12:31:15 PM PST 24	Jan 10 12:32:02 PM PST 24	2685331660 ps
T177	/workspace/coverage/default/43.sysrst_ctrl_smoke.2026154437	Jan 10 12:39:56 PM PST 24	Jan 10 12:40:37 PM PST 24	2122064320 ps
T210	/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.651507442	Jan 10 12:40:26 PM PST 24	Jan 10 12:41:18 PM PST 24	2047085418 ps
T211	/workspace/coverage/default/35.sysrst_ctrl_alert_test.3294908059	Jan 10 12:52:05 PM PST 24	Jan 10 12:53:22 PM PST 24	2043418994 ps
T212	/workspace/coverage/default/1.sysrst_ctrl_sec_cm.1269880394	Jan 10 12:30:22 PM PST 24	Jan 10 12:31:17 PM PST 24	22097320364 ps
T213	/workspace/coverage/default/42.sysrst_ctrl_edge_detect.3237858318	Jan 10 12:38:42 PM PST 24	Jan 10 12:39:17 PM PST 24	3102090225 ps
T214	/workspace/coverage/default/1.sysrst_ctrl_alert_test.2781342118	Jan 10 12:30:26 PM PST 24	Jan 10 12:31:09 PM PST 24	2024879141 ps
T215	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.2790791261	Jan 10 12:31:38 PM PST 24	Jan 10 12:33:52 PM PST 24	67500553197 ps
T101	/workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.861707399	Jan 10 12:32:05 PM PST 24	Jan 10 12:41:11 PM PST 24	200832632697 ps
T431	/workspace/coverage/default/8.sysrst_ctrl_alert_test.3769820101	Jan 10 12:31:05 PM PST 24	Jan 10 12:31:57 PM PST 24	2010110294 ps
T129	/workspace/coverage/default/36.sysrst_ctrl_stress_all.1122218481	Jan 10 12:41:23 PM PST 24	Jan 10 12:43:40 PM PST 24	25577960919 ps
T432	/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.722043953	Jan 10 12:31:07 PM PST 24	Jan 10 12:31:54 PM PST 24	2302050280 ps
T433	/workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1885221483	Jan 10 12:30:44 PM PST 24	Jan 10 12:31:43 PM PST 24	5498842624 ps
T434	/workspace/coverage/default/34.sysrst_ctrl_pin_access_test.528862531	Jan 10 12:40:39 PM PST 24	Jan 10 12:41:28 PM PST 24	2107354435 ps
T435	/workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2973116618	Jan 10 12:31:31 PM PST 24	Jan 10 12:32:22 PM PST 24	2651462979 ps
T436	/workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3630879789	Jan 10 12:44:28 PM PST 24	Jan 10 12:45:48 PM PST 24	3584125334 ps
T69	/workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3758610346	Jan 10 12:31:35 PM PST 24	Jan 10 12:32:28 PM PST 24	4968956426 ps
T149	/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.884340419	Jan 10 12:30:41 PM PST 24	Jan 10 12:31:27 PM PST 24	2622786751 ps
T150	/workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3635807408	Jan 10 12:31:46 PM PST 24	Jan 10 12:32:37 PM PST 24	4493302587 ps
T103	/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3612808485	Jan 10 12:52:07 PM PST 24	Jan 10 12:54:28 PM PST 24	26078033929 ps
T151	/workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.4038006565	Jan 10 12:31:24 PM PST 24	Jan 10 12:32:14 PM PST 24	2674076360 ps
T152	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3502430953	Jan 10 12:39:56 PM PST 24	Jan 10 12:40:35 PM PST 24	2668037603 ps
T153	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1865172030	Jan 10 12:30:42 PM PST 24	Jan 10 12:31:31 PM PST 24	2456374160 ps
T154	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.448400098	Jan 10 12:30:38 PM PST 24	Jan 10 12:31:25 PM PST 24	2306170589 ps
T70	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1957687438	Jan 10 12:30:58 PM PST 24	Jan 10 12:31:47 PM PST 24	4499587240 ps
T155	/workspace/coverage/default/0.sysrst_ctrl_smoke.1935680550	Jan 10 12:30:02 PM PST 24	Jan 10 12:30:47 PM PST 24	2119752360 ps
T437	/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3827841352	Jan 10 12:33:08 PM PST 24	Jan 10 12:33:22 PM PST 24	2612389926 ps
T198	/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1547304951	Jan 10 12:49:15 PM PST 24	Jan 10 12:50:52 PM PST 24	3509353067 ps
T216	/workspace/coverage/default/12.sysrst_ctrl_edge_detect.822307099	Jan 10 12:31:09 PM PST 24	Jan 10 12:32:00 PM PST 24	2971092265 ps
T180	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2612515164	Jan 10 12:48:49 PM PST 24	Jan 10 12:51:27 PM PST 24	31386103856 ps
T438	/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1326972882	Jan 10 12:30:58 PM PST 24	Jan 10 12:31:51 PM PST 24	3682399378 ps
T71	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4236741831	Jan 10 12:31:13 PM PST 24	Jan 10 12:38:02 PM PST 24	1336192717401 ps
T143	/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2277461384	Jan 10 01:00:08 PM PST 24	Jan 10 01:02:05 PM PST 24	61972133325 ps
T47	/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3634504056	Jan 10 12:43:53 PM PST 24	Jan 10 12:45:41 PM PST 24	71651542495 ps
T91	/workspace/coverage/default/3.sysrst_ctrl_edge_detect.3025095014	Jan 10 12:30:43 PM PST 24	Jan 10 12:31:29 PM PST 24	5423731957 ps