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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.34 96.00 100.00 96.15 98.75 99.44 94.41


Total test records in report: 905
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T776 /workspace/coverage/default/28.sysrst_ctrl_smoke.1739072917 Jan 10 12:31:54 PM PST 24 Jan 10 12:32:42 PM PST 24 2150651728 ps
T238 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1286543706 Jan 10 12:31:09 PM PST 24 Jan 10 12:31:58 PM PST 24 3200054587 ps
T190 /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2942275567 Jan 10 12:34:53 PM PST 24 Jan 10 12:35:40 PM PST 24 2877261875 ps
T777 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3411686323 Jan 10 12:31:23 PM PST 24 Jan 10 12:32:31 PM PST 24 27304702739 ps
T778 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3486048874 Jan 10 12:31:20 PM PST 24 Jan 10 12:32:08 PM PST 24 2272284762 ps
T779 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3768908520 Jan 10 12:31:40 PM PST 24 Jan 10 12:32:32 PM PST 24 2167047440 ps
T780 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.723186862 Jan 10 12:31:25 PM PST 24 Jan 10 12:32:18 PM PST 24 2491703648 ps
T781 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1630733126 Jan 10 12:31:14 PM PST 24 Jan 10 12:32:01 PM PST 24 2473739918 ps
T782 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3372141395 Jan 10 12:30:50 PM PST 24 Jan 10 12:31:37 PM PST 24 2636526671 ps
T783 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.132490331 Jan 10 12:45:12 PM PST 24 Jan 10 12:46:36 PM PST 24 2152273884 ps
T784 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3326899160 Jan 10 12:31:33 PM PST 24 Jan 10 12:32:25 PM PST 24 2481180634 ps
T286 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3803961540 Jan 10 12:30:28 PM PST 24 Jan 10 12:32:10 PM PST 24 22014390025 ps
T785 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2072781258 Jan 10 12:31:22 PM PST 24 Jan 10 12:33:34 PM PST 24 158787480129 ps
T786 /workspace/coverage/default/2.sysrst_ctrl_stress_all.997617966 Jan 10 12:30:27 PM PST 24 Jan 10 12:31:21 PM PST 24 10993695272 ps
T787 /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.616974301 Jan 10 12:36:01 PM PST 24 Jan 10 12:36:29 PM PST 24 2516233610 ps
T788 /workspace/coverage/default/37.sysrst_ctrl_alert_test.1874797042 Jan 10 12:43:06 PM PST 24 Jan 10 12:44:25 PM PST 24 2015476019 ps
T789 /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.595791693 Jan 10 12:30:13 PM PST 24 Jan 10 12:30:54 PM PST 24 2754264345 ps
T175 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3604291601 Jan 10 12:31:24 PM PST 24 Jan 10 12:32:21 PM PST 24 4660671465 ps
T142 /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3277455875 Jan 10 12:31:26 PM PST 24 Jan 10 12:32:16 PM PST 24 9086405144 ps
T790 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1927850234 Jan 10 12:30:44 PM PST 24 Jan 10 12:31:29 PM PST 24 2532428064 ps
T791 /workspace/coverage/default/20.sysrst_ctrl_stress_all.1910555244 Jan 10 12:31:44 PM PST 24 Jan 10 12:34:12 PM PST 24 350272602188 ps
T792 /workspace/coverage/default/46.sysrst_ctrl_alert_test.3590437996 Jan 10 12:40:46 PM PST 24 Jan 10 12:41:34 PM PST 24 2081315679 ps
T793 /workspace/coverage/default/45.sysrst_ctrl_smoke.2351313248 Jan 10 12:48:26 PM PST 24 Jan 10 12:49:52 PM PST 24 2124910527 ps
T794 /workspace/coverage/default/16.sysrst_ctrl_stress_all.2827268577 Jan 10 12:31:11 PM PST 24 Jan 10 12:32:02 PM PST 24 10896163750 ps
T795 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2248196529 Jan 10 12:31:30 PM PST 24 Jan 10 12:32:21 PM PST 24 2474630468 ps
T796 /workspace/coverage/default/9.sysrst_ctrl_alert_test.2746065291 Jan 10 12:31:23 PM PST 24 Jan 10 12:32:17 PM PST 24 2009982848 ps
T797 /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1709101924 Jan 10 12:30:49 PM PST 24 Jan 10 12:31:40 PM PST 24 2066922340 ps
T798 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1747312525 Jan 10 12:40:23 PM PST 24 Jan 10 12:46:25 PM PST 24 1993628228212 ps
T799 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1504165386 Jan 10 12:31:30 PM PST 24 Jan 10 12:32:23 PM PST 24 5221271570 ps
T800 /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1992335921 Jan 10 12:40:18 PM PST 24 Jan 10 12:41:09 PM PST 24 6513728256 ps
T239 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.4269105886 Jan 10 12:32:03 PM PST 24 Jan 10 12:32:59 PM PST 24 4172192137 ps
T801 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1198837938 Jan 10 12:31:18 PM PST 24 Jan 10 12:32:07 PM PST 24 2499477704 ps
T802 /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1665766741 Jan 10 12:46:17 PM PST 24 Jan 10 12:47:42 PM PST 24 2509409242 ps
T803 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.917062054 Jan 10 12:55:41 PM PST 24 Jan 10 12:56:59 PM PST 24 3479360497 ps
T804 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3066723124 Jan 10 12:30:31 PM PST 24 Jan 10 12:31:16 PM PST 24 3607503396 ps
T349 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3686974217 Jan 10 12:40:18 PM PST 24 Jan 10 12:43:29 PM PST 24 224582316888 ps
T805 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2010341869 Jan 10 12:40:07 PM PST 24 Jan 10 12:40:58 PM PST 24 11389051986 ps
T806 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3806236479 Jan 10 12:30:28 PM PST 24 Jan 10 12:31:15 PM PST 24 2214354253 ps
T807 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3007152806 Jan 10 12:51:12 PM PST 24 Jan 10 12:52:36 PM PST 24 2246537820 ps
T338 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2283541373 Jan 10 01:12:36 PM PST 24 Jan 10 01:18:40 PM PST 24 207098667079 ps
T808 /workspace/coverage/default/39.sysrst_ctrl_alert_test.1728310717 Jan 10 12:34:03 PM PST 24 Jan 10 12:34:37 PM PST 24 2013405998 ps
T809 /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2777890732 Jan 10 12:52:13 PM PST 24 Jan 10 12:55:59 PM PST 24 224043794585 ps
T810 /workspace/coverage/default/15.sysrst_ctrl_smoke.3547862271 Jan 10 12:31:05 PM PST 24 Jan 10 12:31:58 PM PST 24 2135298370 ps
T811 /workspace/coverage/default/19.sysrst_ctrl_stress_all.1085942715 Jan 10 12:31:26 PM PST 24 Jan 10 12:32:18 PM PST 24 12305567415 ps
T206 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.932327594 Jan 10 12:32:11 PM PST 24 Jan 10 12:33:30 PM PST 24 76136319143 ps
T812 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1531082456 Jan 10 12:31:14 PM PST 24 Jan 10 12:32:01 PM PST 24 3630213307 ps
T813 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2049534811 Jan 10 12:40:19 PM PST 24 Jan 10 12:41:08 PM PST 24 2973368531 ps
T814 /workspace/coverage/default/18.sysrst_ctrl_smoke.1067712457 Jan 10 12:31:18 PM PST 24 Jan 10 12:32:07 PM PST 24 2117114559 ps
T815 /workspace/coverage/default/31.sysrst_ctrl_alert_test.321599410 Jan 10 12:34:50 PM PST 24 Jan 10 12:35:37 PM PST 24 2014620438 ps
T816 /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1522130336 Jan 10 12:49:02 PM PST 24 Jan 10 12:50:51 PM PST 24 2514233087 ps
T817 /workspace/coverage/default/13.sysrst_ctrl_stress_all.920695258 Jan 10 12:31:02 PM PST 24 Jan 10 12:37:08 PM PST 24 378317186365 ps
T818 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3007388308 Jan 10 01:01:43 PM PST 24 Jan 10 01:03:26 PM PST 24 2514296134 ps
T819 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.4065380074 Jan 10 12:36:14 PM PST 24 Jan 10 12:36:49 PM PST 24 2538690126 ps
T227 /workspace/coverage/default/8.sysrst_ctrl_stress_all.2336590559 Jan 10 12:31:16 PM PST 24 Jan 10 12:32:38 PM PST 24 15455728299 ps
T229 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3145228488 Jan 10 12:41:12 PM PST 24 Jan 10 12:42:19 PM PST 24 2636526248 ps
T820 /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2897146745 Jan 10 12:31:37 PM PST 24 Jan 10 12:32:30 PM PST 24 3568524468 ps
T821 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.645806679 Jan 10 12:38:04 PM PST 24 Jan 10 12:52:46 PM PST 24 1291643031497 ps
T822 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.179182134 Jan 10 12:38:52 PM PST 24 Jan 10 12:39:30 PM PST 24 2750415431 ps
T823 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3490512071 Jan 10 12:37:18 PM PST 24 Jan 10 12:37:52 PM PST 24 2476812475 ps
T824 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1952451973 Jan 10 12:45:11 PM PST 24 Jan 10 12:46:40 PM PST 24 2487072306 ps
T825 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.4130958227 Jan 10 12:31:22 PM PST 24 Jan 10 12:32:10 PM PST 24 2495966449 ps
T826 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3526798972 Jan 10 12:30:53 PM PST 24 Jan 10 12:31:45 PM PST 24 2514179588 ps
T827 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.974428761 Jan 10 12:41:01 PM PST 24 Jan 10 12:42:07 PM PST 24 3313435843 ps
T828 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2103558385 Jan 10 12:40:38 PM PST 24 Jan 10 12:41:31 PM PST 24 3428507923 ps
T829 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.2103000220 Jan 10 12:31:25 PM PST 24 Jan 10 12:32:14 PM PST 24 2532634555 ps
T228 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3319625776 Jan 10 12:37:30 PM PST 24 Jan 10 12:38:08 PM PST 24 3401307523 ps
T230 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.744534265 Jan 10 01:14:23 PM PST 24 Jan 10 01:15:13 PM PST 24 4668914689 ps
T231 /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2472148992 Jan 10 12:31:28 PM PST 24 Jan 10 12:32:18 PM PST 24 2105101638 ps
T232 /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.333117325 Jan 10 12:43:32 PM PST 24 Jan 10 12:48:49 PM PST 24 8194089090379 ps
T233 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2868310041 Jan 10 12:31:25 PM PST 24 Jan 10 12:32:18 PM PST 24 2518118002 ps
T234 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1053143608 Jan 10 12:46:19 PM PST 24 Jan 10 12:47:44 PM PST 24 3237339592 ps
T235 /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2453558780 Jan 10 12:30:49 PM PST 24 Jan 10 12:34:35 PM PST 24 133176166509 ps
T236 /workspace/coverage/default/49.sysrst_ctrl_alert_test.2631458211 Jan 10 12:43:26 PM PST 24 Jan 10 12:44:50 PM PST 24 2011009498 ps
T830 /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1574100222 Jan 10 12:30:55 PM PST 24 Jan 10 12:31:42 PM PST 24 2605293620 ps
T831 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2657491194 Jan 10 12:30:54 PM PST 24 Jan 10 12:33:35 PM PST 24 45733190221 ps
T832 /workspace/coverage/default/20.sysrst_ctrl_smoke.319839823 Jan 10 12:31:19 PM PST 24 Jan 10 12:32:07 PM PST 24 2122805563 ps
T833 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2986467498 Jan 10 12:51:52 PM PST 24 Jan 10 12:54:22 PM PST 24 24335039778 ps
T834 /workspace/coverage/default/0.sysrst_ctrl_stress_all.1430236660 Jan 10 12:30:20 PM PST 24 Jan 10 12:31:28 PM PST 24 13661708803 ps
T835 /workspace/coverage/default/5.sysrst_ctrl_alert_test.2109168525 Jan 10 12:30:33 PM PST 24 Jan 10 12:31:18 PM PST 24 2036335820 ps
T836 /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1615262126 Jan 10 12:30:29 PM PST 24 Jan 10 12:31:19 PM PST 24 3264286584 ps
T837 /workspace/coverage/default/6.sysrst_ctrl_smoke.2395621405 Jan 10 12:30:53 PM PST 24 Jan 10 12:31:42 PM PST 24 2113192981 ps
T838 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2750371696 Jan 10 12:40:08 PM PST 24 Jan 10 12:41:15 PM PST 24 27099537889 ps
T839 /workspace/coverage/default/41.sysrst_ctrl_stress_all.2521322825 Jan 10 12:35:02 PM PST 24 Jan 10 12:41:45 PM PST 24 141507707173 ps
T840 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2080652593 Jan 10 12:55:19 PM PST 24 Jan 10 12:58:04 PM PST 24 161978187781 ps
T841 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2141677358 Jan 10 12:44:08 PM PST 24 Jan 10 12:45:29 PM PST 24 2465878096 ps
T842 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3682317044 Jan 10 01:08:09 PM PST 24 Jan 10 01:11:44 PM PST 24 900730239375 ps
T843 /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2706971277 Jan 10 12:30:52 PM PST 24 Jan 10 12:31:43 PM PST 24 2230271307 ps
T337 /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3709665096 Jan 10 01:01:12 PM PST 24 Jan 10 01:03:08 PM PST 24 87587894119 ps
T844 /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3545848473 Jan 10 12:30:29 PM PST 24 Jan 10 12:31:17 PM PST 24 2467256139 ps
T845 /workspace/coverage/default/34.sysrst_ctrl_smoke.2627505287 Jan 10 12:56:08 PM PST 24 Jan 10 12:57:23 PM PST 24 2113029552 ps
T846 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3966472364 Jan 10 12:31:15 PM PST 24 Jan 10 12:32:08 PM PST 24 6351637908 ps
T847 /workspace/coverage/default/46.sysrst_ctrl_stress_all.2814465943 Jan 10 12:37:55 PM PST 24 Jan 10 12:38:56 PM PST 24 21669311082 ps
T241 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1597522619 Jan 10 12:52:05 PM PST 24 Jan 10 12:54:15 PM PST 24 256251680452 ps
T848 /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4009687651 Jan 10 12:30:50 PM PST 24 Jan 10 12:32:43 PM PST 24 105120774356 ps
T849 /workspace/coverage/default/26.sysrst_ctrl_stress_all.2278445574 Jan 10 12:31:52 PM PST 24 Jan 10 12:32:56 PM PST 24 6769885219 ps
T850 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3877194067 Jan 10 12:55:58 PM PST 24 Jan 10 12:57:10 PM PST 24 2112915320 ps
T851 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3498696601 Jan 10 12:55:59 PM PST 24 Jan 10 12:57:12 PM PST 24 2249308047 ps
T852 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1706963892 Jan 10 12:56:28 PM PST 24 Jan 10 12:57:41 PM PST 24 2021159663 ps
T853 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3336111148 Jan 10 12:56:06 PM PST 24 Jan 10 12:57:18 PM PST 24 2047433126 ps
T854 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3238715383 Jan 10 12:56:03 PM PST 24 Jan 10 12:59:04 PM PST 24 42357890954 ps
T855 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3105613395 Jan 10 12:56:27 PM PST 24 Jan 10 12:57:38 PM PST 24 2119194741 ps
T856 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3927878785 Jan 10 12:56:18 PM PST 24 Jan 10 12:57:33 PM PST 24 7859146919 ps
T857 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3048782817 Jan 10 12:56:18 PM PST 24 Jan 10 12:57:31 PM PST 24 2071329530 ps
T858 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.138118893 Jan 10 12:56:28 PM PST 24 Jan 10 12:57:41 PM PST 24 2015093725 ps
T859 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3388824243 Jan 10 12:56:18 PM PST 24 Jan 10 12:57:56 PM PST 24 6973185872 ps
T860 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2642236315 Jan 10 12:56:22 PM PST 24 Jan 10 12:57:40 PM PST 24 2034653176 ps
T861 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.329804957 Jan 10 12:56:41 PM PST 24 Jan 10 12:57:57 PM PST 24 2012952545 ps
T862 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2697407174 Jan 10 12:56:24 PM PST 24 Jan 10 12:57:37 PM PST 24 2086126446 ps
T863 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2057876200 Jan 10 12:56:10 PM PST 24 Jan 10 12:57:26 PM PST 24 2044049497 ps
T864 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3956743492 Jan 10 12:56:22 PM PST 24 Jan 10 12:57:34 PM PST 24 2068785794 ps
T865 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2739086162 Jan 10 12:56:15 PM PST 24 Jan 10 12:57:32 PM PST 24 2081785008 ps
T866 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2932717917 Jan 10 12:56:23 PM PST 24 Jan 10 12:57:35 PM PST 24 2040180134 ps
T321 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1770082032 Jan 10 12:56:01 PM PST 24 Jan 10 12:58:57 PM PST 24 42371592525 ps
T867 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3084362549 Jan 10 12:56:23 PM PST 24 Jan 10 12:57:39 PM PST 24 2010062736 ps
T868 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.431665098 Jan 10 12:56:29 PM PST 24 Jan 10 12:57:42 PM PST 24 2040774005 ps
T869 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2404148905 Jan 10 12:56:23 PM PST 24 Jan 10 12:57:39 PM PST 24 2046216547 ps
T870 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2598172380 Jan 10 12:56:28 PM PST 24 Jan 10 12:57:39 PM PST 24 2041229987 ps
T871 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.4198806507 Jan 10 12:56:03 PM PST 24 Jan 10 12:57:17 PM PST 24 2778685885 ps
T872 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.694613122 Jan 10 12:56:00 PM PST 24 Jan 10 12:57:27 PM PST 24 22529939816 ps
T873 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2453651658 Jan 10 12:55:58 PM PST 24 Jan 10 12:57:16 PM PST 24 2221931351 ps
T874 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3852733512 Jan 10 12:56:14 PM PST 24 Jan 10 12:57:32 PM PST 24 2015570595 ps
T875 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.386613626 Jan 10 12:56:06 PM PST 24 Jan 10 12:57:20 PM PST 24 6107622546 ps
T876 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3538668399 Jan 10 12:55:49 PM PST 24 Jan 10 12:56:59 PM PST 24 2020140553 ps
T877 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3082535308 Jan 10 12:56:00 PM PST 24 Jan 10 12:57:18 PM PST 24 2089798193 ps
T878 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3809598584 Jan 10 12:56:00 PM PST 24 Jan 10 12:57:13 PM PST 24 2048709583 ps
T879 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.727159657 Jan 10 12:55:58 PM PST 24 Jan 10 12:58:05 PM PST 24 75164038071 ps
T880 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1004001831 Jan 10 12:56:15 PM PST 24 Jan 10 12:58:26 PM PST 24 22246754410 ps
T881 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3321430505 Jan 10 12:55:49 PM PST 24 Jan 10 12:57:10 PM PST 24 6055291862 ps
T882 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2474126042 Jan 10 12:57:14 PM PST 24 Jan 10 12:58:36 PM PST 24 22858310257 ps
T883 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.21261774 Jan 10 12:55:57 PM PST 24 Jan 10 12:57:08 PM PST 24 2052292626 ps
T302 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3786981292 Jan 10 12:55:58 PM PST 24 Jan 10 12:57:11 PM PST 24 2067261767 ps
T884 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1768200851 Jan 10 12:56:13 PM PST 24 Jan 10 12:57:44 PM PST 24 9923796581 ps
T885 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3027638418 Jan 10 12:56:10 PM PST 24 Jan 10 12:57:31 PM PST 24 10231071478 ps
T886 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.302882351 Jan 10 12:55:58 PM PST 24 Jan 10 12:57:19 PM PST 24 11077843598 ps
T887 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3343820479 Jan 10 12:56:22 PM PST 24 Jan 10 12:57:34 PM PST 24 2056665795 ps
T888 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4263725143 Jan 10 12:56:01 PM PST 24 Jan 10 12:57:17 PM PST 24 2009304056 ps
T889 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.819426559 Jan 10 12:56:29 PM PST 24 Jan 10 12:57:44 PM PST 24 2009884824 ps
T890 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3861624381 Jan 10 12:55:59 PM PST 24 Jan 10 12:57:21 PM PST 24 4032927245 ps
T891 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4026170170 Jan 10 12:56:26 PM PST 24 Jan 10 12:57:55 PM PST 24 9825548707 ps
T892 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3740185683 Jan 10 12:56:18 PM PST 24 Jan 10 12:57:34 PM PST 24 2050480378 ps
T303 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3347664252 Jan 10 12:56:13 PM PST 24 Jan 10 12:57:28 PM PST 24 2060580935 ps
T893 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4000158459 Jan 10 12:56:15 PM PST 24 Jan 10 12:57:32 PM PST 24 2187905156 ps
T322 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1761353347 Jan 10 12:56:07 PM PST 24 Jan 10 12:58:17 PM PST 24 22184195118 ps
T894 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2645983316 Jan 10 12:56:26 PM PST 24 Jan 10 12:57:41 PM PST 24 2012217294 ps
T895 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.461045974 Jan 10 12:56:17 PM PST 24 Jan 10 12:57:50 PM PST 24 5851419794 ps
T896 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1882623811 Jan 10 12:55:58 PM PST 24 Jan 10 12:57:11 PM PST 24 2194865807 ps
T897 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2535608364 Jan 10 12:56:12 PM PST 24 Jan 10 12:57:29 PM PST 24 2034542385 ps
T898 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3173010309 Jan 10 12:56:00 PM PST 24 Jan 10 12:57:13 PM PST 24 2159122185 ps
T899 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3437677249 Jan 10 12:55:57 PM PST 24 Jan 10 12:57:10 PM PST 24 5123663793 ps
T900 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.401425318 Jan 10 12:56:22 PM PST 24 Jan 10 12:57:34 PM PST 24 2039561276 ps
T901 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1613705663 Jan 10 12:56:20 PM PST 24 Jan 10 12:57:33 PM PST 24 2031850032 ps
T902 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2033117953 Jan 10 12:56:28 PM PST 24 Jan 10 12:57:39 PM PST 24 2032009474 ps
T903 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3862767961 Jan 10 12:56:02 PM PST 24 Jan 10 12:57:15 PM PST 24 2194756043 ps
T904 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2127343982 Jan 10 12:56:20 PM PST 24 Jan 10 12:57:34 PM PST 24 2083076847 ps
T905 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2693224039 Jan 10 12:56:10 PM PST 24 Jan 10 12:57:25 PM PST 24 2333768385 ps

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2947917444
Short name T1
Test name
Test status
Simulation time 22311368741 ps
CPU time 29.97 seconds
Started Jan 10 12:56:05 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 201152 kb
Host smart-ae572563-a3d4-4812-8d9f-a0288edf446c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947917444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.2947917444
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2963550613
Short name T13
Test name
Test status
Simulation time 156125847375 ps
CPU time 411.26 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:38:25 PM PST 24
Peak memory 201416 kb
Host smart-89db5427-42de-4d18-8a1a-f7d319451dad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963550613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.2963550613
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.754100167
Short name T44
Test name
Test status
Simulation time 521108923805 ps
CPU time 180.27 seconds
Started Jan 10 12:30:17 PM PST 24
Finished Jan 10 12:33:56 PM PST 24
Peak memory 218096 kb
Host smart-f23bd2fe-ecc1-41bf-87c6-8747553bd656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754100167 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.754100167
Directory /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3571308367
Short name T22
Test name
Test status
Simulation time 272645979882 ps
CPU time 43.42 seconds
Started Jan 10 12:44:33 PM PST 24
Finished Jan 10 12:46:34 PM PST 24
Peak memory 209984 kb
Host smart-f011ecab-1331-4f57-ae95-d18fa1175c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571308367 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.3571308367
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2147268531
Short name T46
Test name
Test status
Simulation time 168556834175 ps
CPU time 429.95 seconds
Started Jan 10 01:03:03 PM PST 24
Finished Jan 10 01:11:26 PM PST 24
Peak memory 201808 kb
Host smart-9844d368-17ac-426b-9fc1-4f364a24d418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147268531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w
ith_pre_cond.2147268531
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4176724786
Short name T36
Test name
Test status
Simulation time 7831608867 ps
CPU time 20.48 seconds
Started Jan 10 12:56:23 PM PST 24
Finished Jan 10 12:57:54 PM PST 24
Peak memory 201212 kb
Host smart-4c1de36f-b87f-4868-aa9c-77abf2aead4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176724786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.4176724786
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1980921475
Short name T179
Test name
Test status
Simulation time 398261876009 ps
CPU time 60.33 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:32:52 PM PST 24
Peak memory 210096 kb
Host smart-c309e839-b76f-423a-abb2-15e4b3ea1de5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980921475 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.1980921475
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.131458418
Short name T74
Test name
Test status
Simulation time 1515572531458 ps
CPU time 138.6 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:34:50 PM PST 24
Peak memory 215152 kb
Host smart-eb76ec0e-ccff-44c3-99b2-c4cb8d7c6089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131458418 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.131458418
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2437647034
Short name T49
Test name
Test status
Simulation time 5699294039 ps
CPU time 7.29 seconds
Started Jan 10 12:30:50 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201252 kb
Host smart-b507c7c7-116e-41da-ac4d-9e23d841644f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437647034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.2437647034
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1789345510
Short name T79
Test name
Test status
Simulation time 35023960486 ps
CPU time 85.37 seconds
Started Jan 10 12:30:13 PM PST 24
Finished Jan 10 12:32:19 PM PST 24
Peak memory 201276 kb
Host smart-b57497c1-6463-4a78-b7d2-d45485a0bd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789345510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1789345510
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2405655289
Short name T271
Test name
Test status
Simulation time 2097995405 ps
CPU time 2.97 seconds
Started Jan 10 12:56:05 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 201076 kb
Host smart-780dd11d-b9ec-4462-a0f1-047e0af86648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405655289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2405655289
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2533296213
Short name T29
Test name
Test status
Simulation time 2532196138 ps
CPU time 2.34 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 199988 kb
Host smart-944ace6d-515e-4d77-8636-b709f06d78b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533296213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2533296213
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.4236073518
Short name T7
Test name
Test status
Simulation time 2046346874 ps
CPU time 1.73 seconds
Started Jan 10 12:55:53 PM PST 24
Finished Jan 10 12:57:03 PM PST 24
Peak memory 200604 kb
Host smart-f90f510c-e089-4404-bb5e-0908dc9552e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236073518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.4236073518
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2449141782
Short name T269
Test name
Test status
Simulation time 118997947163 ps
CPU time 80.06 seconds
Started Jan 10 12:48:43 PM PST 24
Finished Jan 10 12:51:35 PM PST 24
Peak memory 209928 kb
Host smart-3d64f508-9091-4310-882d-b43d9f1b1f6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449141782 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2449141782
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1641618528
Short name T265
Test name
Test status
Simulation time 175277622358 ps
CPU time 477.56 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 12:39:55 PM PST 24
Peak memory 201468 kb
Host smart-7b18ccc4-8e52-49cd-aeda-162845d02243
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641618528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.1641618528
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.3530480558
Short name T207
Test name
Test status
Simulation time 237680382711 ps
CPU time 160.19 seconds
Started Jan 10 12:31:04 PM PST 24
Finished Jan 10 12:34:31 PM PST 24
Peak memory 209924 kb
Host smart-713910ad-5cd6-4558-830b-5ba25d792e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530480558 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.3530480558
Directory /workspace/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3107560231
Short name T259
Test name
Test status
Simulation time 97712722641 ps
CPU time 85.99 seconds
Started Jan 10 12:35:18 PM PST 24
Finished Jan 10 12:37:15 PM PST 24
Peak memory 201736 kb
Host smart-2a4b70b4-0c22-40d9-9394-686bd9734c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107560231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w
ith_pre_cond.3107560231
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.2293199863
Short name T37
Test name
Test status
Simulation time 2156450442 ps
CPU time 1.09 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 200960 kb
Host smart-c7c5d437-5e20-4aba-b1e1-c959d214a1a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293199863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.2293199863
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.3143146725
Short name T43
Test name
Test status
Simulation time 42160766147 ps
CPU time 26.68 seconds
Started Jan 10 12:30:53 PM PST 24
Finished Jan 10 12:32:04 PM PST 24
Peak memory 221192 kb
Host smart-52522985-add4-4955-ab91-eea4909f7b06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143146725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3143146725
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.1837346912
Short name T58
Test name
Test status
Simulation time 60569911495 ps
CPU time 38.79 seconds
Started Jan 10 12:42:23 PM PST 24
Finished Jan 10 12:44:18 PM PST 24
Peak memory 210104 kb
Host smart-ee127411-c7a9-435c-b824-829bc57f803d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837346912 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.1837346912
Directory /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.200800405
Short name T312
Test name
Test status
Simulation time 98931792005 ps
CPU time 62.93 seconds
Started Jan 10 12:31:22 PM PST 24
Finished Jan 10 12:33:12 PM PST 24
Peak memory 201488 kb
Host smart-185865b9-5af8-43ee-9784-55fe879e0b25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200800405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_combo_detect.200800405
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.477292983
Short name T112
Test name
Test status
Simulation time 158647790856 ps
CPU time 42.59 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 201556 kb
Host smart-cf3bd0ea-bbe4-41c2-8a75-d1a65e079353
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477292983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_combo_detect.477292983
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1266199418
Short name T173
Test name
Test status
Simulation time 983727243221 ps
CPU time 255.21 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:35:41 PM PST 24
Peak memory 209816 kb
Host smart-bb036389-af50-4884-86b5-8be1c316b609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266199418 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1266199418
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.4276081083
Short name T56
Test name
Test status
Simulation time 118465426947 ps
CPU time 278.65 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:37:32 PM PST 24
Peak memory 201532 kb
Host smart-569e7f49-6677-469b-9b09-5ec4d7da5a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276081083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.4276081083
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3093197191
Short name T9
Test name
Test status
Simulation time 42482898444 ps
CPU time 105.1 seconds
Started Jan 10 12:55:50 PM PST 24
Finished Jan 10 12:58:45 PM PST 24
Peak memory 201244 kb
Host smart-796c6ed0-18e5-47a8-843b-271c8528f211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093197191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.3093197191
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.2898413156
Short name T76
Test name
Test status
Simulation time 80462379178 ps
CPU time 110.52 seconds
Started Jan 10 12:31:35 PM PST 24
Finished Jan 10 12:34:16 PM PST 24
Peak memory 201612 kb
Host smart-9444b3e4-bc40-4264-90a6-3d90b80e60f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898413156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.2898413156
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4236741831
Short name T71
Test name
Test status
Simulation time 1336192717401 ps
CPU time 363.13 seconds
Started Jan 10 12:31:13 PM PST 24
Finished Jan 10 12:38:02 PM PST 24
Peak memory 209988 kb
Host smart-c4c219f4-9701-418c-8ca9-b674a7f5fc42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236741831 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.4236741831
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.2447954723
Short name T16
Test name
Test status
Simulation time 40201517006 ps
CPU time 108.66 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:33:13 PM PST 24
Peak memory 209952 kb
Host smart-a6ef83f6-92d2-439f-add4-89c7daba24d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447954723 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.2447954723
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3980787167
Short name T163
Test name
Test status
Simulation time 75388330337 ps
CPU time 129.14 seconds
Started Jan 10 12:49:20 PM PST 24
Finished Jan 10 12:53:01 PM PST 24
Peak memory 201736 kb
Host smart-6d26231a-5bfa-4bc2-8af6-c0a514ca7371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980787167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w
ith_pre_cond.3980787167
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.2325405603
Short name T201
Test name
Test status
Simulation time 81854690970 ps
CPU time 56.06 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:42:19 PM PST 24
Peak memory 210032 kb
Host smart-b1e70d6d-4c9a-4cc6-b2e0-6caebedb7933
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325405603 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.2325405603
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.83791579
Short name T319
Test name
Test status
Simulation time 110632672219 ps
CPU time 68.25 seconds
Started Jan 10 12:55:03 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 201756 kb
Host smart-642a6ac5-b8b4-4755-95a5-4774c13abac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83791579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_wit
h_pre_cond.83791579
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.864452210
Short name T106
Test name
Test status
Simulation time 80912759341 ps
CPU time 55.28 seconds
Started Jan 10 12:31:11 PM PST 24
Finished Jan 10 12:32:52 PM PST 24
Peak memory 215560 kb
Host smart-80c7b6a0-dd41-4fcb-bc4b-ed37df2b590f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864452210 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.864452210
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.3164647586
Short name T109
Test name
Test status
Simulation time 269273651775 ps
CPU time 337.73 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:40:09 PM PST 24
Peak memory 201520 kb
Host smart-325614f7-8753-4f84-879d-5b738625b432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164647586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_s
tress_all.3164647586
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3971455685
Short name T156
Test name
Test status
Simulation time 3447066508 ps
CPU time 2.93 seconds
Started Jan 10 12:30:16 PM PST 24
Finished Jan 10 12:30:58 PM PST 24
Peak memory 201248 kb
Host smart-f9e1c3fe-d52b-4304-88c6-f613a0029b68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971455685 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.3971455685
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.2637627963
Short name T166
Test name
Test status
Simulation time 4182344900 ps
CPU time 7.84 seconds
Started Jan 10 12:31:28 PM PST 24
Finished Jan 10 12:32:25 PM PST 24
Peak memory 201212 kb
Host smart-b475a9cc-edf5-4229-ac4c-8601c1e689b1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637627963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.2637627963
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1582318362
Short name T90
Test name
Test status
Simulation time 3166267560 ps
CPU time 4.69 seconds
Started Jan 10 12:36:19 PM PST 24
Finished Jan 10 12:36:58 PM PST 24
Peak memory 201368 kb
Host smart-17606b4e-8244-4422-bf0f-2fa56520e39e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582318362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.1582318362
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3319625776
Short name T228
Test name
Test status
Simulation time 3401307523 ps
CPU time 2.57 seconds
Started Jan 10 12:37:30 PM PST 24
Finished Jan 10 12:38:08 PM PST 24
Peak memory 201296 kb
Host smart-3325adce-44f0-4d48-a4a7-11c0f27d30cf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319625776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.3319625776
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3574299349
Short name T275
Test name
Test status
Simulation time 2430642981 ps
CPU time 4.73 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:37 PM PST 24
Peak memory 201224 kb
Host smart-67d0d37a-c72d-4f89-8f9f-f5dccf6041fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574299349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3574299349
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.395668303
Short name T220
Test name
Test status
Simulation time 169213232960 ps
CPU time 117.25 seconds
Started Jan 10 01:23:15 PM PST 24
Finished Jan 10 01:25:28 PM PST 24
Peak memory 201824 kb
Host smart-a4cd206c-882d-4e38-b7c0-cc5da3e9a7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395668303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi
th_pre_cond.395668303
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.382061756
Short name T248
Test name
Test status
Simulation time 63379366754 ps
CPU time 15.22 seconds
Started Jan 10 12:30:37 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 201500 kb
Host smart-f1d66d1c-9ba1-4f22-871f-b8afc1088722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382061756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wit
h_pre_cond.382061756
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2781378255
Short name T328
Test name
Test status
Simulation time 119198265295 ps
CPU time 150.37 seconds
Started Jan 10 12:40:43 PM PST 24
Finished Jan 10 12:43:58 PM PST 24
Peak memory 201712 kb
Host smart-2e3fa501-4fdd-446a-88d4-1dec859701b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781378255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.2781378255
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1004330245
Short name T318
Test name
Test status
Simulation time 218634967025 ps
CPU time 576.31 seconds
Started Jan 10 12:37:54 PM PST 24
Finished Jan 10 12:48:04 PM PST 24
Peak memory 201648 kb
Host smart-348850b5-ca58-4933-84f2-defae46ef14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004330245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w
ith_pre_cond.1004330245
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.1266477950
Short name T205
Test name
Test status
Simulation time 269310523800 ps
CPU time 193.46 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:34:55 PM PST 24
Peak memory 201480 kb
Host smart-6f8f9ce0-bd70-4da5-ad05-1ecd10985c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266477950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.1266477950
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.916213158
Short name T379
Test name
Test status
Simulation time 2144785056 ps
CPU time 0.96 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:35 PM PST 24
Peak memory 200596 kb
Host smart-8f7a7722-f115-41c1-9591-aed596d79b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916213158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_tes
t.916213158
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.382983921
Short name T346
Test name
Test status
Simulation time 68218850197 ps
CPU time 54.23 seconds
Started Jan 10 12:42:20 PM PST 24
Finished Jan 10 12:44:31 PM PST 24
Peak memory 201612 kb
Host smart-df92da33-29e3-49ca-a094-085a23cbbca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382983921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_wi
th_pre_cond.382983921
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3640806397
Short name T340
Test name
Test status
Simulation time 75840317880 ps
CPU time 106.71 seconds
Started Jan 10 12:39:42 PM PST 24
Finished Jan 10 12:41:59 PM PST 24
Peak memory 201640 kb
Host smart-2c2cb42f-8cc8-4066-9f8b-753ff7d2fb19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640806397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.3640806397
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.4108989362
Short name T333
Test name
Test status
Simulation time 75830106041 ps
CPU time 195.61 seconds
Started Jan 10 12:43:15 PM PST 24
Finished Jan 10 12:47:45 PM PST 24
Peak memory 201772 kb
Host smart-0643b9db-a2c7-420f-9a94-609d4c2b751d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108989362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.4108989362
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.21451199
Short name T45
Test name
Test status
Simulation time 44085293019 ps
CPU time 30.41 seconds
Started Jan 10 12:41:38 PM PST 24
Finished Jan 10 12:43:14 PM PST 24
Peak memory 201852 kb
Host smart-20105077-6c77-4a06-add0-aa978c6bf957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21451199 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_wit
h_pre_cond.21451199
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.140771965
Short name T34
Test name
Test status
Simulation time 2037220320 ps
CPU time 5.52 seconds
Started Jan 10 12:55:54 PM PST 24
Finished Jan 10 12:57:07 PM PST 24
Peak memory 200908 kb
Host smart-7611288e-c667-47c5-ba0f-b40678b0b81c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140771965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw
.140771965
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.1654897302
Short name T80
Test name
Test status
Simulation time 29594287478 ps
CPU time 77.14 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 201284 kb
Host smart-929e27e5-387d-4992-8be1-b67943a30690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654897302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.1654897302
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.1611661599
Short name T105
Test name
Test status
Simulation time 131468645427 ps
CPU time 75.03 seconds
Started Jan 10 12:43:49 PM PST 24
Finished Jan 10 12:46:18 PM PST 24
Peak memory 210016 kb
Host smart-f06792b2-4e26-4f11-b339-4e4c8abd0b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611661599 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.1611661599
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.3822143349
Short name T97
Test name
Test status
Simulation time 3605931673 ps
CPU time 9.68 seconds
Started Jan 10 12:31:59 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 201332 kb
Host smart-afb67a66-da0a-4909-b1bf-475b3c28526a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822143349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.3
822143349
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.887916407
Short name T249
Test name
Test status
Simulation time 147915183344 ps
CPU time 279.47 seconds
Started Jan 10 12:43:13 PM PST 24
Finished Jan 10 12:49:06 PM PST 24
Peak memory 201472 kb
Host smart-21d216e4-b1f5-4996-9885-a4ab66db5fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887916407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_wi
th_pre_cond.887916407
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3930859924
Short name T320
Test name
Test status
Simulation time 22213022107 ps
CPU time 55.48 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:58:03 PM PST 24
Peak memory 201188 kb
Host smart-b52dc436-0dd4-4a0f-8723-bc2e6844e6ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930859924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_tl_intg_err.3930859924
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1840362868
Short name T12
Test name
Test status
Simulation time 22210937122 ps
CPU time 62.9 seconds
Started Jan 10 12:56:16 PM PST 24
Finished Jan 10 12:58:31 PM PST 24
Peak memory 201100 kb
Host smart-6b11249a-1446-49c0-a946-1ef87018eca2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840362868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.1840362868
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.3734691068
Short name T304
Test name
Test status
Simulation time 76593511083 ps
CPU time 180.87 seconds
Started Jan 10 12:31:11 PM PST 24
Finished Jan 10 12:34:58 PM PST 24
Peak memory 201584 kb
Host smart-ecda50ed-25d9-4078-8d55-b5851de01046
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734691068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.3734691068
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1813809995
Short name T343
Test name
Test status
Simulation time 48059483436 ps
CPU time 34.22 seconds
Started Jan 10 12:54:36 PM PST 24
Finished Jan 10 12:56:16 PM PST 24
Peak memory 201680 kb
Host smart-6979cfb3-df1c-4091-ba38-a294e8f6316f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813809995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_combo_detect.1813809995
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2283541373
Short name T338
Test name
Test status
Simulation time 207098667079 ps
CPU time 277.91 seconds
Started Jan 10 01:12:36 PM PST 24
Finished Jan 10 01:18:40 PM PST 24
Peak memory 201652 kb
Host smart-4eb242cf-39fa-44c0-bc4c-8ae316aca832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283541373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_w
ith_pre_cond.2283541373
Directory /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1238480281
Short name T335
Test name
Test status
Simulation time 51474454389 ps
CPU time 37.99 seconds
Started Jan 10 12:54:58 PM PST 24
Finished Jan 10 12:56:42 PM PST 24
Peak memory 201632 kb
Host smart-a71dd78c-57c1-49de-a8e8-9d54edb610db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238480281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.1238480281
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.3772727245
Short name T183
Test name
Test status
Simulation time 2011627660 ps
CPU time 5.38 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 201248 kb
Host smart-63965dcd-b51c-456e-bed2-560d2c3c9b64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772727245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.3772727245
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1498513233
Short name T84
Test name
Test status
Simulation time 38302120648 ps
CPU time 88.42 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:32:36 PM PST 24
Peak memory 201488 kb
Host smart-9c97759e-3ea4-4228-be30-96615fbf4225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498513233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.1498513233
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3735367024
Short name T296
Test name
Test status
Simulation time 2740663065 ps
CPU time 5.18 seconds
Started Jan 10 12:55:53 PM PST 24
Finished Jan 10 12:57:06 PM PST 24
Peak memory 201164 kb
Host smart-a1ab6b85-e48f-4b71-99a8-ecf13f56b68d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735367024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.3735367024
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.957633371
Short name T361
Test name
Test status
Simulation time 39471202457 ps
CPU time 183.98 seconds
Started Jan 10 12:55:48 PM PST 24
Finished Jan 10 12:59:59 PM PST 24
Peak memory 201172 kb
Host smart-c0503ca5-9136-40b8-9b68-1211fc31fb14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957633371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_
csr_bit_bash.957633371
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1157514874
Short name T301
Test name
Test status
Simulation time 6037266804 ps
CPU time 8.32 seconds
Started Jan 10 12:55:48 PM PST 24
Finished Jan 10 12:57:04 PM PST 24
Peak memory 201012 kb
Host smart-dafbdac8-248e-409b-a9e5-d3a65df98dfb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157514874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.1157514874
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2204551688
Short name T355
Test name
Test status
Simulation time 2125303295 ps
CPU time 2.49 seconds
Started Jan 10 12:55:49 PM PST 24
Finished Jan 10 12:56:59 PM PST 24
Peak memory 209368 kb
Host smart-a6d7aae8-dd0c-4704-9382-4fa088122aed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204551688 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2204551688
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.1518825108
Short name T38
Test name
Test status
Simulation time 4134557799 ps
CPU time 11.25 seconds
Started Jan 10 12:55:49 PM PST 24
Finished Jan 10 12:57:08 PM PST 24
Peak memory 200984 kb
Host smart-2925d9b0-36f7-4f51-9d1d-45d0411a2207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518825108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.1518825108
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.3578169413
Short name T399
Test name
Test status
Simulation time 2031344432 ps
CPU time 6.67 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:14 PM PST 24
Peak memory 201156 kb
Host smart-edb0b0a0-efab-4b23-b863-11a4b75ee20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578169413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.3578169413
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.4123688618
Short name T387
Test name
Test status
Simulation time 2766438654 ps
CPU time 3.81 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 201148 kb
Host smart-82a9b9d4-88c3-4d33-b7bc-28858bfcbce7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123688618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.4123688618
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.103577783
Short name T57
Test name
Test status
Simulation time 39629435502 ps
CPU time 106.95 seconds
Started Jan 10 12:55:50 PM PST 24
Finished Jan 10 12:58:44 PM PST 24
Peak memory 201116 kb
Host smart-c61a8b6e-737e-47b9-b0b9-f54db06eb5e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103577783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.103577783
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3321430505
Short name T881
Test name
Test status
Simulation time 6055291862 ps
CPU time 14.2 seconds
Started Jan 10 12:55:49 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 201100 kb
Host smart-f1ec7055-883a-40a5-ab8e-7ce0377c4b7a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321430505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.3321430505
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2968107200
Short name T289
Test name
Test status
Simulation time 2060474654 ps
CPU time 6.1 seconds
Started Jan 10 12:55:59 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 200992 kb
Host smart-6a96a34c-f273-4631-b38e-a0b3c257e0c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968107200 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2968107200
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3694639494
Short name T402
Test name
Test status
Simulation time 2098327082 ps
CPU time 2.28 seconds
Started Jan 10 12:55:49 PM PST 24
Finished Jan 10 12:56:58 PM PST 24
Peak memory 200960 kb
Host smart-0f56a555-8309-4bc3-86e0-6e24d5abb14e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694639494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.3694639494
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.3538668399
Short name T876
Test name
Test status
Simulation time 2020140553 ps
CPU time 3.32 seconds
Started Jan 10 12:55:49 PM PST 24
Finished Jan 10 12:56:59 PM PST 24
Peak memory 200548 kb
Host smart-90b4488c-b5d3-4c9f-91cb-579eabff4def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538668399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.3538668399
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.1902609683
Short name T371
Test name
Test status
Simulation time 10396434397 ps
CPU time 35.44 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:43 PM PST 24
Peak memory 201188 kb
Host smart-8b2a24e6-045d-4dd8-a4b7-5ae9c402b7ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902609683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.1902609683
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1693321744
Short name T277
Test name
Test status
Simulation time 2249681021 ps
CPU time 2.99 seconds
Started Jan 10 12:55:52 PM PST 24
Finished Jan 10 12:57:02 PM PST 24
Peak memory 209340 kb
Host smart-b5065987-99fa-41dd-ad3b-fbc2334cf32d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693321744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.1693321744
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2601484260
Short name T405
Test name
Test status
Simulation time 2114009970 ps
CPU time 2.03 seconds
Started Jan 10 12:56:05 PM PST 24
Finished Jan 10 12:57:16 PM PST 24
Peak memory 201024 kb
Host smart-44c45ea5-8e4d-4cac-9886-03eec28fec78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601484260 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.2601484260
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3375623463
Short name T299
Test name
Test status
Simulation time 2143217211 ps
CPU time 1.92 seconds
Started Jan 10 12:57:14 PM PST 24
Finished Jan 10 12:58:29 PM PST 24
Peak memory 199124 kb
Host smart-5221c978-2fc8-4e4e-947f-73035aa286e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375623463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3375623463
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3812226778
Short name T406
Test name
Test status
Simulation time 2009482584 ps
CPU time 5.99 seconds
Started Jan 10 12:56:06 PM PST 24
Finished Jan 10 12:57:23 PM PST 24
Peak memory 200712 kb
Host smart-972b9505-6f99-41e8-b813-eac2cad4e54b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812226778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.3812226778
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.588494506
Short name T356
Test name
Test status
Simulation time 5295207919 ps
CPU time 14.03 seconds
Started Jan 10 12:56:05 PM PST 24
Finished Jan 10 12:57:29 PM PST 24
Peak memory 201240 kb
Host smart-79dba1f0-b53e-4754-aefd-4ccf247428b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588494506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.588494506
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1780734575
Short name T396
Test name
Test status
Simulation time 2059659530 ps
CPU time 7.1 seconds
Started Jan 10 12:56:02 PM PST 24
Finished Jan 10 12:57:20 PM PST 24
Peak memory 201056 kb
Host smart-84e9fc4c-66b2-49ab-b2ac-3f17232d54ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780734575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.1780734575
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.527466496
Short name T388
Test name
Test status
Simulation time 2064879615 ps
CPU time 5.99 seconds
Started Jan 10 12:57:32 PM PST 24
Finished Jan 10 12:58:53 PM PST 24
Peak memory 200628 kb
Host smart-c0aad5d9-3bc3-4bd0-b662-c0683daf0d23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527466496 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.527466496
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.615137238
Short name T290
Test name
Test status
Simulation time 2036309122 ps
CPU time 5.64 seconds
Started Jan 10 12:56:05 PM PST 24
Finished Jan 10 12:57:21 PM PST 24
Peak memory 200944 kb
Host smart-86604d73-3e09-4552-b934-42017c1d75fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615137238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_r
w.615137238
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.3125724849
Short name T24
Test name
Test status
Simulation time 2018279159 ps
CPU time 3.2 seconds
Started Jan 10 12:56:05 PM PST 24
Finished Jan 10 12:57:19 PM PST 24
Peak memory 200644 kb
Host smart-363ee1f2-179b-4a86-bc4f-886ae4817583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125724849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_te
st.3125724849
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.461632161
Short name T10
Test name
Test status
Simulation time 8702772029 ps
CPU time 31.84 seconds
Started Jan 10 12:56:26 PM PST 24
Finished Jan 10 12:58:08 PM PST 24
Peak memory 201236 kb
Host smart-421426a1-ea57-45a5-925e-7b2d19aaf9c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461632161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_same_csr_outstanding.461632161
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.431665098
Short name T868
Test name
Test status
Simulation time 2040774005 ps
CPU time 3.71 seconds
Started Jan 10 12:56:29 PM PST 24
Finished Jan 10 12:57:42 PM PST 24
Peak memory 201092 kb
Host smart-26c73fba-cb5d-4bb4-83f9-f57458233c92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431665098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_error
s.431665098
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1040395548
Short name T368
Test name
Test status
Simulation time 2083920485 ps
CPU time 5.33 seconds
Started Jan 10 12:56:05 PM PST 24
Finished Jan 10 12:57:20 PM PST 24
Peak memory 200984 kb
Host smart-c86f565b-a697-4059-ad14-0c8c835c74f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040395548 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1040395548
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1358365339
Short name T2
Test name
Test status
Simulation time 2080545318 ps
CPU time 2.06 seconds
Started Jan 10 12:56:37 PM PST 24
Finished Jan 10 12:57:48 PM PST 24
Peak memory 200896 kb
Host smart-b917a523-ca39-43b2-953e-030d0538ca6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358365339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.1358365339
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3105613395
Short name T855
Test name
Test status
Simulation time 2119194741 ps
CPU time 0.95 seconds
Started Jan 10 12:56:27 PM PST 24
Finished Jan 10 12:57:38 PM PST 24
Peak memory 200544 kb
Host smart-82f1f666-4378-4ca5-96e3-07677f974b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105613395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.3105613395
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2626612276
Short name T400
Test name
Test status
Simulation time 9488262761 ps
CPU time 14.99 seconds
Started Jan 10 12:56:06 PM PST 24
Finished Jan 10 12:57:31 PM PST 24
Peak memory 201136 kb
Host smart-7313f69b-e10a-4552-baea-92cb2e58d005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626612276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.2626612276
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.3690459900
Short name T33
Test name
Test status
Simulation time 43891442673 ps
CPU time 17.08 seconds
Started Jan 10 12:56:06 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 201144 kb
Host smart-369fa2af-8f17-4bb3-a5f0-082970feb2f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690459900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_tl_intg_err.3690459900
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.765725636
Short name T39
Test name
Test status
Simulation time 2141532570 ps
CPU time 2.34 seconds
Started Jan 10 12:56:07 PM PST 24
Finished Jan 10 12:57:19 PM PST 24
Peak memory 201028 kb
Host smart-db8882f1-93d8-4978-87d9-7c1e02f3c50a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765725636 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.765725636
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2840631654
Short name T288
Test name
Test status
Simulation time 2070896821 ps
CPU time 2.17 seconds
Started Jan 10 12:56:03 PM PST 24
Finished Jan 10 12:57:15 PM PST 24
Peak memory 200940 kb
Host smart-c62ae1bc-5ee3-41c7-8f34-836ee196429d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840631654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.2840631654
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3392923098
Short name T369
Test name
Test status
Simulation time 2041018961 ps
CPU time 1.9 seconds
Started Jan 10 12:56:06 PM PST 24
Finished Jan 10 12:57:18 PM PST 24
Peak memory 200636 kb
Host smart-4733e643-0d05-4c0a-ad99-10cb9b0ca33f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392923098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.3392923098
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.3232993420
Short name T382
Test name
Test status
Simulation time 5067427405 ps
CPU time 13.8 seconds
Started Jan 10 12:56:07 PM PST 24
Finished Jan 10 12:57:31 PM PST 24
Peak memory 201216 kb
Host smart-ffa9f75d-f28f-4897-9f7a-04da56089525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232993420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.3232993420
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.52608160
Short name T393
Test name
Test status
Simulation time 3166403279 ps
CPU time 3.05 seconds
Started Jan 10 12:56:06 PM PST 24
Finished Jan 10 12:57:20 PM PST 24
Peak memory 201124 kb
Host smart-368bb848-aa96-4f24-9617-6c25a71a87b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52608160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors
.52608160
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3238715383
Short name T854
Test name
Test status
Simulation time 42357890954 ps
CPU time 111.01 seconds
Started Jan 10 12:56:03 PM PST 24
Finished Jan 10 12:59:04 PM PST 24
Peak memory 201184 kb
Host smart-6039251a-9df9-4a85-84bb-b8f961748f26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238715383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_tl_intg_err.3238715383
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.436715820
Short name T374
Test name
Test status
Simulation time 2050321611 ps
CPU time 3.33 seconds
Started Jan 10 12:56:42 PM PST 24
Finished Jan 10 12:57:55 PM PST 24
Peak memory 200996 kb
Host smart-05a1e98d-a19d-4c64-8505-abb5609fbc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436715820 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.436715820
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2535608364
Short name T897
Test name
Test status
Simulation time 2034542385 ps
CPU time 6.15 seconds
Started Jan 10 12:56:12 PM PST 24
Finished Jan 10 12:57:29 PM PST 24
Peak memory 200912 kb
Host smart-0498bf2f-bf60-4d99-b8d2-d6054b6ecb54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535608364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.2535608364
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1877881475
Short name T370
Test name
Test status
Simulation time 2027054557 ps
CPU time 1.94 seconds
Started Jan 10 12:56:26 PM PST 24
Finished Jan 10 12:57:38 PM PST 24
Peak memory 200728 kb
Host smart-31d7ff38-e5bc-45a6-b337-5d45c9e23395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877881475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1877881475
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4026170170
Short name T891
Test name
Test status
Simulation time 9825548707 ps
CPU time 19.4 seconds
Started Jan 10 12:56:26 PM PST 24
Finished Jan 10 12:57:55 PM PST 24
Peak memory 201212 kb
Host smart-a772081d-2155-4f16-9b26-4cc7777a2504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026170170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_same_csr_outstanding.4026170170
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2693224039
Short name T905
Test name
Test status
Simulation time 2333768385 ps
CPU time 4.4 seconds
Started Jan 10 12:56:10 PM PST 24
Finished Jan 10 12:57:25 PM PST 24
Peak memory 209624 kb
Host smart-d04ef7da-de35-4712-96cb-b65be63b5bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693224039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.2693224039
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2474126042
Short name T882
Test name
Test status
Simulation time 22858310257 ps
CPU time 8.37 seconds
Started Jan 10 12:57:14 PM PST 24
Finished Jan 10 12:58:36 PM PST 24
Peak memory 199412 kb
Host smart-5d5755ff-cf07-4c59-b968-835b4ee599b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474126042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.2474126042
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2942393676
Short name T287
Test name
Test status
Simulation time 2108420320 ps
CPU time 2.13 seconds
Started Jan 10 12:56:42 PM PST 24
Finished Jan 10 12:57:54 PM PST 24
Peak memory 200968 kb
Host smart-8591601e-c583-47e5-a838-6ec0d7e73ff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942393676 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2942393676
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1284809885
Short name T11
Test name
Test status
Simulation time 2063259431 ps
CPU time 3.48 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:36 PM PST 24
Peak memory 200956 kb
Host smart-f45e8034-ca74-4664-bebd-de9551ec2b3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284809885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_
rw.1284809885
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.329804957
Short name T861
Test name
Test status
Simulation time 2012952545 ps
CPU time 5.54 seconds
Started Jan 10 12:56:41 PM PST 24
Finished Jan 10 12:57:57 PM PST 24
Peak memory 200636 kb
Host smart-58e24488-0e5e-4e7a-8bef-7a2caa15d81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329804957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_tes
t.329804957
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1768200851
Short name T884
Test name
Test status
Simulation time 9923796581 ps
CPU time 20.05 seconds
Started Jan 10 12:56:13 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 201236 kb
Host smart-e5454644-c808-4f33-b7f4-eda7ad186d14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768200851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.1768200851
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.2642236315
Short name T860
Test name
Test status
Simulation time 2034653176 ps
CPU time 7.13 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:40 PM PST 24
Peak memory 201088 kb
Host smart-7a43833f-33be-4983-96d3-480f28c498e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642236315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.2642236315
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1149428513
Short name T403
Test name
Test status
Simulation time 22444850979 ps
CPU time 16.07 seconds
Started Jan 10 12:56:34 PM PST 24
Finished Jan 10 12:57:59 PM PST 24
Peak memory 201196 kb
Host smart-95e4c3a5-2d21-498d-a9f6-c33bfb28d3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149428513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1149428513
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2127343982
Short name T904
Test name
Test status
Simulation time 2083076847 ps
CPU time 2.36 seconds
Started Jan 10 12:56:20 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 201028 kb
Host smart-c89e679d-063f-45c2-bf24-fef46c32453e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127343982 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.2127343982
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.23638889
Short name T297
Test name
Test status
Simulation time 2036348838 ps
CPU time 5.56 seconds
Started Jan 10 12:56:13 PM PST 24
Finished Jan 10 12:57:30 PM PST 24
Peak memory 200880 kb
Host smart-6f4892bb-2bab-44b9-a8a0-88f2630941ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23638889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw
.23638889
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3852733512
Short name T874
Test name
Test status
Simulation time 2015570595 ps
CPU time 5.91 seconds
Started Jan 10 12:56:14 PM PST 24
Finished Jan 10 12:57:32 PM PST 24
Peak memory 200552 kb
Host smart-d74b5422-2ce5-428b-a6a5-8ef20e08bb13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852733512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.3852733512
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3927878785
Short name T856
Test name
Test status
Simulation time 7859146919 ps
CPU time 3.48 seconds
Started Jan 10 12:56:18 PM PST 24
Finished Jan 10 12:57:33 PM PST 24
Peak memory 201152 kb
Host smart-79b60dc0-b5cb-4715-9f04-e6fe7be64981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927878785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.3927878785
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1345613322
Short name T273
Test name
Test status
Simulation time 2206078327 ps
CPU time 2.83 seconds
Started Jan 10 12:56:14 PM PST 24
Finished Jan 10 12:57:28 PM PST 24
Peak memory 201212 kb
Host smart-db9ff28a-fd2d-473c-8ee4-1f7660f0ee1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345613322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1345613322
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3344037258
Short name T282
Test name
Test status
Simulation time 42467921698 ps
CPU time 76.73 seconds
Started Jan 10 12:56:19 PM PST 24
Finished Jan 10 12:58:47 PM PST 24
Peak memory 201116 kb
Host smart-1a4d7ddb-43a6-4ea8-a750-d5c320a2f9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344037258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3344037258
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1574568732
Short name T381
Test name
Test status
Simulation time 2111718847 ps
CPU time 2.47 seconds
Started Jan 10 12:56:12 PM PST 24
Finished Jan 10 12:57:26 PM PST 24
Peak memory 200972 kb
Host smart-44aba9c5-78c0-4bf3-afb5-27a521705d85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574568732 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.1574568732
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3347664252
Short name T303
Test name
Test status
Simulation time 2060580935 ps
CPU time 3.95 seconds
Started Jan 10 12:56:13 PM PST 24
Finished Jan 10 12:57:28 PM PST 24
Peak memory 200832 kb
Host smart-20ef9169-98b2-4d45-b862-0381adab10ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347664252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.3347664252
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3182026922
Short name T386
Test name
Test status
Simulation time 2014498642 ps
CPU time 5.7 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:40 PM PST 24
Peak memory 200620 kb
Host smart-9344d257-5b15-4196-ac71-a2248617be8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182026922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.3182026922
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.3388824243
Short name T859
Test name
Test status
Simulation time 6973185872 ps
CPU time 26.67 seconds
Started Jan 10 12:56:18 PM PST 24
Finished Jan 10 12:57:56 PM PST 24
Peak memory 201180 kb
Host smart-d3ec463d-4878-4ade-9c8f-5fc41e588b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388824243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.3388824243
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2739086162
Short name T865
Test name
Test status
Simulation time 2081785008 ps
CPU time 5.16 seconds
Started Jan 10 12:56:15 PM PST 24
Finished Jan 10 12:57:32 PM PST 24
Peak memory 209320 kb
Host smart-a3d47dd4-9c4a-42e4-bb1d-5463cfaa5449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739086162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.2739086162
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1004001831
Short name T880
Test name
Test status
Simulation time 22246754410 ps
CPU time 59.18 seconds
Started Jan 10 12:56:15 PM PST 24
Finished Jan 10 12:58:26 PM PST 24
Peak memory 201188 kb
Host smart-7471c493-e1c6-45e7-8f48-c632ffc62fe1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004001831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.1004001831
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2697407174
Short name T862
Test name
Test status
Simulation time 2086126446 ps
CPU time 2.17 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:37 PM PST 24
Peak memory 200940 kb
Host smart-9d9a1aca-ab6a-455f-bf85-619dc1eff9fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697407174 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2697407174
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2964222569
Short name T3
Test name
Test status
Simulation time 2044068333 ps
CPU time 2.87 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:37 PM PST 24
Peak memory 200888 kb
Host smart-8fa80952-c989-47de-8b36-caf9e21f9568
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964222569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.2964222569
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.610130412
Short name T378
Test name
Test status
Simulation time 2016064884 ps
CPU time 3.26 seconds
Started Jan 10 12:56:21 PM PST 24
Finished Jan 10 12:57:35 PM PST 24
Peak memory 200684 kb
Host smart-42f138b2-3e6a-4207-9561-8eb8cf645d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610130412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_tes
t.610130412
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3960151124
Short name T4
Test name
Test status
Simulation time 5520342937 ps
CPU time 4.64 seconds
Started Jan 10 12:56:29 PM PST 24
Finished Jan 10 12:57:43 PM PST 24
Peak memory 201424 kb
Host smart-72a13e27-5c33-4988-b1f8-dd17fb80b615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960151124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.3960151124
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1959963073
Short name T274
Test name
Test status
Simulation time 2399062392 ps
CPU time 3.63 seconds
Started Jan 10 12:56:27 PM PST 24
Finished Jan 10 12:57:40 PM PST 24
Peak memory 201140 kb
Host smart-b8dec98b-ca26-4a20-9c24-fd18dbdb1265
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959963073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.1959963073
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1185355519
Short name T276
Test name
Test status
Simulation time 42380326483 ps
CPU time 109.46 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:59:24 PM PST 24
Peak memory 201184 kb
Host smart-44b2d37a-eebb-4428-a7ed-4e427aeac1ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185355519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.1185355519
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2404148905
Short name T869
Test name
Test status
Simulation time 2046216547 ps
CPU time 5.84 seconds
Started Jan 10 12:56:23 PM PST 24
Finished Jan 10 12:57:39 PM PST 24
Peak memory 200932 kb
Host smart-d38ff0e7-97a2-4700-aa31-f96adffe6943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404148905 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.2404148905
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1166017745
Short name T394
Test name
Test status
Simulation time 2032437688 ps
CPU time 5.52 seconds
Started Jan 10 12:56:26 PM PST 24
Finished Jan 10 12:57:41 PM PST 24
Peak memory 200924 kb
Host smart-c8243339-2f61-4d3a-a94f-5aaa486dedba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166017745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.1166017745
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3956743492
Short name T864
Test name
Test status
Simulation time 2068785794 ps
CPU time 1.36 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 200636 kb
Host smart-b590cfaa-ad46-4268-b729-39f9558adef1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956743492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.3956743492
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2527870908
Short name T383
Test name
Test status
Simulation time 22263806148 ps
CPU time 30.11 seconds
Started Jan 10 12:56:21 PM PST 24
Finished Jan 10 12:58:02 PM PST 24
Peak memory 201100 kb
Host smart-087ebd33-6301-48b7-a8e2-fbf638df8e63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527870908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.2527870908
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2756972344
Short name T35
Test name
Test status
Simulation time 2135131706 ps
CPU time 4.62 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:12 PM PST 24
Peak memory 200956 kb
Host smart-a6ad85a7-e8e6-4b1c-8ca8-b5c2d39fb3ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756972344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.2756972344
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.3951043040
Short name T397
Test name
Test status
Simulation time 39045723821 ps
CPU time 57.65 seconds
Started Jan 10 12:56:08 PM PST 24
Finished Jan 10 12:58:16 PM PST 24
Peak memory 201096 kb
Host smart-036d8522-dbd4-4b15-b268-3fd6b04a6a32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951043040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.3951043040
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3033328983
Short name T298
Test name
Test status
Simulation time 6046236251 ps
CPU time 5.05 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:13 PM PST 24
Peak memory 200928 kb
Host smart-c98951a8-d397-4b5e-a21f-792ba8a85b52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033328983 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.3033328983
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.571108500
Short name T380
Test name
Test status
Simulation time 2142924185 ps
CPU time 3.76 seconds
Started Jan 10 12:56:02 PM PST 24
Finished Jan 10 12:57:16 PM PST 24
Peak memory 200996 kb
Host smart-c170eebc-fc7c-415a-83c2-f7f7db5f943a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571108500 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.571108500
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3786981292
Short name T302
Test name
Test status
Simulation time 2067261767 ps
CPU time 2.05 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:11 PM PST 24
Peak memory 200896 kb
Host smart-ac4ee4bf-fd27-49bc-ae1a-f7c056e03de7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786981292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.3786981292
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.4263725143
Short name T888
Test name
Test status
Simulation time 2009304056 ps
CPU time 5.56 seconds
Started Jan 10 12:56:01 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 200860 kb
Host smart-ec232be5-ec65-4a22-a7b8-7d2a6b8ac70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263725143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.4263725143
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2511191115
Short name T376
Test name
Test status
Simulation time 5087541905 ps
CPU time 5.68 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:14 PM PST 24
Peak memory 201132 kb
Host smart-25a02aea-08ba-4d30-a7d1-db7a9f6ef028
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511191115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.2511191115
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2453651658
Short name T873
Test name
Test status
Simulation time 2221931351 ps
CPU time 7.25 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:16 PM PST 24
Peak memory 201124 kb
Host smart-cfd77b85-812a-4353-a253-a196becd7617
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453651658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error
s.2453651658
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.242210350
Short name T398
Test name
Test status
Simulation time 43565570988 ps
CPU time 16 seconds
Started Jan 10 12:55:56 PM PST 24
Finished Jan 10 12:57:21 PM PST 24
Peak memory 201172 kb
Host smart-7986877d-470f-40b5-9042-ee9ceed0ef23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242210350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_tl_intg_err.242210350
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2033117953
Short name T902
Test name
Test status
Simulation time 2032009474 ps
CPU time 1.87 seconds
Started Jan 10 12:56:28 PM PST 24
Finished Jan 10 12:57:39 PM PST 24
Peak memory 200536 kb
Host smart-2155f728-cebb-46b8-bec8-5b056b11544f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033117953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te
st.2033117953
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1613705663
Short name T901
Test name
Test status
Simulation time 2031850032 ps
CPU time 2.18 seconds
Started Jan 10 12:56:20 PM PST 24
Finished Jan 10 12:57:33 PM PST 24
Peak memory 200552 kb
Host smart-8db48592-a03e-4fce-9cbb-5969942518da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613705663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1613705663
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1765128859
Short name T345
Test name
Test status
Simulation time 2076009476 ps
CPU time 1.06 seconds
Started Jan 10 12:56:23 PM PST 24
Finished Jan 10 12:57:35 PM PST 24
Peak memory 200700 kb
Host smart-dbbf357c-3f3c-4d15-ad7d-40e2219a892b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765128859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.1765128859
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3732331947
Short name T23
Test name
Test status
Simulation time 2016792404 ps
CPU time 5.54 seconds
Started Jan 10 12:56:23 PM PST 24
Finished Jan 10 12:57:39 PM PST 24
Peak memory 200580 kb
Host smart-1b60220b-c6cf-48c9-b298-5e2959ee6447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732331947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te
st.3732331947
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.2072815688
Short name T384
Test name
Test status
Simulation time 2016365576 ps
CPU time 5.59 seconds
Started Jan 10 12:56:25 PM PST 24
Finished Jan 10 12:57:41 PM PST 24
Peak memory 200668 kb
Host smart-df70f664-1aa8-4bbc-872f-545fb39b8840
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072815688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te
st.2072815688
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2701528547
Short name T395
Test name
Test status
Simulation time 2014646459 ps
CPU time 5.99 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:40 PM PST 24
Peak memory 200736 kb
Host smart-d7ce7e0c-2c91-4a19-974b-d8b148fdedaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701528547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.2701528547
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2645983316
Short name T894
Test name
Test status
Simulation time 2012217294 ps
CPU time 5.08 seconds
Started Jan 10 12:56:26 PM PST 24
Finished Jan 10 12:57:41 PM PST 24
Peak memory 200544 kb
Host smart-32942193-2d57-4ad6-af7f-03267964709f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645983316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.2645983316
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.819426559
Short name T889
Test name
Test status
Simulation time 2009884824 ps
CPU time 6.07 seconds
Started Jan 10 12:56:29 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 200564 kb
Host smart-e32574b1-f1f3-4e8a-a3d8-b19ec2a2dfc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819426559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_tes
t.819426559
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.96103909
Short name T362
Test name
Test status
Simulation time 2040659528 ps
CPU time 1.71 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:35 PM PST 24
Peak memory 200600 kb
Host smart-3a304fae-0445-4d04-ab8b-1e7930346143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96103909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test
.96103909
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.3343820479
Short name T887
Test name
Test status
Simulation time 2056665795 ps
CPU time 1.71 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 200624 kb
Host smart-6ea46cc4-594c-4e58-8d27-50ba777b37a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343820479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_te
st.3343820479
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.417923
Short name T389
Test name
Test status
Simulation time 2511655746 ps
CPU time 9.38 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:16 PM PST 24
Peak memory 201200 kb
Host smart-8d6f3e0d-7f35-4dd5-9ad1-62dc7502351f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr
_aliasing.417923
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.727159657
Short name T879
Test name
Test status
Simulation time 75164038071 ps
CPU time 57.41 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:58:05 PM PST 24
Peak memory 201108 kb
Host smart-7f491e04-29e1-4935-9ce1-713fa53235a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727159657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_bit_bash.727159657
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3861624381
Short name T890
Test name
Test status
Simulation time 4032927245 ps
CPU time 11.5 seconds
Started Jan 10 12:55:59 PM PST 24
Finished Jan 10 12:57:21 PM PST 24
Peak memory 200936 kb
Host smart-436f1d01-b6d3-4841-a106-7a8e534bac43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861624381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.3861624381
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3862767961
Short name T903
Test name
Test status
Simulation time 2194756043 ps
CPU time 2.04 seconds
Started Jan 10 12:56:02 PM PST 24
Finished Jan 10 12:57:15 PM PST 24
Peak memory 209340 kb
Host smart-9eb84015-bd5a-403b-a22f-0275418e3c26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862767961 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3862767961
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2504623134
Short name T300
Test name
Test status
Simulation time 2077700316 ps
CPU time 3.39 seconds
Started Jan 10 12:55:59 PM PST 24
Finished Jan 10 12:57:14 PM PST 24
Peak memory 200236 kb
Host smart-7e2b8d8d-084b-4484-8df0-db9750caa552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504623134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.2504623134
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.631345024
Short name T6
Test name
Test status
Simulation time 2013405811 ps
CPU time 6.05 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:14 PM PST 24
Peak memory 200596 kb
Host smart-cedbf80f-2913-4b07-a651-bc51d807121a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631345024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test
.631345024
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.302882351
Short name T886
Test name
Test status
Simulation time 11077843598 ps
CPU time 10.28 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:19 PM PST 24
Peak memory 201180 kb
Host smart-79d922fd-ba92-4fcd-80f1-61c72b6e0a0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302882351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
sysrst_ctrl_same_csr_outstanding.302882351
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.1882623811
Short name T896
Test name
Test status
Simulation time 2194865807 ps
CPU time 2.64 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:11 PM PST 24
Peak memory 201168 kb
Host smart-ac53e854-75a6-4afa-b144-9f567323ca30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882623811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.1882623811
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.692545483
Short name T278
Test name
Test status
Simulation time 22238133262 ps
CPU time 16.84 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:26 PM PST 24
Peak memory 201176 kb
Host smart-5f1a32ee-6c05-4fa3-abc7-6eed196c5fc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692545483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_tl_intg_err.692545483
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1579195947
Short name T360
Test name
Test status
Simulation time 2014695279 ps
CPU time 4.68 seconds
Started Jan 10 12:56:32 PM PST 24
Finished Jan 10 12:57:46 PM PST 24
Peak memory 200676 kb
Host smart-575a170f-5e58-4a5c-857d-c2912abfd614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579195947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.1579195947
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3496776646
Short name T377
Test name
Test status
Simulation time 2027916587 ps
CPU time 2.06 seconds
Started Jan 10 12:56:27 PM PST 24
Finished Jan 10 12:57:39 PM PST 24
Peak memory 200688 kb
Host smart-b2e6762e-e682-4dbd-92ee-42625bdc8b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496776646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.3496776646
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3128539942
Short name T367
Test name
Test status
Simulation time 2009990534 ps
CPU time 5.94 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:38 PM PST 24
Peak memory 200508 kb
Host smart-5af605f6-c9f7-4f6c-bbca-374e0091a6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128539942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3128539942
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2932717917
Short name T866
Test name
Test status
Simulation time 2040180134 ps
CPU time 1.9 seconds
Started Jan 10 12:56:23 PM PST 24
Finished Jan 10 12:57:35 PM PST 24
Peak memory 200504 kb
Host smart-4b0fa5e1-6d05-4e25-924e-22a673043300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932717917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.2932717917
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.2598172380
Short name T870
Test name
Test status
Simulation time 2041229987 ps
CPU time 1.85 seconds
Started Jan 10 12:56:28 PM PST 24
Finished Jan 10 12:57:39 PM PST 24
Peak memory 200660 kb
Host smart-fed2df2e-902a-4a57-8e91-596c1fd1b627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598172380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.2598172380
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2220162669
Short name T293
Test name
Test status
Simulation time 2031440917 ps
CPU time 2.02 seconds
Started Jan 10 12:56:23 PM PST 24
Finished Jan 10 12:57:36 PM PST 24
Peak memory 200520 kb
Host smart-63bb0070-9206-4a42-ae42-664925663712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220162669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2220162669
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1932371922
Short name T358
Test name
Test status
Simulation time 2106357425 ps
CPU time 1.16 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:36 PM PST 24
Peak memory 200640 kb
Host smart-a2661554-7dba-4a22-bb94-aded61ff0e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932371922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1932371922
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3162914662
Short name T40
Test name
Test status
Simulation time 2012263293 ps
CPU time 5.71 seconds
Started Jan 10 12:56:29 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 200636 kb
Host smart-cb864535-2774-4bb6-a883-c41943111a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162914662 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te
st.3162914662
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.828663626
Short name T359
Test name
Test status
Simulation time 2011333113 ps
CPU time 6.01 seconds
Started Jan 10 12:56:25 PM PST 24
Finished Jan 10 12:57:41 PM PST 24
Peak memory 200548 kb
Host smart-e142dd17-8443-4991-aca3-82d07136102c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828663626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.828663626
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.401425318
Short name T900
Test name
Test status
Simulation time 2039561276 ps
CPU time 1.85 seconds
Started Jan 10 12:56:22 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 200652 kb
Host smart-c8adc955-f961-427c-9ed8-1bd74d85c4e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401425318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_tes
t.401425318
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.4198806507
Short name T871
Test name
Test status
Simulation time 2778685885 ps
CPU time 3.91 seconds
Started Jan 10 12:56:03 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 201144 kb
Host smart-5d242b35-81c3-4a50-b855-9a5b0f94ef31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198806507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.4198806507
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2924734650
Short name T295
Test name
Test status
Simulation time 3522477154 ps
CPU time 6.46 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:12 PM PST 24
Peak memory 201220 kb
Host smart-9706e958-e6ce-4bd6-9b5e-a413569c0e7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924734650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2924734650
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.386613626
Short name T875
Test name
Test status
Simulation time 6107622546 ps
CPU time 3.91 seconds
Started Jan 10 12:56:06 PM PST 24
Finished Jan 10 12:57:20 PM PST 24
Peak memory 201012 kb
Host smart-82340603-dddc-4b72-a032-ba2c6f206799
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386613626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_
csr_hw_reset.386613626
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.410623334
Short name T283
Test name
Test status
Simulation time 2086973686 ps
CPU time 6.35 seconds
Started Jan 10 12:56:15 PM PST 24
Finished Jan 10 12:57:33 PM PST 24
Peak memory 201024 kb
Host smart-c241bfcd-0ad0-45ac-ab4b-88c2a379bbf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410623334 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.410623334
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2990851625
Short name T8
Test name
Test status
Simulation time 2038001519 ps
CPU time 6.02 seconds
Started Jan 10 12:55:55 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 200908 kb
Host smart-e84d94a0-dffa-4a61-91fc-1e615fe73993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990851625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2990851625
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4244390359
Short name T357
Test name
Test status
Simulation time 2012719779 ps
CPU time 5.84 seconds
Started Jan 10 12:56:01 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 200580 kb
Host smart-79243307-e1a8-4541-b08a-9eb71102423d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244390359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.4244390359
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.461045974
Short name T895
Test name
Test status
Simulation time 5851419794 ps
CPU time 21.01 seconds
Started Jan 10 12:56:17 PM PST 24
Finished Jan 10 12:57:50 PM PST 24
Peak memory 201068 kb
Host smart-8f12965d-6287-4d7f-b8ca-07f20e9702c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461045974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
sysrst_ctrl_same_csr_outstanding.461045974
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2574758159
Short name T390
Test name
Test status
Simulation time 2115199661 ps
CPU time 4.22 seconds
Started Jan 10 12:56:01 PM PST 24
Finished Jan 10 12:57:17 PM PST 24
Peak memory 201080 kb
Host smart-06b1f414-f3a1-426e-b907-551745bd7285
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574758159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error
s.2574758159
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.694613122
Short name T872
Test name
Test status
Simulation time 22529939816 ps
CPU time 15.23 seconds
Started Jan 10 12:56:00 PM PST 24
Finished Jan 10 12:57:27 PM PST 24
Peak memory 201176 kb
Host smart-1404c887-50e9-48b2-8884-c7d81a0b5525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694613122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_tl_intg_err.694613122
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.3493457280
Short name T375
Test name
Test status
Simulation time 2039985916 ps
CPU time 1.85 seconds
Started Jan 10 12:56:31 PM PST 24
Finished Jan 10 12:57:42 PM PST 24
Peak memory 200552 kb
Host smart-ab0ea6b4-072e-4ee8-bdd8-7b94f6e07ac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493457280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te
st.3493457280
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.138118893
Short name T858
Test name
Test status
Simulation time 2015093725 ps
CPU time 3.64 seconds
Started Jan 10 12:56:28 PM PST 24
Finished Jan 10 12:57:41 PM PST 24
Peak memory 200644 kb
Host smart-29673079-12ff-49dd-b868-d0226291da5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138118893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_tes
t.138118893
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3084362549
Short name T867
Test name
Test status
Simulation time 2010062736 ps
CPU time 5.9 seconds
Started Jan 10 12:56:23 PM PST 24
Finished Jan 10 12:57:39 PM PST 24
Peak memory 200608 kb
Host smart-eec6d290-86cc-4c7c-b7a4-aa1fa79a9a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084362549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.3084362549
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.701918489
Short name T366
Test name
Test status
Simulation time 2058659578 ps
CPU time 1.39 seconds
Started Jan 10 12:56:27 PM PST 24
Finished Jan 10 12:57:37 PM PST 24
Peak memory 200584 kb
Host smart-332ccc35-704c-4540-8c01-08bea12c74a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701918489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_tes
t.701918489
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3563649904
Short name T363
Test name
Test status
Simulation time 2018795820 ps
CPU time 3.28 seconds
Started Jan 10 12:56:25 PM PST 24
Finished Jan 10 12:57:38 PM PST 24
Peak memory 200640 kb
Host smart-84023c5c-1e38-4268-a5fa-3225ba17ee81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563649904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.3563649904
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3135288789
Short name T372
Test name
Test status
Simulation time 2017207318 ps
CPU time 3.29 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:37 PM PST 24
Peak memory 200536 kb
Host smart-1abfbcbc-e2d2-485a-aab5-ef30d6f5156b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135288789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.3135288789
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.1706963892
Short name T852
Test name
Test status
Simulation time 2021159663 ps
CPU time 3.18 seconds
Started Jan 10 12:56:28 PM PST 24
Finished Jan 10 12:57:41 PM PST 24
Peak memory 200536 kb
Host smart-2059931d-b338-4239-b5b4-42ecc9de62d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706963892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_te
st.1706963892
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.987650225
Short name T291
Test name
Test status
Simulation time 2049506613 ps
CPU time 1.93 seconds
Started Jan 10 12:56:21 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 200592 kb
Host smart-fa8787be-bd72-4bc5-93ae-0b35d9a0f748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987650225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes
t.987650225
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2200264137
Short name T391
Test name
Test status
Simulation time 2044039555 ps
CPU time 1.94 seconds
Started Jan 10 12:56:26 PM PST 24
Finished Jan 10 12:57:38 PM PST 24
Peak memory 200592 kb
Host smart-812c4548-6e6d-46ac-a094-70fea43730e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200264137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te
st.2200264137
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3877194067
Short name T850
Test name
Test status
Simulation time 2112915320 ps
CPU time 2.28 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 200868 kb
Host smart-946d584e-7ca3-4651-b4d2-3f31216568ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877194067 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.3877194067
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3830492875
Short name T5
Test name
Test status
Simulation time 2094753926 ps
CPU time 1.81 seconds
Started Jan 10 12:55:59 PM PST 24
Finished Jan 10 12:57:11 PM PST 24
Peak memory 200856 kb
Host smart-67ab2d9a-d91c-4772-a28c-90ed8c13bcac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830492875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3830492875
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3809598584
Short name T878
Test name
Test status
Simulation time 2048709583 ps
CPU time 1.9 seconds
Started Jan 10 12:56:00 PM PST 24
Finished Jan 10 12:57:13 PM PST 24
Peak memory 200696 kb
Host smart-0fa0a666-786b-45a6-bbd3-acb2c8611411
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809598584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.3809598584
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3437677249
Short name T899
Test name
Test status
Simulation time 5123663793 ps
CPU time 4.15 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:10 PM PST 24
Peak memory 201088 kb
Host smart-7e818f0e-9027-4379-887c-8e01fb0fee0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437677249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_same_csr_outstanding.3437677249
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3740185683
Short name T892
Test name
Test status
Simulation time 2050480378 ps
CPU time 4.47 seconds
Started Jan 10 12:56:18 PM PST 24
Finished Jan 10 12:57:34 PM PST 24
Peak memory 209288 kb
Host smart-a496c3fa-794c-4789-9a5c-2b9291b9d118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740185683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_error
s.3740185683
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.1770082032
Short name T321
Test name
Test status
Simulation time 42371592525 ps
CPU time 104.93 seconds
Started Jan 10 12:56:01 PM PST 24
Finished Jan 10 12:58:57 PM PST 24
Peak memory 201136 kb
Host smart-28c388a2-d704-4c82-98f0-9c99813e693a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770082032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.1770082032
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3498696601
Short name T851
Test name
Test status
Simulation time 2249308047 ps
CPU time 1.38 seconds
Started Jan 10 12:55:59 PM PST 24
Finished Jan 10 12:57:12 PM PST 24
Peak memory 200288 kb
Host smart-1065f189-18ca-4c98-8d56-7b7397b1a6f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498696601 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3498696601
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3173010309
Short name T898
Test name
Test status
Simulation time 2159122185 ps
CPU time 1.29 seconds
Started Jan 10 12:56:00 PM PST 24
Finished Jan 10 12:57:13 PM PST 24
Peak memory 201032 kb
Host smart-89a5b9fc-4d3c-4b0d-9050-093c9b77550d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173010309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r
w.3173010309
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1488158404
Short name T392
Test name
Test status
Simulation time 2012038067 ps
CPU time 5.59 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:13 PM PST 24
Peak memory 200564 kb
Host smart-940d8fae-71e0-4b06-bec2-a1ec647104f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488158404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.1488158404
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.2676540268
Short name T404
Test name
Test status
Simulation time 5151823905 ps
CPU time 7.71 seconds
Started Jan 10 12:56:09 PM PST 24
Finished Jan 10 12:57:26 PM PST 24
Peak memory 201236 kb
Host smart-60b059fa-e961-4ed4-9f42-8c30515b1b8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676540268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.2676540268
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1828057477
Short name T281
Test name
Test status
Simulation time 2065611002 ps
CPU time 4.65 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:57:13 PM PST 24
Peak memory 201056 kb
Host smart-d9d1d79b-7083-43a1-bf5d-b4e5f2cff497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828057477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error
s.1828057477
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.587585368
Short name T364
Test name
Test status
Simulation time 22270413927 ps
CPU time 28.08 seconds
Started Jan 10 12:56:17 PM PST 24
Finished Jan 10 12:57:56 PM PST 24
Peak memory 201172 kb
Host smart-75cff662-4f86-4146-b5e4-3db402d17ffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587585368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_tl_intg_err.587585368
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.96184052
Short name T401
Test name
Test status
Simulation time 2170004123 ps
CPU time 2.76 seconds
Started Jan 10 12:56:16 PM PST 24
Finished Jan 10 12:57:30 PM PST 24
Peak memory 201204 kb
Host smart-eeda016b-64f0-457a-a2d9-ad603dd3ea12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96184052 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.96184052
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.21261774
Short name T883
Test name
Test status
Simulation time 2052292626 ps
CPU time 1.28 seconds
Started Jan 10 12:55:57 PM PST 24
Finished Jan 10 12:57:08 PM PST 24
Peak memory 200620 kb
Host smart-f16d23e9-509b-4938-8d50-665e1df2ad15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21261774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.21261774
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1872958898
Short name T373
Test name
Test status
Simulation time 5995150951 ps
CPU time 15.61 seconds
Started Jan 10 12:56:19 PM PST 24
Finished Jan 10 12:57:46 PM PST 24
Peak memory 201160 kb
Host smart-90836ae8-0f13-42da-9bad-d4cd897d1356
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872958898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.1872958898
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3082535308
Short name T877
Test name
Test status
Simulation time 2089798193 ps
CPU time 7.08 seconds
Started Jan 10 12:56:00 PM PST 24
Finished Jan 10 12:57:18 PM PST 24
Peak memory 201008 kb
Host smart-536fd0cc-aa88-4bc6-8bbc-23d2da53a4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082535308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error
s.3082535308
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1905670377
Short name T280
Test name
Test status
Simulation time 42407736149 ps
CPU time 59.98 seconds
Started Jan 10 12:55:58 PM PST 24
Finished Jan 10 12:58:09 PM PST 24
Peak memory 201208 kb
Host smart-a982578b-f95d-4994-8299-716fa911852a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905670377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.1905670377
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2057876200
Short name T863
Test name
Test status
Simulation time 2044049497 ps
CPU time 6.02 seconds
Started Jan 10 12:56:10 PM PST 24
Finished Jan 10 12:57:26 PM PST 24
Peak memory 201004 kb
Host smart-4c1fba74-77e3-43fe-a02e-3b0cc6c01117
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057876200 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2057876200
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.468531556
Short name T294
Test name
Test status
Simulation time 2062738961 ps
CPU time 2.17 seconds
Started Jan 10 12:56:04 PM PST 24
Finished Jan 10 12:57:16 PM PST 24
Peak memory 200872 kb
Host smart-3bd4a817-fdd5-4ab7-911e-1470e18c21a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468531556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw
.468531556
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3336111148
Short name T853
Test name
Test status
Simulation time 2047433126 ps
CPU time 1.83 seconds
Started Jan 10 12:56:06 PM PST 24
Finished Jan 10 12:57:18 PM PST 24
Peak memory 200504 kb
Host smart-700b9efa-2bd2-4c5a-8731-6d63d0e82150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336111148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.3336111148
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3027638418
Short name T885
Test name
Test status
Simulation time 10231071478 ps
CPU time 10.79 seconds
Started Jan 10 12:56:10 PM PST 24
Finished Jan 10 12:57:31 PM PST 24
Peak memory 201156 kb
Host smart-7d00675e-7a95-48e9-994c-a6ee7aea4e5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027638418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.3027638418
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3790580719
Short name T279
Test name
Test status
Simulation time 2114750517 ps
CPU time 2.09 seconds
Started Jan 10 12:56:00 PM PST 24
Finished Jan 10 12:57:13 PM PST 24
Peak memory 201060 kb
Host smart-2dcce837-0ea4-470d-a573-0cda08b2bd6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790580719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.3790580719
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1761353347
Short name T322
Test name
Test status
Simulation time 22184195118 ps
CPU time 60.2 seconds
Started Jan 10 12:56:07 PM PST 24
Finished Jan 10 12:58:17 PM PST 24
Peak memory 201148 kb
Host smart-a6648330-45eb-41c1-ba0c-2c3ecc58c113
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761353347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1761353347
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2730172181
Short name T292
Test name
Test status
Simulation time 2043823443 ps
CPU time 3.49 seconds
Started Jan 10 12:56:25 PM PST 24
Finished Jan 10 12:57:39 PM PST 24
Peak memory 200988 kb
Host smart-0c2bc1c4-9e01-4520-9e26-c4a03bf4adea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730172181 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.2730172181
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3048782817
Short name T857
Test name
Test status
Simulation time 2071329530 ps
CPU time 1.91 seconds
Started Jan 10 12:56:18 PM PST 24
Finished Jan 10 12:57:31 PM PST 24
Peak memory 200924 kb
Host smart-a4681a38-ebc6-4b4b-9cd4-1366ba709b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048782817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3048782817
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.2831512486
Short name T344
Test name
Test status
Simulation time 2024485521 ps
CPU time 2.35 seconds
Started Jan 10 12:56:24 PM PST 24
Finished Jan 10 12:57:37 PM PST 24
Peak memory 200580 kb
Host smart-fbc47c85-93de-43fd-927b-80182cd066ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831512486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes
t.2831512486
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.4184133471
Short name T365
Test name
Test status
Simulation time 7743122720 ps
CPU time 33.92 seconds
Started Jan 10 12:56:03 PM PST 24
Finished Jan 10 12:57:47 PM PST 24
Peak memory 201192 kb
Host smart-602a345b-c9d1-49f2-ad09-7f91a11e965d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184133471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9
.sysrst_ctrl_same_csr_outstanding.4184133471
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4000158459
Short name T893
Test name
Test status
Simulation time 2187905156 ps
CPU time 5.51 seconds
Started Jan 10 12:56:15 PM PST 24
Finished Jan 10 12:57:32 PM PST 24
Peak memory 201140 kb
Host smart-1a0fab4d-6408-4396-9ec7-3759a29ba2b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000158459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.4000158459
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1783211833
Short name T385
Test name
Test status
Simulation time 42561133858 ps
CPU time 55.03 seconds
Started Jan 10 12:56:25 PM PST 24
Finished Jan 10 12:58:30 PM PST 24
Peak memory 201232 kb
Host smart-f3d7cbab-d882-4c18-ad35-7100fba22919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783211833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.1783211833
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.681159836
Short name T506
Test name
Test status
Simulation time 2031449177 ps
CPU time 1.87 seconds
Started Jan 10 12:30:24 PM PST 24
Finished Jan 10 12:31:07 PM PST 24
Peak memory 201220 kb
Host smart-f49e86ae-c8c7-4d68-91f0-fd2268e1559d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681159836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test
.681159836
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.1569477117
Short name T591
Test name
Test status
Simulation time 3951740144 ps
CPU time 3.23 seconds
Started Jan 10 12:30:03 PM PST 24
Finished Jan 10 12:30:47 PM PST 24
Peak memory 201308 kb
Host smart-611c32b6-c503-419c-9157-d348241a5cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569477117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.1569477117
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3260494134
Short name T305
Test name
Test status
Simulation time 146317279723 ps
CPU time 177.14 seconds
Started Jan 10 12:30:14 PM PST 24
Finished Jan 10 12:33:51 PM PST 24
Peak memory 201580 kb
Host smart-a3b8bbf1-27b7-439b-b738-1c9d4034e57c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260494134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_combo_detect.3260494134
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3806236479
Short name T806
Test name
Test status
Simulation time 2214354253 ps
CPU time 5.41 seconds
Started Jan 10 12:30:28 PM PST 24
Finished Jan 10 12:31:15 PM PST 24
Peak memory 201624 kb
Host smart-97a93842-6f2a-44c2-8d34-cbc5e0b22526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806236479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.3806236479
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.379110830
Short name T577
Test name
Test status
Simulation time 2567533046 ps
CPU time 1.71 seconds
Started Jan 10 12:30:09 PM PST 24
Finished Jan 10 12:30:51 PM PST 24
Peak memory 201248 kb
Host smart-e5cb7410-ce6d-4eb5-8cbf-cff5cc4eb7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379110830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.379110830
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2274374206
Short name T696
Test name
Test status
Simulation time 3061107465 ps
CPU time 2.54 seconds
Started Jan 10 12:30:17 PM PST 24
Finished Jan 10 12:30:59 PM PST 24
Peak memory 201276 kb
Host smart-0a18da7c-7c4e-488d-8dc2-2cb38301276e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274374206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ec_pwr_on_rst.2274374206
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1709800744
Short name T757
Test name
Test status
Simulation time 4410709261 ps
CPU time 10.44 seconds
Started Jan 10 12:30:10 PM PST 24
Finished Jan 10 12:31:01 PM PST 24
Peak memory 201284 kb
Host smart-4239dbe5-7997-4d8f-ac33-0c570c85cd82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709800744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1709800744
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.595791693
Short name T789
Test name
Test status
Simulation time 2754264345 ps
CPU time 1.06 seconds
Started Jan 10 12:30:13 PM PST 24
Finished Jan 10 12:30:54 PM PST 24
Peak memory 201324 kb
Host smart-04c5c0b9-2493-461a-a085-703d645ab639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595791693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.595791693
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1713388010
Short name T505
Test name
Test status
Simulation time 2490376768 ps
CPU time 2.26 seconds
Started Jan 10 12:30:31 PM PST 24
Finished Jan 10 12:31:16 PM PST 24
Peak memory 201244 kb
Host smart-03016777-b142-4520-bb46-770c2abc0cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713388010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1713388010
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.3926775493
Short name T26
Test name
Test status
Simulation time 2240572602 ps
CPU time 4.19 seconds
Started Jan 10 12:30:38 PM PST 24
Finished Jan 10 12:31:25 PM PST 24
Peak memory 201308 kb
Host smart-f94aa698-6270-4d86-b770-e315b4e82a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926775493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.3926775493
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3301609654
Short name T448
Test name
Test status
Simulation time 2511660947 ps
CPU time 7.09 seconds
Started Jan 10 12:30:15 PM PST 24
Finished Jan 10 12:31:01 PM PST 24
Peak memory 201292 kb
Host smart-574c547c-993d-4732-bc6a-a9ab4a031164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301609654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3301609654
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3803961540
Short name T286
Test name
Test status
Simulation time 22014390025 ps
CPU time 60.6 seconds
Started Jan 10 12:30:28 PM PST 24
Finished Jan 10 12:32:10 PM PST 24
Peak memory 221032 kb
Host smart-766cdd6b-2724-4d1e-9d37-8bcd2b283a02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803961540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3803961540
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.1935680550
Short name T155
Test name
Test status
Simulation time 2119752360 ps
CPU time 3.37 seconds
Started Jan 10 12:30:02 PM PST 24
Finished Jan 10 12:30:47 PM PST 24
Peak memory 201220 kb
Host smart-d470b22b-d603-4921-b6a9-b47e9aad6800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935680550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.1935680550
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.1430236660
Short name T834
Test name
Test status
Simulation time 13661708803 ps
CPU time 28.96 seconds
Started Jan 10 12:30:20 PM PST 24
Finished Jan 10 12:31:28 PM PST 24
Peak memory 201272 kb
Host smart-d0e2f213-ad38-4c42-9506-b6100b4a57d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430236660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.1430236660
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.2781342118
Short name T214
Test name
Test status
Simulation time 2024879141 ps
CPU time 1.9 seconds
Started Jan 10 12:30:26 PM PST 24
Finished Jan 10 12:31:09 PM PST 24
Peak memory 201176 kb
Host smart-05b40a76-70bf-4306-944d-cb5858551c89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781342118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_tes
t.2781342118
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1524222948
Short name T707
Test name
Test status
Simulation time 3269215856 ps
CPU time 9 seconds
Started Jan 10 12:30:36 PM PST 24
Finished Jan 10 12:31:28 PM PST 24
Peak memory 201252 kb
Host smart-d7813980-52dc-4f6f-b0dc-920b84821daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524222948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1524222948
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.43725948
Short name T257
Test name
Test status
Simulation time 102630054927 ps
CPU time 61.69 seconds
Started Jan 10 12:30:18 PM PST 24
Finished Jan 10 12:31:58 PM PST 24
Peak memory 201444 kb
Host smart-b03a753f-d5d5-4004-8da3-68178aabd648
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43725948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_combo_detect.43725948
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2636423166
Short name T488
Test name
Test status
Simulation time 2181136092 ps
CPU time 6.45 seconds
Started Jan 10 12:30:30 PM PST 24
Finished Jan 10 12:31:18 PM PST 24
Peak memory 201276 kb
Host smart-3beb742f-e7e5-4e44-b42e-ee0eeb57c386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636423166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2636423166
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.448400098
Short name T154
Test name
Test status
Simulation time 2306170589 ps
CPU time 3.58 seconds
Started Jan 10 12:30:38 PM PST 24
Finished Jan 10 12:31:25 PM PST 24
Peak memory 201352 kb
Host smart-427de134-fd9b-4401-b0fa-52a3e9bf2d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448400098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.448400098
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.100071225
Short name T325
Test name
Test status
Simulation time 110911365490 ps
CPU time 69.96 seconds
Started Jan 10 12:30:24 PM PST 24
Finished Jan 10 12:32:15 PM PST 24
Peak memory 201572 kb
Host smart-8bfca51c-4d2a-4fc4-b960-1b93c7262418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100071225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wit
h_pre_cond.100071225
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.4138835566
Short name T755
Test name
Test status
Simulation time 2910716332 ps
CPU time 8.5 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:31:07 PM PST 24
Peak memory 201232 kb
Host smart-8cd1ed08-15f4-4c00-801c-0dc1fc74749b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138835566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.4138835566
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.4005159111
Short name T189
Test name
Test status
Simulation time 3861612494 ps
CPU time 1.26 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:13 PM PST 24
Peak memory 201188 kb
Host smart-2ba0d0d6-96f1-4c1d-bdad-8856a1452257
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005159111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.4005159111
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2423687656
Short name T514
Test name
Test status
Simulation time 2635139445 ps
CPU time 2.48 seconds
Started Jan 10 12:30:24 PM PST 24
Finished Jan 10 12:31:08 PM PST 24
Peak memory 201220 kb
Host smart-c9d34907-9997-4341-971f-862d66a06dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423687656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2423687656
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.3545848473
Short name T844
Test name
Test status
Simulation time 2467256139 ps
CPU time 7.34 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:17 PM PST 24
Peak memory 201204 kb
Host smart-cad9f4ec-30e2-4a94-bf29-6a18814d8189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545848473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3545848473
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.3879707190
Short name T125
Test name
Test status
Simulation time 2163162405 ps
CPU time 1.94 seconds
Started Jan 10 12:30:10 PM PST 24
Finished Jan 10 12:30:53 PM PST 24
Peak memory 201348 kb
Host smart-c60e5a32-caca-496a-99ff-fcd394cd7c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879707190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3879707190
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1395588944
Short name T661
Test name
Test status
Simulation time 2523378795 ps
CPU time 2.4 seconds
Started Jan 10 12:30:20 PM PST 24
Finished Jan 10 12:31:02 PM PST 24
Peak memory 201236 kb
Host smart-b3535615-9c6d-48f2-a376-cae7ae3f86df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395588944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1395588944
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.1269880394
Short name T212
Test name
Test status
Simulation time 22097320364 ps
CPU time 13.98 seconds
Started Jan 10 12:30:22 PM PST 24
Finished Jan 10 12:31:17 PM PST 24
Peak memory 220908 kb
Host smart-dec23139-1905-4664-a8f7-0f172ab66b18
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269880394 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.1269880394
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.892983673
Short name T407
Test name
Test status
Simulation time 2108299970 ps
CPU time 6.33 seconds
Started Jan 10 12:30:35 PM PST 24
Finished Jan 10 12:31:23 PM PST 24
Peak memory 201300 kb
Host smart-b33f01b1-b1b6-45b3-92c9-fbd0d10f704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892983673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.892983673
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.2914653469
Short name T219
Test name
Test status
Simulation time 97491296667 ps
CPU time 240.42 seconds
Started Jan 10 12:30:30 PM PST 24
Finished Jan 10 12:35:12 PM PST 24
Peak memory 201612 kb
Host smart-ef5f2776-343c-4416-9bbb-ddfc0504256d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914653469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.2914653469
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3211843492
Short name T209
Test name
Test status
Simulation time 23495362386 ps
CPU time 56.55 seconds
Started Jan 10 12:30:31 PM PST 24
Finished Jan 10 12:32:10 PM PST 24
Peak memory 209948 kb
Host smart-bacc2b87-aed2-473e-827e-77ffcd96de20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211843492 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3211843492
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.1889196814
Short name T133
Test name
Test status
Simulation time 4552235748 ps
CPU time 2.1 seconds
Started Jan 10 12:30:23 PM PST 24
Finished Jan 10 12:31:06 PM PST 24
Peak memory 201224 kb
Host smart-2b5c4079-2cfb-47ce-af80-fb0fd2c0ac5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889196814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.1889196814
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.1741331479
Short name T580
Test name
Test status
Simulation time 2019511152 ps
CPU time 3.07 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:36 PM PST 24
Peak memory 201212 kb
Host smart-c388e411-4c10-42e2-9dd7-cbe56a00b9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741331479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.1741331479
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3635254503
Short name T571
Test name
Test status
Simulation time 4092866037 ps
CPU time 3.4 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 201332 kb
Host smart-452366aa-f7ae-4a22-83cf-c51fe79d4eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635254503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3
635254503
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.681201488
Short name T254
Test name
Test status
Simulation time 107206920424 ps
CPU time 77.14 seconds
Started Jan 10 12:31:04 PM PST 24
Finished Jan 10 12:33:08 PM PST 24
Peak memory 201544 kb
Host smart-cc74373d-0d1d-4df1-9523-eea722a47066
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681201488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_combo_detect.681201488
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3825746798
Short name T102
Test name
Test status
Simulation time 32104220140 ps
CPU time 85.88 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:34:07 PM PST 24
Peak memory 199844 kb
Host smart-799abce8-4e41-4cc1-a078-40cb8a4e79be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825746798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.3825746798
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.712478171
Short name T713
Test name
Test status
Simulation time 5437463789 ps
CPU time 15.25 seconds
Started Jan 10 12:30:46 PM PST 24
Finished Jan 10 12:31:46 PM PST 24
Peak memory 201272 kb
Host smart-e4cfcb61-a5ae-43ff-8203-c877c48822f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712478171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ec_pwr_on_rst.712478171
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1625537598
Short name T172
Test name
Test status
Simulation time 4333808070 ps
CPU time 2.87 seconds
Started Jan 10 12:31:00 PM PST 24
Finished Jan 10 12:31:51 PM PST 24
Peak memory 201332 kb
Host smart-f08f32c1-d7a1-4ebf-9241-abad9ed421b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625537598 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.1625537598
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.247888029
Short name T474
Test name
Test status
Simulation time 2614197448 ps
CPU time 7.12 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:33:01 PM PST 24
Peak memory 200944 kb
Host smart-fd6bfb11-b9c4-4963-8e5e-32ee6e360df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247888029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.247888029
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1198837938
Short name T801
Test name
Test status
Simulation time 2499477704 ps
CPU time 2.5 seconds
Started Jan 10 12:31:18 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 201220 kb
Host smart-b6d9e274-dd48-46e3-966e-9d7258685404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198837938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1198837938
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.2081009353
Short name T600
Test name
Test status
Simulation time 2094319283 ps
CPU time 1.29 seconds
Started Jan 10 12:30:40 PM PST 24
Finished Jan 10 12:31:24 PM PST 24
Peak memory 201328 kb
Host smart-04184298-3694-4386-8c41-b2733176d099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081009353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.2081009353
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.533435354
Short name T520
Test name
Test status
Simulation time 2514854307 ps
CPU time 7.72 seconds
Started Jan 10 12:30:56 PM PST 24
Finished Jan 10 12:31:51 PM PST 24
Peak memory 201236 kb
Host smart-ff9762a7-41d1-4758-9272-345f299592bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533435354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.533435354
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.621421538
Short name T608
Test name
Test status
Simulation time 2118006578 ps
CPU time 3.34 seconds
Started Jan 10 12:31:34 PM PST 24
Finished Jan 10 12:32:27 PM PST 24
Peak memory 201276 kb
Host smart-d668954f-c375-4edd-8998-d43c57450e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621421538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.621421538
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3394386964
Short name T559
Test name
Test status
Simulation time 21566591160 ps
CPU time 54.03 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:32:20 PM PST 24
Peak memory 201548 kb
Host smart-9f6b64f9-4116-45a2-829d-7440272dc3ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394386964 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.3394386964
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.910868096
Short name T560
Test name
Test status
Simulation time 8058862849 ps
CPU time 4.53 seconds
Started Jan 10 12:30:58 PM PST 24
Finished Jan 10 12:31:50 PM PST 24
Peak memory 201244 kb
Host smart-58969a1d-9dfe-4842-b83e-243a679ed613
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910868096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_ultra_low_pwr.910868096
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1693836943
Short name T547
Test name
Test status
Simulation time 2015304642 ps
CPU time 5.9 seconds
Started Jan 10 12:30:52 PM PST 24
Finished Jan 10 12:31:43 PM PST 24
Peak memory 201240 kb
Host smart-929d7cd1-5258-42a1-816e-3e0b4fabc016
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693836943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1693836943
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3715337648
Short name T693
Test name
Test status
Simulation time 3377626755 ps
CPU time 1.46 seconds
Started Jan 10 12:32:11 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 201040 kb
Host smart-e9231c12-591d-4be2-b87a-b20c632be1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715337648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.3
715337648
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2408651080
Short name T170
Test name
Test status
Simulation time 128887996835 ps
CPU time 91.32 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:34:12 PM PST 24
Peak memory 199524 kb
Host smart-3b5cad02-c061-4125-8e00-e4e3d7cf4142
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408651080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_combo_detect.2408651080
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.746150492
Short name T684
Test name
Test status
Simulation time 52546900575 ps
CPU time 68.85 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:33:04 PM PST 24
Peak memory 201504 kb
Host smart-c4d8c7af-9b12-4ffb-9e72-b8862807acf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746150492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_wi
th_pre_cond.746150492
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.1262058886
Short name T679
Test name
Test status
Simulation time 3674839791 ps
CPU time 10.42 seconds
Started Jan 10 12:30:39 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 201288 kb
Host smart-5b5f2268-bbac-47cd-a456-c2c92e038fbc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262058886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ec_pwr_on_rst.1262058886
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1176903789
Short name T52
Test name
Test status
Simulation time 273998995083 ps
CPU time 280.93 seconds
Started Jan 10 12:31:02 PM PST 24
Finished Jan 10 12:36:30 PM PST 24
Peak memory 201220 kb
Host smart-d74adf70-c785-480d-a98c-3598b1a7cc8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176903789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.1176903789
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3533191364
Short name T731
Test name
Test status
Simulation time 2627932737 ps
CPU time 2.43 seconds
Started Jan 10 12:32:09 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 200932 kb
Host smart-a9a7ea16-80dd-489d-8be8-4843093528b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533191364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.3533191364
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3470909010
Short name T65
Test name
Test status
Simulation time 2463914488 ps
CPU time 2.21 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 201244 kb
Host smart-640b081e-5695-45f0-b8f8-48d5e0c468fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470909010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.3470909010
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.331908319
Short name T597
Test name
Test status
Simulation time 2182801431 ps
CPU time 3.59 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:31:37 PM PST 24
Peak memory 201228 kb
Host smart-ec27b42a-9d15-447e-b8bf-9609cf4737f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331908319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.331908319
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.3794714651
Short name T121
Test name
Test status
Simulation time 2534476963 ps
CPU time 2.34 seconds
Started Jan 10 12:30:59 PM PST 24
Finished Jan 10 12:31:50 PM PST 24
Peak memory 201328 kb
Host smart-8422baf7-5d5c-42a3-893d-9af003f30469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794714651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.3794714651
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.805708195
Short name T747
Test name
Test status
Simulation time 2110165710 ps
CPU time 5.78 seconds
Started Jan 10 12:30:52 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201184 kb
Host smart-0003baf0-1a92-4ca4-9716-76587a64bf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805708195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.805708195
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.2675486308
Short name T701
Test name
Test status
Simulation time 6865888954 ps
CPU time 16.05 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:44 PM PST 24
Peak memory 201232 kb
Host smart-8926b919-34d3-4a16-a9b7-bbcf82b5022d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675486308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.2675486308
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1957687438
Short name T70
Test name
Test status
Simulation time 4499587240 ps
CPU time 1.46 seconds
Started Jan 10 12:30:58 PM PST 24
Finished Jan 10 12:31:47 PM PST 24
Peak memory 201224 kb
Host smart-94305f1a-08db-46ba-a031-46774713d064
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957687438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1957687438
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.3503060912
Short name T572
Test name
Test status
Simulation time 2015546607 ps
CPU time 5.39 seconds
Started Jan 10 12:31:07 PM PST 24
Finished Jan 10 12:31:59 PM PST 24
Peak memory 201268 kb
Host smart-76a41f62-4291-476d-af25-6492430b4541
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503060912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te
st.3503060912
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2952573169
Short name T469
Test name
Test status
Simulation time 3753723196 ps
CPU time 3.15 seconds
Started Jan 10 12:31:06 PM PST 24
Finished Jan 10 12:31:55 PM PST 24
Peak memory 201300 kb
Host smart-afecdd33-8834-4b28-9c6a-a87dd48bb22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952573169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.2
952573169
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.3360203037
Short name T255
Test name
Test status
Simulation time 83095409844 ps
CPU time 37.76 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:32:21 PM PST 24
Peak memory 201468 kb
Host smart-69accb14-2e61-4217-9d81-093f67e4c8b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360203037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.3360203037
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.257736359
Short name T313
Test name
Test status
Simulation time 82725240117 ps
CPU time 18.41 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:17 PM PST 24
Peak memory 201080 kb
Host smart-fe425130-b1b6-4e55-b7a6-921e5e93c93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257736359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_wi
th_pre_cond.257736359
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.544642164
Short name T582
Test name
Test status
Simulation time 3028157368 ps
CPU time 8.59 seconds
Started Jan 10 12:31:07 PM PST 24
Finished Jan 10 12:32:02 PM PST 24
Peak memory 201328 kb
Host smart-49d2279c-dcd4-4b45-b8f5-4f48b1d214fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544642164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_ec_pwr_on_rst.544642164
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.822307099
Short name T216
Test name
Test status
Simulation time 2971092265 ps
CPU time 4.66 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 201248 kb
Host smart-a259c721-1a70-4696-92b5-a82b82e63820
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822307099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctr
l_edge_detect.822307099
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3771439396
Short name T575
Test name
Test status
Simulation time 2618099821 ps
CPU time 3.79 seconds
Started Jan 10 12:30:50 PM PST 24
Finished Jan 10 12:31:39 PM PST 24
Peak memory 201224 kb
Host smart-aca93909-264d-4b31-b429-a83aebb81dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771439396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3771439396
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.489640512
Short name T64
Test name
Test status
Simulation time 2482621660 ps
CPU time 2.77 seconds
Started Jan 10 12:30:54 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201252 kb
Host smart-8477039f-5320-445d-bfb3-c8b04f1ce312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489640512 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.489640512
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3718970184
Short name T623
Test name
Test status
Simulation time 2058151868 ps
CPU time 1.64 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:31:57 PM PST 24
Peak memory 201148 kb
Host smart-bf1730ed-b7d4-448e-88ec-13a2fe2d7304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718970184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3718970184
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1058376584
Short name T651
Test name
Test status
Simulation time 2536350776 ps
CPU time 2.43 seconds
Started Jan 10 12:30:54 PM PST 24
Finished Jan 10 12:31:43 PM PST 24
Peak memory 201248 kb
Host smart-1ff34b8d-93c4-48ce-aa98-68751149be14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058376584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1058376584
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.2414760628
Short name T551
Test name
Test status
Simulation time 2129716103 ps
CPU time 1.85 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:31:38 PM PST 24
Peak memory 201192 kb
Host smart-181fbc71-e0f5-4513-b127-87b469bf6de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414760628 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2414760628
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.618237358
Short name T610
Test name
Test status
Simulation time 7072828728 ps
CPU time 5.51 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201308 kb
Host smart-f47f7f06-248e-494b-a10d-9142f1695fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618237358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.618237358
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1336669433
Short name T63
Test name
Test status
Simulation time 6272058143 ps
CPU time 6.35 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:06 PM PST 24
Peak memory 201248 kb
Host smart-77458d77-830b-402c-b393-aedde9b5629d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336669433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.1336669433
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.3112205395
Short name T590
Test name
Test status
Simulation time 2014099443 ps
CPU time 6.14 seconds
Started Jan 10 12:30:53 PM PST 24
Finished Jan 10 12:31:45 PM PST 24
Peak memory 201212 kb
Host smart-a89fa17d-9529-46ea-b0bd-d1f17334085f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112205395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.3112205395
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2450655231
Short name T752
Test name
Test status
Simulation time 182497742733 ps
CPU time 425.94 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:39:06 PM PST 24
Peak memory 201372 kb
Host smart-4d570db0-38ec-44c3-8772-259327e4eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450655231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2
450655231
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1284579420
Short name T326
Test name
Test status
Simulation time 101665344582 ps
CPU time 40.45 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:39 PM PST 24
Peak memory 201540 kb
Host smart-888b539b-06ec-45a8-b77b-cd3a82226249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284579420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w
ith_pre_cond.1284579420
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1202658770
Short name T581
Test name
Test status
Simulation time 4071553599 ps
CPU time 3.21 seconds
Started Jan 10 12:31:27 PM PST 24
Finished Jan 10 12:32:19 PM PST 24
Peak memory 201224 kb
Host smart-afe1e04f-ccdb-4618-abbd-ecb2e5737e77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202658770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1202658770
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.1849837307
Short name T468
Test name
Test status
Simulation time 2701275288 ps
CPU time 3.17 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:31:39 PM PST 24
Peak memory 201284 kb
Host smart-5fb42232-947c-4b7a-9cdb-570414b2f390
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849837307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.1849837307
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3917492922
Short name T410
Test name
Test status
Simulation time 2610051859 ps
CPU time 7.13 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201264 kb
Host smart-fa604ccd-4d20-4a1e-943b-bb77c62718db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917492922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.3917492922
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.724082473
Short name T607
Test name
Test status
Simulation time 2479381490 ps
CPU time 4.32 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:37 PM PST 24
Peak memory 201284 kb
Host smart-641ce5f5-cbdf-44d2-8066-ce2bfa7e71ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724082473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.724082473
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3714055256
Short name T692
Test name
Test status
Simulation time 2092583721 ps
CPU time 3.13 seconds
Started Jan 10 12:30:54 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201220 kb
Host smart-aad9f91e-620c-429c-af43-22adc7583552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714055256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3714055256
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.717258116
Short name T86
Test name
Test status
Simulation time 2593578163 ps
CPU time 1.18 seconds
Started Jan 10 12:31:37 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 201212 kb
Host smart-c35d12ae-ab4f-4de6-9fab-7c4bccc3a482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717258116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.717258116
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.962101508
Short name T408
Test name
Test status
Simulation time 2113889354 ps
CPU time 3.1 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:32:09 PM PST 24
Peak memory 201296 kb
Host smart-b7dab7f3-fbf4-43db-a5ef-db8cf1d0359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962101508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.962101508
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.920695258
Short name T817
Test name
Test status
Simulation time 378317186365 ps
CPU time 318.43 seconds
Started Jan 10 12:31:02 PM PST 24
Finished Jan 10 12:37:08 PM PST 24
Peak memory 201632 kb
Host smart-a3651bfa-3d31-4404-8378-9e08ce698baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920695258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_st
ress_all.920695258
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3576074069
Short name T159
Test name
Test status
Simulation time 56398517975 ps
CPU time 96.54 seconds
Started Jan 10 12:30:53 PM PST 24
Finished Jan 10 12:33:14 PM PST 24
Peak memory 210044 kb
Host smart-0525205e-f187-4b36-aedf-95d31efb715e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576074069 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3576074069
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1699927269
Short name T176
Test name
Test status
Simulation time 2685331660 ps
CPU time 1.8 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:02 PM PST 24
Peak memory 201108 kb
Host smart-419417ff-a779-4f2e-b26c-85467e53074e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699927269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.1699927269
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2994666661
Short name T499
Test name
Test status
Simulation time 3387765059 ps
CPU time 4.97 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 201264 kb
Host smart-8c8a38f6-5eda-4453-95e0-03fb82e0f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994666661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2
994666661
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.3407016797
Short name T21
Test name
Test status
Simulation time 184877499760 ps
CPU time 108.97 seconds
Started Jan 10 12:31:07 PM PST 24
Finished Jan 10 12:33:41 PM PST 24
Peak memory 201424 kb
Host smart-5a790fa7-9787-4b95-82a7-827c3d40536f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407016797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.3407016797
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2956229420
Short name T330
Test name
Test status
Simulation time 31221579096 ps
CPU time 85.49 seconds
Started Jan 10 12:31:17 PM PST 24
Finished Jan 10 12:33:28 PM PST 24
Peak memory 201572 kb
Host smart-77324665-ce9d-44f6-9a93-a7500d669ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956229420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.2956229420
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2544516829
Short name T426
Test name
Test status
Simulation time 2631154534 ps
CPU time 2.24 seconds
Started Jan 10 12:31:11 PM PST 24
Finished Jan 10 12:31:59 PM PST 24
Peak memory 201220 kb
Host smart-df73a05f-84c0-4bea-ad1c-1c830e03cca9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544516829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ec_pwr_on_rst.2544516829
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2357871533
Short name T199
Test name
Test status
Simulation time 2685073868 ps
CPU time 1.9 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:31:57 PM PST 24
Peak memory 201220 kb
Host smart-32416c3a-5387-4a05-a72f-7a4a211f6650
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357871533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct
rl_edge_detect.2357871533
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2383939858
Short name T549
Test name
Test status
Simulation time 2609440240 ps
CPU time 7.14 seconds
Started Jan 10 12:31:21 PM PST 24
Finished Jan 10 12:32:15 PM PST 24
Peak memory 201312 kb
Host smart-ea5cfbb2-45f8-4b49-9651-49de61a67362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383939858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2383939858
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1630733126
Short name T781
Test name
Test status
Simulation time 2473739918 ps
CPU time 2.19 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 201316 kb
Host smart-ba85a8e4-9813-40d6-b19a-dee0f68eff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630733126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1630733126
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.3486048874
Short name T778
Test name
Test status
Simulation time 2272284762 ps
CPU time 2 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:32:08 PM PST 24
Peak memory 201264 kb
Host smart-ae077061-d6cc-4d01-9d43-f53706dd8209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486048874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3486048874
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.2434092590
Short name T764
Test name
Test status
Simulation time 2514280303 ps
CPU time 6.85 seconds
Started Jan 10 12:31:19 PM PST 24
Finished Jan 10 12:32:12 PM PST 24
Peak memory 201240 kb
Host smart-401ce13f-ec13-4525-a4e9-879425bbeffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434092590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.2434092590
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.2306529470
Short name T616
Test name
Test status
Simulation time 2113724989 ps
CPU time 5.94 seconds
Started Jan 10 12:30:52 PM PST 24
Finished Jan 10 12:31:43 PM PST 24
Peak memory 201152 kb
Host smart-3641333e-42ed-4bf3-a149-b3f4965c42b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306529470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.2306529470
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2705746707
Short name T669
Test name
Test status
Simulation time 11318701805 ps
CPU time 7.57 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:31:59 PM PST 24
Peak memory 201232 kb
Host smart-9597327c-769f-40d9-b058-a8a10b9087b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705746707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2705746707
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3941115966
Short name T178
Test name
Test status
Simulation time 42325892152 ps
CPU time 106.42 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:33:45 PM PST 24
Peak memory 209912 kb
Host smart-b57adacb-df3a-4902-9460-bbc249e62173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941115966 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.3941115966
Directory /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3966472364
Short name T846
Test name
Test status
Simulation time 6351637908 ps
CPU time 8.35 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:08 PM PST 24
Peak memory 201284 kb
Host smart-10c4b23c-37c5-4edd-9eda-4bc3006e5597
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966472364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.3966472364
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.604679617
Short name T169
Test name
Test status
Simulation time 2025679305 ps
CPU time 2.9 seconds
Started Jan 10 12:31:40 PM PST 24
Finished Jan 10 12:32:34 PM PST 24
Peak memory 201328 kb
Host smart-c9e04066-fbe6-4ef3-aaa2-aa00c1c76a2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604679617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_tes
t.604679617
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2496796020
Short name T750
Test name
Test status
Simulation time 3617185507 ps
CPU time 5.07 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:04 PM PST 24
Peak memory 200972 kb
Host smart-427e4fb1-39ac-4734-9cf8-029de878b7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496796020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2
496796020
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.2736189145
Short name T712
Test name
Test status
Simulation time 177044032938 ps
CPU time 475.01 seconds
Started Jan 10 12:31:00 PM PST 24
Finished Jan 10 12:39:43 PM PST 24
Peak memory 201424 kb
Host smart-b8a3e4f6-def1-4b46-82a4-035e67de2087
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736189145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.2736189145
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1912508428
Short name T324
Test name
Test status
Simulation time 59406138739 ps
CPU time 31.32 seconds
Started Jan 10 12:31:08 PM PST 24
Finished Jan 10 12:32:26 PM PST 24
Peak memory 201644 kb
Host smart-94b2c953-3e50-4f31-9a3b-93ad1ab4809b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912508428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.1912508428
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2995603248
Short name T122
Test name
Test status
Simulation time 3602767246 ps
CPU time 1.69 seconds
Started Jan 10 12:30:56 PM PST 24
Finished Jan 10 12:31:45 PM PST 24
Peak memory 201272 kb
Host smart-5a30b288-6f62-4efb-8cf0-23681613b8d9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995603248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.2995603248
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.850036332
Short name T168
Test name
Test status
Simulation time 5101288345 ps
CPU time 3.88 seconds
Started Jan 10 12:31:04 PM PST 24
Finished Jan 10 12:31:55 PM PST 24
Peak memory 201332 kb
Host smart-c1535679-f778-451f-b402-d382f5d42760
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850036332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctr
l_edge_detect.850036332
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.274416216
Short name T31
Test name
Test status
Simulation time 2613973753 ps
CPU time 7.54 seconds
Started Jan 10 12:31:21 PM PST 24
Finished Jan 10 12:32:14 PM PST 24
Peak memory 201240 kb
Host smart-3494349a-81cf-433b-abff-a8b2ced1f003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274416216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.274416216
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.4130958227
Short name T825
Test name
Test status
Simulation time 2495966449 ps
CPU time 1.64 seconds
Started Jan 10 12:31:22 PM PST 24
Finished Jan 10 12:32:10 PM PST 24
Peak memory 201208 kb
Host smart-9c304eaa-71c3-4bc5-81cb-e0d49da62613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130958227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.4130958227
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.49833506
Short name T467
Test name
Test status
Simulation time 2269746050 ps
CPU time 2.01 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 201160 kb
Host smart-45a6d715-5252-4d14-a469-7143a331f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49833506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.49833506
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2301749386
Short name T489
Test name
Test status
Simulation time 2512045954 ps
CPU time 7.25 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 201240 kb
Host smart-7e50b6da-6fb9-49fe-b39c-678075afbac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301749386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2301749386
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3547862271
Short name T810
Test name
Test status
Simulation time 2135298370 ps
CPU time 1.9 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:31:58 PM PST 24
Peak memory 201184 kb
Host smart-2807853e-34a3-4cf9-b196-64f4d2b5704f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547862271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3547862271
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.3460827558
Short name T139
Test name
Test status
Simulation time 16873891655 ps
CPU time 37.78 seconds
Started Jan 10 12:31:11 PM PST 24
Finished Jan 10 12:32:35 PM PST 24
Peak memory 201272 kb
Host smart-f7c888b7-a2ac-4343-ad5f-9b38ff8c1c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460827558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.3460827558
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2895505071
Short name T350
Test name
Test status
Simulation time 140168574538 ps
CPU time 36.38 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:32:13 PM PST 24
Peak memory 209884 kb
Host smart-1e969187-2ee4-4e2d-892f-ba9a724f6021
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895505071 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2895505071
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3207716232
Short name T161
Test name
Test status
Simulation time 5746104083 ps
CPU time 2.31 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:02 PM PST 24
Peak memory 201068 kb
Host smart-49738aab-67c9-4a64-ba05-fb1ed1927863
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207716232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.3207716232
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.968520326
Short name T649
Test name
Test status
Simulation time 2025405727 ps
CPU time 2.94 seconds
Started Jan 10 12:31:17 PM PST 24
Finished Jan 10 12:32:06 PM PST 24
Peak memory 201192 kb
Host smart-ec4879e5-efc8-4e6c-b0d1-4acb6b346e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968520326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_tes
t.968520326
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.2512252879
Short name T491
Test name
Test status
Simulation time 3010829871 ps
CPU time 2.48 seconds
Started Jan 10 12:31:00 PM PST 24
Finished Jan 10 12:31:50 PM PST 24
Peak memory 201336 kb
Host smart-741a0519-5f54-4b94-bd06-e6d447ff9d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512252879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.2
512252879
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.1058484247
Short name T307
Test name
Test status
Simulation time 161105977007 ps
CPU time 107.91 seconds
Started Jan 10 12:31:07 PM PST 24
Finished Jan 10 12:33:41 PM PST 24
Peak memory 201548 kb
Host smart-25a30b12-f1ee-4aed-9334-fe4e1ec92bf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058484247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_combo_detect.1058484247
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.29116608
Short name T624
Test name
Test status
Simulation time 24078245171 ps
CPU time 61.29 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:32:57 PM PST 24
Peak memory 201700 kb
Host smart-60e50d2b-40e0-450e-bf51-eaaea356d55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29116608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_wit
h_pre_cond.29116608
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3135458708
Short name T194
Test name
Test status
Simulation time 4372864345 ps
CPU time 3.49 seconds
Started Jan 10 12:31:28 PM PST 24
Finished Jan 10 12:32:20 PM PST 24
Peak memory 201232 kb
Host smart-60344770-7060-4168-9430-fae45ba87296
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135458708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ec_pwr_on_rst.3135458708
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.299313133
Short name T135
Test name
Test status
Simulation time 3036046896 ps
CPU time 1.41 seconds
Started Jan 10 12:30:52 PM PST 24
Finished Jan 10 12:31:38 PM PST 24
Peak memory 201280 kb
Host smart-77fe5592-7028-49ff-b059-283272d4dfc4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299313133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctr
l_edge_detect.299313133
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3968776890
Short name T203
Test name
Test status
Simulation time 2630327958 ps
CPU time 2.37 seconds
Started Jan 10 12:31:13 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 201276 kb
Host smart-586558a1-8fbb-476c-b8b3-4fc38f1ad9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968776890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3968776890
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2822198498
Short name T425
Test name
Test status
Simulation time 2459625524 ps
CPU time 8.06 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 201372 kb
Host smart-da25b65f-2041-4e46-a5d2-2dbcc3f0ef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822198498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2822198498
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.2706971277
Short name T843
Test name
Test status
Simulation time 2230271307 ps
CPU time 6.31 seconds
Started Jan 10 12:30:52 PM PST 24
Finished Jan 10 12:31:43 PM PST 24
Peak memory 201380 kb
Host smart-4c1cdad7-dc66-47af-a234-1116f1842388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706971277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.2706971277
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.1870488217
Short name T561
Test name
Test status
Simulation time 2508982680 ps
CPU time 7.09 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:31:58 PM PST 24
Peak memory 201204 kb
Host smart-0f617fac-e3de-45e6-b649-060253903e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870488217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.1870488217
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.3406966148
Short name T497
Test name
Test status
Simulation time 2180416030 ps
CPU time 1.04 seconds
Started Jan 10 12:31:21 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 201356 kb
Host smart-8153227a-59c0-4abb-ba65-8be7586dafc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406966148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.3406966148
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.2827268577
Short name T794
Test name
Test status
Simulation time 10896163750 ps
CPU time 4.76 seconds
Started Jan 10 12:31:11 PM PST 24
Finished Jan 10 12:32:02 PM PST 24
Peak memory 201412 kb
Host smart-620e868d-d5de-41d4-ba15-280d1174b1e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827268577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.2827268577
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1177212707
Short name T633
Test name
Test status
Simulation time 21477101929 ps
CPU time 15.46 seconds
Started Jan 10 12:31:02 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 209920 kb
Host smart-c40d08db-3b4d-407a-96fa-93460e93dc26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177212707 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1177212707
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1645764471
Short name T73
Test name
Test status
Simulation time 403353079932 ps
CPU time 12.35 seconds
Started Jan 10 12:30:50 PM PST 24
Finished Jan 10 12:31:47 PM PST 24
Peak memory 201228 kb
Host smart-35f49558-c5ba-4213-88e9-418feb07bca2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645764471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.1645764471
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.2516539838
Short name T613
Test name
Test status
Simulation time 2043583345 ps
CPU time 1.74 seconds
Started Jan 10 12:31:21 PM PST 24
Finished Jan 10 12:32:09 PM PST 24
Peak memory 201220 kb
Host smart-19666863-31b9-45a2-86f3-11c15774285b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516539838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.2516539838
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.3395243226
Short name T507
Test name
Test status
Simulation time 3335561794 ps
CPU time 9.4 seconds
Started Jan 10 12:31:01 PM PST 24
Finished Jan 10 12:31:58 PM PST 24
Peak memory 201356 kb
Host smart-3fcd5c00-9c55-4755-b6fe-de2561b6f3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395243226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.3
395243226
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.986356688
Short name T260
Test name
Test status
Simulation time 173635790095 ps
CPU time 414.93 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:38:54 PM PST 24
Peak memory 201492 kb
Host smart-245f2e98-9cf0-4aa6-9e54-2f47d7196c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986356688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_wi
th_pre_cond.986356688
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3036839567
Short name T430
Test name
Test status
Simulation time 4033308083 ps
CPU time 5.33 seconds
Started Jan 10 12:31:03 PM PST 24
Finished Jan 10 12:31:56 PM PST 24
Peak memory 201284 kb
Host smart-0d327db5-5d0e-48e0-a9bc-f7d238949758
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036839567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.3036839567
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.1286543706
Short name T238
Test name
Test status
Simulation time 3200054587 ps
CPU time 2.5 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:31:58 PM PST 24
Peak memory 201340 kb
Host smart-4189c19e-e30d-4273-85ba-9f9db971ccb7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286543706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct
rl_edge_detect.1286543706
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.651780786
Short name T534
Test name
Test status
Simulation time 2608321833 ps
CPU time 7.19 seconds
Started Jan 10 12:31:21 PM PST 24
Finished Jan 10 12:32:15 PM PST 24
Peak memory 201316 kb
Host smart-7143c878-03cd-4561-912c-51b36bae9ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651780786 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.651780786
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1574100222
Short name T830
Test name
Test status
Simulation time 2605293620 ps
CPU time 0.99 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201320 kb
Host smart-eaaf5f1a-3b8a-455f-888b-40acd70c3af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574100222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1574100222
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.1324449894
Short name T454
Test name
Test status
Simulation time 2205055223 ps
CPU time 2.47 seconds
Started Jan 10 12:31:27 PM PST 24
Finished Jan 10 12:32:17 PM PST 24
Peak memory 201172 kb
Host smart-df0797e9-31e1-4e39-9bcb-a9b6d96adfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324449894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.1324449894
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.4233890502
Short name T576
Test name
Test status
Simulation time 2530937442 ps
CPU time 2.27 seconds
Started Jan 10 12:31:06 PM PST 24
Finished Jan 10 12:31:54 PM PST 24
Peak memory 201272 kb
Host smart-b0058524-fdb8-465b-af06-3925e17e6d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233890502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.4233890502
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.114832012
Short name T587
Test name
Test status
Simulation time 2129881841 ps
CPU time 1.57 seconds
Started Jan 10 12:31:15 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 201156 kb
Host smart-cf4db39b-2b93-4212-a0e3-664489b1fc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114832012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.114832012
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.3939481885
Short name T187
Test name
Test status
Simulation time 20783379242 ps
CPU time 11.18 seconds
Started Jan 10 12:30:58 PM PST 24
Finished Jan 10 12:31:57 PM PST 24
Peak memory 201296 kb
Host smart-bbe2bcb9-11ba-4782-a9ba-6931fcf31c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939481885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s
tress_all.3939481885
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1512553948
Short name T191
Test name
Test status
Simulation time 5533468080 ps
CPU time 2.31 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:31:54 PM PST 24
Peak memory 201248 kb
Host smart-20caf714-f608-4cd7-ad35-f583ae9cd0b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512553948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ultra_low_pwr.1512553948
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.3912797204
Short name T589
Test name
Test status
Simulation time 2032028584 ps
CPU time 2.07 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:15 PM PST 24
Peak memory 201160 kb
Host smart-60cb18bf-bcf8-4ffc-82ca-cdf8da30127f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912797204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.3912797204
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2222357548
Short name T41
Test name
Test status
Simulation time 3450323882 ps
CPU time 2.38 seconds
Started Jan 10 12:31:21 PM PST 24
Finished Jan 10 12:32:10 PM PST 24
Peak memory 201356 kb
Host smart-3622d6c5-f323-4c3c-8158-ae818a4161d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222357548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.2
222357548
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.3411686323
Short name T777
Test name
Test status
Simulation time 27304702739 ps
CPU time 19.8 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:31 PM PST 24
Peak memory 201572 kb
Host smart-be37584a-266b-4877-831c-27b730b77f79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411686323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.3411686323
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.480121170
Short name T739
Test name
Test status
Simulation time 30892241570 ps
CPU time 20.81 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 201896 kb
Host smart-eef2b18b-1e2c-49bb-9a2a-3ae77d103f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480121170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_wi
th_pre_cond.480121170
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.644217506
Short name T428
Test name
Test status
Simulation time 2926329310 ps
CPU time 7.94 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:32:14 PM PST 24
Peak memory 201216 kb
Host smart-2be78f24-664e-44d8-a597-05880d30d156
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644217506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_ec_pwr_on_rst.644217506
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1551242837
Short name T599
Test name
Test status
Simulation time 2630848616 ps
CPU time 2.32 seconds
Started Jan 10 12:31:16 PM PST 24
Finished Jan 10 12:32:03 PM PST 24
Peak memory 201292 kb
Host smart-5abc74af-9b14-474f-ae94-764ee1d0ebe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551242837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1551242837
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3005048435
Short name T656
Test name
Test status
Simulation time 2485437390 ps
CPU time 2.13 seconds
Started Jan 10 12:31:29 PM PST 24
Finished Jan 10 12:32:20 PM PST 24
Peak memory 201340 kb
Host smart-71c76143-0df2-40b0-abda-b8faae87ad29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005048435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3005048435
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3485448247
Short name T640
Test name
Test status
Simulation time 2275888279 ps
CPU time 2.05 seconds
Started Jan 10 12:31:26 PM PST 24
Finished Jan 10 12:32:17 PM PST 24
Peak memory 201248 kb
Host smart-b3af81a5-3383-4a04-ac8b-2784307f8ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485448247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3485448247
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.383960382
Short name T354
Test name
Test status
Simulation time 2519665303 ps
CPU time 2.37 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:32:25 PM PST 24
Peak memory 201296 kb
Host smart-98fdc4b7-7fa6-4953-8826-9c461ab0c74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383960382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.383960382
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.1067712457
Short name T814
Test name
Test status
Simulation time 2117114559 ps
CPU time 3.3 seconds
Started Jan 10 12:31:18 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 201188 kb
Host smart-c222029c-3bc5-47ec-b09f-fc6de6ddfc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067712457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1067712457
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.421740847
Short name T771
Test name
Test status
Simulation time 6027122672 ps
CPU time 16.49 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 12:32:14 PM PST 24
Peak memory 201400 kb
Host smart-d6b5ad72-3c45-4b0f-b7c0-aafa180e2529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421740847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_st
ress_all.421740847
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.3277455875
Short name T142
Test name
Test status
Simulation time 9086405144 ps
CPU time 1.8 seconds
Started Jan 10 12:31:26 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201232 kb
Host smart-3e688906-c3fb-4031-bae1-25145f181267
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277455875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ultra_low_pwr.3277455875
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.2397446912
Short name T668
Test name
Test status
Simulation time 2034337896 ps
CPU time 2.23 seconds
Started Jan 10 12:31:32 PM PST 24
Finished Jan 10 12:32:24 PM PST 24
Peak memory 201196 kb
Host smart-9925fcef-e68a-4fec-85bd-94d2ab00f18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397446912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.2397446912
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1531082456
Short name T812
Test name
Test status
Simulation time 3630213307 ps
CPU time 1.21 seconds
Started Jan 10 12:31:14 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 201332 kb
Host smart-dbb0f9ea-2ab6-493b-92b0-5f17e9f844d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531082456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.1
531082456
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3325448042
Short name T555
Test name
Test status
Simulation time 50126237495 ps
CPU time 32.85 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 201760 kb
Host smart-cb6db1f0-8722-493f-96c4-27852fa7f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325448042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_w
ith_pre_cond.3325448042
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.723186862
Short name T780
Test name
Test status
Simulation time 2491703648 ps
CPU time 3.88 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:18 PM PST 24
Peak memory 201212 kb
Host smart-59b37ea1-3860-41d1-84e3-eade173f5529
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723186862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_ec_pwr_on_rst.723186862
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.4013653796
Short name T19
Test name
Test status
Simulation time 492266519436 ps
CPU time 98.79 seconds
Started Jan 10 12:31:19 PM PST 24
Finished Jan 10 12:33:44 PM PST 24
Peak memory 201236 kb
Host smart-6977349d-fd28-4f7e-bab6-810278b9aa30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013653796 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.4013653796
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3065678035
Short name T650
Test name
Test status
Simulation time 2609532004 ps
CPU time 7.09 seconds
Started Jan 10 12:31:22 PM PST 24
Finished Jan 10 12:32:15 PM PST 24
Peak memory 201384 kb
Host smart-7882d664-871c-4f0f-900f-880490849824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065678035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3065678035
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.2103000220
Short name T829
Test name
Test status
Simulation time 2532634555 ps
CPU time 1.11 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:14 PM PST 24
Peak memory 201364 kb
Host smart-8456a06c-a81d-4325-950c-7cc6d3a0fba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103000220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.2103000220
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.1350229794
Short name T493
Test name
Test status
Simulation time 2282167947 ps
CPU time 2.1 seconds
Started Jan 10 12:31:18 PM PST 24
Finished Jan 10 12:32:05 PM PST 24
Peak memory 201296 kb
Host smart-db55fb75-a0ca-41e6-8254-0ebb9edc2e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350229794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1350229794
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3727954754
Short name T579
Test name
Test status
Simulation time 2565223848 ps
CPU time 1.29 seconds
Started Jan 10 12:31:26 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201256 kb
Host smart-11af47b3-8e33-454b-bb2f-29ac8842e640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727954754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3727954754
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.3512815013
Short name T667
Test name
Test status
Simulation time 2254347992 ps
CPU time 0.86 seconds
Started Jan 10 12:31:27 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201228 kb
Host smart-454d0a50-2b63-4e44-a0a0-9570dfd0da9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512815013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3512815013
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.1085942715
Short name T811
Test name
Test status
Simulation time 12305567415 ps
CPU time 3.01 seconds
Started Jan 10 12:31:26 PM PST 24
Finished Jan 10 12:32:18 PM PST 24
Peak memory 201336 kb
Host smart-2ab591c3-70c7-43ba-9650-5c5ede4e6a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085942715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.1085942715
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.462334013
Short name T552
Test name
Test status
Simulation time 37634385305 ps
CPU time 45.28 seconds
Started Jan 10 12:31:17 PM PST 24
Finished Jan 10 12:32:48 PM PST 24
Peak memory 210084 kb
Host smart-bd7b0f8c-df2d-444b-81ff-2b0d3b6dec08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462334013 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.462334013
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.4115500742
Short name T32
Test name
Test status
Simulation time 7479616943 ps
CPU time 2.45 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:13 PM PST 24
Peak memory 201216 kb
Host smart-ff629ee0-3404-4caa-9ad0-ab4792a02f6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115500742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.4115500742
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.4051493953
Short name T485
Test name
Test status
Simulation time 2011254747 ps
CPU time 6.09 seconds
Started Jan 10 12:30:25 PM PST 24
Finished Jan 10 12:31:12 PM PST 24
Peak memory 201220 kb
Host smart-7183abf1-2e34-4e6c-ab6a-35dda9946b77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051493953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.4051493953
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1615262126
Short name T836
Test name
Test status
Simulation time 3264286584 ps
CPU time 8.09 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:19 PM PST 24
Peak memory 201272 kb
Host smart-03d32bb6-3e20-4652-b63f-259f1f1cb339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615262126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1615262126
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.2011034872
Short name T341
Test name
Test status
Simulation time 77436521680 ps
CPU time 213.85 seconds
Started Jan 10 12:30:24 PM PST 24
Finished Jan 10 12:34:39 PM PST 24
Peak memory 201440 kb
Host smart-2763c713-e04a-401e-8128-5ad9788a37ae
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011034872 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_combo_detect.2011034872
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.2114580158
Short name T694
Test name
Test status
Simulation time 2201039317 ps
CPU time 1.86 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:13 PM PST 24
Peak memory 201316 kb
Host smart-fad6b354-b141-4fa8-8805-d665807092cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114580158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.2114580158
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4083173008
Short name T440
Test name
Test status
Simulation time 2548506028 ps
CPU time 2.99 seconds
Started Jan 10 12:30:17 PM PST 24
Finished Jan 10 12:30:59 PM PST 24
Peak memory 201368 kb
Host smart-c843c779-1a9e-4e30-a29c-76358b4b3182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083173008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.4083173008
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.3442644568
Short name T690
Test name
Test status
Simulation time 3643864507 ps
CPU time 4.59 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:20 PM PST 24
Peak memory 201352 kb
Host smart-e116337a-a23d-4527-9e87-70ba24b769c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442644568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.3442644568
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.541241701
Short name T186
Test name
Test status
Simulation time 3598588320 ps
CPU time 4.23 seconds
Started Jan 10 12:30:34 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 201224 kb
Host smart-0961e033-f197-4c40-a62e-466e6ffb39b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541241701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_edge_detect.541241701
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.4053844931
Short name T569
Test name
Test status
Simulation time 2611370835 ps
CPU time 7.28 seconds
Started Jan 10 12:30:28 PM PST 24
Finished Jan 10 12:31:17 PM PST 24
Peak memory 201280 kb
Host smart-e8666c91-1f6d-40e9-9210-b44dbbd88e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053844931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.4053844931
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1181669812
Short name T137
Test name
Test status
Simulation time 2476108806 ps
CPU time 6.37 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:31:05 PM PST 24
Peak memory 201200 kb
Host smart-5ef02356-346a-401c-8c09-27f586de9ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181669812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.1181669812
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.4189083382
Short name T421
Test name
Test status
Simulation time 2125294935 ps
CPU time 5.96 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:31:05 PM PST 24
Peak memory 201296 kb
Host smart-7e291dd9-b78a-44c4-aa4d-83c82199b179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189083382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.4189083382
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.1120442468
Short name T594
Test name
Test status
Simulation time 2520389970 ps
CPU time 3.74 seconds
Started Jan 10 12:30:19 PM PST 24
Finished Jan 10 12:31:02 PM PST 24
Peak memory 201364 kb
Host smart-dbab0462-799f-4646-b63e-2c368ec22f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120442468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.1120442468
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.3145586445
Short name T285
Test name
Test status
Simulation time 22029752191 ps
CPU time 26.63 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 221200 kb
Host smart-64ca2250-b53e-4d94-a6aa-a6e625b5c927
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145586445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.3145586445
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.263834016
Short name T504
Test name
Test status
Simulation time 2111238865 ps
CPU time 6.11 seconds
Started Jan 10 12:30:20 PM PST 24
Finished Jan 10 12:31:06 PM PST 24
Peak memory 201304 kb
Host smart-89a3e05e-1261-4070-83a5-0a9b5ea9293f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263834016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.263834016
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.997617966
Short name T786
Test name
Test status
Simulation time 10993695272 ps
CPU time 12.94 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 201276 kb
Host smart-06d41db8-f476-4b8a-beab-0b23036b8030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997617966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str
ess_all.997617966
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3462748012
Short name T261
Test name
Test status
Simulation time 83969951354 ps
CPU time 191.36 seconds
Started Jan 10 12:30:40 PM PST 24
Finished Jan 10 12:34:34 PM PST 24
Peak memory 209856 kb
Host smart-1750af1a-e76b-4b7c-b4f9-401bacbb3b33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462748012 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.3462748012
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.700024175
Short name T128
Test name
Test status
Simulation time 106069933661 ps
CPU time 13.36 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 201188 kb
Host smart-860379fe-03da-418c-ad25-7ed41ff8c88e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700024175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ct
rl_ultra_low_pwr.700024175
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.1791168631
Short name T775
Test name
Test status
Simulation time 2016722954 ps
CPU time 5.22 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:32:39 PM PST 24
Peak memory 201344 kb
Host smart-4a483ce0-fa33-4a16-a00a-5d5d446a59af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791168631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.1791168631
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.4149396538
Short name T732
Test name
Test status
Simulation time 138329931255 ps
CPU time 381.26 seconds
Started Jan 10 12:31:40 PM PST 24
Finished Jan 10 12:38:51 PM PST 24
Peak memory 201332 kb
Host smart-1965805d-555c-4401-93e0-a46967ad8a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149396538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.4
149396538
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2072781258
Short name T785
Test name
Test status
Simulation time 158787480129 ps
CPU time 85.96 seconds
Started Jan 10 12:31:22 PM PST 24
Finished Jan 10 12:33:34 PM PST 24
Peak memory 201344 kb
Host smart-52742fb5-2e18-4e01-b082-f45241157171
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072781258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.2072781258
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3186285082
Short name T95
Test name
Test status
Simulation time 21851382155 ps
CPU time 14.62 seconds
Started Jan 10 12:31:16 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201776 kb
Host smart-2089148b-f930-4056-be1b-0df48ebe53f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186285082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.3186285082
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3068788224
Short name T484
Test name
Test status
Simulation time 4421190802 ps
CPU time 12.26 seconds
Started Jan 10 12:31:36 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 201352 kb
Host smart-9ebd1603-09dd-434f-84eb-c84f1a4f163b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068788224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.3068788224
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3604291601
Short name T175
Test name
Test status
Simulation time 4660671465 ps
CPU time 8.78 seconds
Started Jan 10 12:31:24 PM PST 24
Finished Jan 10 12:32:21 PM PST 24
Peak memory 201316 kb
Host smart-a79e0408-d3e1-4946-b748-b970fdb5cdb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604291601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3604291601
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.1748415829
Short name T422
Test name
Test status
Simulation time 2634630543 ps
CPU time 2.05 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:33 PM PST 24
Peak memory 201204 kb
Host smart-4d3f50a6-9f17-4160-b7bd-340a72ff2fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748415829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.1748415829
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.3811343675
Short name T512
Test name
Test status
Simulation time 2495034981 ps
CPU time 2.37 seconds
Started Jan 10 12:31:39 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 201252 kb
Host smart-79b2e625-d16c-46b5-9cf0-7fc606bf3d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811343675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.3811343675
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.370935274
Short name T537
Test name
Test status
Simulation time 2216128108 ps
CPU time 2.68 seconds
Started Jan 10 12:31:29 PM PST 24
Finished Jan 10 12:32:21 PM PST 24
Peak memory 201204 kb
Host smart-ec338685-2530-4054-832d-1a43f7ace161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370935274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.370935274
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.1125628458
Short name T748
Test name
Test status
Simulation time 2518388974 ps
CPU time 3.86 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:13 PM PST 24
Peak memory 201224 kb
Host smart-9db40068-f85b-433f-a456-027810f3bd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125628458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1125628458
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.319839823
Short name T832
Test name
Test status
Simulation time 2122805563 ps
CPU time 1.93 seconds
Started Jan 10 12:31:19 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 201224 kb
Host smart-fe0ac988-1bcc-4160-b244-9288d0a15070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319839823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.319839823
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.1910555244
Short name T791
Test name
Test status
Simulation time 350272602188 ps
CPU time 98.77 seconds
Started Jan 10 12:31:44 PM PST 24
Finished Jan 10 12:34:12 PM PST 24
Peak memory 201232 kb
Host smart-8fbd7e37-1c23-40cb-844e-741fc8269623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910555244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.1910555244
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3250457991
Short name T621
Test name
Test status
Simulation time 28022032228 ps
CPU time 17.62 seconds
Started Jan 10 12:31:38 PM PST 24
Finished Jan 10 12:32:46 PM PST 24
Peak memory 209764 kb
Host smart-8fa2c113-7cb3-426c-b046-5f86d831a9cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250457991 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.3250457991
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.1124243265
Short name T737
Test name
Test status
Simulation time 7971297335 ps
CPU time 8.71 seconds
Started Jan 10 12:31:53 PM PST 24
Finished Jan 10 12:32:49 PM PST 24
Peak memory 201220 kb
Host smart-6b96c905-e8a4-40cd-9061-05f699081d9b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124243265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ultra_low_pwr.1124243265
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.1570224695
Short name T144
Test name
Test status
Simulation time 2011568453 ps
CPU time 5.77 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201304 kb
Host smart-b4668478-2980-42a1-a5d4-86679c409577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570224695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.1570224695
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.2088704990
Short name T148
Test name
Test status
Simulation time 3687824324 ps
CPU time 10.31 seconds
Started Jan 10 12:31:27 PM PST 24
Finished Jan 10 12:32:27 PM PST 24
Peak memory 201456 kb
Host smart-b560e51c-0877-4bf1-8fa7-f973e83c2a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088704990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.2
088704990
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.4256330618
Short name T270
Test name
Test status
Simulation time 56210523224 ps
CPU time 63.95 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:33:39 PM PST 24
Peak memory 200780 kb
Host smart-54ec5df6-613c-48a2-8ce7-05b6d2b0b2a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256330618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.4256330618
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.2669916281
Short name T246
Test name
Test status
Simulation time 44116914902 ps
CPU time 29.89 seconds
Started Jan 10 12:31:31 PM PST 24
Finished Jan 10 12:32:50 PM PST 24
Peak memory 201548 kb
Host smart-62da8500-90f1-4f27-b215-3315a813d081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669916281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.2669916281
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3079306534
Short name T500
Test name
Test status
Simulation time 3786797099 ps
CPU time 5.53 seconds
Started Jan 10 12:31:24 PM PST 24
Finished Jan 10 12:32:18 PM PST 24
Peak memory 201128 kb
Host smart-5d2e55bc-c8c1-44eb-b5f0-02c1607238cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079306534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.3079306534
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2897146745
Short name T820
Test name
Test status
Simulation time 3568524468 ps
CPU time 2.93 seconds
Started Jan 10 12:31:37 PM PST 24
Finished Jan 10 12:32:30 PM PST 24
Peak memory 201268 kb
Host smart-6b663f48-8297-4a5e-88f3-c1a8fd487206
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897146745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.2897146745
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.4038006565
Short name T151
Test name
Test status
Simulation time 2674076360 ps
CPU time 1.39 seconds
Started Jan 10 12:31:24 PM PST 24
Finished Jan 10 12:32:14 PM PST 24
Peak memory 201256 kb
Host smart-9e974560-450f-4ed6-ad74-bc3180ee60bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038006565 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.4038006565
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3268728097
Short name T471
Test name
Test status
Simulation time 2459878910 ps
CPU time 2.18 seconds
Started Jan 10 12:31:28 PM PST 24
Finished Jan 10 12:32:19 PM PST 24
Peak memory 201276 kb
Host smart-4aa3ddea-4902-47c6-8019-18c344d84ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268728097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3268728097
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.1987691389
Short name T116
Test name
Test status
Simulation time 2048144396 ps
CPU time 6.01 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:32:29 PM PST 24
Peak memory 201280 kb
Host smart-5aa5feb1-c633-4d5f-9312-31e6d89166a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987691389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1987691389
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3050190266
Short name T678
Test name
Test status
Simulation time 2512601189 ps
CPU time 6.84 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:32:42 PM PST 24
Peak memory 201212 kb
Host smart-801b6096-81ad-4c0d-a2dd-8bbcee05a08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050190266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3050190266
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.3387975877
Short name T419
Test name
Test status
Simulation time 2127969682 ps
CPU time 1.87 seconds
Started Jan 10 12:31:34 PM PST 24
Finished Jan 10 12:32:26 PM PST 24
Peak memory 201256 kb
Host smart-922b34dc-f66c-454f-b2aa-e3e9077a30a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387975877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.3387975877
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.3691964608
Short name T242
Test name
Test status
Simulation time 240077968508 ps
CPU time 524 seconds
Started Jan 10 12:31:21 PM PST 24
Finished Jan 10 12:40:51 PM PST 24
Peak memory 201276 kb
Host smart-d3df9029-8b8e-4a1c-88aa-1b02fee9ca9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691964608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.3691964608
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.760393744
Short name T110
Test name
Test status
Simulation time 465049558550 ps
CPU time 136.62 seconds
Started Jan 10 12:31:20 PM PST 24
Finished Jan 10 12:34:22 PM PST 24
Peak memory 209876 kb
Host smart-a3c577f7-f04b-4853-b422-8b488a9088ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760393744 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.760393744
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2770598535
Short name T140
Test name
Test status
Simulation time 958661395220 ps
CPU time 11.01 seconds
Started Jan 10 12:31:32 PM PST 24
Finished Jan 10 12:32:33 PM PST 24
Peak memory 201244 kb
Host smart-f27508a4-70c7-46e0-8842-35262608af2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770598535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ultra_low_pwr.2770598535
Directory /workspace/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.3776286639
Short name T449
Test name
Test status
Simulation time 2059797802 ps
CPU time 1.11 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 201112 kb
Host smart-dd6f5e05-9a7b-478a-8eb5-ba290af670ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776286639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.3776286639
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3752441444
Short name T306
Test name
Test status
Simulation time 44165267164 ps
CPU time 22.46 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:36 PM PST 24
Peak memory 201424 kb
Host smart-54e5b9f5-8ddb-46fe-bcf3-2bf2730b5e54
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752441444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3752441444
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1071921862
Short name T654
Test name
Test status
Simulation time 33771229184 ps
CPU time 87.19 seconds
Started Jan 10 12:57:09 PM PST 24
Finished Jan 10 12:59:48 PM PST 24
Peak memory 201796 kb
Host smart-b9b2c387-7c97-4e3d-bf26-629a59424f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071921862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.1071921862
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1522461694
Short name T126
Test name
Test status
Simulation time 3418840160 ps
CPU time 2.68 seconds
Started Jan 10 12:31:30 PM PST 24
Finished Jan 10 12:32:22 PM PST 24
Peak memory 201360 kb
Host smart-a6cd9b92-3f08-4c5e-aebe-ca02514e0844
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522461694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1522461694
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.95038426
Short name T18
Test name
Test status
Simulation time 2959176543 ps
CPU time 6.9 seconds
Started Jan 10 12:31:28 PM PST 24
Finished Jan 10 12:32:24 PM PST 24
Peak memory 201248 kb
Host smart-d61a518a-a50c-49d9-9e93-ee90ed33e989
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95038426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl
_edge_detect.95038426
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3287400783
Short name T662
Test name
Test status
Simulation time 2617064560 ps
CPU time 3.92 seconds
Started Jan 10 12:31:37 PM PST 24
Finished Jan 10 12:32:31 PM PST 24
Peak memory 201244 kb
Host smart-eeef2a33-cc36-4344-896c-8196e347321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287400783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3287400783
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.176703178
Short name T673
Test name
Test status
Simulation time 2474108456 ps
CPU time 7.8 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:17 PM PST 24
Peak memory 201316 kb
Host smart-e2b4eb2d-696a-4ccc-9bde-d388c3462422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176703178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.176703178
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2472148992
Short name T231
Test name
Test status
Simulation time 2105101638 ps
CPU time 1.41 seconds
Started Jan 10 12:31:28 PM PST 24
Finished Jan 10 12:32:18 PM PST 24
Peak memory 201204 kb
Host smart-d6299769-3d23-4914-be85-4776b1eab968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472148992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2472148992
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2692443946
Short name T515
Test name
Test status
Simulation time 2539552291 ps
CPU time 2.37 seconds
Started Jan 10 12:55:41 PM PST 24
Finished Jan 10 12:56:51 PM PST 24
Peak memory 201308 kb
Host smart-f158764e-373c-4350-94f1-d97a6a4b8fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692443946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2692443946
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.856491699
Short name T483
Test name
Test status
Simulation time 2122905499 ps
CPU time 3.28 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201104 kb
Host smart-e74a1e53-e6c8-4100-a152-dfd186f43908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856491699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.856491699
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.383443948
Short name T620
Test name
Test status
Simulation time 6870412877 ps
CPU time 2.54 seconds
Started Jan 10 12:31:35 PM PST 24
Finished Jan 10 12:32:30 PM PST 24
Peak memory 201236 kb
Host smart-065e0ce8-ddb4-432c-bfcd-dc63ea1247f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383443948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_st
ress_all.383443948
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3758610346
Short name T69
Test name
Test status
Simulation time 4968956426 ps
CPU time 2.61 seconds
Started Jan 10 12:31:35 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 201216 kb
Host smart-dc8c33bb-b36b-4d46-8448-9b95f5ebc455
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758610346 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3758610346
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.1085902947
Short name T455
Test name
Test status
Simulation time 2047248429 ps
CPU time 1.3 seconds
Started Jan 10 12:31:52 PM PST 24
Finished Jan 10 12:32:40 PM PST 24
Peak memory 201184 kb
Host smart-d417f5ce-0cf0-4cfb-94ad-0c4fd0096069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085902947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te
st.1085902947
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2798132779
Short name T462
Test name
Test status
Simulation time 271128337920 ps
CPU time 266.95 seconds
Started Jan 10 12:31:39 PM PST 24
Finished Jan 10 12:36:56 PM PST 24
Peak memory 201416 kb
Host smart-4648c20a-c232-4e84-a215-b432014eb83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798132779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2
798132779
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.940820316
Short name T48
Test name
Test status
Simulation time 149394893625 ps
CPU time 44.86 seconds
Started Jan 10 12:42:54 PM PST 24
Finished Jan 10 12:44:51 PM PST 24
Peak memory 201560 kb
Host smart-3d774be3-8ea3-4da6-a05c-2339355d8b0b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940820316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_combo_detect.940820316
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.1389058892
Short name T54
Test name
Test status
Simulation time 137285645403 ps
CPU time 35.64 seconds
Started Jan 10 12:31:29 PM PST 24
Finished Jan 10 12:32:53 PM PST 24
Peak memory 201676 kb
Host smart-cff1a3e2-4680-4d93-86ab-3233ad2c9eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389058892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.1389058892
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.55567575
Short name T609
Test name
Test status
Simulation time 3685629314 ps
CPU time 2.76 seconds
Started Jan 10 12:58:13 PM PST 24
Finished Jan 10 12:59:35 PM PST 24
Peak memory 201308 kb
Host smart-ef461173-801f-41f6-9bd5-32436332969e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55567575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_ec_pwr_on_rst.55567575
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.792496475
Short name T634
Test name
Test status
Simulation time 2426592494 ps
CPU time 5.79 seconds
Started Jan 10 12:31:35 PM PST 24
Finished Jan 10 12:32:31 PM PST 24
Peak memory 201212 kb
Host smart-b0ed8a34-a8e6-4c07-8fb5-f7b32721fac4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792496475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctr
l_edge_detect.792496475
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2973116618
Short name T435
Test name
Test status
Simulation time 2651462979 ps
CPU time 1.61 seconds
Started Jan 10 12:31:31 PM PST 24
Finished Jan 10 12:32:22 PM PST 24
Peak memory 201256 kb
Host smart-fa803a9c-9dd8-4f53-acf4-1f2f2d21ba14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973116618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2973116618
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.895446289
Short name T470
Test name
Test status
Simulation time 2453968892 ps
CPU time 6.92 seconds
Started Jan 10 12:39:48 PM PST 24
Finished Jan 10 12:40:27 PM PST 24
Peak memory 201352 kb
Host smart-9c192a9e-3001-4a5f-82ab-6d9a6544d58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895446289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.895446289
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1551608465
Short name T409
Test name
Test status
Simulation time 2184680844 ps
CPU time 1.45 seconds
Started Jan 10 12:31:43 PM PST 24
Finished Jan 10 12:32:33 PM PST 24
Peak memory 201244 kb
Host smart-ae59aad2-3d1e-44c7-bf06-be4b1f9f8e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551608465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1551608465
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.464640185
Short name T192
Test name
Test status
Simulation time 2511222977 ps
CPU time 6.76 seconds
Started Jan 10 12:31:49 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 201356 kb
Host smart-01cc0ac5-8f5b-4647-a4ef-cbb15c93d33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464640185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.464640185
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.4196163616
Short name T725
Test name
Test status
Simulation time 2108115818 ps
CPU time 5.67 seconds
Started Jan 10 12:31:43 PM PST 24
Finished Jan 10 12:32:40 PM PST 24
Peak memory 201220 kb
Host smart-6348a023-bc33-4ee1-80c9-e2c5d20e9f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196163616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.4196163616
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.2830404348
Short name T734
Test name
Test status
Simulation time 421448096077 ps
CPU time 1004.97 seconds
Started Jan 10 12:31:35 PM PST 24
Finished Jan 10 12:49:11 PM PST 24
Peak memory 201384 kb
Host smart-99059242-cd78-4a87-ac42-068d5af071ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830404348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.2830404348
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.4018294804
Short name T72
Test name
Test status
Simulation time 95656805780 ps
CPU time 18.92 seconds
Started Jan 10 12:31:42 PM PST 24
Finished Jan 10 12:32:51 PM PST 24
Peak memory 217984 kb
Host smart-7a68239f-550d-495f-ac78-3184344498b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018294804 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.4018294804
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.2144470047
Short name T222
Test name
Test status
Simulation time 2046427042813 ps
CPU time 130.83 seconds
Started Jan 10 12:38:01 PM PST 24
Finished Jan 10 12:40:45 PM PST 24
Peak memory 201380 kb
Host smart-fc273f1f-3543-4d1a-80d4-7a37d25d31e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144470047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ultra_low_pwr.2144470047
Directory /workspace/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.1840382607
Short name T557
Test name
Test status
Simulation time 2010986741 ps
CPU time 6.2 seconds
Started Jan 10 12:32:57 PM PST 24
Finished Jan 10 12:33:18 PM PST 24
Peak memory 199604 kb
Host smart-bdb621b4-1713-46e2-b2c4-78e9418e59e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840382607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.1840382607
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.516596375
Short name T451
Test name
Test status
Simulation time 78669316692 ps
CPU time 194.54 seconds
Started Jan 10 12:31:38 PM PST 24
Finished Jan 10 12:35:42 PM PST 24
Peak memory 201236 kb
Host smart-c7953a73-32d5-41dc-acf2-ea303edf3140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516596375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.516596375
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.2400534999
Short name T686
Test name
Test status
Simulation time 131485458358 ps
CPU time 87.39 seconds
Started Jan 10 12:31:40 PM PST 24
Finished Jan 10 12:33:57 PM PST 24
Peak memory 201468 kb
Host smart-715df19c-c073-461c-aef0-3d8d037461bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400534999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_c
trl_combo_detect.2400534999
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1571842120
Short name T223
Test name
Test status
Simulation time 30083396059 ps
CPU time 36.18 seconds
Started Jan 10 12:31:37 PM PST 24
Finished Jan 10 12:33:04 PM PST 24
Peak memory 201668 kb
Host smart-e2759296-71dd-4951-8f1b-05dfb4500448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571842120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w
ith_pre_cond.1571842120
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1338552807
Short name T476
Test name
Test status
Simulation time 3125380865 ps
CPU time 8.87 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:32:44 PM PST 24
Peak memory 200668 kb
Host smart-31ac1d65-1164-4590-87bb-7fffb924315e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338552807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.1338552807
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3326899160
Short name T784
Test name
Test status
Simulation time 2481180634 ps
CPU time 1.85 seconds
Started Jan 10 12:31:33 PM PST 24
Finished Jan 10 12:32:25 PM PST 24
Peak memory 201328 kb
Host smart-f9995ed6-9876-471e-9e4b-d4760cc909ee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326899160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.3326899160
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.3853275118
Short name T687
Test name
Test status
Simulation time 2639153475 ps
CPU time 2.27 seconds
Started Jan 10 12:31:35 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 201324 kb
Host smart-f245259c-5f2f-4baa-80a9-12dfc6da90eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853275118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.3853275118
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.2248196529
Short name T795
Test name
Test status
Simulation time 2474630468 ps
CPU time 1.96 seconds
Started Jan 10 12:31:30 PM PST 24
Finished Jan 10 12:32:21 PM PST 24
Peak memory 201324 kb
Host smart-5126c476-6d85-4ccb-8098-04a19420fbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248196529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.2248196529
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3768908520
Short name T779
Test name
Test status
Simulation time 2167047440 ps
CPU time 1.81 seconds
Started Jan 10 12:31:40 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 201196 kb
Host smart-c4c45611-1bc6-4835-9378-e07d66afbcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768908520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3768908520
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.1948639461
Short name T715
Test name
Test status
Simulation time 2529306439 ps
CPU time 2.3 seconds
Started Jan 10 12:31:32 PM PST 24
Finished Jan 10 12:32:24 PM PST 24
Peak memory 201352 kb
Host smart-bdaed95e-a22e-4a7a-b79a-f6d351734336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948639461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.1948639461
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.4294465180
Short name T647
Test name
Test status
Simulation time 2115590890 ps
CPU time 3.22 seconds
Started Jan 10 12:31:37 PM PST 24
Finished Jan 10 12:32:31 PM PST 24
Peak memory 201296 kb
Host smart-2f4d16f4-3a57-4d07-ada0-03734a1e51d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294465180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.4294465180
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.475967319
Short name T196
Test name
Test status
Simulation time 9916647353 ps
CPU time 13.2 seconds
Started Jan 10 12:33:13 PM PST 24
Finished Jan 10 12:33:28 PM PST 24
Peak memory 200852 kb
Host smart-c6a640a8-f5c7-444b-a90c-d09be907f360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475967319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_st
ress_all.475967319
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.1690944793
Short name T314
Test name
Test status
Simulation time 570685264438 ps
CPU time 107.97 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:34:22 PM PST 24
Peak memory 209960 kb
Host smart-3e8f8d46-4d73-4e26-9eb3-96c625a54b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690944793 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.1690944793
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3541809475
Short name T134
Test name
Test status
Simulation time 3388881328 ps
CPU time 7.28 seconds
Started Jan 10 12:31:26 PM PST 24
Finished Jan 10 12:32:22 PM PST 24
Peak memory 201032 kb
Host smart-4c515073-af6e-4179-b450-66a9c632401d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541809475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.3541809475
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.2796799944
Short name T519
Test name
Test status
Simulation time 2158205103 ps
CPU time 0.91 seconds
Started Jan 10 12:31:34 PM PST 24
Finished Jan 10 12:32:26 PM PST 24
Peak memory 201300 kb
Host smart-93e7adc1-9d48-4271-ad51-0dff560be2b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796799944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.2796799944
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3298515883
Short name T622
Test name
Test status
Simulation time 31913057529 ps
CPU time 85.3 seconds
Started Jan 10 12:33:30 PM PST 24
Finished Jan 10 12:35:01 PM PST 24
Peak memory 201260 kb
Host smart-ee7bc4b7-01a3-436c-ac17-403b76c8b5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298515883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.3
298515883
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.3807158377
Short name T252
Test name
Test status
Simulation time 30209773539 ps
CPU time 22.16 seconds
Started Jan 10 12:33:32 PM PST 24
Finished Jan 10 12:34:00 PM PST 24
Peak memory 201356 kb
Host smart-03d8a237-2bba-4782-8a73-5f4ea3b869cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807158377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.3807158377
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4167140049
Short name T627
Test name
Test status
Simulation time 1602550925597 ps
CPU time 388.24 seconds
Started Jan 10 12:32:02 PM PST 24
Finished Jan 10 12:39:17 PM PST 24
Peak memory 201272 kb
Host smart-84705357-c0ed-4d7c-9d4d-6a0db0976397
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167140049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.4167140049
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.1135940098
Short name T167
Test name
Test status
Simulation time 3470742209 ps
CPU time 2.81 seconds
Started Jan 10 12:33:32 PM PST 24
Finished Jan 10 12:33:40 PM PST 24
Peak memory 201180 kb
Host smart-51408a87-f318-4ed1-a66c-76fe1363cd85
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135940098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.1135940098
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3827841352
Short name T437
Test name
Test status
Simulation time 2612389926 ps
CPU time 7.3 seconds
Started Jan 10 12:33:08 PM PST 24
Finished Jan 10 12:33:22 PM PST 24
Peak memory 199968 kb
Host smart-52d75b46-8c49-4b30-8b4e-543e9bcfd2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827841352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3827841352
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.2086586493
Short name T75
Test name
Test status
Simulation time 2483985138 ps
CPU time 2.23 seconds
Started Jan 10 12:33:37 PM PST 24
Finished Jan 10 12:33:59 PM PST 24
Peak memory 201180 kb
Host smart-abcc2de5-85b4-4311-9c6d-04ed305915bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086586493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.2086586493
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2238195538
Short name T682
Test name
Test status
Simulation time 2114388360 ps
CPU time 5.72 seconds
Started Jan 10 12:31:45 PM PST 24
Finished Jan 10 12:32:39 PM PST 24
Peak memory 201180 kb
Host smart-c7d50935-d014-412d-9874-3313a32a9af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238195538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.2238195538
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.2306240859
Short name T543
Test name
Test status
Simulation time 2508704888 ps
CPU time 6.92 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:32:54 PM PST 24
Peak memory 201212 kb
Host smart-b5b4fb3a-3dd4-4ea5-8ae0-3766c329b7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306240859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.2306240859
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.1067395236
Short name T459
Test name
Test status
Simulation time 2122100631 ps
CPU time 1.97 seconds
Started Jan 10 12:31:38 PM PST 24
Finished Jan 10 12:32:30 PM PST 24
Peak memory 201184 kb
Host smart-c4446a73-30bc-45bd-bc6e-8af76b4a17c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067395236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1067395236
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.2550921895
Short name T20
Test name
Test status
Simulation time 15414660470 ps
CPU time 38.86 seconds
Started Jan 10 12:33:13 PM PST 24
Finished Jan 10 12:33:54 PM PST 24
Peak memory 200832 kb
Host smart-00e292ab-9152-4dc1-b8d8-e9d6796dc609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550921895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.2550921895
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2727410178
Short name T595
Test name
Test status
Simulation time 14016124224 ps
CPU time 36.4 seconds
Started Jan 10 12:31:37 PM PST 24
Finished Jan 10 12:33:03 PM PST 24
Peak memory 209952 kb
Host smart-82d6080b-5936-4e69-a3b6-39de2ea96b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727410178 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2727410178
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.1504165386
Short name T799
Test name
Test status
Simulation time 5221271570 ps
CPU time 3.61 seconds
Started Jan 10 12:31:30 PM PST 24
Finished Jan 10 12:32:23 PM PST 24
Peak memory 201248 kb
Host smart-9503f284-44f5-4087-b00b-a0eab55f5885
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504165386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ultra_low_pwr.1504165386
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.369455573
Short name T418
Test name
Test status
Simulation time 2013322213 ps
CPU time 5.35 seconds
Started Jan 10 12:31:42 PM PST 24
Finished Jan 10 12:32:37 PM PST 24
Peak memory 201184 kb
Host smart-0b13188b-bd48-43de-b696-ad7e3273682f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369455573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_tes
t.369455573
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2542173869
Short name T453
Test name
Test status
Simulation time 3587291023 ps
CPU time 2.84 seconds
Started Jan 10 12:31:43 PM PST 24
Finished Jan 10 12:32:37 PM PST 24
Peak memory 201328 kb
Host smart-e5bc97e0-d302-4289-a845-af2ca3470865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542173869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2
542173869
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.3685244010
Short name T111
Test name
Test status
Simulation time 162909190690 ps
CPU time 96.63 seconds
Started Jan 10 12:31:59 PM PST 24
Finished Jan 10 12:34:22 PM PST 24
Peak memory 201424 kb
Host smart-3ace5c33-e3ba-4db4-828e-f0bcadd8c593
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685244010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.3685244010
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3643512519
Short name T164
Test name
Test status
Simulation time 3718712008 ps
CPU time 5.83 seconds
Started Jan 10 12:33:13 PM PST 24
Finished Jan 10 12:33:21 PM PST 24
Peak memory 200992 kb
Host smart-d0ebc30d-76b5-4ffa-b4d6-53ac83be4cee
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643512519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.3643512519
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.1565869073
Short name T636
Test name
Test status
Simulation time 3018720683 ps
CPU time 2.4 seconds
Started Jan 10 12:31:52 PM PST 24
Finished Jan 10 12:32:41 PM PST 24
Peak memory 201228 kb
Host smart-8ddd0528-3eb4-4fbc-8d82-08afd459676c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565869073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.1565869073
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1825225881
Short name T618
Test name
Test status
Simulation time 2611175035 ps
CPU time 7.43 seconds
Started Jan 10 12:33:08 PM PST 24
Finished Jan 10 12:33:22 PM PST 24
Peak memory 200036 kb
Host smart-c91b3f1d-ea30-42fb-be47-4c71bbe6516a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825225881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1825225881
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.253052212
Short name T648
Test name
Test status
Simulation time 2458175975 ps
CPU time 3.6 seconds
Started Jan 10 12:33:13 PM PST 24
Finished Jan 10 12:33:18 PM PST 24
Peak memory 200988 kb
Host smart-9643fe21-5d2a-4b9a-9798-304f3d47001a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253052212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.253052212
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2350868071
Short name T568
Test name
Test status
Simulation time 2071557726 ps
CPU time 3.43 seconds
Started Jan 10 12:32:57 PM PST 24
Finished Jan 10 12:33:16 PM PST 24
Peak memory 199624 kb
Host smart-c293aafc-d97b-4152-be44-913ec3b8a256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350868071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2350868071
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.707724809
Short name T573
Test name
Test status
Simulation time 2580545249 ps
CPU time 1.31 seconds
Started Jan 10 12:33:13 PM PST 24
Finished Jan 10 12:33:16 PM PST 24
Peak memory 201016 kb
Host smart-f0cae800-c098-4f2e-b3c3-eba01f6b7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707724809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.707724809
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.3493592700
Short name T763
Test name
Test status
Simulation time 2116750388 ps
CPU time 3.38 seconds
Started Jan 10 12:33:30 PM PST 24
Finished Jan 10 12:33:39 PM PST 24
Peak memory 201112 kb
Host smart-76e13161-02ee-4bcc-96d5-cec52965d247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493592700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3493592700
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.2278445574
Short name T849
Test name
Test status
Simulation time 6769885219 ps
CPU time 16.92 seconds
Started Jan 10 12:31:52 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 201308 kb
Host smart-30b0a80f-70d0-4750-b8c5-11050f8798e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278445574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.2278445574
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.932327594
Short name T206
Test name
Test status
Simulation time 76136319143 ps
CPU time 36.36 seconds
Started Jan 10 12:32:11 PM PST 24
Finished Jan 10 12:33:30 PM PST 24
Peak memory 209944 kb
Host smart-fc9d3988-34e0-4b77-abea-6696164ca613
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932327594 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.932327594
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.410379340
Short name T87
Test name
Test status
Simulation time 5137986833 ps
CPU time 6.97 seconds
Started Jan 10 12:31:43 PM PST 24
Finished Jan 10 12:32:39 PM PST 24
Peak memory 201244 kb
Host smart-49984344-7d61-48ab-908c-07f548cc2bf9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410379340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_ultra_low_pwr.410379340
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.2761026678
Short name T492
Test name
Test status
Simulation time 2039280256 ps
CPU time 1.68 seconds
Started Jan 10 12:32:16 PM PST 24
Finished Jan 10 12:32:58 PM PST 24
Peak memory 201252 kb
Host smart-d37760eb-5889-4913-8b89-d6b936c99ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761026678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.2761026678
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1556075700
Short name T481
Test name
Test status
Simulation time 3546307049 ps
CPU time 2.91 seconds
Started Jan 10 12:31:50 PM PST 24
Finished Jan 10 12:32:40 PM PST 24
Peak memory 201332 kb
Host smart-7bbe0042-2df5-4da7-be43-1d53a4d4fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556075700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.1
556075700
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.922393739
Short name T744
Test name
Test status
Simulation time 131485191488 ps
CPU time 350.04 seconds
Started Jan 10 12:31:58 PM PST 24
Finished Jan 10 12:38:34 PM PST 24
Peak memory 201456 kb
Host smart-ddd44f21-09ba-4061-845c-b071969fd3e5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922393739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_combo_detect.922393739
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1434699529
Short name T327
Test name
Test status
Simulation time 54754163431 ps
CPU time 148.39 seconds
Started Jan 10 12:31:50 PM PST 24
Finished Jan 10 12:35:05 PM PST 24
Peak memory 201576 kb
Host smart-dd79ad79-53ea-47c9-9e2d-b65617820835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434699529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.1434699529
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3635807408
Short name T150
Test name
Test status
Simulation time 4493302587 ps
CPU time 3.56 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:32:37 PM PST 24
Peak memory 201224 kb
Host smart-4a3c2e52-c8e7-42b9-b96e-704737291779
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635807408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.3635807408
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.136553728
Short name T237
Test name
Test status
Simulation time 3911039197 ps
CPU time 1.79 seconds
Started Jan 10 12:32:00 PM PST 24
Finished Jan 10 12:32:48 PM PST 24
Peak memory 201244 kb
Host smart-dfb58ad5-2b21-46bb-9201-36b4c4de0b52
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136553728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctr
l_edge_detect.136553728
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.519981971
Short name T766
Test name
Test status
Simulation time 2614841659 ps
CPU time 3.91 seconds
Started Jan 10 12:31:34 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 201300 kb
Host smart-25320867-1b03-474b-bf7a-0c5fb65f023a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519981971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.519981971
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2074457968
Short name T66
Test name
Test status
Simulation time 2492905717 ps
CPU time 2.11 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 201248 kb
Host smart-6d450d23-2387-42d6-996d-3f47ed70f9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074457968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2074457968
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.1666403703
Short name T529
Test name
Test status
Simulation time 2101981357 ps
CPU time 2.45 seconds
Started Jan 10 12:31:40 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 201272 kb
Host smart-b3478b5a-c70c-4291-8573-70018fac9d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666403703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1666403703
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.613283286
Short name T457
Test name
Test status
Simulation time 2536729309 ps
CPU time 2.3 seconds
Started Jan 10 12:32:05 PM PST 24
Finished Jan 10 12:32:53 PM PST 24
Peak memory 201348 kb
Host smart-401849f5-06a3-4155-8978-d043de977ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613283286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.613283286
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.1915947718
Short name T30
Test name
Test status
Simulation time 2118565125 ps
CPU time 3.47 seconds
Started Jan 10 12:31:37 PM PST 24
Finished Jan 10 12:32:31 PM PST 24
Peak memory 201188 kb
Host smart-69371297-4e6b-44fb-aafe-34a4c686a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915947718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1915947718
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.2000715203
Short name T768
Test name
Test status
Simulation time 14727209524 ps
CPU time 39.28 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:33:20 PM PST 24
Peak memory 201300 kb
Host smart-1b322fc9-25a3-4d3a-9d8d-8bc230b467ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000715203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.2000715203
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.560371204
Short name T351
Test name
Test status
Simulation time 64160957516 ps
CPU time 24.36 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:55 PM PST 24
Peak memory 209376 kb
Host smart-b44c6dbc-5eb5-4d53-9806-ff93fa5369aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560371204 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.560371204
Directory /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3081883601
Short name T131
Test name
Test status
Simulation time 3250800666 ps
CPU time 1.85 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:32:37 PM PST 24
Peak memory 201244 kb
Host smart-d8cbaef8-ad44-41a1-933f-5da481c6d3b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081883601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3081883601
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.250075244
Short name T115
Test name
Test status
Simulation time 2118680724 ps
CPU time 1.02 seconds
Started Jan 10 12:32:01 PM PST 24
Finished Jan 10 12:32:48 PM PST 24
Peak memory 201244 kb
Host smart-f62abc4a-5f25-4d71-aca5-d9a781d2c329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250075244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_tes
t.250075244
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3512876996
Short name T619
Test name
Test status
Simulation time 3623584158 ps
CPU time 1.61 seconds
Started Jan 10 12:31:42 PM PST 24
Finished Jan 10 12:32:34 PM PST 24
Peak memory 201336 kb
Host smart-963a5c5f-8c52-454f-bf5b-60abfbf7b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512876996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3
512876996
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.4228652499
Short name T642
Test name
Test status
Simulation time 51693614072 ps
CPU time 125.49 seconds
Started Jan 10 12:31:51 PM PST 24
Finished Jan 10 12:34:43 PM PST 24
Peak memory 201640 kb
Host smart-db6c56fb-5885-4596-bdd9-4afc879c5bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228652499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.4228652499
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3675145325
Short name T465
Test name
Test status
Simulation time 2575283744 ps
CPU time 2.18 seconds
Started Jan 10 12:32:14 PM PST 24
Finished Jan 10 12:32:58 PM PST 24
Peak memory 201260 kb
Host smart-e9e58b0b-f69e-4f55-bc47-cbec84eae58f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675145325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.3675145325
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3463281566
Short name T185
Test name
Test status
Simulation time 4080696049 ps
CPU time 6.02 seconds
Started Jan 10 12:31:36 PM PST 24
Finished Jan 10 12:32:32 PM PST 24
Peak memory 201320 kb
Host smart-c5bed1b3-6630-4ea9-ab62-8adc27baa572
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463281566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.3463281566
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1042045334
Short name T439
Test name
Test status
Simulation time 2612070722 ps
CPU time 6.87 seconds
Started Jan 10 12:31:50 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 201216 kb
Host smart-48778678-6ad2-44c5-9659-a25a8e017f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042045334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1042045334
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.4001821529
Short name T765
Test name
Test status
Simulation time 2475399410 ps
CPU time 4.22 seconds
Started Jan 10 12:31:34 PM PST 24
Finished Jan 10 12:32:28 PM PST 24
Peak memory 201252 kb
Host smart-32b481ba-4ff4-4731-b88c-e9a32ac2e11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001821529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.4001821529
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1723800396
Short name T423
Test name
Test status
Simulation time 2191630657 ps
CPU time 6.32 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:37 PM PST 24
Peak memory 200796 kb
Host smart-46ce0c49-a1a4-4859-9edf-31aee1c64e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723800396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.1723800396
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.152120481
Short name T528
Test name
Test status
Simulation time 2523405802 ps
CPU time 2.38 seconds
Started Jan 10 12:32:14 PM PST 24
Finished Jan 10 12:32:58 PM PST 24
Peak memory 201220 kb
Host smart-a60f8bfc-f637-4bee-abb6-00f107cf5347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152120481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.152120481
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.1739072917
Short name T776
Test name
Test status
Simulation time 2150651728 ps
CPU time 1.54 seconds
Started Jan 10 12:31:54 PM PST 24
Finished Jan 10 12:32:42 PM PST 24
Peak memory 201364 kb
Host smart-8a4bc243-4826-43ad-86e1-7a99726cebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739072917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1739072917
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.137907720
Short name T53
Test name
Test status
Simulation time 128297178176 ps
CPU time 316.67 seconds
Started Jan 10 12:31:48 PM PST 24
Finished Jan 10 12:37:52 PM PST 24
Peak memory 200800 kb
Host smart-e7d80b9e-939a-42c9-bb5e-c1aaa5d7cf3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137907720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_st
ress_all.137907720
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2789834194
Short name T545
Test name
Test status
Simulation time 24043536288 ps
CPU time 15.26 seconds
Started Jan 10 12:31:39 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 209860 kb
Host smart-02a426b7-8cf7-46fa-832e-6ada6d8e3537
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789834194 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2789834194
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.3185930373
Short name T704
Test name
Test status
Simulation time 2026738382 ps
CPU time 1.86 seconds
Started Jan 10 12:31:50 PM PST 24
Finished Jan 10 12:32:39 PM PST 24
Peak memory 201300 kb
Host smart-0ca00326-be46-4b19-8540-0f10c95d8d21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185930373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.3185930373
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.974428761
Short name T827
Test name
Test status
Simulation time 3313435843 ps
CPU time 9.44 seconds
Started Jan 10 12:41:01 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 201360 kb
Host smart-697e52a3-9066-4bd4-8f41-8442ac10ae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974428761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.974428761
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.415226375
Short name T726
Test name
Test status
Simulation time 101299219782 ps
CPU time 137.64 seconds
Started Jan 10 12:46:58 PM PST 24
Finished Jan 10 12:50:33 PM PST 24
Peak memory 201580 kb
Host smart-5f9d5424-7008-4c35-a7a0-abd9d25c7749
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415226375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_combo_detect.415226375
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3844749516
Short name T323
Test name
Test status
Simulation time 180772225662 ps
CPU time 129.24 seconds
Started Jan 10 12:31:49 PM PST 24
Finished Jan 10 12:34:46 PM PST 24
Peak memory 201592 kb
Host smart-ba963f38-5911-4fd3-b7cd-311b0b85bde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844749516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.3844749516
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3168118939
Short name T226
Test name
Test status
Simulation time 3071257552 ps
CPU time 2.45 seconds
Started Jan 10 12:32:05 PM PST 24
Finished Jan 10 12:32:53 PM PST 24
Peak memory 201244 kb
Host smart-a42fa2f2-1ad4-4a8a-88c7-5703da8b793a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168118939 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.3168118939
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.4269105886
Short name T239
Test name
Test status
Simulation time 4172192137 ps
CPU time 10.35 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:32:59 PM PST 24
Peak memory 201268 kb
Host smart-800de253-33d3-4da3-b4b8-50113242159b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269105886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.4269105886
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.884746024
Short name T727
Test name
Test status
Simulation time 2612753812 ps
CPU time 5.18 seconds
Started Jan 10 12:31:55 PM PST 24
Finished Jan 10 12:32:47 PM PST 24
Peak memory 201276 kb
Host smart-32322c0c-0e28-4637-8099-90458fb0e927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884746024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.884746024
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2365586336
Short name T181
Test name
Test status
Simulation time 2472477042 ps
CPU time 3.7 seconds
Started Jan 10 12:31:46 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 201272 kb
Host smart-6ce6823d-19e0-4315-a097-0fa699a4d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365586336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2365586336
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.3773857778
Short name T710
Test name
Test status
Simulation time 2222676274 ps
CPU time 6.3 seconds
Started Jan 10 12:32:03 PM PST 24
Finished Jan 10 12:32:55 PM PST 24
Peak memory 201240 kb
Host smart-1ee4f720-d284-4e46-af25-552951ce37f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773857778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.3773857778
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1796897222
Short name T708
Test name
Test status
Simulation time 2516957525 ps
CPU time 4 seconds
Started Jan 10 12:32:07 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 201240 kb
Host smart-d59cea46-979c-44be-a1ed-9365be78e887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796897222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1796897222
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.3780628994
Short name T653
Test name
Test status
Simulation time 2109704366 ps
CPU time 6.29 seconds
Started Jan 10 12:31:55 PM PST 24
Finished Jan 10 12:32:48 PM PST 24
Peak memory 201328 kb
Host smart-c29a0ead-0b18-4abc-b189-537b53a3dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780628994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3780628994
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.4102044657
Short name T699
Test name
Test status
Simulation time 6398561997 ps
CPU time 15.56 seconds
Started Jan 10 12:31:41 PM PST 24
Finished Jan 10 12:32:47 PM PST 24
Peak memory 201264 kb
Host smart-f2524b57-1d64-4c25-99ad-8136bb1ea44d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102044657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.4102044657
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.981329072
Short name T756
Test name
Test status
Simulation time 134096395821 ps
CPU time 87.74 seconds
Started Jan 10 12:31:49 PM PST 24
Finished Jan 10 12:34:04 PM PST 24
Peak memory 201620 kb
Host smart-cd2d9329-3ed3-4a78-883c-964989f33781
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981329072 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.981329072
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.1488838074
Short name T637
Test name
Test status
Simulation time 1282898936687 ps
CPU time 6.06 seconds
Started Jan 10 12:31:47 PM PST 24
Finished Jan 10 12:32:41 PM PST 24
Peak memory 201252 kb
Host smart-897706fb-de40-44cf-ab03-6ba4f3c16ef3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488838074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.1488838074
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.2182465179
Short name T605
Test name
Test status
Simulation time 2032229445 ps
CPU time 1.97 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:34 PM PST 24
Peak memory 201556 kb
Host smart-446d6245-4b4b-4519-8c77-244b6ae981d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182465179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.2182465179
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1911816410
Short name T705
Test name
Test status
Simulation time 3732411779 ps
CPU time 1.15 seconds
Started Jan 10 12:30:40 PM PST 24
Finished Jan 10 12:31:24 PM PST 24
Peak memory 201220 kb
Host smart-537d453a-005b-4b99-ae9a-0af2f6a0e9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911816410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1911816410
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.2453558780
Short name T235
Test name
Test status
Simulation time 133176166509 ps
CPU time 180.27 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:34:35 PM PST 24
Peak memory 201544 kb
Host smart-6f9a62ba-cf12-4daf-9a9d-463a47fa973d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453558780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.2453558780
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1597533645
Short name T685
Test name
Test status
Simulation time 2427274406 ps
CPU time 6.44 seconds
Started Jan 10 12:30:17 PM PST 24
Finished Jan 10 12:31:02 PM PST 24
Peak memory 201256 kb
Host smart-49e54e1d-de0a-44f8-8ec9-b66eeb4028f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597533645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.1597533645
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.857904566
Short name T62
Test name
Test status
Simulation time 2531553999 ps
CPU time 2.49 seconds
Started Jan 10 12:30:04 PM PST 24
Finished Jan 10 12:30:48 PM PST 24
Peak memory 201248 kb
Host smart-70504fb7-183c-4b91-a2e4-a4660dddb2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857904566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.857904566
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2110018289
Short name T675
Test name
Test status
Simulation time 39219439278 ps
CPU time 19.21 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:31:53 PM PST 24
Peak memory 201460 kb
Host smart-fccf9039-7713-4e38-832d-0c6cf2b073c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110018289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi
th_pre_cond.2110018289
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.1885221483
Short name T433
Test name
Test status
Simulation time 5498842624 ps
CPU time 14.72 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:43 PM PST 24
Peak memory 201184 kb
Host smart-778ee8a7-4ef0-4d97-8135-1eef9b32c49a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885221483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.1885221483
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3025095014
Short name T91
Test name
Test status
Simulation time 5423731957 ps
CPU time 2.86 seconds
Started Jan 10 12:30:43 PM PST 24
Finished Jan 10 12:31:29 PM PST 24
Peak memory 201268 kb
Host smart-fb677cb3-83f9-48a1-bc9b-4eb3705e5fb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025095014 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.3025095014
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3478912754
Short name T67
Test name
Test status
Simulation time 2621655059 ps
CPU time 4.21 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:36 PM PST 24
Peak memory 201244 kb
Host smart-903e6e57-01a9-4c55-a368-041acf760188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478912754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3478912754
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.1251979664
Short name T460
Test name
Test status
Simulation time 2480789869 ps
CPU time 2.24 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:18 PM PST 24
Peak memory 201264 kb
Host smart-ca675120-a9ff-4c6a-b2c6-771499374e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251979664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1251979664
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.1959695759
Short name T544
Test name
Test status
Simulation time 2068361092 ps
CPU time 3.23 seconds
Started Jan 10 12:30:31 PM PST 24
Finished Jan 10 12:31:17 PM PST 24
Peak memory 201180 kb
Host smart-39d03cca-c23c-4883-a9d0-2ae34d64d38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959695759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.1959695759
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1927850234
Short name T790
Test name
Test status
Simulation time 2532428064 ps
CPU time 1.82 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:29 PM PST 24
Peak memory 201224 kb
Host smart-5453e9d9-80d2-4766-a94b-eddd88590c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927850234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1927850234
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2129515246
Short name T272
Test name
Test status
Simulation time 42080492396 ps
CPU time 38.88 seconds
Started Jan 10 12:30:41 PM PST 24
Finished Jan 10 12:32:03 PM PST 24
Peak memory 221188 kb
Host smart-b5e0af40-f249-4815-90f0-f12270a8aaff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129515246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.2129515246
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.3353727906
Short name T539
Test name
Test status
Simulation time 2111692343 ps
CPU time 6.23 seconds
Started Jan 10 12:30:27 PM PST 24
Finished Jan 10 12:31:14 PM PST 24
Peak memory 201188 kb
Host smart-b9ef1a81-6fad-4bd9-8c92-5ba3f5df18d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353727906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.3353727906
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.3051375335
Short name T762
Test name
Test status
Simulation time 8206443299 ps
CPU time 2.43 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:31:27 PM PST 24
Peak memory 201200 kb
Host smart-6b2a85db-1fe5-47d6-9fb0-9f94a529a0ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051375335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.3051375335
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4163216838
Short name T88
Test name
Test status
Simulation time 1140159025019 ps
CPU time 31.33 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:59 PM PST 24
Peak memory 218076 kb
Host smart-c3fa6d8e-32ff-4d84-bc74-53ac62ecb4ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163216838 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.4163216838
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2942759631
Short name T643
Test name
Test status
Simulation time 4009044910 ps
CPU time 6.53 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:34 PM PST 24
Peak memory 201304 kb
Host smart-82359994-db0a-4e0a-9d23-5a13983d48b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942759631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2942759631
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.290889371
Short name T424
Test name
Test status
Simulation time 2028380236 ps
CPU time 2.61 seconds
Started Jan 10 12:41:38 PM PST 24
Finished Jan 10 12:42:46 PM PST 24
Peak memory 201256 kb
Host smart-5dd21653-4b9c-4fa2-b5ac-33ebf6b0ca66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290889371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_tes
t.290889371
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.861707399
Short name T101
Test name
Test status
Simulation time 200832632697 ps
CPU time 499.55 seconds
Started Jan 10 12:32:05 PM PST 24
Finished Jan 10 12:41:11 PM PST 24
Peak memory 201268 kb
Host smart-8bebda09-6b71-43be-b21e-caa0d7d9d26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861707399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.861707399
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2790791261
Short name T215
Test name
Test status
Simulation time 67500553197 ps
CPU time 83.61 seconds
Started Jan 10 12:31:38 PM PST 24
Finished Jan 10 12:33:52 PM PST 24
Peak memory 201596 kb
Host smart-4b26beb4-b72f-45e9-a6a0-1b4b6f343f4d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790791261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.2790791261
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1441085080
Short name T258
Test name
Test status
Simulation time 39817462284 ps
CPU time 20.88 seconds
Started Jan 10 12:38:46 PM PST 24
Finished Jan 10 12:39:41 PM PST 24
Peak memory 201732 kb
Host smart-17775bba-4382-493b-9a84-3a50ffae3a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441085080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w
ith_pre_cond.1441085080
Directory /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.344097943
Short name T501
Test name
Test status
Simulation time 4813805172 ps
CPU time 3.54 seconds
Started Jan 10 12:32:00 PM PST 24
Finished Jan 10 12:32:50 PM PST 24
Peak memory 201336 kb
Host smart-f5c1b929-aa82-48c4-83b7-9a25e2a00b69
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344097943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_ec_pwr_on_rst.344097943
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3145228488
Short name T229
Test name
Test status
Simulation time 2636526248 ps
CPU time 6.42 seconds
Started Jan 10 12:41:12 PM PST 24
Finished Jan 10 12:42:19 PM PST 24
Peak memory 201336 kb
Host smart-013855bf-e925-4bd8-8a3a-220b8fc044e3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145228488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.3145228488
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1717541621
Short name T546
Test name
Test status
Simulation time 2636791614 ps
CPU time 2.49 seconds
Started Jan 10 12:59:00 PM PST 24
Finished Jan 10 01:00:33 PM PST 24
Peak memory 201316 kb
Host smart-e1be802e-1b47-494b-95f5-e7cede085217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717541621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1717541621
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1696297887
Short name T751
Test name
Test status
Simulation time 2480690974 ps
CPU time 3.79 seconds
Started Jan 10 12:31:49 PM PST 24
Finished Jan 10 12:32:40 PM PST 24
Peak memory 201176 kb
Host smart-72e30754-9c40-4a79-933d-82b37f33b8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696297887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1696297887
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3671159134
Short name T735
Test name
Test status
Simulation time 2029967365 ps
CPU time 6.16 seconds
Started Jan 10 12:32:05 PM PST 24
Finished Jan 10 12:32:58 PM PST 24
Peak memory 201144 kb
Host smart-5a2f9705-12e3-4848-8df8-c01b83388ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671159134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3671159134
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1178811034
Short name T672
Test name
Test status
Simulation time 2512555720 ps
CPU time 7.72 seconds
Started Jan 10 12:32:02 PM PST 24
Finished Jan 10 12:32:56 PM PST 24
Peak memory 201244 kb
Host smart-0106af97-841b-47f4-9024-d3c47d2e749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178811034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1178811034
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.1878430804
Short name T525
Test name
Test status
Simulation time 2111520853 ps
CPU time 5.71 seconds
Started Jan 10 01:16:08 PM PST 24
Finished Jan 10 01:16:41 PM PST 24
Peak memory 201316 kb
Host smart-1b7c2bd7-9917-44e3-a949-cd726c1cc6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878430804 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1878430804
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.1723139894
Short name T723
Test name
Test status
Simulation time 9978671176 ps
CPU time 24.07 seconds
Started Jan 10 12:51:17 PM PST 24
Finished Jan 10 12:53:00 PM PST 24
Peak memory 201468 kb
Host smart-f99a71cd-d408-4955-a82c-deaa32386a20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723139894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.1723139894
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.4084672217
Short name T548
Test name
Test status
Simulation time 6107197789 ps
CPU time 1.32 seconds
Started Jan 10 12:55:16 PM PST 24
Finished Jan 10 12:56:25 PM PST 24
Peak memory 201312 kb
Host smart-5d44f00e-8c1c-465d-b3fb-830d69eea4ff
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084672217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ultra_low_pwr.4084672217
Directory /workspace/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.321599410
Short name T815
Test name
Test status
Simulation time 2014620438 ps
CPU time 5.63 seconds
Started Jan 10 12:34:50 PM PST 24
Finished Jan 10 12:35:37 PM PST 24
Peak memory 201344 kb
Host smart-33580d06-1875-467c-a265-fe5dce0033bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321599410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_tes
t.321599410
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3630879789
Short name T436
Test name
Test status
Simulation time 3584125334 ps
CPU time 3.22 seconds
Started Jan 10 12:44:28 PM PST 24
Finished Jan 10 12:45:48 PM PST 24
Peak memory 201460 kb
Host smart-f25dd7a5-c7a8-43dd-8c75-1870ea5b2674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630879789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
630879789
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.1874877742
Short name T158
Test name
Test status
Simulation time 171712674470 ps
CPU time 106.55 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:43:19 PM PST 24
Peak memory 201500 kb
Host smart-c0b6cc42-bdb0-4831-83ab-e82ea4d194c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874877742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.1874877742
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.2312523919
Short name T329
Test name
Test status
Simulation time 47410671298 ps
CPU time 113.75 seconds
Started Jan 10 12:58:15 PM PST 24
Finished Jan 10 01:01:30 PM PST 24
Peak memory 201692 kb
Host smart-8a440a1e-0d84-4e0c-a31d-8c57a864f01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312523919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.2312523919
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3611658312
Short name T496
Test name
Test status
Simulation time 4490166701 ps
CPU time 3.11 seconds
Started Jan 10 12:48:45 PM PST 24
Finished Jan 10 12:50:15 PM PST 24
Peak memory 201348 kb
Host smart-befa6b86-000c-4520-a490-928c6e1de649
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611658312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3611658312
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.179182134
Short name T822
Test name
Test status
Simulation time 2750415431 ps
CPU time 6.73 seconds
Started Jan 10 12:38:52 PM PST 24
Finished Jan 10 12:39:30 PM PST 24
Peak memory 201348 kb
Host smart-03fa2ac4-6b6f-4fbd-87b9-5c5ba233aa83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179182134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctr
l_edge_detect.179182134
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1968593726
Short name T542
Test name
Test status
Simulation time 2612157256 ps
CPU time 7.66 seconds
Started Jan 10 12:44:15 PM PST 24
Finished Jan 10 12:45:38 PM PST 24
Peak memory 201380 kb
Host smart-a865937d-9f63-4be9-9b87-0f2277828a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968593726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.1968593726
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1995793430
Short name T570
Test name
Test status
Simulation time 2495001821 ps
CPU time 1.92 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:34 PM PST 24
Peak memory 201316 kb
Host smart-5a5c4901-0ab0-4809-9c42-5355de167774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995793430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1995793430
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.3734176803
Short name T171
Test name
Test status
Simulation time 2259690547 ps
CPU time 2.13 seconds
Started Jan 10 12:52:55 PM PST 24
Finished Jan 10 12:54:10 PM PST 24
Peak memory 201348 kb
Host smart-0ce31089-24f9-40a5-8b6e-0543c41699ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734176803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3734176803
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.4065380074
Short name T819
Test name
Test status
Simulation time 2538690126 ps
CPU time 2.24 seconds
Started Jan 10 12:36:14 PM PST 24
Finished Jan 10 12:36:49 PM PST 24
Peak memory 201240 kb
Host smart-dca19778-d1ff-4337-86b1-b79725197441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065380074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.4065380074
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3201317472
Short name T626
Test name
Test status
Simulation time 2132831849 ps
CPU time 2.11 seconds
Started Jan 10 12:45:07 PM PST 24
Finished Jan 10 12:46:32 PM PST 24
Peak memory 201288 kb
Host smart-adb992aa-0836-48c2-96f5-0d5130936a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201317472 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3201317472
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.601553496
Short name T615
Test name
Test status
Simulation time 10519982726 ps
CPU time 14.11 seconds
Started Jan 10 12:58:22 PM PST 24
Finished Jan 10 12:59:56 PM PST 24
Peak memory 201364 kb
Host smart-21914839-0093-4767-adea-140f90121e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601553496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_st
ress_all.601553496
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.74596242
Short name T93
Test name
Test status
Simulation time 32542508029 ps
CPU time 68.48 seconds
Started Jan 10 12:40:48 PM PST 24
Finished Jan 10 12:42:44 PM PST 24
Peak memory 210000 kb
Host smart-d4c9eb3c-d02a-48e4-a45b-bebae9d72447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74596242 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.74596242
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2333275610
Short name T165
Test name
Test status
Simulation time 4317260696 ps
CPU time 2.32 seconds
Started Jan 10 12:45:45 PM PST 24
Finished Jan 10 12:47:07 PM PST 24
Peak memory 201368 kb
Host smart-5a4ee09a-3264-4d71-b75d-81a21232de95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333275610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.2333275610
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.3259082557
Short name T535
Test name
Test status
Simulation time 2029044628 ps
CPU time 1.84 seconds
Started Jan 10 01:16:45 PM PST 24
Finished Jan 10 01:17:46 PM PST 24
Peak memory 201288 kb
Host smart-fb37b349-71cf-4bbf-a0b3-bbe56c2b0e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259082557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te
st.3259082557
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.3656321442
Short name T478
Test name
Test status
Simulation time 3097842305 ps
CPU time 2.73 seconds
Started Jan 10 12:49:18 PM PST 24
Finished Jan 10 12:50:50 PM PST 24
Peak memory 201348 kb
Host smart-a90718f5-f158-4b42-af4c-6d35b7b5c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656321442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.3
656321442
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3337651337
Short name T632
Test name
Test status
Simulation time 143587118660 ps
CPU time 380.77 seconds
Started Jan 10 12:49:58 PM PST 24
Finished Jan 10 12:57:57 PM PST 24
Peak memory 201668 kb
Host smart-3af2a0dd-1b6c-4f2c-ac23-d9e7ed9ed0c3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337651337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3337651337
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3713557610
Short name T503
Test name
Test status
Simulation time 4796610686 ps
CPU time 2.29 seconds
Started Jan 10 12:37:51 PM PST 24
Finished Jan 10 12:38:27 PM PST 24
Peak memory 201316 kb
Host smart-9088f800-4859-4871-bdc0-18bd80b8ed04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713557610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.3713557610
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.4149521747
Short name T202
Test name
Test status
Simulation time 2974082865 ps
CPU time 2.18 seconds
Started Jan 10 01:04:28 PM PST 24
Finished Jan 10 01:05:48 PM PST 24
Peak memory 201424 kb
Host smart-db4f4050-27d7-4f7a-a957-dc3104a43960
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149521747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.4149521747
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3465931168
Short name T68
Test name
Test status
Simulation time 2619017758 ps
CPU time 4.33 seconds
Started Jan 10 12:40:13 PM PST 24
Finished Jan 10 12:41:05 PM PST 24
Peak memory 201304 kb
Host smart-a1fc1903-e4f1-42b7-804a-34810b99ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465931168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3465931168
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.3634861726
Short name T754
Test name
Test status
Simulation time 2480227528 ps
CPU time 6.36 seconds
Started Jan 10 12:40:00 PM PST 24
Finished Jan 10 12:40:47 PM PST 24
Peak memory 201296 kb
Host smart-e5cb110f-04e1-4ab2-a704-b2e748533b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634861726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.3634861726
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.1653637019
Short name T123
Test name
Test status
Simulation time 2161688997 ps
CPU time 1.52 seconds
Started Jan 10 01:14:00 PM PST 24
Finished Jan 10 01:15:08 PM PST 24
Peak memory 201316 kb
Host smart-913152ac-6fac-40a3-9405-a50b3447a8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653637019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.1653637019
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.706046280
Short name T700
Test name
Test status
Simulation time 2511817207 ps
CPU time 3.9 seconds
Started Jan 10 12:46:28 PM PST 24
Finished Jan 10 12:48:01 PM PST 24
Peak memory 201248 kb
Host smart-b89c1489-f5fc-4617-99b8-acffea595e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706046280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.706046280
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2999066852
Short name T602
Test name
Test status
Simulation time 2135638286 ps
CPU time 1.55 seconds
Started Jan 10 12:47:39 PM PST 24
Finished Jan 10 12:49:02 PM PST 24
Peak memory 201288 kb
Host smart-748a682e-1f56-4277-87f4-c6f4c9c2a6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999066852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2999066852
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.601225398
Short name T641
Test name
Test status
Simulation time 6779184848 ps
CPU time 4.99 seconds
Started Jan 10 12:46:26 PM PST 24
Finished Jan 10 12:47:50 PM PST 24
Peak memory 201300 kb
Host smart-844c1149-54ea-43d4-83a5-379c1d647305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601225398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_st
ress_all.601225398
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.623909015
Short name T92
Test name
Test status
Simulation time 46816958111 ps
CPU time 124.79 seconds
Started Jan 10 12:38:01 PM PST 24
Finished Jan 10 12:40:39 PM PST 24
Peak memory 213284 kb
Host smart-78f3a6a8-c7de-4439-9c26-70b52a187870
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623909015 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.623909015
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.3171913373
Short name T14
Test name
Test status
Simulation time 7749078596 ps
CPU time 8.73 seconds
Started Jan 10 12:43:58 PM PST 24
Finished Jan 10 12:45:21 PM PST 24
Peak memory 201276 kb
Host smart-c072dc91-0774-4f57-97d1-27af66ad07b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171913373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.3171913373
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.218861255
Short name T603
Test name
Test status
Simulation time 2020914857 ps
CPU time 2.21 seconds
Started Jan 10 12:40:35 PM PST 24
Finished Jan 10 12:41:21 PM PST 24
Peak memory 201280 kb
Host smart-7b64f95e-52e6-4206-b46d-38f96d4e134c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218861255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_tes
t.218861255
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2103558385
Short name T828
Test name
Test status
Simulation time 3428507923 ps
CPU time 8.92 seconds
Started Jan 10 12:40:38 PM PST 24
Finished Jan 10 12:41:31 PM PST 24
Peak memory 201440 kb
Host smart-db76775a-e4e8-4f26-882e-e3cf154be97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103558385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2
103558385
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.3778080150
Short name T256
Test name
Test status
Simulation time 149400176443 ps
CPU time 367.55 seconds
Started Jan 10 12:41:08 PM PST 24
Finished Jan 10 12:48:15 PM PST 24
Peak memory 201640 kb
Host smart-7ac31e43-714d-46ca-a0ff-5bc6d2f98fd3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778080150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_combo_detect.3778080150
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.1035917639
Short name T652
Test name
Test status
Simulation time 33006555911 ps
CPU time 19.82 seconds
Started Jan 10 12:39:24 PM PST 24
Finished Jan 10 12:40:13 PM PST 24
Peak memory 201724 kb
Host smart-cc6a048a-8408-4e39-ada1-08fe398f8edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035917639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.1035917639
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.864100879
Short name T611
Test name
Test status
Simulation time 4806593323 ps
CPU time 6.9 seconds
Started Jan 10 12:47:04 PM PST 24
Finished Jan 10 12:48:31 PM PST 24
Peak memory 201292 kb
Host smart-fe4fcd3f-595e-4b01-818d-49ee1bdb62f2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864100879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ec_pwr_on_rst.864100879
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.669720980
Short name T461
Test name
Test status
Simulation time 2615455975 ps
CPU time 4.03 seconds
Started Jan 10 12:45:03 PM PST 24
Finished Jan 10 12:46:29 PM PST 24
Peak memory 201344 kb
Host smart-d3230071-5669-4945-9f59-d1c65af2ed03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669720980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.669720980
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1678499743
Short name T118
Test name
Test status
Simulation time 2458532796 ps
CPU time 3.96 seconds
Started Jan 10 12:45:42 PM PST 24
Finished Jan 10 12:47:06 PM PST 24
Peak memory 201336 kb
Host smart-c547bfba-312e-4460-b5d3-e82ffae656ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678499743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1678499743
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.658249890
Short name T540
Test name
Test status
Simulation time 2232785056 ps
CPU time 6.6 seconds
Started Jan 10 12:40:09 PM PST 24
Finished Jan 10 12:41:02 PM PST 24
Peak memory 201372 kb
Host smart-eba27dc2-a0c6-421e-ab8d-b8064118e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658249890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.658249890
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2533013919
Short name T655
Test name
Test status
Simulation time 2513798446 ps
CPU time 6.85 seconds
Started Jan 10 12:45:47 PM PST 24
Finished Jan 10 12:47:15 PM PST 24
Peak memory 201272 kb
Host smart-0d838523-6511-407f-8a5d-8e1dd2bf1f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533013919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2533013919
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.1422969451
Short name T464
Test name
Test status
Simulation time 2130460296 ps
CPU time 1.88 seconds
Started Jan 10 12:44:20 PM PST 24
Finished Jan 10 12:45:39 PM PST 24
Peak memory 201208 kb
Host smart-01e9d40e-d23a-4e42-ad4f-692eecccd072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422969451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1422969451
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.1565883885
Short name T480
Test name
Test status
Simulation time 10534123886 ps
CPU time 29.76 seconds
Started Jan 10 12:53:27 PM PST 24
Finished Jan 10 12:55:09 PM PST 24
Peak memory 201388 kb
Host smart-0b481d03-4631-4b13-aa5b-7819b6affbca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565883885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s
tress_all.1565883885
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.438477653
Short name T348
Test name
Test status
Simulation time 25456215794 ps
CPU time 68.06 seconds
Started Jan 10 12:45:41 PM PST 24
Finished Jan 10 12:48:09 PM PST 24
Peak memory 209768 kb
Host smart-a4c8e59d-ee78-40d6-9d0e-1970496e6721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438477653 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.438477653
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.333117325
Short name T232
Test name
Test status
Simulation time 8194089090379 ps
CPU time 241.42 seconds
Started Jan 10 12:43:32 PM PST 24
Finished Jan 10 12:48:49 PM PST 24
Peak memory 201220 kb
Host smart-80425c68-b5b2-4339-aa79-f5bdd41a318a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333117325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ultra_low_pwr.333117325
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3295467892
Short name T596
Test name
Test status
Simulation time 3080993507 ps
CPU time 8.44 seconds
Started Jan 10 12:45:43 PM PST 24
Finished Jan 10 12:47:14 PM PST 24
Peak memory 201440 kb
Host smart-d8af2419-714e-42c7-964c-7d1eeccf5b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295467892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3
295467892
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.2442170018
Short name T308
Test name
Test status
Simulation time 107182186219 ps
CPU time 259.15 seconds
Started Jan 10 12:45:18 PM PST 24
Finished Jan 10 12:51:02 PM PST 24
Peak memory 201616 kb
Host smart-e76f7bb1-6d3b-422d-905f-95a24a9360fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442170018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.2442170018
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.2572717339
Short name T104
Test name
Test status
Simulation time 25100660208 ps
CPU time 16.9 seconds
Started Jan 10 12:42:55 PM PST 24
Finished Jan 10 12:44:25 PM PST 24
Peak memory 201700 kb
Host smart-71ed2a98-1180-4f54-ab88-cabcb1f51b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572717339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.2572717339
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.23082877
Short name T566
Test name
Test status
Simulation time 2626806899 ps
CPU time 6.92 seconds
Started Jan 10 01:07:12 PM PST 24
Finished Jan 10 01:08:46 PM PST 24
Peak memory 201348 kb
Host smart-19a4d38d-7346-49ae-8faf-cff55c736a6b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23082877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_ec_pwr_on_rst.23082877
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1981524882
Short name T564
Test name
Test status
Simulation time 2677912119 ps
CPU time 1.12 seconds
Started Jan 10 12:44:10 PM PST 24
Finished Jan 10 12:45:28 PM PST 24
Peak memory 201296 kb
Host smart-6dcefbdb-2c21-43d3-9f1c-c084def83a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981524882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1981524882
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2557217709
Short name T629
Test name
Test status
Simulation time 2443977247 ps
CPU time 8.47 seconds
Started Jan 10 12:53:09 PM PST 24
Finished Jan 10 12:54:29 PM PST 24
Peak memory 201392 kb
Host smart-43accbcb-4860-4577-8bae-9eadc05ffce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557217709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2557217709
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.528862531
Short name T434
Test name
Test status
Simulation time 2107354435 ps
CPU time 3.2 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:41:28 PM PST 24
Peak memory 201372 kb
Host smart-fde1c362-98b0-4e00-9eb6-cb71b7deb07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528862531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.528862531
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.616974301
Short name T787
Test name
Test status
Simulation time 2516233610 ps
CPU time 4 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:29 PM PST 24
Peak memory 201284 kb
Host smart-57224fbc-02a4-4c98-bc20-7e7f14e82283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616974301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.616974301
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.2627505287
Short name T845
Test name
Test status
Simulation time 2113029552 ps
CPU time 5.61 seconds
Started Jan 10 12:56:08 PM PST 24
Finished Jan 10 12:57:23 PM PST 24
Peak memory 201224 kb
Host smart-26cee4c0-3bd6-4bb8-af00-c2ca5361df12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627505287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2627505287
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.684024480
Short name T761
Test name
Test status
Simulation time 6185983761 ps
CPU time 4.71 seconds
Started Jan 10 12:59:57 PM PST 24
Finished Jan 10 01:01:41 PM PST 24
Peak memory 201308 kb
Host smart-89a2faa6-fc48-472e-b120-9ec27fbfa2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684024480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_st
ress_all.684024480
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2617753506
Short name T217
Test name
Test status
Simulation time 62353421094 ps
CPU time 144.68 seconds
Started Jan 10 12:54:52 PM PST 24
Finished Jan 10 12:58:22 PM PST 24
Peak memory 218352 kb
Host smart-07c48593-5b90-40f2-8572-5f3b8a666d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617753506 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2617753506
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2637567046
Short name T567
Test name
Test status
Simulation time 2878039341 ps
CPU time 6.53 seconds
Started Jan 10 12:41:49 PM PST 24
Finished Jan 10 12:43:07 PM PST 24
Peak memory 201252 kb
Host smart-d5fc7ab2-8637-4fcc-a91a-b1adbc7038d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637567046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_
ctrl_ultra_low_pwr.2637567046
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.3294908059
Short name T211
Test name
Test status
Simulation time 2043418994 ps
CPU time 2.01 seconds
Started Jan 10 12:52:05 PM PST 24
Finished Jan 10 12:53:22 PM PST 24
Peak memory 201252 kb
Host smart-7eec64ce-4cc7-4c68-a073-4ba89f0bb331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294908059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.3294908059
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.3614058458
Short name T592
Test name
Test status
Simulation time 3362164563 ps
CPU time 9.5 seconds
Started Jan 10 12:37:55 PM PST 24
Finished Jan 10 12:38:37 PM PST 24
Peak memory 201464 kb
Host smart-7f59a383-ccac-4a57-862a-4f86d24845d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614058458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.3
614058458
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.659067884
Short name T113
Test name
Test status
Simulation time 66879330265 ps
CPU time 44.05 seconds
Started Jan 10 12:53:16 PM PST 24
Finished Jan 10 12:55:13 PM PST 24
Peak memory 201468 kb
Host smart-d486bb4e-2721-4a22-ac65-44951889ff46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659067884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.659067884
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2642595981
Short name T268
Test name
Test status
Simulation time 125073107702 ps
CPU time 86.65 seconds
Started Jan 10 12:38:49 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 201808 kb
Host smart-895fcd61-5b8f-4558-a68f-11c475ae8495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642595981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.2642595981
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.842321715
Short name T162
Test name
Test status
Simulation time 468584896232 ps
CPU time 17.67 seconds
Started Jan 10 12:43:52 PM PST 24
Finished Jan 10 12:45:24 PM PST 24
Peak memory 201304 kb
Host smart-b9e08fc7-a8d6-48cb-a20c-46a0f0766c44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842321715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctr
l_edge_detect.842321715
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2550818369
Short name T671
Test name
Test status
Simulation time 2636476342 ps
CPU time 2.31 seconds
Started Jan 10 12:40:07 PM PST 24
Finished Jan 10 12:40:54 PM PST 24
Peak memory 201304 kb
Host smart-2c99b358-b6ba-4451-bda2-57211a28ea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550818369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.2550818369
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2141677358
Short name T841
Test name
Test status
Simulation time 2465878096 ps
CPU time 6.24 seconds
Started Jan 10 12:44:08 PM PST 24
Finished Jan 10 12:45:29 PM PST 24
Peak memory 201376 kb
Host smart-9e80c561-8b51-4eb7-9555-612c555e66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141677358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2141677358
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1374385237
Short name T516
Test name
Test status
Simulation time 2149537683 ps
CPU time 2.24 seconds
Started Jan 10 12:43:30 PM PST 24
Finished Jan 10 12:44:50 PM PST 24
Peak memory 201436 kb
Host smart-8a2b1d2c-55a9-4505-8906-ebf34bd292a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374385237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1374385237
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2261163397
Short name T759
Test name
Test status
Simulation time 2561509398 ps
CPU time 1.49 seconds
Started Jan 10 12:51:12 PM PST 24
Finished Jan 10 12:52:31 PM PST 24
Peak memory 201276 kb
Host smart-4903b018-4fa4-47d5-9fcb-424ffed813da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261163397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.2261163397
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.3906692277
Short name T414
Test name
Test status
Simulation time 2164759196 ps
CPU time 1.15 seconds
Started Jan 10 12:34:35 PM PST 24
Finished Jan 10 12:35:16 PM PST 24
Peak memory 201360 kb
Host smart-6368dbc3-5cef-4e0a-942f-7eefd03068a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906692277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3906692277
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.2862859839
Short name T107
Test name
Test status
Simulation time 175440255270 ps
CPU time 76.57 seconds
Started Jan 10 12:38:39 PM PST 24
Finished Jan 10 12:40:27 PM PST 24
Peak memory 201740 kb
Host smart-f00e041c-58dd-441e-b73e-45458f4b758d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862859839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.2862859839
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1217719413
Short name T174
Test name
Test status
Simulation time 151040459845 ps
CPU time 101.07 seconds
Started Jan 10 12:39:58 PM PST 24
Finished Jan 10 12:42:18 PM PST 24
Peak memory 210040 kb
Host smart-e388741f-fc00-416f-853b-f459afa5133f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217719413 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1217719413
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.4044096973
Short name T628
Test name
Test status
Simulation time 4273596445 ps
CPU time 2.31 seconds
Started Jan 10 12:43:50 PM PST 24
Finished Jan 10 12:45:06 PM PST 24
Peak memory 201280 kb
Host smart-4ccbe61a-525b-447b-bafc-4ed7ffe9c64f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044096973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ultra_low_pwr.4044096973
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.1363767162
Short name T494
Test name
Test status
Simulation time 2012270195 ps
CPU time 4.18 seconds
Started Jan 10 01:11:26 PM PST 24
Finished Jan 10 01:12:52 PM PST 24
Peak memory 201316 kb
Host smart-382b0e65-b4f3-457e-b121-fba736a234d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363767162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te
st.1363767162
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.4060034616
Short name T114
Test name
Test status
Simulation time 3653135805 ps
CPU time 2.73 seconds
Started Jan 10 12:42:26 PM PST 24
Finished Jan 10 12:43:42 PM PST 24
Peak memory 201400 kb
Host smart-c7923afb-8fc1-43bc-b255-ac7dd6f4497b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060034616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.4
060034616
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.936975252
Short name T315
Test name
Test status
Simulation time 172879049183 ps
CPU time 115.99 seconds
Started Jan 10 12:46:01 PM PST 24
Finished Jan 10 12:49:18 PM PST 24
Peak memory 201508 kb
Host smart-5229d757-a0c6-4204-9d2f-bb1453064ddf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936975252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_combo_detect.936975252
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2530517141
Short name T15
Test name
Test status
Simulation time 101341258188 ps
CPU time 27.84 seconds
Started Jan 10 12:55:42 PM PST 24
Finished Jan 10 12:57:18 PM PST 24
Peak memory 201668 kb
Host smart-c86a6d13-e7e3-46ac-9449-3d0edec0abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530517141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_w
ith_pre_cond.2530517141
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2446056919
Short name T204
Test name
Test status
Simulation time 3244133556 ps
CPU time 2.84 seconds
Started Jan 10 12:36:15 PM PST 24
Finished Jan 10 12:36:50 PM PST 24
Peak memory 201428 kb
Host smart-aeac0c99-f69f-46d3-9b57-bbc8f0d20a30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446056919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.2446056919
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.3067040033
Short name T240
Test name
Test status
Simulation time 3326466322 ps
CPU time 4.82 seconds
Started Jan 10 12:39:58 PM PST 24
Finished Jan 10 12:40:42 PM PST 24
Peak memory 201372 kb
Host smart-83ec6319-cfe4-4854-b217-26c29c20a4dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067040033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.3067040033
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.4132930884
Short name T413
Test name
Test status
Simulation time 2616058536 ps
CPU time 5 seconds
Started Jan 10 12:56:33 PM PST 24
Finished Jan 10 12:57:47 PM PST 24
Peak memory 201244 kb
Host smart-4f652723-b54f-496d-ac63-d44610344fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132930884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.4132930884
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.3490512071
Short name T823
Test name
Test status
Simulation time 2476812475 ps
CPU time 3.32 seconds
Started Jan 10 12:37:18 PM PST 24
Finished Jan 10 12:37:52 PM PST 24
Peak memory 201368 kb
Host smart-39c53a8e-93a3-4516-95d2-a58baf8e904a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490512071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.3490512071
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1609556228
Short name T117
Test name
Test status
Simulation time 2141157013 ps
CPU time 6.14 seconds
Started Jan 10 12:40:20 PM PST 24
Finished Jan 10 12:41:13 PM PST 24
Peak memory 201288 kb
Host smart-4c6121d5-d18c-427a-a5e8-77c52495085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609556228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1609556228
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.640746879
Short name T444
Test name
Test status
Simulation time 2112537981 ps
CPU time 6.07 seconds
Started Jan 10 12:39:48 PM PST 24
Finished Jan 10 12:40:26 PM PST 24
Peak memory 201204 kb
Host smart-c5acdea2-3556-4c6f-8a8e-3ec6f28a7c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640746879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.640746879
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.1122218481
Short name T129
Test name
Test status
Simulation time 25577960919 ps
CPU time 70.64 seconds
Started Jan 10 12:41:23 PM PST 24
Finished Jan 10 12:43:40 PM PST 24
Peak memory 201384 kb
Host smart-a2537a4e-a1a7-463b-bddd-52c14102bdef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122218481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.1122218481
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2612515164
Short name T180
Test name
Test status
Simulation time 31386103856 ps
CPU time 71.66 seconds
Started Jan 10 12:48:49 PM PST 24
Finished Jan 10 12:51:27 PM PST 24
Peak memory 201752 kb
Host smart-839be550-3833-4965-8b1c-c7922be5927d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612515164 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2612515164
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.744534265
Short name T230
Test name
Test status
Simulation time 4668914689 ps
CPU time 3.76 seconds
Started Jan 10 01:14:23 PM PST 24
Finished Jan 10 01:15:13 PM PST 24
Peak memory 201364 kb
Host smart-e574b5fc-7e59-4801-9ed8-7194bf52a4d4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744534265 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_ultra_low_pwr.744534265
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.1874797042
Short name T788
Test name
Test status
Simulation time 2015476019 ps
CPU time 5.65 seconds
Started Jan 10 12:43:06 PM PST 24
Finished Jan 10 12:44:25 PM PST 24
Peak memory 201340 kb
Host smart-6f9a5bcb-4a9b-4305-ac0b-2f10d289191f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874797042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.1874797042
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1032228202
Short name T130
Test name
Test status
Simulation time 3217698595 ps
CPU time 9.39 seconds
Started Jan 10 12:39:06 PM PST 24
Finished Jan 10 12:39:47 PM PST 24
Peak memory 201428 kb
Host smart-1a0351eb-c983-4ad2-81f1-4c093e4d0a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032228202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.1
032228202
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2503151590
Short name T772
Test name
Test status
Simulation time 188508192538 ps
CPU time 483.15 seconds
Started Jan 10 12:51:14 PM PST 24
Finished Jan 10 01:00:37 PM PST 24
Peak memory 201564 kb
Host smart-d881a619-1ee0-4c04-ad22-b7c3407fd275
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503151590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2503151590
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3841287362
Short name T714
Test name
Test status
Simulation time 2623190098 ps
CPU time 7.16 seconds
Started Jan 10 12:38:09 PM PST 24
Finished Jan 10 12:38:52 PM PST 24
Peak memory 201288 kb
Host smart-7b73a230-60dc-42cf-ad25-3d1302f12497
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841287362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.3841287362
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3840864328
Short name T760
Test name
Test status
Simulation time 3407567983 ps
CPU time 4.31 seconds
Started Jan 10 12:38:34 PM PST 24
Finished Jan 10 12:39:10 PM PST 24
Peak memory 201292 kb
Host smart-ae73b092-bf9d-4461-9790-8101dbb62b61
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840864328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.3840864328
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1619962524
Short name T182
Test name
Test status
Simulation time 2611675629 ps
CPU time 7.44 seconds
Started Jan 10 12:57:14 PM PST 24
Finished Jan 10 12:58:35 PM PST 24
Peak memory 199812 kb
Host smart-d58fba3b-ee4e-4928-8fa0-f9e67025b4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619962524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1619962524
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.3654010352
Short name T743
Test name
Test status
Simulation time 2460868246 ps
CPU time 6.89 seconds
Started Jan 10 12:36:27 PM PST 24
Finished Jan 10 12:37:07 PM PST 24
Peak memory 201312 kb
Host smart-4e6cb726-71ad-448c-8ad1-2490c2bf8825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654010352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.3654010352
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.132490331
Short name T783
Test name
Test status
Simulation time 2152273884 ps
CPU time 1.88 seconds
Started Jan 10 12:45:12 PM PST 24
Finished Jan 10 12:46:36 PM PST 24
Peak memory 201324 kb
Host smart-0d906237-d450-42df-8f5a-23e3d32da942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132490331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.132490331
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2856161525
Short name T635
Test name
Test status
Simulation time 2512750160 ps
CPU time 3.88 seconds
Started Jan 10 12:51:58 PM PST 24
Finished Jan 10 12:53:29 PM PST 24
Peak memory 201340 kb
Host smart-639897d4-9f4d-4638-be09-d4f1d17e0b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856161525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2856161525
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.514332908
Short name T541
Test name
Test status
Simulation time 5284368547 ps
CPU time 4.22 seconds
Started Jan 10 01:23:09 PM PST 24
Finished Jan 10 01:23:32 PM PST 24
Peak memory 201300 kb
Host smart-5e4df44e-d867-4961-8a2e-d2aa8e2b53d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514332908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_ultra_low_pwr.514332908
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.3275859742
Short name T427
Test name
Test status
Simulation time 2015198069 ps
CPU time 5.76 seconds
Started Jan 10 12:35:40 PM PST 24
Finished Jan 10 12:36:11 PM PST 24
Peak memory 201316 kb
Host smart-ce2416e0-43f7-4b81-a60e-df255c262b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275859742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te
st.3275859742
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.273292398
Short name T530
Test name
Test status
Simulation time 4087512051 ps
CPU time 10.09 seconds
Started Jan 10 12:47:46 PM PST 24
Finished Jan 10 12:49:20 PM PST 24
Peak memory 201344 kb
Host smart-811f252b-54b6-4deb-b129-76fb32c5c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273292398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.273292398
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.351467883
Short name T77
Test name
Test status
Simulation time 150066537298 ps
CPU time 388.87 seconds
Started Jan 10 01:06:57 PM PST 24
Finished Jan 10 01:14:41 PM PST 24
Peak memory 201600 kb
Host smart-b8302a94-cb63-4730-89fe-dbabf097fd95
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351467883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_combo_detect.351467883
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.4113613953
Short name T334
Test name
Test status
Simulation time 74733522593 ps
CPU time 204.67 seconds
Started Jan 10 12:35:12 PM PST 24
Finished Jan 10 12:39:11 PM PST 24
Peak memory 201564 kb
Host smart-072bb60a-9b87-4dfe-9f0f-fd968f9a62a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113613953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.4113613953
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.1615875463
Short name T588
Test name
Test status
Simulation time 4583747858 ps
CPU time 12.29 seconds
Started Jan 10 12:46:41 PM PST 24
Finished Jan 10 12:48:19 PM PST 24
Peak memory 201348 kb
Host smart-eeb78d78-0712-4248-84bb-0fd7590ebf8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615875463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ec_pwr_on_rst.1615875463
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2639531125
Short name T711
Test name
Test status
Simulation time 3846404214 ps
CPU time 1.47 seconds
Started Jan 10 12:54:56 PM PST 24
Finished Jan 10 12:56:02 PM PST 24
Peak memory 201288 kb
Host smart-b3b66d59-0f6e-49b9-84b5-408e4f82cd1f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639531125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.2639531125
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2357330519
Short name T511
Test name
Test status
Simulation time 2639593690 ps
CPU time 2.22 seconds
Started Jan 10 01:10:18 PM PST 24
Finished Jan 10 01:11:35 PM PST 24
Peak memory 201336 kb
Host smart-8cfbe4c9-71ed-407f-af04-20d8f4d160fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357330519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2357330519
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.1952451973
Short name T824
Test name
Test status
Simulation time 2487072306 ps
CPU time 2.13 seconds
Started Jan 10 12:45:11 PM PST 24
Finished Jan 10 12:46:40 PM PST 24
Peak memory 201404 kb
Host smart-79bd0fbd-ec4a-432f-a7ce-8fab88366f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952451973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1952451973
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.3007152806
Short name T807
Test name
Test status
Simulation time 2246537820 ps
CPU time 6.4 seconds
Started Jan 10 12:51:12 PM PST 24
Finished Jan 10 12:52:36 PM PST 24
Peak memory 201360 kb
Host smart-5c0c0fc4-2fc9-4b5b-929f-cc10da94afdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007152806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3007152806
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3190351792
Short name T583
Test name
Test status
Simulation time 2519630044 ps
CPU time 3.94 seconds
Started Jan 10 12:36:25 PM PST 24
Finished Jan 10 12:37:03 PM PST 24
Peak memory 201212 kb
Host smart-a0b58303-5e0b-406d-8e9d-ac7a6286adce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190351792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.3190351792
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.3681818949
Short name T584
Test name
Test status
Simulation time 2135440522 ps
CPU time 2.07 seconds
Started Jan 10 12:58:12 PM PST 24
Finished Jan 10 12:59:33 PM PST 24
Peak memory 201280 kb
Host smart-a4c5b76f-abc2-4ec8-978f-38efc702e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681818949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.3681818949
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1054663354
Short name T614
Test name
Test status
Simulation time 14129626449 ps
CPU time 4.31 seconds
Started Jan 10 12:50:59 PM PST 24
Finished Jan 10 12:52:40 PM PST 24
Peak memory 201440 kb
Host smart-a5e3af79-c436-42ec-9d09-1f529da8aa12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054663354 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1054663354
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3688986628
Short name T612
Test name
Test status
Simulation time 142942182201 ps
CPU time 189.01 seconds
Started Jan 10 12:37:17 PM PST 24
Finished Jan 10 12:40:56 PM PST 24
Peak memory 210008 kb
Host smart-b0b2e281-cd5b-4d5c-b108-6f4cd5b605ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688986628 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3688986628
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3682317044
Short name T842
Test name
Test status
Simulation time 900730239375 ps
CPU time 130.74 seconds
Started Jan 10 01:08:09 PM PST 24
Finished Jan 10 01:11:44 PM PST 24
Peak memory 201312 kb
Host smart-d5902d0c-90e8-4743-ae50-b0414cb244ca
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682317044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.3682317044
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.1728310717
Short name T808
Test name
Test status
Simulation time 2013405998 ps
CPU time 5.68 seconds
Started Jan 10 12:34:03 PM PST 24
Finished Jan 10 12:34:37 PM PST 24
Peak memory 201252 kb
Host smart-34c305ca-05a0-40c8-bce1-e213e5421197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728310717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te
st.1728310717
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2955201031
Short name T658
Test name
Test status
Simulation time 241230884030 ps
CPU time 640.73 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:46:14 PM PST 24
Peak memory 201364 kb
Host smart-5ef9af43-8471-4933-929e-248a9021e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955201031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.2
955201031
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.2074768230
Short name T703
Test name
Test status
Simulation time 58191876137 ps
CPU time 11.24 seconds
Started Jan 10 12:52:30 PM PST 24
Finished Jan 10 12:54:03 PM PST 24
Peak memory 201588 kb
Host smart-aff92c26-90e7-45e9-aac2-969fb2fec1da
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074768230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.2074768230
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.955793292
Short name T27
Test name
Test status
Simulation time 26079590675 ps
CPU time 66.62 seconds
Started Jan 10 12:40:59 PM PST 24
Finished Jan 10 12:43:03 PM PST 24
Peak memory 201684 kb
Host smart-d9fffe69-2428-4b72-b2ce-78d506f7e70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955793292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_wi
th_pre_cond.955793292
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2049534811
Short name T813
Test name
Test status
Simulation time 2973368531 ps
CPU time 2.49 seconds
Started Jan 10 12:40:19 PM PST 24
Finished Jan 10 12:41:08 PM PST 24
Peak memory 201248 kb
Host smart-9bcd86a2-a08d-4755-a6fb-14db1d81798b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049534811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.2049534811
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.813650605
Short name T200
Test name
Test status
Simulation time 3897580990 ps
CPU time 2.93 seconds
Started Jan 10 12:35:12 PM PST 24
Finished Jan 10 12:35:49 PM PST 24
Peak memory 201272 kb
Host smart-d7dc87f1-637b-4492-a189-695696c18b08
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813650605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr
l_edge_detect.813650605
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1952711476
Short name T769
Test name
Test status
Simulation time 2612986481 ps
CPU time 4.27 seconds
Started Jan 10 12:39:22 PM PST 24
Finished Jan 10 12:39:55 PM PST 24
Peak memory 201348 kb
Host smart-a89bb704-c95b-403f-a9bf-b78fb0827da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952711476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1952711476
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2313585506
Short name T691
Test name
Test status
Simulation time 2474310392 ps
CPU time 8 seconds
Started Jan 10 12:34:52 PM PST 24
Finished Jan 10 12:35:41 PM PST 24
Peak memory 201312 kb
Host smart-34574dee-c61b-4533-b226-b276da4bfcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313585506 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2313585506
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.367231699
Short name T456
Test name
Test status
Simulation time 2014581588 ps
CPU time 5.92 seconds
Started Jan 10 12:43:05 PM PST 24
Finished Jan 10 12:44:24 PM PST 24
Peak memory 201316 kb
Host smart-3fad6ab7-b6f9-4de4-9dca-4a9dfbc3674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367231699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.367231699
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.573096655
Short name T554
Test name
Test status
Simulation time 2529835367 ps
CPU time 2.37 seconds
Started Jan 10 12:36:01 PM PST 24
Finished Jan 10 12:36:27 PM PST 24
Peak memory 201328 kb
Host smart-45ffb818-bfd7-441d-9b6e-ee9347e41d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573096655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.573096655
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.725766362
Short name T486
Test name
Test status
Simulation time 2135324031 ps
CPU time 1.94 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:06 PM PST 24
Peak memory 201300 kb
Host smart-58c97fff-32a3-4355-8461-0fe659f7e1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725766362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.725766362
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.2110853182
Short name T124
Test name
Test status
Simulation time 8900810723 ps
CPU time 9.86 seconds
Started Jan 10 12:47:43 PM PST 24
Finished Jan 10 12:49:16 PM PST 24
Peak memory 201376 kb
Host smart-f10f7e88-91d8-4cbb-8a3e-64b3ff92f41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110853182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.2110853182
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1057568559
Short name T677
Test name
Test status
Simulation time 8954747659 ps
CPU time 6.94 seconds
Started Jan 10 12:48:43 PM PST 24
Finished Jan 10 12:50:14 PM PST 24
Peak memory 201364 kb
Host smart-a37a70f8-bd65-4b64-a377-68c2b77fa1c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057568559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.1057568559
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.3244192052
Short name T509
Test name
Test status
Simulation time 2012142031 ps
CPU time 5.81 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:31:39 PM PST 24
Peak memory 201184 kb
Host smart-13c1d2cc-6945-4950-9690-150681b88582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244192052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.3244192052
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.662241344
Short name T586
Test name
Test status
Simulation time 189522101397 ps
CPU time 541.76 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:40:58 PM PST 24
Peak memory 201316 kb
Host smart-c6179512-f49d-43bb-93e2-d096cf9e4164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662241344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.662241344
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.1121070440
Short name T310
Test name
Test status
Simulation time 89491537974 ps
CPU time 131.82 seconds
Started Jan 10 12:30:34 PM PST 24
Finished Jan 10 12:33:28 PM PST 24
Peak memory 201520 kb
Host smart-3b3895e6-7de2-4939-a1f7-b392433d5611
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121070440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_combo_detect.1121070440
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2957188704
Short name T550
Test name
Test status
Simulation time 2415647916 ps
CPU time 3.04 seconds
Started Jan 10 12:30:43 PM PST 24
Finished Jan 10 12:31:30 PM PST 24
Peak memory 201280 kb
Host smart-74d6800a-b082-4d64-9d86-0628bde53b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957188704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2957188704
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3851931398
Short name T61
Test name
Test status
Simulation time 2510123294 ps
CPU time 6.38 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 201164 kb
Host smart-a2120e13-b844-47e4-8167-a77e8014f3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851931398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3851931398
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2228093897
Short name T695
Test name
Test status
Simulation time 79389614997 ps
CPU time 206.65 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:35:22 PM PST 24
Peak memory 201504 kb
Host smart-9636cada-77ea-4aa1-9353-414ba3285063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228093897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.2228093897
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1375656966
Short name T521
Test name
Test status
Simulation time 3187095652 ps
CPU time 4.6 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:31:41 PM PST 24
Peak memory 201308 kb
Host smart-05503bf1-501d-4436-aa1c-1b3ced5e173e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375656966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ec_pwr_on_rst.1375656966
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.4040002688
Short name T218
Test name
Test status
Simulation time 4970549445 ps
CPU time 5.82 seconds
Started Jan 10 12:30:50 PM PST 24
Finished Jan 10 12:31:40 PM PST 24
Peak memory 201252 kb
Host smart-c2440afd-87d3-491c-832f-b6991fe6092a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040002688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.4040002688
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2143859676
Short name T517
Test name
Test status
Simulation time 2634091978 ps
CPU time 2.35 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:12 PM PST 24
Peak memory 201232 kb
Host smart-8e390d59-7884-4851-aa2a-efd72d4fca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143859676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2143859676
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.4217875812
Short name T749
Test name
Test status
Simulation time 2459282372 ps
CPU time 3.82 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:18 PM PST 24
Peak memory 201252 kb
Host smart-b6c2eec2-bc79-4a4b-b94c-456718f8676d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217875812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.4217875812
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.352836067
Short name T729
Test name
Test status
Simulation time 2103726044 ps
CPU time 5.78 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:31:31 PM PST 24
Peak memory 201188 kb
Host smart-5b3f5da6-88af-4678-830f-dd45506f2d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352836067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.352836067
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2868310041
Short name T233
Test name
Test status
Simulation time 2518118002 ps
CPU time 3.92 seconds
Started Jan 10 12:31:25 PM PST 24
Finished Jan 10 12:32:18 PM PST 24
Peak memory 201300 kb
Host smart-89018676-62c3-47ba-87a3-9cbe83f60652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868310041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.2868310041
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.60323083
Short name T740
Test name
Test status
Simulation time 2111143791 ps
CPU time 6.1 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:31:40 PM PST 24
Peak memory 201148 kb
Host smart-d13e8230-2478-463f-801f-e22ab5276ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60323083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.60323083
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.1082622899
Short name T311
Test name
Test status
Simulation time 90720468122 ps
CPU time 60.8 seconds
Started Jan 10 12:30:59 PM PST 24
Finished Jan 10 12:32:47 PM PST 24
Peak memory 201648 kb
Host smart-eca6a36d-2287-43be-8946-a8a04ece97be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082622899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.1082622899
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.3372141395
Short name T782
Test name
Test status
Simulation time 2636526671 ps
CPU time 2.14 seconds
Started Jan 10 12:30:50 PM PST 24
Finished Jan 10 12:31:37 PM PST 24
Peak memory 201288 kb
Host smart-7f6b4087-f321-45c1-aa9b-bf2aa15d66cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372141395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c
trl_ultra_low_pwr.3372141395
Directory /workspace/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.1811787242
Short name T442
Test name
Test status
Simulation time 2024061860 ps
CPU time 3.17 seconds
Started Jan 10 12:38:21 PM PST 24
Finished Jan 10 12:38:58 PM PST 24
Peak memory 201204 kb
Host smart-62f6be91-4413-4d2c-8160-39b05cadc1d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811787242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te
st.1811787242
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1596834524
Short name T721
Test name
Test status
Simulation time 3176106465 ps
CPU time 2.66 seconds
Started Jan 10 12:43:30 PM PST 24
Finished Jan 10 12:44:51 PM PST 24
Peak memory 201468 kb
Host smart-c2915bce-0ada-4de1-ba12-cebffb88c4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596834524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.1
596834524
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.1439239704
Short name T262
Test name
Test status
Simulation time 120939123466 ps
CPU time 79.86 seconds
Started Jan 10 12:40:37 PM PST 24
Finished Jan 10 12:42:41 PM PST 24
Peak memory 201708 kb
Host smart-ece22f89-a054-4b5d-b157-6c086fdf0163
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439239704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.1439239704
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1027809374
Short name T670
Test name
Test status
Simulation time 2687525916 ps
CPU time 7.81 seconds
Started Jan 10 12:48:29 PM PST 24
Finished Jan 10 12:50:00 PM PST 24
Peak memory 201280 kb
Host smart-a7363c72-e2a8-4652-8fc2-d317264de9e6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027809374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.1027809374
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3455074834
Short name T51
Test name
Test status
Simulation time 3322469000 ps
CPU time 3.64 seconds
Started Jan 10 12:49:45 PM PST 24
Finished Jan 10 12:51:17 PM PST 24
Peak memory 201276 kb
Host smart-3f4baa2e-7cf1-478d-ad92-ac2288b98ae3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455074834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.3455074834
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3502430953
Short name T152
Test name
Test status
Simulation time 2668037603 ps
CPU time 1.55 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:35 PM PST 24
Peak memory 201376 kb
Host smart-d2d49a51-0de1-4601-b217-d5b209d5cd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502430953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3502430953
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3567521630
Short name T657
Test name
Test status
Simulation time 2468305796 ps
CPU time 7.53 seconds
Started Jan 10 12:51:06 PM PST 24
Finished Jan 10 12:52:32 PM PST 24
Peak memory 201324 kb
Host smart-889bce09-de50-4ef8-a2c0-c5607de1e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567521630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3567521630
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.676139867
Short name T526
Test name
Test status
Simulation time 2137195739 ps
CPU time 1.76 seconds
Started Jan 10 12:46:10 PM PST 24
Finished Jan 10 12:47:33 PM PST 24
Peak memory 201200 kb
Host smart-7b7418a5-315d-4d09-8d45-0e3b17d25147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676139867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.676139867
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2392367356
Short name T490
Test name
Test status
Simulation time 2551240617 ps
CPU time 1.76 seconds
Started Jan 10 12:40:19 PM PST 24
Finished Jan 10 12:41:07 PM PST 24
Peak memory 201272 kb
Host smart-032e88f1-68fb-4946-ab39-6c6c671ae862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392367356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2392367356
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.3755804195
Short name T676
Test name
Test status
Simulation time 2113301691 ps
CPU time 6.2 seconds
Started Jan 10 12:44:01 PM PST 24
Finished Jan 10 12:45:21 PM PST 24
Peak memory 201256 kb
Host smart-67ad03e9-968b-46e4-8884-ba09c471fbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755804195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.3755804195
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.1186058549
Short name T522
Test name
Test status
Simulation time 14297132936 ps
CPU time 2.58 seconds
Started Jan 10 12:34:27 PM PST 24
Finished Jan 10 12:35:07 PM PST 24
Peak memory 201264 kb
Host smart-fcfb7e22-2de7-416b-8d58-8cb4b69fbdb3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186058549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ultra_low_pwr.1186058549
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.1804570825
Short name T532
Test name
Test status
Simulation time 2017757495 ps
CPU time 3.2 seconds
Started Jan 10 12:43:55 PM PST 24
Finished Jan 10 12:45:13 PM PST 24
Peak memory 201364 kb
Host smart-7659d56b-d088-43cd-a7d8-e04015e23c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804570825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.1804570825
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1266961663
Short name T604
Test name
Test status
Simulation time 161188547852 ps
CPU time 212.79 seconds
Started Jan 10 12:54:12 PM PST 24
Finished Jan 10 12:58:51 PM PST 24
Peak memory 201360 kb
Host smart-22da5166-7e91-4af6-ba04-fea625400a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266961663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.1
266961663
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.140378281
Short name T664
Test name
Test status
Simulation time 64433756168 ps
CPU time 43.66 seconds
Started Jan 10 12:39:57 PM PST 24
Finished Jan 10 12:41:18 PM PST 24
Peak memory 201576 kb
Host smart-0d83ebbb-77c5-4929-98e8-b51614ec43fa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140378281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_combo_detect.140378281
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2277461384
Short name T143
Test name
Test status
Simulation time 61972133325 ps
CPU time 17.89 seconds
Started Jan 10 01:00:08 PM PST 24
Finished Jan 10 01:02:05 PM PST 24
Peak memory 201760 kb
Host smart-65c73447-f057-4f4e-8192-6795f86c3d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277461384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.2277461384
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.645806679
Short name T821
Test name
Test status
Simulation time 1291643031497 ps
CPU time 849.1 seconds
Started Jan 10 12:38:04 PM PST 24
Finished Jan 10 12:52:46 PM PST 24
Peak memory 201216 kb
Host smart-74323a3f-617b-441f-87ec-aa875ab3d516
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645806679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.645806679
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3420222319
Short name T184
Test name
Test status
Simulation time 2573820309 ps
CPU time 1.34 seconds
Started Jan 10 12:37:29 PM PST 24
Finished Jan 10 12:38:06 PM PST 24
Peak memory 201268 kb
Host smart-fe37e027-76c2-45b2-af08-bda239843bfa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420222319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3420222319
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1050817256
Short name T523
Test name
Test status
Simulation time 2612686230 ps
CPU time 7.57 seconds
Started Jan 10 12:35:31 PM PST 24
Finished Jan 10 12:36:06 PM PST 24
Peak memory 201292 kb
Host smart-c6da4be2-10be-4475-8669-e5ddcd3cf0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050817256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1050817256
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.1152475351
Short name T495
Test name
Test status
Simulation time 2457699982 ps
CPU time 7.7 seconds
Started Jan 10 12:44:54 PM PST 24
Finished Jan 10 12:46:24 PM PST 24
Peak memory 201260 kb
Host smart-7e9534c6-f3dd-4c60-ac6b-89f1f01ac585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152475351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.1152475351
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.2642182584
Short name T702
Test name
Test status
Simulation time 2163741430 ps
CPU time 3.7 seconds
Started Jan 10 12:46:53 PM PST 24
Finished Jan 10 12:48:22 PM PST 24
Peak memory 201396 kb
Host smart-9e7a7c0e-ddf9-4938-b20d-c453c371c7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642182584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2642182584
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.498366839
Short name T264
Test name
Test status
Simulation time 2516048528 ps
CPU time 3.66 seconds
Started Jan 10 12:37:43 PM PST 24
Finished Jan 10 12:38:22 PM PST 24
Peak memory 201312 kb
Host smart-900dffef-6837-41a6-ae20-7839fffcd8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498366839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.498366839
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.481153823
Short name T536
Test name
Test status
Simulation time 2115375392 ps
CPU time 3.33 seconds
Started Jan 10 12:40:39 PM PST 24
Finished Jan 10 12:41:28 PM PST 24
Peak memory 201128 kb
Host smart-54be892c-9250-4a7a-aced-13719a52995a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481153823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.481153823
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.2521322825
Short name T839
Test name
Test status
Simulation time 141507707173 ps
CPU time 364.83 seconds
Started Jan 10 12:35:02 PM PST 24
Finished Jan 10 12:41:45 PM PST 24
Peak memory 201480 kb
Host smart-c49606a6-a4da-47c4-91c0-6e2e2bd00acf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521322825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.2521322825
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2010341869
Short name T805
Test name
Test status
Simulation time 11389051986 ps
CPU time 4.88 seconds
Started Jan 10 12:40:07 PM PST 24
Finished Jan 10 12:40:58 PM PST 24
Peak memory 201264 kb
Host smart-ef4533bc-1d0f-4b7d-b0ce-dcfc52003492
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010341869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.2010341869
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.911238133
Short name T429
Test name
Test status
Simulation time 2027990119 ps
CPU time 1.85 seconds
Started Jan 10 12:48:54 PM PST 24
Finished Jan 10 12:50:26 PM PST 24
Peak memory 201236 kb
Host smart-dba345dc-3866-494e-90b0-346c958f0a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911238133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_tes
t.911238133
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2130645442
Short name T659
Test name
Test status
Simulation time 276140686670 ps
CPU time 680.3 seconds
Started Jan 10 12:43:10 PM PST 24
Finished Jan 10 12:55:51 PM PST 24
Peak memory 201452 kb
Host smart-f8b3ce77-2624-4958-b5c5-eb32add41418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130645442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2
130645442
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2777890732
Short name T809
Test name
Test status
Simulation time 224043794585 ps
CPU time 150.89 seconds
Started Jan 10 12:52:13 PM PST 24
Finished Jan 10 12:55:59 PM PST 24
Peak memory 201620 kb
Host smart-1445ae10-c94e-4243-890e-cb8006529ea6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777890732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.2777890732
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3350966465
Short name T243
Test name
Test status
Simulation time 4338716205 ps
CPU time 2.15 seconds
Started Jan 10 01:00:25 PM PST 24
Finished Jan 10 01:02:25 PM PST 24
Peak memory 201412 kb
Host smart-c8dd40f6-4713-4ed8-8819-2c844c7d3a3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350966465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.3350966465
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3237858318
Short name T213
Test name
Test status
Simulation time 3102090225 ps
CPU time 2.77 seconds
Started Jan 10 12:38:42 PM PST 24
Finished Jan 10 12:39:17 PM PST 24
Peak memory 201332 kb
Host smart-22a8f785-8604-4179-9e1d-3a29a9f2d827
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237858318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3237858318
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.84053044
Short name T562
Test name
Test status
Simulation time 2611783830 ps
CPU time 7.28 seconds
Started Jan 10 12:50:06 PM PST 24
Finished Jan 10 12:51:36 PM PST 24
Peak memory 201352 kb
Host smart-7c7fdff1-6d80-4e6d-b736-ffea796e6d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84053044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.84053044
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1017403191
Short name T663
Test name
Test status
Simulation time 2175493630 ps
CPU time 6.12 seconds
Started Jan 10 12:44:51 PM PST 24
Finished Jan 10 12:46:17 PM PST 24
Peak memory 201324 kb
Host smart-aa336620-87ca-4874-8976-e977a93b0823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017403191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1017403191
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.319085562
Short name T352
Test name
Test status
Simulation time 2516425657 ps
CPU time 3.75 seconds
Started Jan 10 12:38:03 PM PST 24
Finished Jan 10 12:38:40 PM PST 24
Peak memory 201620 kb
Host smart-83062e4e-c07f-4373-9830-3831a13e0b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319085562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.319085562
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.2395898940
Short name T601
Test name
Test status
Simulation time 2108933374 ps
CPU time 6.14 seconds
Started Jan 10 12:51:10 PM PST 24
Finished Jan 10 12:52:38 PM PST 24
Peak memory 201228 kb
Host smart-dc3ab138-6cfa-40ca-a7f6-d8ae4ae685cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395898940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2395898940
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.3098313316
Short name T452
Test name
Test status
Simulation time 12261553386 ps
CPU time 7.79 seconds
Started Jan 10 12:51:12 PM PST 24
Finished Jan 10 12:52:38 PM PST 24
Peak memory 201500 kb
Host smart-49ce7a5c-fac9-4cf4-914e-ca58d8547a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098313316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.3098313316
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1597522619
Short name T241
Test name
Test status
Simulation time 256251680452 ps
CPU time 49.82 seconds
Started Jan 10 12:52:05 PM PST 24
Finished Jan 10 12:54:15 PM PST 24
Peak memory 210000 kb
Host smart-a8d504b2-012d-45c4-912b-e6351f51906d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597522619 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.1597522619
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.3629774502
Short name T674
Test name
Test status
Simulation time 2018815897 ps
CPU time 3.13 seconds
Started Jan 10 12:42:55 PM PST 24
Finished Jan 10 12:44:11 PM PST 24
Peak memory 201240 kb
Host smart-f874e2ea-b729-499b-bf5c-4c0394f090b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629774502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.3629774502
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1381347648
Short name T719
Test name
Test status
Simulation time 281670432803 ps
CPU time 726.58 seconds
Started Jan 10 01:14:00 PM PST 24
Finished Jan 10 01:27:14 PM PST 24
Peak memory 201464 kb
Host smart-52c97b40-e52c-47c3-a4b6-f888cdb98c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381347648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1
381347648
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.4137166658
Short name T443
Test name
Test status
Simulation time 3343660790 ps
CPU time 1.38 seconds
Started Jan 10 12:47:15 PM PST 24
Finished Jan 10 12:48:35 PM PST 24
Peak memory 201280 kb
Host smart-0ab2326d-a427-4d9f-8b65-5cd4c0bbf294
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137166658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.4137166658
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.1839474910
Short name T188
Test name
Test status
Simulation time 3252249971 ps
CPU time 2.43 seconds
Started Jan 10 12:50:06 PM PST 24
Finished Jan 10 12:51:46 PM PST 24
Peak memory 201276 kb
Host smart-2dce63f2-d558-4bf9-a064-038a372d935d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839474910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.1839474910
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.3115160178
Short name T722
Test name
Test status
Simulation time 2618444048 ps
CPU time 3.74 seconds
Started Jan 10 12:36:05 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 201336 kb
Host smart-1f184ec7-5497-4a05-9308-1b0c34a45c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115160178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.3115160178
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2014092819
Short name T25
Test name
Test status
Simulation time 2452169264 ps
CPU time 3.78 seconds
Started Jan 10 12:47:09 PM PST 24
Finished Jan 10 12:48:46 PM PST 24
Peak memory 201284 kb
Host smart-692d6124-a612-44f4-8b07-140839831908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014092819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.2014092819
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3389944695
Short name T138
Test name
Test status
Simulation time 2243228651 ps
CPU time 6.62 seconds
Started Jan 10 12:45:40 PM PST 24
Finished Jan 10 12:47:05 PM PST 24
Peak memory 201372 kb
Host smart-32493df5-b16e-4f0c-aa30-bb85f577dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389944695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.3389944695
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3008546716
Short name T477
Test name
Test status
Simulation time 2514621317 ps
CPU time 3.47 seconds
Started Jan 10 12:46:15 PM PST 24
Finished Jan 10 12:47:36 PM PST 24
Peak memory 201384 kb
Host smart-12dcb478-8f2d-46b8-977c-d42f4449d2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008546716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3008546716
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2026154437
Short name T177
Test name
Test status
Simulation time 2122064320 ps
CPU time 3.17 seconds
Started Jan 10 12:39:56 PM PST 24
Finished Jan 10 12:40:37 PM PST 24
Peak memory 201216 kb
Host smart-2f8ea1af-c7ab-47ec-8cf8-fc22b865a981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026154437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2026154437
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.544950990
Short name T666
Test name
Test status
Simulation time 12671114416 ps
CPU time 35.17 seconds
Started Jan 10 12:55:59 PM PST 24
Finished Jan 10 12:57:44 PM PST 24
Peak memory 201356 kb
Host smart-5c4373b8-1bd9-4e7c-b6d9-087c26444b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544950990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_st
ress_all.544950990
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3686974217
Short name T349
Test name
Test status
Simulation time 224582316888 ps
CPU time 143.28 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:43:29 PM PST 24
Peak memory 214604 kb
Host smart-a46dd63d-7de3-4c18-860a-bdcef5b6e4f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686974217 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.3686974217
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1762045194
Short name T17
Test name
Test status
Simulation time 5111619952 ps
CPU time 7.94 seconds
Started Jan 10 12:40:55 PM PST 24
Finished Jan 10 12:41:57 PM PST 24
Peak memory 201252 kb
Host smart-1c5e8464-a53a-4f18-97ab-188d4a58d55f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762045194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ultra_low_pwr.1762045194
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.3827845587
Short name T195
Test name
Test status
Simulation time 2012239982 ps
CPU time 5.71 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:24 PM PST 24
Peak memory 201248 kb
Host smart-b5acd2a9-fe73-4413-a9e9-d46b7bba005b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827845587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.3827845587
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.366606748
Short name T100
Test name
Test status
Simulation time 3326421719 ps
CPU time 2.7 seconds
Started Jan 10 01:03:48 PM PST 24
Finished Jan 10 01:05:07 PM PST 24
Peak memory 201408 kb
Host smart-e791dd1f-f0b2-410f-8989-e9bba5969bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366606748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.366606748
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1340694336
Short name T342
Test name
Test status
Simulation time 54756599216 ps
CPU time 137.56 seconds
Started Jan 10 12:44:43 PM PST 24
Finished Jan 10 12:48:18 PM PST 24
Peak memory 201584 kb
Host smart-20eca504-3890-45dc-bbe1-bf3279cf1b90
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340694336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1340694336
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1780572875
Short name T441
Test name
Test status
Simulation time 3353045469 ps
CPU time 2.68 seconds
Started Jan 10 12:57:41 PM PST 24
Finished Jan 10 12:59:02 PM PST 24
Peak memory 201364 kb
Host smart-56377657-2260-446b-858e-aacb603eeb2a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780572875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.1780572875
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.3174268586
Short name T208
Test name
Test status
Simulation time 4081583148 ps
CPU time 2.13 seconds
Started Jan 10 12:54:51 PM PST 24
Finished Jan 10 12:55:59 PM PST 24
Peak memory 201300 kb
Host smart-5fa4301e-9932-4896-83cb-94d0b5f04684
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174268586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.3174268586
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2312829811
Short name T445
Test name
Test status
Simulation time 2638982446 ps
CPU time 2.38 seconds
Started Jan 10 12:40:44 PM PST 24
Finished Jan 10 12:41:33 PM PST 24
Peak memory 201220 kb
Host smart-41c68e9d-c4c2-46df-ad81-213dc14ac692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312829811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2312829811
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.45321829
Short name T556
Test name
Test status
Simulation time 2484457841 ps
CPU time 3.29 seconds
Started Jan 10 01:15:11 PM PST 24
Finished Jan 10 01:15:17 PM PST 24
Peak memory 201300 kb
Host smart-9f55e116-f945-49ba-9c73-85aa7a721240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45321829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.45321829
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.4160954861
Short name T157
Test name
Test status
Simulation time 2242835370 ps
CPU time 2 seconds
Started Jan 10 01:03:47 PM PST 24
Finished Jan 10 01:05:00 PM PST 24
Peak memory 201376 kb
Host smart-645b40b3-70ec-43d4-9bc3-af6d9df3e889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160954861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.4160954861
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1727047599
Short name T353
Test name
Test status
Simulation time 2518825105 ps
CPU time 4.12 seconds
Started Jan 10 12:49:13 PM PST 24
Finished Jan 10 12:50:47 PM PST 24
Peak memory 201312 kb
Host smart-bedeefea-333d-4c7c-87df-e81af8918758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727047599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.1727047599
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.3032034458
Short name T415
Test name
Test status
Simulation time 2120137021 ps
CPU time 2.41 seconds
Started Jan 10 12:49:42 PM PST 24
Finished Jan 10 12:51:13 PM PST 24
Peak memory 201216 kb
Host smart-9de4baa9-8efd-4310-bfea-72297db1c21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032034458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.3032034458
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.743874536
Short name T728
Test name
Test status
Simulation time 12227491855 ps
CPU time 34.1 seconds
Started Jan 10 12:48:31 PM PST 24
Finished Jan 10 12:50:43 PM PST 24
Peak memory 201320 kb
Host smart-6d3937ff-2a29-4e07-ac32-1d88ad94490d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743874536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_st
ress_all.743874536
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1065246147
Short name T147
Test name
Test status
Simulation time 7008467675 ps
CPU time 3.69 seconds
Started Jan 10 12:37:18 PM PST 24
Finished Jan 10 12:37:53 PM PST 24
Peak memory 201380 kb
Host smart-5dfb1219-1c7d-49ed-a6c8-8c3634fd2ca3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065246147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.1065246147
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.707435307
Short name T284
Test name
Test status
Simulation time 2011113204 ps
CPU time 5.96 seconds
Started Jan 10 12:38:12 PM PST 24
Finished Jan 10 12:38:55 PM PST 24
Peak memory 201248 kb
Host smart-6333e081-a7ce-4eb0-be94-6f0ac576297c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707435307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_tes
t.707435307
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1908797841
Short name T585
Test name
Test status
Simulation time 3792020410 ps
CPU time 2.85 seconds
Started Jan 10 12:58:09 PM PST 24
Finished Jan 10 12:59:32 PM PST 24
Peak memory 201344 kb
Host smart-2fefccbe-3259-467c-8dfa-bcdf2af51bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908797841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
908797841
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.251094946
Short name T108
Test name
Test status
Simulation time 145343553574 ps
CPU time 341.67 seconds
Started Jan 10 12:46:19 PM PST 24
Finished Jan 10 12:53:17 PM PST 24
Peak memory 201576 kb
Host smart-5858a3a5-6976-4836-97fc-d2e8883e2f9d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251094946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_combo_detect.251094946
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.917062054
Short name T803
Test name
Test status
Simulation time 3479360497 ps
CPU time 9.9 seconds
Started Jan 10 12:55:41 PM PST 24
Finished Jan 10 12:56:59 PM PST 24
Peak memory 201268 kb
Host smart-fc040e80-f0f6-4891-9173-4b81196d0cce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917062054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_ec_pwr_on_rst.917062054
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2392954009
Short name T473
Test name
Test status
Simulation time 2612219350 ps
CPU time 7.37 seconds
Started Jan 10 12:38:14 PM PST 24
Finished Jan 10 12:38:57 PM PST 24
Peak memory 201356 kb
Host smart-c25ee6d5-c145-4a30-a2c2-018030d5cb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392954009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2392954009
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.4265640249
Short name T412
Test name
Test status
Simulation time 2465734061 ps
CPU time 4.01 seconds
Started Jan 10 12:46:20 PM PST 24
Finished Jan 10 12:47:43 PM PST 24
Peak memory 201380 kb
Host smart-86495757-960e-4975-9fbe-8398613aad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265640249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.4265640249
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2672815291
Short name T553
Test name
Test status
Simulation time 2125994457 ps
CPU time 5.83 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:41:20 PM PST 24
Peak memory 201236 kb
Host smart-3f1b9c0d-7b87-4ad8-a41a-87ba1cf0a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672815291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2672815291
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3007388308
Short name T818
Test name
Test status
Simulation time 2514296134 ps
CPU time 6.03 seconds
Started Jan 10 01:01:43 PM PST 24
Finished Jan 10 01:03:26 PM PST 24
Peak memory 201380 kb
Host smart-3dfbd52a-92b1-4192-a56c-4e33b5c703da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007388308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.3007388308
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.2351313248
Short name T793
Test name
Test status
Simulation time 2124910527 ps
CPU time 2.54 seconds
Started Jan 10 12:48:26 PM PST 24
Finished Jan 10 12:49:52 PM PST 24
Peak memory 201308 kb
Host smart-a0db075d-9832-4296-a187-c375051a78c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351313248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2351313248
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1887477536
Short name T538
Test name
Test status
Simulation time 51097208936 ps
CPU time 32.07 seconds
Started Jan 10 12:41:48 PM PST 24
Finished Jan 10 12:43:29 PM PST 24
Peak memory 201388 kb
Host smart-c6b4a4ee-e9d1-4549-8536-7990ca56a804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887477536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1887477536
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.910120300
Short name T446
Test name
Test status
Simulation time 46823309050 ps
CPU time 30.59 seconds
Started Jan 10 12:49:57 PM PST 24
Finished Jan 10 12:52:09 PM PST 24
Peak memory 209884 kb
Host smart-5d044215-9a98-4848-8e8a-7252d7a508e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910120300 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.910120300
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2739273847
Short name T458
Test name
Test status
Simulation time 8293547301 ps
CPU time 4.38 seconds
Started Jan 10 12:41:31 PM PST 24
Finished Jan 10 12:42:42 PM PST 24
Peak memory 201280 kb
Host smart-5b1e700a-c377-45c1-a6b3-966faaffdf07
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739273847 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ultra_low_pwr.2739273847
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.3590437996
Short name T792
Test name
Test status
Simulation time 2081315679 ps
CPU time 1 seconds
Started Jan 10 12:40:46 PM PST 24
Finished Jan 10 12:41:34 PM PST 24
Peak memory 201304 kb
Host smart-e6af078f-6f16-4b9c-a3b6-56c900dc0df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590437996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.3590437996
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.441642420
Short name T533
Test name
Test status
Simulation time 3222540223 ps
CPU time 2.66 seconds
Started Jan 10 01:06:19 PM PST 24
Finished Jan 10 01:07:40 PM PST 24
Peak memory 201452 kb
Host smart-f55ee761-9c32-4af0-a006-aff0e3d1a205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441642420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.441642420
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.3947271921
Short name T697
Test name
Test status
Simulation time 60415897831 ps
CPU time 38.32 seconds
Started Jan 10 12:40:11 PM PST 24
Finished Jan 10 12:41:36 PM PST 24
Peak memory 201420 kb
Host smart-ae10407d-7a21-4369-951b-d46281de78b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947271921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_combo_detect.3947271921
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.578277086
Short name T119
Test name
Test status
Simulation time 2798218884 ps
CPU time 3.83 seconds
Started Jan 10 01:04:16 PM PST 24
Finished Jan 10 01:05:41 PM PST 24
Peak memory 201352 kb
Host smart-a26c63ec-e4d0-4aea-a1aa-b28b7b6dd991
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578277086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_c
trl_ec_pwr_on_rst.578277086
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.2942275567
Short name T190
Test name
Test status
Simulation time 2877261875 ps
CPU time 6.31 seconds
Started Jan 10 12:34:53 PM PST 24
Finished Jan 10 12:35:40 PM PST 24
Peak memory 201260 kb
Host smart-9ffb59d2-ab06-40c1-927a-4c1116c9b1a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942275567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.2942275567
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.739360369
Short name T558
Test name
Test status
Simulation time 2632681020 ps
CPU time 2.57 seconds
Started Jan 10 12:40:05 PM PST 24
Finished Jan 10 12:40:53 PM PST 24
Peak memory 201180 kb
Host smart-5e52d45f-8217-48df-a9dc-3cf1c86e9d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739360369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.739360369
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.3574277111
Short name T450
Test name
Test status
Simulation time 2491148282 ps
CPU time 2.36 seconds
Started Jan 10 12:40:06 PM PST 24
Finished Jan 10 12:40:53 PM PST 24
Peak memory 201212 kb
Host smart-9d0970cb-afa7-4c7f-a48c-f1c5caf4271a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574277111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.3574277111
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.773958723
Short name T193
Test name
Test status
Simulation time 2017315532 ps
CPU time 5.86 seconds
Started Jan 10 12:45:00 PM PST 24
Finished Jan 10 12:46:31 PM PST 24
Peak memory 201352 kb
Host smart-9949963c-2534-43e8-8baf-0d252a66f8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773958723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.773958723
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.4184149517
Short name T709
Test name
Test status
Simulation time 2539398488 ps
CPU time 2.2 seconds
Started Jan 10 12:55:05 PM PST 24
Finished Jan 10 12:56:12 PM PST 24
Peak memory 201360 kb
Host smart-6f40cab7-28c8-4590-b0cb-b41a8bc2ea65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184149517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.4184149517
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2325731646
Short name T508
Test name
Test status
Simulation time 2112042811 ps
CPU time 5.86 seconds
Started Jan 10 12:58:06 PM PST 24
Finished Jan 10 12:59:32 PM PST 24
Peak memory 201288 kb
Host smart-a055e496-eec7-4496-aa56-bd09fe86c36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325731646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2325731646
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.2814465943
Short name T847
Test name
Test status
Simulation time 21669311082 ps
CPU time 27.22 seconds
Started Jan 10 12:37:55 PM PST 24
Finished Jan 10 12:38:56 PM PST 24
Peak memory 201392 kb
Host smart-db7a60fe-c24f-4864-9679-1c73377fea02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814465943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s
tress_all.2814465943
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1617113554
Short name T680
Test name
Test status
Simulation time 46212654819 ps
CPU time 15.28 seconds
Started Jan 10 12:38:05 PM PST 24
Finished Jan 10 12:38:55 PM PST 24
Peak memory 201880 kb
Host smart-bc6ac43c-3360-475c-806c-1fad9604daad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617113554 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1617113554
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.3368587547
Short name T767
Test name
Test status
Simulation time 2035391950 ps
CPU time 1.89 seconds
Started Jan 10 01:07:59 PM PST 24
Finished Jan 10 01:09:35 PM PST 24
Peak memory 201396 kb
Host smart-df1df95a-a44e-41f9-990c-43b1af3285b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368587547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.3368587547
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1053143608
Short name T234
Test name
Test status
Simulation time 3237339592 ps
CPU time 8.45 seconds
Started Jan 10 12:46:19 PM PST 24
Finished Jan 10 12:47:44 PM PST 24
Peak memory 201364 kb
Host smart-5dbb1f39-81a6-402b-8c79-f8e91124df52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053143608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1
053143608
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2728255717
Short name T681
Test name
Test status
Simulation time 230024633413 ps
CPU time 157.78 seconds
Started Jan 10 01:13:12 PM PST 24
Finished Jan 10 01:17:16 PM PST 24
Peak memory 201760 kb
Host smart-d7b89acc-5f0c-4261-a7b6-e44e44cad21f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728255717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2728255717
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.230803048
Short name T339
Test name
Test status
Simulation time 114917081547 ps
CPU time 285.86 seconds
Started Jan 10 12:44:01 PM PST 24
Finished Jan 10 12:50:01 PM PST 24
Peak memory 201756 kb
Host smart-e4f2713c-3ccf-46d6-ae08-ccfec41e6ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230803048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_wi
th_pre_cond.230803048
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2095409294
Short name T531
Test name
Test status
Simulation time 3741670906 ps
CPU time 3.31 seconds
Started Jan 10 12:49:09 PM PST 24
Finished Jan 10 12:50:43 PM PST 24
Peak memory 201376 kb
Host smart-c2b4a5fc-a61c-448a-bf78-2e636f36f67e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095409294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ec_pwr_on_rst.2095409294
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1547304951
Short name T198
Test name
Test status
Simulation time 3509353067 ps
CPU time 5.02 seconds
Started Jan 10 12:49:15 PM PST 24
Finished Jan 10 12:50:52 PM PST 24
Peak memory 201360 kb
Host smart-083ca894-fdf2-40c0-95a0-da5598dfe3a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547304951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.1547304951
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.992886915
Short name T447
Test name
Test status
Simulation time 2630177870 ps
CPU time 2.34 seconds
Started Jan 10 12:40:16 PM PST 24
Finished Jan 10 12:41:05 PM PST 24
Peak memory 201272 kb
Host smart-8584c5fd-9823-4b48-81d0-2e82d9ffa9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992886915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.992886915
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2034470536
Short name T411
Test name
Test status
Simulation time 2466713934 ps
CPU time 6.37 seconds
Started Jan 10 01:08:19 PM PST 24
Finished Jan 10 01:09:44 PM PST 24
Peak memory 201300 kb
Host smart-aeb92ed4-5910-45b6-b811-d93f1a033992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034470536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.2034470536
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2160131467
Short name T645
Test name
Test status
Simulation time 2194192007 ps
CPU time 1.98 seconds
Started Jan 10 12:36:11 PM PST 24
Finished Jan 10 12:36:43 PM PST 24
Peak memory 201300 kb
Host smart-474812db-5ec2-453e-88b8-b9b6661eec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160131467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2160131467
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1665766741
Short name T802
Test name
Test status
Simulation time 2509409242 ps
CPU time 6.84 seconds
Started Jan 10 12:46:17 PM PST 24
Finished Jan 10 12:47:42 PM PST 24
Peak memory 201296 kb
Host smart-7eed09c2-d14a-475a-ba83-151335dfb97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665766741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1665766741
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.3686856775
Short name T487
Test name
Test status
Simulation time 2136998033 ps
CPU time 1.62 seconds
Started Jan 10 12:36:09 PM PST 24
Finished Jan 10 12:36:40 PM PST 24
Peak memory 201380 kb
Host smart-a14a31d6-5e35-4571-ad77-489a3cc102dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686856775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3686856775
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1747312525
Short name T798
Test name
Test status
Simulation time 1993628228212 ps
CPU time 315.45 seconds
Started Jan 10 12:40:23 PM PST 24
Finished Jan 10 12:46:25 PM PST 24
Peak memory 218224 kb
Host smart-050cfac1-e8ea-47ef-8920-1965820e0fa5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747312525 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1747312525
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3732757982
Short name T660
Test name
Test status
Simulation time 11475229239 ps
CPU time 4.97 seconds
Started Jan 10 12:37:36 PM PST 24
Finished Jan 10 12:38:14 PM PST 24
Peak memory 201280 kb
Host smart-6f4e3d04-50bc-4cdd-83dc-be4eceacdba2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732757982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.3732757982
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.3431707984
Short name T606
Test name
Test status
Simulation time 2037064534 ps
CPU time 1.84 seconds
Started Jan 10 12:40:23 PM PST 24
Finished Jan 10 12:41:12 PM PST 24
Peak memory 201304 kb
Host smart-f4b7a2af-c7df-45b2-8ec9-1b94030217b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431707984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.3431707984
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1585472763
Short name T160
Test name
Test status
Simulation time 3589927789 ps
CPU time 5.36 seconds
Started Jan 10 01:06:27 PM PST 24
Finished Jan 10 01:07:55 PM PST 24
Peak memory 200156 kb
Host smart-ea1047ff-53c6-4585-a888-260a2263d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585472763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.1
585472763
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2080652593
Short name T840
Test name
Test status
Simulation time 161978187781 ps
CPU time 97.66 seconds
Started Jan 10 12:55:19 PM PST 24
Finished Jan 10 12:58:04 PM PST 24
Peak memory 201564 kb
Host smart-06e301a7-7de4-4a91-a01b-3e4885c6fb47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080652593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.2080652593
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1036672924
Short name T741
Test name
Test status
Simulation time 3318157589 ps
CPU time 2.86 seconds
Started Jan 10 12:35:17 PM PST 24
Finished Jan 10 12:35:51 PM PST 24
Peak memory 201288 kb
Host smart-b7b64623-07ae-4cc6-bd02-0a0495c81557
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036672924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.1036672924
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1072972232
Short name T730
Test name
Test status
Simulation time 2616856576 ps
CPU time 7.59 seconds
Started Jan 10 12:38:57 PM PST 24
Finished Jan 10 12:39:36 PM PST 24
Peak memory 201308 kb
Host smart-b4f3856c-7d98-43b6-9351-09da72f9c471
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072972232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.1072972232
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3586453221
Short name T416
Test name
Test status
Simulation time 2625790357 ps
CPU time 2.42 seconds
Started Jan 10 12:38:25 PM PST 24
Finished Jan 10 12:39:01 PM PST 24
Peak memory 201276 kb
Host smart-90549bb5-b705-48a4-b21a-9dbb9cf807fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586453221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3586453221
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.672020998
Short name T482
Test name
Test status
Simulation time 2485417420 ps
CPU time 1.64 seconds
Started Jan 10 01:16:27 PM PST 24
Finished Jan 10 01:17:30 PM PST 24
Peak memory 201304 kb
Host smart-4b737837-573b-4221-83c9-0e88f7162032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672020998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.672020998
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.625021312
Short name T665
Test name
Test status
Simulation time 2209545716 ps
CPU time 6.34 seconds
Started Jan 10 12:39:59 PM PST 24
Finished Jan 10 12:40:46 PM PST 24
Peak memory 201364 kb
Host smart-204125c8-2201-42b0-93ca-710144e35e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625021312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.625021312
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.63097964
Short name T631
Test name
Test status
Simulation time 2511740628 ps
CPU time 5.73 seconds
Started Jan 10 01:06:49 PM PST 24
Finished Jan 10 01:08:13 PM PST 24
Peak memory 201008 kb
Host smart-492dcfc3-f814-47de-912a-d6fee3ce90fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63097964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.63097964
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.2034222859
Short name T197
Test name
Test status
Simulation time 2137527353 ps
CPU time 1.94 seconds
Started Jan 10 12:46:54 PM PST 24
Finished Jan 10 12:48:13 PM PST 24
Peak memory 201332 kb
Host smart-3a5b4339-d0cb-46ac-af69-b29294512b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034222859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2034222859
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.3861095538
Short name T98
Test name
Test status
Simulation time 7767171694 ps
CPU time 11.13 seconds
Started Jan 10 01:10:24 PM PST 24
Finished Jan 10 01:11:52 PM PST 24
Peak memory 201500 kb
Host smart-391d3e49-5a9b-4c07-9c0e-76e7d015d2fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861095538 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.3861095538
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3744666158
Short name T683
Test name
Test status
Simulation time 33445667343 ps
CPU time 84.48 seconds
Started Jan 10 12:50:55 PM PST 24
Finished Jan 10 12:53:44 PM PST 24
Peak memory 209912 kb
Host smart-ddc03495-27a5-4179-8fbf-c8d873019600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744666158 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3744666158
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2724324994
Short name T574
Test name
Test status
Simulation time 9719265339 ps
CPU time 2.19 seconds
Started Jan 10 12:41:11 PM PST 24
Finished Jan 10 12:42:14 PM PST 24
Peak memory 201288 kb
Host smart-f0f03749-818c-41a4-bc9c-b0e504249b7c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724324994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.2724324994
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.2631458211
Short name T236
Test name
Test status
Simulation time 2011009498 ps
CPU time 5.7 seconds
Started Jan 10 12:43:26 PM PST 24
Finished Jan 10 12:44:50 PM PST 24
Peak memory 201240 kb
Host smart-32c670aa-1c59-4709-9603-32f551b33663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631458211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.2631458211
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.1461087463
Short name T758
Test name
Test status
Simulation time 3837792730 ps
CPU time 3.38 seconds
Started Jan 10 12:47:43 PM PST 24
Finished Jan 10 12:49:10 PM PST 24
Peak memory 201420 kb
Host smart-8c77d12f-70e4-4b5b-8d95-9e07b4847f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461087463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.1
461087463
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.4152611304
Short name T253
Test name
Test status
Simulation time 60946147763 ps
CPU time 160.49 seconds
Started Jan 10 01:05:55 PM PST 24
Finished Jan 10 01:09:57 PM PST 24
Peak memory 201740 kb
Host smart-741cd820-4c19-4cab-b8a3-c4e7ff153ce1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152611304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_combo_detect.4152611304
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2639059120
Short name T745
Test name
Test status
Simulation time 49029379962 ps
CPU time 131.26 seconds
Started Jan 10 12:51:15 PM PST 24
Finished Jan 10 12:54:53 PM PST 24
Peak memory 201724 kb
Host smart-a4aff943-7a7e-4e9c-ba5d-20d150eaa38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639059120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.2639059120
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.3024231318
Short name T466
Test name
Test status
Simulation time 3719485609 ps
CPU time 5.38 seconds
Started Jan 10 12:36:04 PM PST 24
Finished Jan 10 12:36:34 PM PST 24
Peak memory 201396 kb
Host smart-59c86e8d-90e7-406d-8500-61eca29e8da0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024231318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ec_pwr_on_rst.3024231318
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.2977013464
Short name T82
Test name
Test status
Simulation time 3509801684 ps
CPU time 2.62 seconds
Started Jan 10 12:44:05 PM PST 24
Finished Jan 10 12:45:22 PM PST 24
Peak memory 201232 kb
Host smart-854f3925-e4e2-41eb-98a6-e1d90bbc2445
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977013464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.2977013464
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4078844865
Short name T578
Test name
Test status
Simulation time 2615787751 ps
CPU time 6.35 seconds
Started Jan 10 12:53:46 PM PST 24
Finished Jan 10 12:55:02 PM PST 24
Peak memory 201296 kb
Host smart-0cf1aa86-480e-4d5b-9440-b59688faa10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078844865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.4078844865
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.651507442
Short name T210
Test name
Test status
Simulation time 2047085418 ps
CPU time 6.29 seconds
Started Jan 10 12:40:26 PM PST 24
Finished Jan 10 12:41:18 PM PST 24
Peak memory 201164 kb
Host smart-ac43ea32-36a6-466c-9563-35d3f5e5d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651507442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.651507442
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.1522130336
Short name T816
Test name
Test status
Simulation time 2514233087 ps
CPU time 7.12 seconds
Started Jan 10 12:49:02 PM PST 24
Finished Jan 10 12:50:51 PM PST 24
Peak memory 201388 kb
Host smart-e37d4869-34c7-4a69-a5db-cd0588dc19d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522130336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1522130336
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.1388217281
Short name T774
Test name
Test status
Simulation time 2111420557 ps
CPU time 6.02 seconds
Started Jan 10 12:40:33 PM PST 24
Finished Jan 10 12:41:23 PM PST 24
Peak memory 201220 kb
Host smart-28ca8dbe-6ef2-40fc-934b-1647655ce679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388217281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1388217281
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.4062185984
Short name T417
Test name
Test status
Simulation time 10082105667 ps
CPU time 7.86 seconds
Started Jan 10 12:44:10 PM PST 24
Finished Jan 10 12:45:34 PM PST 24
Peak memory 201420 kb
Host smart-9480e5af-4f36-41cd-80c9-4e8caebb5162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062185984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.4062185984
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2749579966
Short name T225
Test name
Test status
Simulation time 43746679231 ps
CPU time 24.13 seconds
Started Jan 10 12:40:34 PM PST 24
Finished Jan 10 12:41:42 PM PST 24
Peak memory 209976 kb
Host smart-5e7f29c4-4c36-425c-af98-c83947d8c37a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749579966 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.2749579966
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.1992335921
Short name T800
Test name
Test status
Simulation time 6513728256 ps
CPU time 3.74 seconds
Started Jan 10 12:40:18 PM PST 24
Finished Jan 10 12:41:09 PM PST 24
Peak memory 201352 kb
Host smart-631cd579-f774-43f0-8937-81312e7efdc9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992335921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.1992335921
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.2109168525
Short name T835
Test name
Test status
Simulation time 2036335820 ps
CPU time 1.82 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:18 PM PST 24
Peak memory 201116 kb
Host smart-44b774b5-b729-4523-afb1-0612deca4270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109168525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes
t.2109168525
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3066723124
Short name T804
Test name
Test status
Simulation time 3607503396 ps
CPU time 2.96 seconds
Started Jan 10 12:30:31 PM PST 24
Finished Jan 10 12:31:16 PM PST 24
Peak memory 201344 kb
Host smart-3341065f-4f88-4f64-9be4-d59b84bea18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066723124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.3066723124
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3224867048
Short name T145
Test name
Test status
Simulation time 107036086894 ps
CPU time 69.22 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 201584 kb
Host smart-a96bde79-a0ed-4d3f-8295-38661af308c5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224867048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.3224867048
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.297959694
Short name T332
Test name
Test status
Simulation time 93359795046 ps
CPU time 127.47 seconds
Started Jan 10 12:30:39 PM PST 24
Finished Jan 10 12:33:30 PM PST 24
Peak memory 201500 kb
Host smart-4d3e27b3-1397-466f-8868-08ea0d530495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297959694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wit
h_pre_cond.297959694
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.143127902
Short name T524
Test name
Test status
Simulation time 4422171730 ps
CPU time 3.07 seconds
Started Jan 10 12:30:43 PM PST 24
Finished Jan 10 12:31:30 PM PST 24
Peak memory 201260 kb
Host smart-4f868de8-e8bd-4c94-afc1-404b9c9bba2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143127902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ec_pwr_on_rst.143127902
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.3477238604
Short name T50
Test name
Test status
Simulation time 2392442260 ps
CPU time 1.87 seconds
Started Jan 10 12:30:47 PM PST 24
Finished Jan 10 12:31:33 PM PST 24
Peak memory 201372 kb
Host smart-a797ce86-8113-42c6-b4c2-b919bc22b875
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477238604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.3477238604
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1954548639
Short name T221
Test name
Test status
Simulation time 2613960351 ps
CPU time 7 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 201284 kb
Host smart-09a5e08e-7b30-4d49-98a7-bb79d151156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954548639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.1954548639
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1865172030
Short name T153
Test name
Test status
Simulation time 2456374160 ps
CPU time 6.62 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:31:31 PM PST 24
Peak memory 201360 kb
Host smart-7b60010e-66ab-498e-a2f0-26e2d7dece85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865172030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1865172030
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.343324221
Short name T472
Test name
Test status
Simulation time 2074835350 ps
CPU time 3.28 seconds
Started Jan 10 12:30:32 PM PST 24
Finished Jan 10 12:31:24 PM PST 24
Peak memory 201160 kb
Host smart-41669a31-2548-430f-8974-059d69efefae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343324221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.343324221
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.4111128164
Short name T463
Test name
Test status
Simulation time 2516965464 ps
CPU time 3.96 seconds
Started Jan 10 12:30:36 PM PST 24
Finished Jan 10 12:31:23 PM PST 24
Peak memory 201324 kb
Host smart-be6eb552-0ab7-40c9-ba45-d12dd6277210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111128164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.4111128164
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.1058006675
Short name T738
Test name
Test status
Simulation time 2132478885 ps
CPU time 2.06 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:31:38 PM PST 24
Peak memory 201272 kb
Host smart-0b8dd2cd-03e9-45e6-976f-d004442d571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058006675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1058006675
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.2195146526
Short name T563
Test name
Test status
Simulation time 15656434260 ps
CPU time 5.95 seconds
Started Jan 10 12:30:38 PM PST 24
Finished Jan 10 12:31:27 PM PST 24
Peak memory 201420 kb
Host smart-46a67fff-ab90-4f51-ab21-a353e3e190b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195146526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st
ress_all.2195146526
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1643294398
Short name T141
Test name
Test status
Simulation time 5297513673 ps
CPU time 6.96 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:23 PM PST 24
Peak memory 201264 kb
Host smart-7d46217f-8c1a-4392-8d5a-0e98d46e7808
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643294398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.1643294398
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3311001297
Short name T28
Test name
Test status
Simulation time 36508306457 ps
CPU time 92.99 seconds
Started Jan 10 12:44:00 PM PST 24
Finished Jan 10 12:46:48 PM PST 24
Peak memory 201636 kb
Host smart-646d1d72-a995-4b82-a75e-e483ae395149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311001297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.3311001297
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2026610434
Short name T724
Test name
Test status
Simulation time 25610733402 ps
CPU time 16.36 seconds
Started Jan 10 12:46:18 PM PST 24
Finished Jan 10 12:47:51 PM PST 24
Peak memory 201736 kb
Host smart-4aa6a53c-c334-46bf-9f4f-a07c41b4aef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026610434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.2026610434
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.292072699
Short name T746
Test name
Test status
Simulation time 51243723764 ps
CPU time 32.56 seconds
Started Jan 10 12:56:27 PM PST 24
Finished Jan 10 12:58:09 PM PST 24
Peak memory 201748 kb
Host smart-76cdc800-b201-4336-a0f2-229dafec35c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292072699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_wi
th_pre_cond.292072699
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.3740116578
Short name T347
Test name
Test status
Simulation time 118717379023 ps
CPU time 82.9 seconds
Started Jan 10 12:47:56 PM PST 24
Finished Jan 10 12:50:48 PM PST 24
Peak memory 201736 kb
Host smart-23bdd474-615e-4036-ab00-1c862568fcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740116578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_w
ith_pre_cond.3740116578
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.3395706274
Short name T81
Test name
Test status
Simulation time 91356756644 ps
CPU time 251.05 seconds
Started Jan 10 12:35:53 PM PST 24
Finished Jan 10 12:40:27 PM PST 24
Peak memory 201612 kb
Host smart-0f1a3d54-e49b-4ad9-b185-56eea73dcfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395706274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.3395706274
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.3709665096
Short name T337
Test name
Test status
Simulation time 87587894119 ps
CPU time 32.48 seconds
Started Jan 10 01:01:12 PM PST 24
Finished Jan 10 01:03:08 PM PST 24
Peak memory 201680 kb
Host smart-6f838937-7b4d-4963-855c-6fe4397ea80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709665096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_w
ith_pre_cond.3709665096
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1041850514
Short name T267
Test name
Test status
Simulation time 25091232184 ps
CPU time 35.13 seconds
Started Jan 10 12:45:27 PM PST 24
Finished Jan 10 12:47:22 PM PST 24
Peak memory 201672 kb
Host smart-2e0d2b3c-ffae-4100-809b-e4f70bed94f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041850514 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.1041850514
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3676100135
Short name T317
Test name
Test status
Simulation time 59500749496 ps
CPU time 150.59 seconds
Started Jan 10 12:37:42 PM PST 24
Finished Jan 10 12:40:48 PM PST 24
Peak memory 201624 kb
Host smart-33e5536c-2358-4d4b-8422-186e8fc201b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676100135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w
ith_pre_cond.3676100135
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.3155539759
Short name T136
Test name
Test status
Simulation time 2028153720 ps
CPU time 1.87 seconds
Started Jan 10 12:30:35 PM PST 24
Finished Jan 10 12:31:20 PM PST 24
Peak memory 201124 kb
Host smart-2c484c26-19b9-437a-b5a0-2fba66a7474c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155539759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes
t.3155539759
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.4227743417
Short name T644
Test name
Test status
Simulation time 3532120747 ps
CPU time 10.06 seconds
Started Jan 10 12:30:44 PM PST 24
Finished Jan 10 12:31:38 PM PST 24
Peak memory 201248 kb
Host smart-5627067c-3859-4f83-bb24-7e3377e21ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227743417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.4227743417
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.409418862
Short name T127
Test name
Test status
Simulation time 3741350462 ps
CPU time 2.64 seconds
Started Jan 10 12:30:29 PM PST 24
Finished Jan 10 12:31:13 PM PST 24
Peak memory 201324 kb
Host smart-981e84b1-17a0-418c-846f-507e35ed7daa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409418862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_ec_pwr_on_rst.409418862
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.37907684
Short name T224
Test name
Test status
Simulation time 2522527365 ps
CPU time 3.68 seconds
Started Jan 10 12:30:35 PM PST 24
Finished Jan 10 12:31:22 PM PST 24
Peak memory 201184 kb
Host smart-4b334f91-5491-4f21-9337-90cd553c06b6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37907684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_
edge_detect.37907684
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.884340419
Short name T149
Test name
Test status
Simulation time 2622786751 ps
CPU time 4.01 seconds
Started Jan 10 12:30:41 PM PST 24
Finished Jan 10 12:31:27 PM PST 24
Peak memory 201240 kb
Host smart-b9ae01be-6993-4671-8def-b922992d28b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884340419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.884340419
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3954071257
Short name T717
Test name
Test status
Simulation time 2453280902 ps
CPU time 6.68 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:22 PM PST 24
Peak memory 201144 kb
Host smart-4b56b28f-b947-4801-99af-884d00e27f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954071257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.3954071257
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.1011784713
Short name T698
Test name
Test status
Simulation time 2235587837 ps
CPU time 2.11 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:31:38 PM PST 24
Peak memory 201564 kb
Host smart-78d38d0f-b199-4f18-8f2b-c7f0cfa4ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011784713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.1011784713
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1290617363
Short name T502
Test name
Test status
Simulation time 2518027852 ps
CPU time 3.68 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:31:38 PM PST 24
Peak memory 201268 kb
Host smart-245646a9-5fed-423b-a69f-08e6dcf8ec74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290617363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1290617363
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.2395621405
Short name T837
Test name
Test status
Simulation time 2113192981 ps
CPU time 3.23 seconds
Started Jan 10 12:30:53 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201164 kb
Host smart-b22578c2-af66-402b-b335-680eec55b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395621405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.2395621405
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.1498081374
Short name T498
Test name
Test status
Simulation time 9196241121 ps
CPU time 3.59 seconds
Started Jan 10 12:31:06 PM PST 24
Finished Jan 10 12:31:55 PM PST 24
Peak memory 201200 kb
Host smart-d423cb5d-a3df-4c10-a278-dd9c45224fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498081374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.1498081374
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3665895989
Short name T510
Test name
Test status
Simulation time 11543281382 ps
CPU time 1.97 seconds
Started Jan 10 12:30:36 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 201368 kb
Host smart-c5d91a7e-28b5-4229-9777-bb0128af2ce3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665895989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ultra_low_pwr.3665895989
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3107177871
Short name T251
Test name
Test status
Simulation time 121304082505 ps
CPU time 86.85 seconds
Started Jan 10 12:46:02 PM PST 24
Finished Jan 10 12:48:53 PM PST 24
Peak memory 201700 kb
Host smart-b6f72cf7-7a2a-4405-813f-422062a75787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107177871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_w
ith_pre_cond.3107177871
Directory /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.443005001
Short name T309
Test name
Test status
Simulation time 144115590234 ps
CPU time 180.42 seconds
Started Jan 10 12:50:04 PM PST 24
Finished Jan 10 12:55:09 PM PST 24
Peak memory 201596 kb
Host smart-b8063fd2-9e43-458c-b749-bef3400758d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443005001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_wi
th_pre_cond.443005001
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.2588445704
Short name T736
Test name
Test status
Simulation time 27602521770 ps
CPU time 20.02 seconds
Started Jan 10 12:45:37 PM PST 24
Finished Jan 10 12:47:15 PM PST 24
Peak memory 201724 kb
Host smart-2b415cbd-d444-48d9-8711-b5b89883ef5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588445704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_w
ith_pre_cond.2588445704
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.599748043
Short name T720
Test name
Test status
Simulation time 54992261821 ps
CPU time 39.1 seconds
Started Jan 10 12:35:26 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 201588 kb
Host smart-07d82fcb-3bd4-4ff0-81a2-da97d149ac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599748043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_wi
th_pre_cond.599748043
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1917288701
Short name T316
Test name
Test status
Simulation time 48399266952 ps
CPU time 14.17 seconds
Started Jan 10 12:45:10 PM PST 24
Finished Jan 10 12:46:47 PM PST 24
Peak memory 201576 kb
Host smart-ad4ba93b-e61e-408c-9d06-77b160d0d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917288701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.1917288701
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2272758390
Short name T245
Test name
Test status
Simulation time 25080376153 ps
CPU time 65.42 seconds
Started Jan 10 12:40:29 PM PST 24
Finished Jan 10 12:42:19 PM PST 24
Peak memory 201680 kb
Host smart-d4b0ebed-9650-4627-84c0-917709409c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272758390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.2272758390
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1643220998
Short name T638
Test name
Test status
Simulation time 34609055642 ps
CPU time 23.6 seconds
Started Jan 10 12:41:05 PM PST 24
Finished Jan 10 12:42:28 PM PST 24
Peak memory 201580 kb
Host smart-281019d8-7c88-4c43-b5ea-3507c61d3c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643220998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.1643220998
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.3758125122
Short name T617
Test name
Test status
Simulation time 2009291412 ps
CPU time 5.66 seconds
Started Jan 10 12:30:42 PM PST 24
Finished Jan 10 12:31:31 PM PST 24
Peak memory 200952 kb
Host smart-797bc83a-e77f-4bef-bce5-c758094a797a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758125122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes
t.3758125122
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.2152060678
Short name T479
Test name
Test status
Simulation time 3407759299 ps
CPU time 1.61 seconds
Started Jan 10 12:31:09 PM PST 24
Finished Jan 10 12:31:57 PM PST 24
Peak memory 201240 kb
Host smart-fdcfb46e-de22-4014-a161-2cef2b341861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152060678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.2152060678
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.4009687651
Short name T848
Test name
Test status
Simulation time 105120774356 ps
CPU time 67.99 seconds
Started Jan 10 12:30:50 PM PST 24
Finished Jan 10 12:32:43 PM PST 24
Peak memory 201588 kb
Host smart-56868d15-eeae-4964-a796-d0c7d51c9ac3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009687651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct
rl_combo_detect.4009687651
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.554620894
Short name T639
Test name
Test status
Simulation time 57899978563 ps
CPU time 17.04 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:33:10 PM PST 24
Peak memory 201300 kb
Host smart-5707a553-e330-417e-a347-7875933d68ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554620894 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.554620894
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2323742008
Short name T42
Test name
Test status
Simulation time 740710510524 ps
CPU time 548.55 seconds
Started Jan 10 12:32:08 PM PST 24
Finished Jan 10 12:42:01 PM PST 24
Peak memory 200964 kb
Host smart-45681dfb-10a5-4f75-a5dc-c4b8ee29c9d3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323742008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.2323742008
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.1537237868
Short name T120
Test name
Test status
Simulation time 4328878806 ps
CPU time 2.79 seconds
Started Jan 10 12:30:54 PM PST 24
Finished Jan 10 12:31:42 PM PST 24
Peak memory 201272 kb
Host smart-f5b38c67-764c-4658-b5d4-63586d0e603a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537237868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.1537237868
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.4085478707
Short name T475
Test name
Test status
Simulation time 2611233559 ps
CPU time 7.17 seconds
Started Jan 10 12:32:10 PM PST 24
Finished Jan 10 12:33:02 PM PST 24
Peak memory 200980 kb
Host smart-41f227d1-4240-432b-9586-db983b3b79ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085478707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.4085478707
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.1139535321
Short name T565
Test name
Test status
Simulation time 2456524892 ps
CPU time 7.07 seconds
Started Jan 10 12:31:02 PM PST 24
Finished Jan 10 12:31:56 PM PST 24
Peak memory 201300 kb
Host smart-e9588e5a-48d7-445e-bf39-f84246871d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139535321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.1139535321
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.556407
Short name T420
Test name
Test status
Simulation time 2255537177 ps
CPU time 6.21 seconds
Started Jan 10 12:30:38 PM PST 24
Finished Jan 10 12:31:27 PM PST 24
Peak memory 201376 kb
Host smart-2906bf39-5882-48c5-a6be-6d1ede00315e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.556407
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.963388150
Short name T527
Test name
Test status
Simulation time 2516843594 ps
CPU time 3.86 seconds
Started Jan 10 12:30:50 PM PST 24
Finished Jan 10 12:31:39 PM PST 24
Peak memory 201252 kb
Host smart-a8116338-d1b1-43a3-b499-0f49d33f6fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963388150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.963388150
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.1308694954
Short name T733
Test name
Test status
Simulation time 2110360574 ps
CPU time 5.33 seconds
Started Jan 10 12:30:33 PM PST 24
Finished Jan 10 12:31:21 PM PST 24
Peak memory 201192 kb
Host smart-4493af8d-d34c-4fc5-bcf3-3d31fd60b49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308694954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1308694954
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.3303725324
Short name T94
Test name
Test status
Simulation time 7780876767 ps
CPU time 20.09 seconds
Started Jan 10 12:31:10 PM PST 24
Finished Jan 10 12:32:16 PM PST 24
Peak memory 201416 kb
Host smart-07af7b2d-6d0c-4361-9032-0367c6ff12e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303725324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.3303725324
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2418646815
Short name T770
Test name
Test status
Simulation time 36180984295 ps
CPU time 24.4 seconds
Started Jan 10 12:30:51 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 209972 kb
Host smart-0e68d5ea-43a8-4dbc-aed4-c1a87bc41af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418646815 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2418646815
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2172361867
Short name T60
Test name
Test status
Simulation time 39113177261 ps
CPU time 26.87 seconds
Started Jan 10 12:37:29 PM PST 24
Finished Jan 10 12:38:32 PM PST 24
Peak memory 201700 kb
Host smart-2523cf2e-ac55-4436-9971-380ae48dbd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172361867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w
ith_pre_cond.2172361867
Directory /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.1275894026
Short name T331
Test name
Test status
Simulation time 64812380632 ps
CPU time 168.29 seconds
Started Jan 10 01:06:40 PM PST 24
Finished Jan 10 01:10:40 PM PST 24
Peak memory 201724 kb
Host smart-e9ba20c3-5772-4aaf-abdc-bd4d0ee89176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275894026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.1275894026
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2986467498
Short name T833
Test name
Test status
Simulation time 24335039778 ps
CPU time 67.03 seconds
Started Jan 10 12:51:52 PM PST 24
Finished Jan 10 12:54:22 PM PST 24
Peak memory 201636 kb
Host smart-0e8b6d5c-743a-4ba0-bb44-addc0d0560e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986467498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.2986467498
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2417978259
Short name T513
Test name
Test status
Simulation time 26864091155 ps
CPU time 17.29 seconds
Started Jan 10 01:05:00 PM PST 24
Finished Jan 10 01:06:57 PM PST 24
Peak memory 201708 kb
Host smart-2882d4d4-58df-4d71-b416-6bbba2015c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417978259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w
ith_pre_cond.2417978259
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2750371696
Short name T838
Test name
Test status
Simulation time 27099537889 ps
CPU time 21.02 seconds
Started Jan 10 12:40:08 PM PST 24
Finished Jan 10 12:41:15 PM PST 24
Peak memory 201664 kb
Host smart-1a85c331-2ed2-4445-90fd-3c62166076c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750371696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w
ith_pre_cond.2750371696
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3331870279
Short name T625
Test name
Test status
Simulation time 27341617446 ps
CPU time 35.43 seconds
Started Jan 10 01:01:58 PM PST 24
Finished Jan 10 01:03:59 PM PST 24
Peak memory 201772 kb
Host smart-3aa9b737-bc9f-4196-a087-434cdd52e5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331870279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.3331870279
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.597322140
Short name T598
Test name
Test status
Simulation time 68403402180 ps
CPU time 45.73 seconds
Started Jan 10 12:47:13 PM PST 24
Finished Jan 10 12:49:15 PM PST 24
Peak memory 201600 kb
Host smart-8d0a119f-917e-49b1-bca0-2f199b7c09cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597322140 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_wi
th_pre_cond.597322140
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.3769820101
Short name T431
Test name
Test status
Simulation time 2010110294 ps
CPU time 5.42 seconds
Started Jan 10 12:31:05 PM PST 24
Finished Jan 10 12:31:57 PM PST 24
Peak memory 201248 kb
Host smart-b0f4ebf7-ec7e-4d39-8d25-6bc5f800d06f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769820101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.3769820101
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.218132148
Short name T99
Test name
Test status
Simulation time 3403966834 ps
CPU time 3.1 seconds
Started Jan 10 12:30:45 PM PST 24
Finished Jan 10 12:31:32 PM PST 24
Peak memory 201312 kb
Host smart-d759fce4-c80a-40a9-ab4f-15f5dccabc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218132148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.218132148
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2106133321
Short name T718
Test name
Test status
Simulation time 38419683849 ps
CPU time 26.09 seconds
Started Jan 10 12:30:48 PM PST 24
Finished Jan 10 12:31:59 PM PST 24
Peak memory 201592 kb
Host smart-925ee892-67c7-4081-8f91-c970db9f5ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106133321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.2106133321
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2112083624
Short name T742
Test name
Test status
Simulation time 3207608390 ps
CPU time 8.29 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 12:32:06 PM PST 24
Peak memory 201392 kb
Host smart-28918234-0ee5-4282-843b-64e17b966fa6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112083624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.2112083624
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.3092941211
Short name T85
Test name
Test status
Simulation time 2609696443 ps
CPU time 7.15 seconds
Started Jan 10 12:30:53 PM PST 24
Finished Jan 10 12:31:52 PM PST 24
Peak memory 201316 kb
Host smart-126a9e1f-f726-4bac-84bb-cb50d948e87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092941211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.3092941211
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3420000292
Short name T689
Test name
Test status
Simulation time 2467903641 ps
CPU time 4.06 seconds
Started Jan 10 12:31:12 PM PST 24
Finished Jan 10 12:32:01 PM PST 24
Peak memory 201268 kb
Host smart-d4055ecf-ce29-4c40-8368-d522973ac9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420000292 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.3420000292
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1709101924
Short name T797
Test name
Test status
Simulation time 2066922340 ps
CPU time 6.12 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:31:40 PM PST 24
Peak memory 201184 kb
Host smart-ca70397a-67e5-40ca-9f13-2311ee6daa30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709101924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1709101924
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.672253434
Short name T646
Test name
Test status
Simulation time 2121096739 ps
CPU time 2.92 seconds
Started Jan 10 12:30:58 PM PST 24
Finished Jan 10 12:31:47 PM PST 24
Peak memory 201112 kb
Host smart-09bd7736-b387-457b-a83a-06da86191056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672253434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.672253434
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.2336590559
Short name T227
Test name
Test status
Simulation time 15455728299 ps
CPU time 38.31 seconds
Started Jan 10 12:31:16 PM PST 24
Finished Jan 10 12:32:38 PM PST 24
Peak memory 201268 kb
Host smart-97710211-c989-4290-a9bb-ccbc229b03ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336590559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_st
ress_all.2336590559
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1465544185
Short name T132
Test name
Test status
Simulation time 8710512641 ps
CPU time 2.1 seconds
Started Jan 10 12:31:13 PM PST 24
Finished Jan 10 12:32:00 PM PST 24
Peak memory 201248 kb
Host smart-ad615c28-8cae-467c-9fde-9c075648640e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465544185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.1465544185
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1123951811
Short name T247
Test name
Test status
Simulation time 26600904223 ps
CPU time 19.25 seconds
Started Jan 10 12:40:07 PM PST 24
Finished Jan 10 12:41:13 PM PST 24
Peak memory 201668 kb
Host smart-2dbf10e8-ca36-4f48-a4b3-47f302988720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123951811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.1123951811
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1780820581
Short name T336
Test name
Test status
Simulation time 196257882825 ps
CPU time 490.29 seconds
Started Jan 10 12:40:54 PM PST 24
Finished Jan 10 12:49:55 PM PST 24
Peak memory 201576 kb
Host smart-a3e2f812-5a7c-49f6-9c02-0575cf840244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780820581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w
ith_pre_cond.1780820581
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1187457437
Short name T250
Test name
Test status
Simulation time 78999737790 ps
CPU time 52.39 seconds
Started Jan 10 12:41:22 PM PST 24
Finished Jan 10 12:43:20 PM PST 24
Peak memory 201704 kb
Host smart-5b90e266-7dbd-4f18-ad0e-b3d14a090a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187457437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.1187457437
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.598465348
Short name T266
Test name
Test status
Simulation time 85013412287 ps
CPU time 59.27 seconds
Started Jan 10 12:34:51 PM PST 24
Finished Jan 10 12:36:32 PM PST 24
Peak memory 201592 kb
Host smart-fb7b5e56-7a4c-49d9-b036-c840bbcd1594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598465348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi
th_pre_cond.598465348
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3634504056
Short name T47
Test name
Test status
Simulation time 71651542495 ps
CPU time 33.96 seconds
Started Jan 10 12:43:53 PM PST 24
Finished Jan 10 12:45:41 PM PST 24
Peak memory 201668 kb
Host smart-2b4138ff-21cc-41e8-8299-fad1fc2d534e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634504056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.3634504056
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1404001501
Short name T593
Test name
Test status
Simulation time 30478610183 ps
CPU time 85.46 seconds
Started Jan 10 12:40:00 PM PST 24
Finished Jan 10 12:42:07 PM PST 24
Peak memory 201712 kb
Host smart-f28f539b-a8b5-4d98-88e5-ffe0c901d780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404001501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_w
ith_pre_cond.1404001501
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.2746065291
Short name T796
Test name
Test status
Simulation time 2009982848 ps
CPU time 5.9 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:17 PM PST 24
Peak memory 201304 kb
Host smart-ba92f74c-31df-4cc6-9f91-e623bffdf333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746065291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.2746065291
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.891666281
Short name T96
Test name
Test status
Simulation time 3465656923 ps
CPU time 5.18 seconds
Started Jan 10 12:31:13 PM PST 24
Finished Jan 10 12:32:04 PM PST 24
Peak memory 201244 kb
Host smart-bcf0f396-57d0-4c1e-ad33-ca193c9cb32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891666281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.891666281
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3942207307
Short name T263
Test name
Test status
Simulation time 84189745092 ps
CPU time 45.72 seconds
Started Jan 10 12:31:00 PM PST 24
Finished Jan 10 12:32:33 PM PST 24
Peak memory 201520 kb
Host smart-a63b8875-cd57-43f1-9319-508968befff3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942207307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3942207307
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.2657491194
Short name T831
Test name
Test status
Simulation time 45733190221 ps
CPU time 115.76 seconds
Started Jan 10 12:30:54 PM PST 24
Finished Jan 10 12:33:35 PM PST 24
Peak memory 201644 kb
Host smart-fa9289cd-1c67-4f91-929b-17f7403db5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657491194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.2657491194
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1326972882
Short name T438
Test name
Test status
Simulation time 3682399378 ps
CPU time 5.24 seconds
Started Jan 10 12:30:58 PM PST 24
Finished Jan 10 12:31:51 PM PST 24
Peak memory 201268 kb
Host smart-44c87032-19d9-4eb4-a30f-91ded496a8f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326972882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_ec_pwr_on_rst.1326972882
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.4250988280
Short name T59
Test name
Test status
Simulation time 3480078478 ps
CPU time 3.44 seconds
Started Jan 10 12:31:22 PM PST 24
Finished Jan 10 12:32:13 PM PST 24
Peak memory 201236 kb
Host smart-a6b9a529-5ee8-45a2-a2a0-db58e67114a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250988280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.4250988280
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2079732243
Short name T630
Test name
Test status
Simulation time 2618085608 ps
CPU time 3.75 seconds
Started Jan 10 12:31:23 PM PST 24
Finished Jan 10 12:32:14 PM PST 24
Peak memory 201228 kb
Host smart-06bb9672-1411-4b22-b0ed-6fd04f9eb2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079732243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2079732243
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.3564443503
Short name T518
Test name
Test status
Simulation time 2483735768 ps
CPU time 2.78 seconds
Started Jan 10 12:31:27 PM PST 24
Finished Jan 10 12:32:18 PM PST 24
Peak memory 201212 kb
Host smart-2560de64-388e-41e6-b1a6-c08a5bcc393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564443503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.3564443503
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.722043953
Short name T432
Test name
Test status
Simulation time 2302050280 ps
CPU time 1.17 seconds
Started Jan 10 12:31:07 PM PST 24
Finished Jan 10 12:31:54 PM PST 24
Peak memory 201220 kb
Host smart-74d51c86-64c5-4765-8150-32d7fc01dc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722043953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.722043953
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3526798972
Short name T826
Test name
Test status
Simulation time 2514179588 ps
CPU time 6.69 seconds
Started Jan 10 12:30:53 PM PST 24
Finished Jan 10 12:31:45 PM PST 24
Peak memory 201172 kb
Host smart-7f53260f-2342-46b5-a414-af3dad7158ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526798972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.3526798972
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3578842771
Short name T688
Test name
Test status
Simulation time 2128123759 ps
CPU time 1.96 seconds
Started Jan 10 12:30:49 PM PST 24
Finished Jan 10 12:31:35 PM PST 24
Peak memory 201116 kb
Host smart-08bac349-1610-4c19-8330-0635644ce368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578842771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3578842771
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.4291754059
Short name T753
Test name
Test status
Simulation time 11407035022 ps
CPU time 30.81 seconds
Started Jan 10 12:30:55 PM PST 24
Finished Jan 10 12:32:12 PM PST 24
Peak memory 201328 kb
Host smart-83be6b67-9d3d-44da-934a-e945feb0fe3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291754059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.4291754059
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3434904783
Short name T146
Test name
Test status
Simulation time 543844480582 ps
CPU time 16.56 seconds
Started Jan 10 12:31:03 PM PST 24
Finished Jan 10 12:32:07 PM PST 24
Peak memory 201740 kb
Host smart-63806058-70bd-4cc1-baa7-d8cbad762c73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434904783 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3434904783
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.257189100
Short name T89
Test name
Test status
Simulation time 6004540565 ps
CPU time 7.63 seconds
Started Jan 10 12:31:13 PM PST 24
Finished Jan 10 12:32:06 PM PST 24
Peak memory 201244 kb
Host smart-efccc21c-d2e5-44ad-8bc8-3619c677ba1a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257189100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ultra_low_pwr.257189100
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1443284626
Short name T716
Test name
Test status
Simulation time 27341533710 ps
CPU time 17.85 seconds
Started Jan 10 12:46:10 PM PST 24
Finished Jan 10 12:47:50 PM PST 24
Peak memory 201700 kb
Host smart-06cfd8cb-0f71-44b9-ab93-df2bb9de39ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443284626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.1443284626
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.3315520572
Short name T244
Test name
Test status
Simulation time 131328676266 ps
CPU time 341.6 seconds
Started Jan 10 01:03:51 PM PST 24
Finished Jan 10 01:10:45 PM PST 24
Peak memory 201692 kb
Host smart-4b675a2a-af07-4ed8-8ca7-b31133d26bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315520572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.3315520572
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.366427834
Short name T773
Test name
Test status
Simulation time 29334917351 ps
CPU time 83.39 seconds
Started Jan 10 12:44:33 PM PST 24
Finished Jan 10 12:47:14 PM PST 24
Peak memory 201584 kb
Host smart-baef06f0-37b6-44c8-87be-4b420042d201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366427834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_wi
th_pre_cond.366427834
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3041542686
Short name T706
Test name
Test status
Simulation time 21362339258 ps
CPU time 15.08 seconds
Started Jan 10 12:36:04 PM PST 24
Finished Jan 10 12:36:45 PM PST 24
Peak memory 201664 kb
Host smart-8c0e1a24-46bf-4edf-896a-cb0a41ce1274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041542686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w
ith_pre_cond.3041542686
Directory /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3685630399
Short name T78
Test name
Test status
Simulation time 111010279236 ps
CPU time 295.87 seconds
Started Jan 10 12:47:33 PM PST 24
Finished Jan 10 12:53:48 PM PST 24
Peak memory 201704 kb
Host smart-bed54d20-0ec4-4b2b-bd61-f6cfb515b93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685630399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w
ith_pre_cond.3685630399
Directory /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3736405840
Short name T83
Test name
Test status
Simulation time 55906606232 ps
CPU time 46.18 seconds
Started Jan 10 12:46:10 PM PST 24
Finished Jan 10 12:48:18 PM PST 24
Peak memory 201668 kb
Host smart-c6bd3ef3-7f3e-4718-88e5-3965f584883d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736405840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.3736405840
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3340195903
Short name T55
Test name
Test status
Simulation time 52982115942 ps
CPU time 143.55 seconds
Started Jan 10 12:45:13 PM PST 24
Finished Jan 10 12:48:59 PM PST 24
Peak memory 201716 kb
Host smart-d53b50af-4ce7-4c5f-91db-d10fbe07c55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340195903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.3340195903
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.3612808485
Short name T103
Test name
Test status
Simulation time 26078033929 ps
CPU time 65.05 seconds
Started Jan 10 12:52:07 PM PST 24
Finished Jan 10 12:54:28 PM PST 24
Peak memory 201760 kb
Host smart-6950a37b-8aa6-4a66-ba2f-5f2631443068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612808485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_w
ith_pre_cond.3612808485
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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