Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
953 |
1 |
|
|
T15 |
13 |
|
T58 |
10 |
|
T72 |
14 |
| auto[1] |
937 |
1 |
|
|
T15 |
7 |
|
T58 |
10 |
|
T72 |
6 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
903 |
1 |
|
|
T15 |
8 |
|
T58 |
11 |
|
T72 |
10 |
| auto[1] |
987 |
1 |
|
|
T15 |
12 |
|
T58 |
9 |
|
T72 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
981 |
1 |
|
|
T15 |
15 |
|
T58 |
7 |
|
T72 |
7 |
| auto[1] |
909 |
1 |
|
|
T15 |
5 |
|
T58 |
13 |
|
T72 |
13 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
943 |
1 |
|
|
T15 |
7 |
|
T58 |
15 |
|
T72 |
14 |
| auto[1] |
947 |
1 |
|
|
T15 |
13 |
|
T58 |
5 |
|
T72 |
6 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
944 |
1 |
|
|
T15 |
9 |
|
T58 |
14 |
|
T72 |
11 |
| auto[1] |
946 |
1 |
|
|
T15 |
11 |
|
T58 |
6 |
|
T72 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
972 |
1 |
|
|
T15 |
13 |
|
T58 |
10 |
|
T72 |
14 |
| auto[1] |
918 |
1 |
|
|
T15 |
7 |
|
T58 |
10 |
|
T72 |
6 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
983 |
1 |
|
|
T15 |
11 |
|
T58 |
12 |
|
T72 |
11 |
| auto[1] |
907 |
1 |
|
|
T15 |
9 |
|
T58 |
8 |
|
T72 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
934 |
1 |
|
|
T15 |
11 |
|
T58 |
7 |
|
T72 |
6 |
| auto[1] |
956 |
1 |
|
|
T15 |
9 |
|
T58 |
13 |
|
T72 |
14 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
948 |
1 |
|
|
T15 |
8 |
|
T58 |
11 |
|
T72 |
6 |
| auto[1] |
942 |
1 |
|
|
T15 |
12 |
|
T58 |
9 |
|
T72 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
940 |
1 |
|
|
T15 |
9 |
|
T58 |
11 |
|
T72 |
11 |
| auto[1] |
950 |
1 |
|
|
T15 |
11 |
|
T58 |
9 |
|
T72 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
937 |
1 |
|
|
T15 |
9 |
|
T58 |
11 |
|
T72 |
11 |
| auto[1] |
953 |
1 |
|
|
T15 |
11 |
|
T58 |
9 |
|
T72 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
944 |
1 |
|
|
T15 |
14 |
|
T58 |
8 |
|
T72 |
9 |
| auto[1] |
946 |
1 |
|
|
T15 |
6 |
|
T58 |
12 |
|
T72 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T15 |
8 |
|
T58 |
7 |
|
T72 |
7 |
| auto[1] |
989 |
1 |
|
|
T15 |
12 |
|
T58 |
13 |
|
T72 |
13 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
903 |
1 |
|
|
T15 |
8 |
|
T58 |
11 |
|
T72 |
10 |
| auto[1] |
987 |
1 |
|
|
T15 |
12 |
|
T58 |
9 |
|
T72 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
958 |
1 |
|
|
T15 |
8 |
|
T58 |
13 |
|
T72 |
12 |
| auto[1] |
932 |
1 |
|
|
T15 |
12 |
|
T58 |
7 |
|
T72 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
920 |
1 |
|
|
T15 |
12 |
|
T58 |
9 |
|
T72 |
9 |
| auto[1] |
970 |
1 |
|
|
T15 |
8 |
|
T58 |
11 |
|
T72 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
975 |
1 |
|
|
T15 |
11 |
|
T58 |
10 |
|
T72 |
10 |
| auto[1] |
915 |
1 |
|
|
T15 |
9 |
|
T58 |
10 |
|
T72 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
965 |
1 |
|
|
T15 |
11 |
|
T58 |
10 |
|
T72 |
9 |
| auto[1] |
925 |
1 |
|
|
T15 |
9 |
|
T58 |
10 |
|
T72 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
916 |
1 |
|
|
T15 |
7 |
|
T58 |
11 |
|
T72 |
10 |
| auto[1] |
974 |
1 |
|
|
T15 |
13 |
|
T58 |
9 |
|
T72 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
983 |
1 |
|
|
T15 |
11 |
|
T58 |
12 |
|
T72 |
13 |
| auto[1] |
907 |
1 |
|
|
T15 |
9 |
|
T58 |
8 |
|
T72 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
941 |
1 |
|
|
T15 |
7 |
|
T58 |
7 |
|
T72 |
11 |
| auto[1] |
949 |
1 |
|
|
T15 |
13 |
|
T58 |
13 |
|
T72 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
925 |
1 |
|
|
T15 |
9 |
|
T58 |
9 |
|
T72 |
4 |
| auto[1] |
965 |
1 |
|
|
T15 |
11 |
|
T58 |
11 |
|
T72 |
16 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
962 |
1 |
|
|
T15 |
13 |
|
T58 |
11 |
|
T72 |
10 |
| auto[1] |
928 |
1 |
|
|
T15 |
7 |
|
T58 |
9 |
|
T72 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
944 |
1 |
|
|
T15 |
14 |
|
T58 |
8 |
|
T72 |
9 |
| auto[1] |
946 |
1 |
|
|
T15 |
6 |
|
T58 |
12 |
|
T72 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
505 |
1 |
|
|
T15 |
6 |
|
T58 |
5 |
|
T72 |
4 |
| auto[0] |
auto[1] |
453 |
1 |
|
|
T15 |
2 |
|
T58 |
8 |
|
T72 |
8 |
| auto[1] |
auto[0] |
476 |
1 |
|
|
T15 |
9 |
|
T58 |
2 |
|
T72 |
3 |
| auto[1] |
auto[1] |
456 |
1 |
|
|
T15 |
3 |
|
T58 |
5 |
|
T72 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
467 |
1 |
|
|
T15 |
4 |
|
T58 |
7 |
|
T72 |
6 |
| auto[0] |
auto[1] |
453 |
1 |
|
|
T15 |
8 |
|
T58 |
2 |
|
T72 |
3 |
| auto[1] |
auto[0] |
476 |
1 |
|
|
T15 |
3 |
|
T58 |
8 |
|
T72 |
8 |
| auto[1] |
auto[1] |
494 |
1 |
|
|
T15 |
5 |
|
T58 |
3 |
|
T72 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
487 |
1 |
|
|
T15 |
4 |
|
T58 |
7 |
|
T72 |
3 |
| auto[0] |
auto[1] |
488 |
1 |
|
|
T15 |
7 |
|
T58 |
3 |
|
T72 |
7 |
| auto[1] |
auto[0] |
457 |
1 |
|
|
T15 |
5 |
|
T58 |
7 |
|
T72 |
8 |
| auto[1] |
auto[1] |
458 |
1 |
|
|
T15 |
4 |
|
T58 |
3 |
|
T72 |
2 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
496 |
1 |
|
|
T15 |
6 |
|
T58 |
5 |
|
T72 |
4 |
| auto[0] |
auto[1] |
469 |
1 |
|
|
T15 |
5 |
|
T58 |
5 |
|
T72 |
5 |
| auto[1] |
auto[0] |
476 |
1 |
|
|
T15 |
7 |
|
T58 |
5 |
|
T72 |
10 |
| auto[1] |
auto[1] |
449 |
1 |
|
|
T15 |
2 |
|
T58 |
5 |
|
T72 |
1 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
483 |
1 |
|
|
T15 |
3 |
|
T58 |
7 |
|
T72 |
4 |
| auto[0] |
auto[1] |
433 |
1 |
|
|
T15 |
4 |
|
T58 |
4 |
|
T72 |
6 |
| auto[1] |
auto[0] |
500 |
1 |
|
|
T15 |
8 |
|
T58 |
5 |
|
T72 |
7 |
| auto[1] |
auto[1] |
474 |
1 |
|
|
T15 |
5 |
|
T58 |
4 |
|
T72 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
492 |
1 |
|
|
T15 |
5 |
|
T58 |
5 |
|
T72 |
3 |
| auto[0] |
auto[1] |
491 |
1 |
|
|
T15 |
6 |
|
T58 |
7 |
|
T72 |
10 |
| auto[1] |
auto[0] |
442 |
1 |
|
|
T15 |
6 |
|
T58 |
2 |
|
T72 |
3 |
| auto[1] |
auto[1] |
465 |
1 |
|
|
T15 |
3 |
|
T58 |
6 |
|
T72 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
455 |
1 |
|
|
T15 |
6 |
|
T58 |
5 |
|
T72 |
2 |
| auto[0] |
auto[1] |
470 |
1 |
|
|
T15 |
3 |
|
T58 |
4 |
|
T72 |
2 |
| auto[1] |
auto[0] |
485 |
1 |
|
|
T15 |
3 |
|
T58 |
6 |
|
T72 |
9 |
| auto[1] |
auto[1] |
480 |
1 |
|
|
T15 |
8 |
|
T58 |
5 |
|
T72 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
472 |
1 |
|
|
T15 |
8 |
|
T58 |
6 |
|
T72 |
5 |
| auto[0] |
auto[1] |
490 |
1 |
|
|
T15 |
5 |
|
T58 |
5 |
|
T72 |
5 |
| auto[1] |
auto[0] |
465 |
1 |
|
|
T15 |
1 |
|
T58 |
5 |
|
T72 |
6 |
| auto[1] |
auto[1] |
463 |
1 |
|
|
T15 |
6 |
|
T58 |
4 |
|
T72 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
431 |
1 |
|
|
T15 |
5 |
|
T58 |
5 |
|
T72 |
4 |
| auto[0] |
auto[1] |
470 |
1 |
|
|
T15 |
3 |
|
T58 |
2 |
|
T72 |
3 |
| auto[1] |
auto[0] |
522 |
1 |
|
|
T15 |
8 |
|
T58 |
5 |
|
T72 |
10 |
| auto[1] |
auto[1] |
467 |
1 |
|
|
T15 |
4 |
|
T58 |
8 |
|
T72 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
903 |
1 |
|
|
T15 |
8 |
|
T58 |
11 |
|
T72 |
10 |
| auto[1] |
auto[1] |
987 |
1 |
|
|
T15 |
12 |
|
T58 |
9 |
|
T72 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
472 |
1 |
|
|
T15 |
4 |
|
T58 |
5 |
|
T72 |
4 |
| auto[0] |
auto[1] |
469 |
1 |
|
|
T15 |
3 |
|
T58 |
2 |
|
T72 |
7 |
| auto[1] |
auto[0] |
476 |
1 |
|
|
T15 |
4 |
|
T58 |
6 |
|
T72 |
2 |
| auto[1] |
auto[1] |
473 |
1 |
|
|
T15 |
9 |
|
T58 |
7 |
|
T72 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
944 |
1 |
|
|
T15 |
14 |
|
T58 |
8 |
|
T72 |
9 |
| auto[1] |
auto[1] |
946 |
1 |
|
|
T15 |
6 |
|
T58 |
12 |
|
T72 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
201 |
1 |
|
|
T15 |
14 |
|
T39 |
7 |
|
T257 |
5 |
| auto[1] |
219 |
1 |
|
|
T15 |
6 |
|
T39 |
13 |
|
T257 |
15 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
224 |
1 |
|
|
T15 |
12 |
|
T39 |
9 |
|
T257 |
12 |
| auto[1] |
196 |
1 |
|
|
T15 |
8 |
|
T39 |
11 |
|
T257 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
212 |
1 |
|
|
T15 |
12 |
|
T39 |
7 |
|
T257 |
10 |
| auto[1] |
208 |
1 |
|
|
T15 |
8 |
|
T39 |
13 |
|
T257 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
205 |
1 |
|
|
T15 |
5 |
|
T39 |
8 |
|
T257 |
8 |
| auto[1] |
215 |
1 |
|
|
T15 |
15 |
|
T39 |
12 |
|
T257 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
200 |
1 |
|
|
T15 |
7 |
|
T39 |
11 |
|
T257 |
8 |
| auto[1] |
220 |
1 |
|
|
T15 |
13 |
|
T39 |
9 |
|
T257 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
231 |
1 |
|
|
T15 |
15 |
|
T39 |
10 |
|
T257 |
15 |
| auto[1] |
189 |
1 |
|
|
T15 |
5 |
|
T39 |
10 |
|
T257 |
5 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
204 |
1 |
|
|
T15 |
7 |
|
T39 |
9 |
|
T257 |
12 |
| auto[1] |
216 |
1 |
|
|
T15 |
13 |
|
T39 |
11 |
|
T257 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
213 |
1 |
|
|
T15 |
12 |
|
T39 |
12 |
|
T257 |
9 |
| auto[1] |
207 |
1 |
|
|
T15 |
8 |
|
T39 |
8 |
|
T257 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T15 |
12 |
|
T39 |
10 |
|
T257 |
8 |
| auto[1] |
218 |
1 |
|
|
T15 |
8 |
|
T39 |
10 |
|
T257 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
217 |
1 |
|
|
T15 |
9 |
|
T39 |
12 |
|
T257 |
8 |
| auto[1] |
203 |
1 |
|
|
T15 |
11 |
|
T39 |
8 |
|
T257 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T15 |
9 |
|
T39 |
10 |
|
T257 |
10 |
| auto[1] |
218 |
1 |
|
|
T15 |
11 |
|
T39 |
10 |
|
T257 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
211 |
1 |
|
|
T15 |
8 |
|
T39 |
10 |
|
T257 |
10 |
| auto[1] |
209 |
1 |
|
|
T15 |
12 |
|
T39 |
10 |
|
T257 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
204 |
1 |
|
|
T15 |
11 |
|
T39 |
8 |
|
T257 |
9 |
| auto[1] |
216 |
1 |
|
|
T15 |
9 |
|
T39 |
12 |
|
T257 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
224 |
1 |
|
|
T15 |
12 |
|
T39 |
9 |
|
T257 |
12 |
| auto[1] |
196 |
1 |
|
|
T15 |
8 |
|
T39 |
11 |
|
T257 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
194 |
1 |
|
|
T15 |
8 |
|
T39 |
10 |
|
T257 |
5 |
| auto[1] |
226 |
1 |
|
|
T15 |
12 |
|
T39 |
10 |
|
T257 |
15 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T15 |
11 |
|
T39 |
9 |
|
T257 |
9 |
| auto[1] |
217 |
1 |
|
|
T15 |
9 |
|
T39 |
11 |
|
T257 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
199 |
1 |
|
|
T15 |
11 |
|
T39 |
8 |
|
T257 |
7 |
| auto[1] |
221 |
1 |
|
|
T15 |
9 |
|
T39 |
12 |
|
T257 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
208 |
1 |
|
|
T15 |
11 |
|
T39 |
9 |
|
T257 |
6 |
| auto[1] |
212 |
1 |
|
|
T15 |
9 |
|
T39 |
11 |
|
T257 |
14 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
195 |
1 |
|
|
T15 |
11 |
|
T39 |
10 |
|
T257 |
10 |
| auto[1] |
225 |
1 |
|
|
T15 |
9 |
|
T39 |
10 |
|
T257 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
224 |
1 |
|
|
T15 |
10 |
|
T39 |
13 |
|
T257 |
13 |
| auto[1] |
196 |
1 |
|
|
T15 |
10 |
|
T39 |
7 |
|
T257 |
7 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
209 |
1 |
|
|
T15 |
9 |
|
T39 |
9 |
|
T257 |
11 |
| auto[1] |
211 |
1 |
|
|
T15 |
11 |
|
T39 |
11 |
|
T257 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
207 |
1 |
|
|
T15 |
11 |
|
T39 |
13 |
|
T257 |
11 |
| auto[1] |
213 |
1 |
|
|
T15 |
9 |
|
T39 |
7 |
|
T257 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
224 |
1 |
|
|
T15 |
13 |
|
T39 |
11 |
|
T257 |
13 |
| auto[1] |
196 |
1 |
|
|
T15 |
7 |
|
T39 |
9 |
|
T257 |
7 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
211 |
1 |
|
|
T15 |
8 |
|
T39 |
10 |
|
T257 |
10 |
| auto[1] |
209 |
1 |
|
|
T15 |
12 |
|
T39 |
10 |
|
T257 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T15 |
6 |
|
T39 |
5 |
|
T257 |
3 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T15 |
2 |
|
T39 |
5 |
|
T257 |
2 |
| auto[1] |
auto[0] |
109 |
1 |
|
|
T15 |
6 |
|
T39 |
2 |
|
T257 |
7 |
| auto[1] |
auto[1] |
117 |
1 |
|
|
T15 |
6 |
|
T39 |
8 |
|
T257 |
8 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
104 |
1 |
|
|
T15 |
4 |
|
T39 |
5 |
|
T257 |
4 |
| auto[0] |
auto[1] |
99 |
1 |
|
|
T15 |
7 |
|
T39 |
4 |
|
T257 |
5 |
| auto[1] |
auto[0] |
101 |
1 |
|
|
T15 |
1 |
|
T39 |
3 |
|
T257 |
4 |
| auto[1] |
auto[1] |
116 |
1 |
|
|
T15 |
8 |
|
T39 |
8 |
|
T257 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
96 |
1 |
|
|
T15 |
3 |
|
T39 |
4 |
|
T257 |
1 |
| auto[0] |
auto[1] |
103 |
1 |
|
|
T15 |
8 |
|
T39 |
4 |
|
T257 |
6 |
| auto[1] |
auto[0] |
104 |
1 |
|
|
T15 |
4 |
|
T39 |
7 |
|
T257 |
7 |
| auto[1] |
auto[1] |
117 |
1 |
|
|
T15 |
5 |
|
T39 |
5 |
|
T257 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
116 |
1 |
|
|
T15 |
7 |
|
T39 |
4 |
|
T257 |
4 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T15 |
4 |
|
T39 |
5 |
|
T257 |
2 |
| auto[1] |
auto[0] |
115 |
1 |
|
|
T15 |
8 |
|
T39 |
6 |
|
T257 |
11 |
| auto[1] |
auto[1] |
97 |
1 |
|
|
T15 |
1 |
|
T39 |
5 |
|
T257 |
3 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
99 |
1 |
|
|
T15 |
4 |
|
T39 |
6 |
|
T257 |
4 |
| auto[0] |
auto[1] |
96 |
1 |
|
|
T15 |
7 |
|
T39 |
4 |
|
T257 |
6 |
| auto[1] |
auto[0] |
105 |
1 |
|
|
T15 |
3 |
|
T39 |
3 |
|
T257 |
8 |
| auto[1] |
auto[1] |
120 |
1 |
|
|
T15 |
6 |
|
T39 |
7 |
|
T257 |
2 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
118 |
1 |
|
|
T15 |
6 |
|
T39 |
9 |
|
T257 |
4 |
| auto[0] |
auto[1] |
106 |
1 |
|
|
T15 |
4 |
|
T39 |
4 |
|
T257 |
9 |
| auto[1] |
auto[0] |
95 |
1 |
|
|
T15 |
6 |
|
T39 |
3 |
|
T257 |
5 |
| auto[1] |
auto[1] |
101 |
1 |
|
|
T15 |
4 |
|
T39 |
4 |
|
T257 |
2 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T15 |
6 |
|
T39 |
7 |
|
T257 |
3 |
| auto[0] |
auto[1] |
104 |
1 |
|
|
T15 |
5 |
|
T39 |
6 |
|
T257 |
8 |
| auto[1] |
auto[0] |
114 |
1 |
|
|
T15 |
3 |
|
T39 |
5 |
|
T257 |
5 |
| auto[1] |
auto[1] |
99 |
1 |
|
|
T15 |
6 |
|
T39 |
2 |
|
T257 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
104 |
1 |
|
|
T15 |
7 |
|
T39 |
5 |
|
T257 |
5 |
| auto[0] |
auto[1] |
120 |
1 |
|
|
T15 |
6 |
|
T39 |
6 |
|
T257 |
8 |
| auto[1] |
auto[0] |
98 |
1 |
|
|
T15 |
2 |
|
T39 |
5 |
|
T257 |
5 |
| auto[1] |
auto[1] |
98 |
1 |
|
|
T15 |
5 |
|
T39 |
4 |
|
T257 |
2 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T15 |
8 |
|
T39 |
1 |
|
T257 |
3 |
| auto[0] |
auto[1] |
120 |
1 |
|
|
T15 |
3 |
|
T39 |
7 |
|
T257 |
6 |
| auto[1] |
auto[0] |
117 |
1 |
|
|
T15 |
6 |
|
T39 |
6 |
|
T257 |
2 |
| auto[1] |
auto[1] |
99 |
1 |
|
|
T15 |
3 |
|
T39 |
6 |
|
T257 |
9 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
224 |
1 |
|
|
T15 |
12 |
|
T39 |
9 |
|
T257 |
12 |
| auto[1] |
auto[1] |
196 |
1 |
|
|
T15 |
8 |
|
T39 |
11 |
|
T257 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
103 |
1 |
|
|
T15 |
7 |
|
T39 |
3 |
|
T257 |
5 |
| auto[0] |
auto[1] |
106 |
1 |
|
|
T15 |
2 |
|
T39 |
6 |
|
T257 |
6 |
| auto[1] |
auto[0] |
99 |
1 |
|
|
T15 |
5 |
|
T39 |
7 |
|
T257 |
3 |
| auto[1] |
auto[1] |
112 |
1 |
|
|
T15 |
6 |
|
T39 |
4 |
|
T257 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
211 |
1 |
|
|
T15 |
8 |
|
T39 |
10 |
|
T257 |
10 |
| auto[1] |
auto[1] |
209 |
1 |
|
|
T15 |
12 |
|
T39 |
10 |
|
T257 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T257 |
13 |
|
T65 |
10 |
|
T140 |
13 |
| auto[1] |
72 |
1 |
|
|
T257 |
7 |
|
T65 |
10 |
|
T140 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T257 |
13 |
|
T65 |
8 |
|
T140 |
9 |
| auto[1] |
92 |
1 |
|
|
T257 |
7 |
|
T65 |
12 |
|
T140 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T257 |
8 |
|
T65 |
11 |
|
T140 |
11 |
| auto[1] |
91 |
1 |
|
|
T257 |
12 |
|
T65 |
9 |
|
T140 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
90 |
1 |
|
|
T257 |
9 |
|
T65 |
13 |
|
T140 |
7 |
| auto[1] |
90 |
1 |
|
|
T257 |
11 |
|
T65 |
7 |
|
T140 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T257 |
9 |
|
T65 |
6 |
|
T140 |
10 |
| auto[1] |
86 |
1 |
|
|
T257 |
11 |
|
T65 |
14 |
|
T140 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T257 |
12 |
|
T65 |
10 |
|
T140 |
9 |
| auto[1] |
91 |
1 |
|
|
T257 |
8 |
|
T65 |
10 |
|
T140 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
90 |
1 |
|
|
T257 |
10 |
|
T65 |
11 |
|
T140 |
13 |
| auto[1] |
90 |
1 |
|
|
T257 |
10 |
|
T65 |
9 |
|
T140 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T257 |
8 |
|
T65 |
7 |
|
T140 |
13 |
| auto[1] |
95 |
1 |
|
|
T257 |
12 |
|
T65 |
13 |
|
T140 |
7 |