Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.91	99.36	96.33	100.00	96.79	98.75	99.53	94.61

Total tests in report: 918

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
64.48	64.48	69.61	69.61	65.77	65.77	84.97	84.97	96.79	96.79	73.86	73.86	54.03	54.03	6.37	6.37	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.4009887174
77.23	12.74	84.89	15.28	80.19	14.42	91.57	6.61	96.79	0.00	86.49	12.63	73.50	19.48	27.13	20.76	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1226892901
82.88	5.66	88.11	3.21	83.58	3.38	92.03	0.46	96.79	0.00	89.21	2.71	81.84	8.33	48.63	21.50	/workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.4256989198
87.14	4.26	91.46	3.35	87.87	4.29	94.08	2.05	96.79	0.00	92.03	2.82	86.05	4.21	61.70	13.08	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.489116432
91.01	3.87	95.09	3.63	91.20	3.34	96.13	2.05	96.79	0.00	94.71	2.68	92.60	6.55	70.52	8.81	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.227323467
93.05	2.05	97.00	1.91	92.78	1.57	99.09	2.96	96.79	0.00	96.10	1.39	96.07	3.46	73.56	3.04	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2980516907
94.03	0.98	97.43	0.43	93.18	0.41	99.09	0.00	96.79	0.00	96.55	0.45	97.10	1.03	78.06	4.51	/workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2594849251
94.60	0.57	97.50	0.07	93.42	0.24	99.09	0.00	96.79	0.00	96.59	0.03	97.19	0.09	81.59	3.53	/workspace/coverage/default/3.sysrst_ctrl_stress_all.629552540
94.99	0.39	97.57	0.07	93.64	0.21	99.32	0.23	96.79	0.00	96.66	0.07	97.19	0.00	83.74	2.15	/workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3423845239
95.30	0.31	98.54	0.97	93.78	0.14	99.32	0.00	96.79	0.00	97.70	1.04	97.19	0.00	83.74	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.884427256
95.57	0.27	98.54	0.00	94.78	1.00	99.32	0.00	96.79	0.00	97.74	0.03	97.38	0.19	84.43	0.69	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2574308051
95.83	0.26	98.54	0.00	94.78	0.00	99.32	0.00	96.79	0.00	97.74	0.00	97.38	0.00	86.24	1.81	/workspace/coverage/default/46.sysrst_ctrl_stress_all.3537646738
96.05	0.23	98.58	0.03	94.80	0.02	99.32	0.00	96.79	0.00	97.81	0.07	97.38	0.00	87.71	1.47	/workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3486009019
96.24	0.19	98.58	0.00	94.95	0.14	99.32	0.00	96.79	0.00	97.81	0.00	97.85	0.47	88.39	0.69	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3060014306
96.41	0.17	98.61	0.03	95.02	0.07	99.32	0.00	96.79	0.00	97.84	0.03	97.94	0.09	89.32	0.93	/workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.279360726
96.54	0.13	98.73	0.12	95.18	0.17	99.32	0.00	96.79	0.00	97.91	0.07	98.13	0.19	89.72	0.39	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1104524348
96.64	0.10	98.73	0.00	95.21	0.02	99.77	0.46	96.79	0.00	97.91	0.00	98.22	0.09	89.81	0.10	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.520836000
96.73	0.09	98.73	0.00	95.33	0.12	99.77	0.00	96.79	0.00	97.91	0.00	98.41	0.19	90.16	0.34	/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1603326395
96.82	0.09	98.78	0.05	95.33	0.00	99.77	0.00	96.79	0.00	98.02	0.10	98.41	0.00	90.65	0.49	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.3249174556
96.91	0.09	98.78	0.00	95.33	0.00	99.77	0.00	96.79	0.00	98.02	0.00	98.41	0.00	91.28	0.64	/workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2498735054
96.99	0.08	98.87	0.09	95.38	0.05	99.77	0.00	96.79	0.00	98.12	0.10	98.60	0.19	91.43	0.15	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.413768556
97.07	0.08	98.87	0.00	95.38	0.00	99.77	0.00	96.79	0.00	98.12	0.00	98.60	0.00	91.97	0.54	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.4063330804
97.14	0.07	98.96	0.09	95.42	0.05	99.77	0.00	96.79	0.00	98.22	0.10	98.78	0.19	92.02	0.05	/workspace/coverage/default/44.sysrst_ctrl_stress_all.2330146000
97.19	0.05	98.96	0.00	95.80	0.38	99.77	0.00	96.79	0.00	98.22	0.00	98.78	0.00	92.02	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.4071042417
97.25	0.05	99.03	0.07	95.85	0.05	99.77	0.00	96.79	0.00	98.29	0.07	98.97	0.19	92.02	0.00	/workspace/coverage/default/21.sysrst_ctrl_edge_detect.2622445147
97.30	0.05	99.10	0.07	95.88	0.02	99.77	0.00	96.79	0.00	98.36	0.07	99.06	0.09	92.12	0.10	/workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.584309092
97.35	0.05	99.10	0.00	95.88	0.00	99.77	0.00	96.79	0.00	98.36	0.00	99.06	0.00	92.46	0.34	/workspace/coverage/default/37.sysrst_ctrl_combo_detect.1280857722
97.39	0.05	99.10	0.00	95.97	0.10	99.77	0.00	96.79	0.00	98.36	0.00	99.16	0.09	92.61	0.15	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3466909962
97.44	0.04	99.10	0.00	96.02	0.05	100.00	0.23	96.79	0.00	98.40	0.03	99.16	0.00	92.61	0.00	/workspace/coverage/default/17.sysrst_ctrl_alert_test.2951042636
97.48	0.04	99.15	0.05	96.04	0.02	100.00	0.00	96.79	0.00	98.47	0.07	99.25	0.09	92.65	0.05	/workspace/coverage/default/5.sysrst_ctrl_stress_all.3186166330
97.52	0.04	99.18	0.03	96.09	0.05	100.00	0.00	96.79	0.00	98.50	0.03	99.34	0.09	92.70	0.05	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2393559718
97.55	0.03	99.22	0.03	96.09	0.00	100.00	0.00	96.79	0.00	98.54	0.03	99.34	0.00	92.85	0.15	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1503308429
97.58	0.03	99.22	0.00	96.09	0.00	100.00	0.00	96.79	0.00	98.54	0.00	99.34	0.00	93.05	0.20	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.4108504435
97.60	0.03	99.22	0.00	96.09	0.00	100.00	0.00	96.79	0.00	98.54	0.00	99.34	0.00	93.24	0.20	/workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2028245179
97.63	0.03	99.25	0.03	96.11	0.02	100.00	0.00	96.79	0.00	98.57	0.03	99.44	0.09	93.24	0.00	/workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1497962854
97.66	0.03	99.29	0.03	96.14	0.02	100.00	0.00	96.79	0.00	98.61	0.03	99.53	0.09	93.24	0.00	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3746897288
97.68	0.02	99.29	0.00	96.14	0.00	100.00	0.00	96.79	0.00	98.61	0.00	99.53	0.00	93.39	0.15	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.1163983602
97.70	0.02	99.29	0.00	96.14	0.00	100.00	0.00	96.79	0.00	98.61	0.00	99.53	0.00	93.54	0.15	/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.4183687892
97.72	0.02	99.29	0.00	96.14	0.00	100.00	0.00	96.79	0.00	98.61	0.00	99.53	0.00	93.68	0.15	/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1937964109
97.74	0.02	99.29	0.00	96.16	0.02	100.00	0.00	96.79	0.00	98.61	0.00	99.53	0.00	93.78	0.10	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3875490520
97.75	0.01	99.32	0.03	96.16	0.00	100.00	0.00	96.79	0.00	98.68	0.07	99.53	0.00	93.78	0.00	/workspace/coverage/default/24.sysrst_ctrl_stress_all.3132223145
97.77	0.01	99.34	0.02	96.16	0.00	100.00	0.00	96.79	0.00	98.71	0.03	99.53	0.00	93.83	0.05	/workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3680864241
97.78	0.01	99.34	0.00	96.16	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.53	0.00	93.93	0.10	/workspace/coverage/default/11.sysrst_ctrl_combo_detect.2619336579
97.80	0.01	99.34	0.00	96.16	0.00	100.00	0.00	96.79	0.00	98.71	0.00	99.53	0.00	94.03	0.10	/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1394298203
97.81	0.01	99.34	0.00	96.23	0.07	100.00	0.00	96.79	0.00	98.71	0.00	99.53	0.00	94.03	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3739694493
97.81	0.01	99.36	0.02	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.03	99.53	0.00	94.03	0.00	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3248407276
97.82	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.07	0.05	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3624085509
97.83	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.12	0.05	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.97948308
97.83	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.17	0.05	/workspace/coverage/default/0.sysrst_ctrl_combo_detect.2246549101
97.84	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.22	0.05	/workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.440193929
97.85	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.27	0.05	/workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2035702881
97.85	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.32	0.05	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2364921884
97.86	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.37	0.05	/workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3919635959
97.87	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.42	0.05	/workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3076526280
97.88	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.47	0.05	/workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.2655176308
97.88	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.52	0.05	/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.634033975
97.89	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.56	0.05	/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3894268438
97.90	0.01	99.36	0.00	96.23	0.00	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.61	0.05	/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4085652727
97.90	0.01	99.36	0.00	96.26	0.02	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.61	0.00	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.3464204418
97.90	0.01	99.36	0.00	96.28	0.02	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.61	0.00	/workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.3963321123
97.91	0.01	99.36	0.00	96.31	0.02	100.00	0.00	96.79	0.00	98.75	0.00	99.53	0.00	94.61	0.00	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.632441990

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2593614393
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.247473467
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3903797965
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2142826423
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3783319372
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.534669848
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.4074523985
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1500607356
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1639428326
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1068859924
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2307613021
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.233901408
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.722337568
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3996035025
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.361997590
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4139902525
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3732825290
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.3271996603
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.1640301980
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3989053767
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.247951628
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4069023493
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1413632415
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3379264846
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.4128453010
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2973683099
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2357094030
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1749280742
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.81320737
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2047756836
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1366224449
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.122893713
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3053193466
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2817943735
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.921125605
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2650564960
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3276895192
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.565693231
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2965948095
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.207130818
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3601884548
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2737831643
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.2867889935
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1495540505
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.174537907
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.851677402
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2753441214
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.41972413
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2363052387
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1846525148
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.963100233
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.687068873
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1503876970
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3024086600
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.342050491
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4114133554
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2865742686
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2010656015
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4110100909
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3009659160
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.4205013446
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2430031210
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.234500744
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1530465299
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1913267402
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4130969677
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/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3628720358
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2631062922
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.257410262
/workspace/coverage/default/40.sysrst_ctrl_smoke.3483154231
/workspace/coverage/default/40.sysrst_ctrl_stress_all.1273862695
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3517344116
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.436463187
/workspace/coverage/default/41.sysrst_ctrl_alert_test.114919175
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.229322704
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.2093816849
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3029001876
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3259922775
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.1377439903
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3804867227
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.801452846
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1590480973
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.988397845
/workspace/coverage/default/41.sysrst_ctrl_smoke.11758971
/workspace/coverage/default/41.sysrst_ctrl_stress_all.3172058454
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.3749144104
/workspace/coverage/default/42.sysrst_ctrl_alert_test.3736860342
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2471525913
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3826739904
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.282418162
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.1292258969
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2021309998
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1891879175
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4235216939
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1626111990
/workspace/coverage/default/42.sysrst_ctrl_smoke.2799563382
/workspace/coverage/default/42.sysrst_ctrl_stress_all.1392573175
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.2738346667
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3157835806
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1041990939
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2845733891
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1384154988
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3007172937
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.880965347
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3675975887
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1640639348
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.4245943960
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.303081825
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.335215086
/workspace/coverage/default/43.sysrst_ctrl_smoke.4178208111
/workspace/coverage/default/43.sysrst_ctrl_stress_all.915135752
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.577899978
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3927182103
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.4227096272
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2518832659
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.312057322
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3242964472
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1512451326
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1773312332
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2872238451
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.610959530
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.743337190
/workspace/coverage/default/44.sysrst_ctrl_smoke.2861856712
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1846314700
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.509770532
/workspace/coverage/default/45.sysrst_ctrl_alert_test.4283331420
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.599004898
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.478504104
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.3048312446
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.982387742
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.876738961
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.895021046
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.305878110
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2906798144
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.1408181441
/workspace/coverage/default/45.sysrst_ctrl_smoke.23954222
/workspace/coverage/default/45.sysrst_ctrl_stress_all.35156653
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1297066633
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.4220229247
/workspace/coverage/default/46.sysrst_ctrl_alert_test.524389400
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3098111357
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3054630657
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3032266743
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1738236647
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3441590801
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2366482613
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.920970223
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1191878986
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.3789523902
/workspace/coverage/default/46.sysrst_ctrl_smoke.1514663778
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.941182509
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3793302276
/workspace/coverage/default/47.sysrst_ctrl_alert_test.557362185
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3839843897
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2158567822
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2878784886
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.351805928
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3129861920
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1384743747
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.448249568
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.763271644
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2692262459
/workspace/coverage/default/47.sysrst_ctrl_smoke.1404940663
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2701773870
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.2299110437
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3701227322
/workspace/coverage/default/48.sysrst_ctrl_alert_test.2812162154
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2271400331
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3965253901
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3351048044
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.328178047
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2165850848
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2556550134
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2626373973
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1308997753
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4240259268
/workspace/coverage/default/48.sysrst_ctrl_smoke.1701228312
/workspace/coverage/default/48.sysrst_ctrl_stress_all.563827699
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3775128650
/workspace/coverage/default/49.sysrst_ctrl_alert_test.318296091
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.4076532906
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2496355098
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1634807796
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.213432876
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3209592155
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3550227635
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3222518991
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.868843454
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3605275975
/workspace/coverage/default/49.sysrst_ctrl_smoke.2342884350
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2300116971
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2028661922
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3968145004
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1113514462
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.632353774
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.1962576236
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.803096325
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.1571586629
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.3786907436
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3948839688
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2513426353
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3932655860
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.95822504
/workspace/coverage/default/5.sysrst_ctrl_smoke.3724246412
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1876225870
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2850414469
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1144298699
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2636087668
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1322318702
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1315598292
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1258750081
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2518103110
/workspace/coverage/default/6.sysrst_ctrl_alert_test.4201566184
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1735557450
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.920893390
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1189164002
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2512662184
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2668574263
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3784178728
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.761491164
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3952900300
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.3955207234
/workspace/coverage/default/6.sysrst_ctrl_smoke.3500264979
/workspace/coverage/default/6.sysrst_ctrl_stress_all.3294668719
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3629464273
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.226378613
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.1183230495
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3466741763
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1623988072
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.35947152
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3845365680
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3779812178
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2995852107
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.723525887
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2959357069
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3955311504
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.784516698
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1315245523
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.4196847969
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.3485225276
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1806451878
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.1432183913
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3634672675
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2731136598
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.430594495
/workspace/coverage/default/7.sysrst_ctrl_smoke.1918627362
/workspace/coverage/default/7.sysrst_ctrl_stress_all.668009141
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2988860147
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3505538348
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3390019538
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1120920020
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.1580001588
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3212604477
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.3923311474
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3913419291
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1659037965
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2456363929
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1982442141
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.686743847
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2290596205
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3670074954
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.93536756
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.1096011119
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.679412672
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3998573849
/workspace/coverage/default/8.sysrst_ctrl_smoke.3861261525
/workspace/coverage/default/8.sysrst_ctrl_stress_all.589914732
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.26614212
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3995032897
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.229945812
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1809146759
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2054540756
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1847134185
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1799343920
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3040319041
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3836651147
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.2704091606
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.2315151533
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.947836571
/workspace/coverage/default/9.sysrst_ctrl_alert_test.2585393106
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3277478519
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.2476780477
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.916982438
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1206458361
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3448117492
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.259959977
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2024426606
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1037672394
/workspace/coverage/default/9.sysrst_ctrl_smoke.1108883545
/workspace/coverage/default/9.sysrst_ctrl_stress_all.631489121
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2652742432
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2851399358
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.391032856
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.175233289
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1841098167
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1185434310
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1772874697
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1578066774
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2105529948
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1900715305

Total test records in report: 918

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.4009887174	Jan 14 12:22:39 PM PST 24	Jan 14 12:23:01 PM PST 24	5001876551 ps
T2	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.831924946	Jan 14 12:22:37 PM PST 24	Jan 14 12:23:58 PM PST 24	42449593756 ps
T3	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.489116432	Jan 14 12:22:40 PM PST 24	Jan 14 12:24:26 PM PST 24	42591573350 ps
T21	/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2399030560	Jan 14 12:17:26 PM PST 24	Jan 14 12:17:32 PM PST 24	2009474636 ps
T22	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3563490572	Jan 14 12:23:16 PM PST 24	Jan 14 12:23:28 PM PST 24	2029487967 ps
T4	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.247951628	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:19 PM PST 24	7571948533 ps
T23	/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.2310023409	Jan 14 12:17:35 PM PST 24	Jan 14 12:17:38 PM PST 24	2025497872 ps
T24	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1846525148	Jan 14 12:18:34 PM PST 24	Jan 14 12:18:38 PM PST 24	2296310773 ps
T25	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3850755393	Jan 14 12:23:04 PM PST 24	Jan 14 12:23:08 PM PST 24	2290026139 ps
T26	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1530465299	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:24 PM PST 24	2027469516 ps
T35	/workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.4254692237	Jan 14 12:20:57 PM PST 24	Jan 14 12:21:00 PM PST 24	2033221493 ps
T5	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.4128453010	Jan 14 12:20:44 PM PST 24	Jan 14 12:20:48 PM PST 24	2067570500 ps
T264	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3053193466	Jan 14 12:23:01 PM PST 24	Jan 14 12:23:06 PM PST 24	2148678005 ps
T266	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3485011602	Jan 14 12:17:07 PM PST 24	Jan 14 12:17:13 PM PST 24	2186288931 ps
T6	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1308507537	Jan 14 12:23:27 PM PST 24	Jan 14 12:23:31 PM PST 24	5204366560 ps
T289	/workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3423845239	Jan 14 12:18:27 PM PST 24	Jan 14 12:18:34 PM PST 24	2010651523 ps
T290	/workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.631312399	Jan 14 12:20:57 PM PST 24	Jan 14 12:21:03 PM PST 24	2015878195 ps
T267	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2574308051	Jan 14 12:22:12 PM PST 24	Jan 14 12:22:18 PM PST 24	2220832152 ps
T268	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2965948095	Jan 14 12:18:46 PM PST 24	Jan 14 12:18:53 PM PST 24	2071365350 ps
T297	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.2825192884	Jan 14 12:20:13 PM PST 24	Jan 14 12:20:14 PM PST 24	2060239529 ps
T291	/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.15731194	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:26 PM PST 24	2012071081 ps
T7	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.3466909962	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:03 PM PST 24	2071847973 ps
T292	/workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.697038167	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:26 PM PST 24	2016540616 ps
T301	/workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.647278990	Jan 14 12:18:10 PM PST 24	Jan 14 12:18:17 PM PST 24	2009712582 ps
T302	/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2418715201	Jan 14 12:20:36 PM PST 24	Jan 14 12:20:38 PM PST 24	2025112191 ps
T269	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3739694493	Jan 14 12:19:02 PM PST 24	Jan 14 12:19:09 PM PST 24	2044416869 ps
T303	/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1497086072	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:06 PM PST 24	2011734851 ps
T270	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.3212190784	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:09 PM PST 24	2088573650 ps
T8	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3916584475	Jan 14 12:23:16 PM PST 24	Jan 14 12:23:40 PM PST 24	8256925385 ps
T9	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2593614393	Jan 14 12:20:35 PM PST 24	Jan 14 12:20:43 PM PST 24	2295785480 ps
T10	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2533935125	Jan 14 12:18:11 PM PST 24	Jan 14 12:18:21 PM PST 24	6043571160 ps
T50	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2753441214	Jan 14 12:22:45 PM PST 24	Jan 14 12:22:53 PM PST 24	2053415483 ps
T32	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.342050491	Jan 14 12:18:34 PM PST 24	Jan 14 12:18:57 PM PST 24	7917353719 ps
T368	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3629089424	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:05 PM PST 24	2060656509 ps
T33	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1413632415	Jan 14 12:17:14 PM PST 24	Jan 14 12:18:05 PM PST 24	42680238348 ps
T293	/workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4021024728	Jan 14 12:20:57 PM PST 24	Jan 14 12:21:01 PM PST 24	2026529377 ps
T295	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1495540505	Jan 14 12:18:27 PM PST 24	Jan 14 12:18:30 PM PST 24	2277007041 ps
T296	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.247473467	Jan 14 12:22:15 PM PST 24	Jan 14 12:23:17 PM PST 24	23917009898 ps
T294	/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1627394470	Jan 14 12:17:28 PM PST 24	Jan 14 12:17:32 PM PST 24	2026048092 ps
T73	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3903797965	Jan 14 12:23:27 PM PST 24	Jan 14 12:23:32 PM PST 24	4054724476 ps
T369	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2335662547	Jan 14 12:21:44 PM PST 24	Jan 14 12:21:48 PM PST 24	2044048264 ps
T34	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.122893713	Jan 14 12:22:43 PM PST 24	Jan 14 12:23:07 PM PST 24	5536168024 ps
T36	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.2650564960	Jan 14 12:22:41 PM PST 24	Jan 14 12:22:45 PM PST 24	2086418276 ps
T280	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3060014306	Jan 14 12:22:02 PM PST 24	Jan 14 12:22:06 PM PST 24	2084074805 ps
T370	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.4074523985	Jan 14 12:20:20 PM PST 24	Jan 14 12:20:28 PM PST 24	5052637650 ps
T298	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2719783937	Jan 14 12:22:47 PM PST 24	Jan 14 12:22:58 PM PST 24	2027601071 ps
T281	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.2639416365	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:57 PM PST 24	42586074429 ps
T371	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3624085509	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:07 PM PST 24	2012853276 ps
T372	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2737831643	Jan 14 12:23:07 PM PST 24	Jan 14 12:23:15 PM PST 24	2010678051 ps
T373	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.233901408	Jan 14 12:22:34 PM PST 24	Jan 14 12:22:43 PM PST 24	6021208033 ps
T299	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2291689172	Jan 14 12:19:30 PM PST 24	Jan 14 12:20:50 PM PST 24	39018632212 ps
T351	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2973683099	Jan 14 12:19:16 PM PST 24	Jan 14 12:19:26 PM PST 24	2013703329 ps
T374	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2010656015	Jan 14 12:17:05 PM PST 24	Jan 14 12:17:11 PM PST 24	2044006701 ps
T375	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.852963395	Jan 14 12:17:15 PM PST 24	Jan 14 12:17:32 PM PST 24	10831101444 ps
T367	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3379264846	Jan 14 12:16:49 PM PST 24	Jan 14 12:16:58 PM PST 24	2149398100 ps
T376	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2878628710	Jan 14 12:18:54 PM PST 24	Jan 14 12:18:58 PM PST 24	8501937184 ps
T377	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1518231394	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:06 PM PST 24	2017365894 ps
T378	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.4110100909	Jan 14 12:22:09 PM PST 24	Jan 14 12:22:16 PM PST 24	2040712475 ps
T379	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.81320737	Jan 14 12:18:49 PM PST 24	Jan 14 12:18:58 PM PST 24	2137974461 ps
T380	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.851677402	Jan 14 12:22:12 PM PST 24	Jan 14 12:22:16 PM PST 24	2040484189 ps
T381	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.722337568	Jan 14 12:20:05 PM PST 24	Jan 14 12:20:07 PM PST 24	2097382778 ps
T382	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3024086600	Jan 14 12:22:12 PM PST 24	Jan 14 12:22:15 PM PST 24	2027856336 ps
T282	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.2759427607	Jan 14 12:19:30 PM PST 24	Jan 14 12:20:00 PM PST 24	43002027987 ps
T383	/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2999991449	Jan 14 12:23:01 PM PST 24	Jan 14 12:23:04 PM PST 24	2034813633 ps
T271	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1410674442	Jan 14 12:17:32 PM PST 24	Jan 14 12:17:39 PM PST 24	2270412504 ps
T384	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3875490520	Jan 14 12:21:54 PM PST 24	Jan 14 12:23:48 PM PST 24	42419060631 ps
T300	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2819950828	Jan 14 12:23:33 PM PST 24	Jan 14 12:23:37 PM PST 24	2397189905 ps
T328	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1552908039	Jan 14 12:22:58 PM PST 24	Jan 14 12:24:57 PM PST 24	42375398417 ps
T283	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2266874658	Jan 14 12:22:09 PM PST 24	Jan 14 12:22:14 PM PST 24	4703826191 ps
T385	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3009659160	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:05 PM PST 24	2014841985 ps
T304	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2307613021	Jan 14 12:20:20 PM PST 24	Jan 14 12:21:31 PM PST 24	53233461650 ps
T284	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.234500744	Jan 14 12:17:14 PM PST 24	Jan 14 12:17:22 PM PST 24	2034981155 ps
T307	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.45956867	Jan 14 12:17:20 PM PST 24	Jan 14 12:17:24 PM PST 24	2078336267 ps
T386	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2357094030	Jan 14 12:22:18 PM PST 24	Jan 14 12:22:31 PM PST 24	8196622690 ps
T387	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.2845641069	Jan 14 12:22:12 PM PST 24	Jan 14 12:22:15 PM PST 24	2020784410 ps
T388	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.4130969677	Jan 14 12:22:59 PM PST 24	Jan 14 12:23:04 PM PST 24	2084250374 ps
T389	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.371258605	Jan 14 12:22:37 PM PST 24	Jan 14 12:22:39 PM PST 24	2038246430 ps
T390	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2047756836	Jan 14 12:22:41 PM PST 24	Jan 14 12:22:44 PM PST 24	2037753022 ps
T285	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.2436765801	Jan 14 12:22:54 PM PST 24	Jan 14 12:23:07 PM PST 24	4018426509 ps
T305	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.874697223	Jan 14 12:23:33 PM PST 24	Jan 14 12:23:42 PM PST 24	2080763724 ps
T391	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1821665690	Jan 14 12:23:32 PM PST 24	Jan 14 12:23:42 PM PST 24	6056224936 ps
T392	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3018828916	Jan 14 12:17:26 PM PST 24	Jan 14 12:17:28 PM PST 24	2035754872 ps
T393	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.41972413	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:26 PM PST 24	2015776407 ps
T286	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4139902525	Jan 14 12:21:54 PM PST 24	Jan 14 12:22:22 PM PST 24	10883920001 ps
T287	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1500607356	Jan 14 12:22:34 PM PST 24	Jan 14 12:22:42 PM PST 24	2138217094 ps
T394	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.510309064	Jan 14 12:22:39 PM PST 24	Jan 14 12:22:45 PM PST 24	2093235597 ps
T395	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1366224449	Jan 14 12:17:05 PM PST 24	Jan 14 12:17:11 PM PST 24	2011286269 ps
T396	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4114133554	Jan 14 12:22:12 PM PST 24	Jan 14 12:22:19 PM PST 24	2045238649 ps
T397	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2142826423	Jan 14 12:21:54 PM PST 24	Jan 14 12:22:01 PM PST 24	2045235959 ps
T398	/workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2690109981	Jan 14 12:18:11 PM PST 24	Jan 14 12:18:16 PM PST 24	2014229638 ps
T288	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2541298152	Jan 14 12:21:35 PM PST 24	Jan 14 12:21:52 PM PST 24	9865030961 ps
T399	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3276895192	Jan 14 12:18:46 PM PST 24	Jan 14 12:18:49 PM PST 24	2040092543 ps
T400	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.687068873	Jan 14 12:17:06 PM PST 24	Jan 14 12:17:12 PM PST 24	2081212851 ps
T306	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1014951488	Jan 14 12:17:33 PM PST 24	Jan 14 12:17:37 PM PST 24	2035016631 ps
T401	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.361997590	Jan 14 12:22:15 PM PST 24	Jan 14 12:22:17 PM PST 24	2028740168 ps
T402	/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2147738338	Jan 14 12:17:28 PM PST 24	Jan 14 12:17:30 PM PST 24	2093498675 ps
T403	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.4269165357	Jan 14 12:19:47 PM PST 24	Jan 14 12:19:51 PM PST 24	2025658040 ps
T404	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2581677477	Jan 14 12:20:36 PM PST 24	Jan 14 12:23:03 PM PST 24	39173278594 ps
T405	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3972301677	Jan 14 12:19:02 PM PST 24	Jan 14 12:19:32 PM PST 24	42550829755 ps
T406	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.3601884548	Jan 14 12:17:39 PM PST 24	Jan 14 12:17:42 PM PST 24	2069987319 ps
T407	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.659950800	Jan 14 12:23:42 PM PST 24	Jan 14 12:23:45 PM PST 24	2043616657 ps
T408	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.426028796	Jan 14 12:17:12 PM PST 24	Jan 14 12:17:32 PM PST 24	22289595705 ps
T409	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3423102102	Jan 14 12:22:11 PM PST 24	Jan 14 12:22:15 PM PST 24	2171745107 ps
T410	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2430031210	Jan 14 12:23:43 PM PST 24	Jan 14 12:23:50 PM PST 24	2090669769 ps
T411	/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1508622411	Jan 14 12:17:31 PM PST 24	Jan 14 12:17:35 PM PST 24	2021164005 ps
T412	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.4230758062	Jan 14 12:22:36 PM PST 24	Jan 14 12:22:43 PM PST 24	5320862272 ps
T413	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3849703576	Jan 14 12:20:35 PM PST 24	Jan 14 12:20:43 PM PST 24	2146575531 ps
T414	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.305575305	Jan 14 12:22:15 PM PST 24	Jan 14 12:22:18 PM PST 24	2231259949 ps
T415	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3783319372	Jan 14 12:19:46 PM PST 24	Jan 14 12:19:50 PM PST 24	2056714227 ps
T416	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.746341816	Jan 14 12:17:24 PM PST 24	Jan 14 12:17:31 PM PST 24	2088319872 ps
T417	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.174537907	Jan 14 12:18:51 PM PST 24	Jan 14 12:19:55 PM PST 24	22245409141 ps
T418	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.478936023	Jan 14 12:22:14 PM PST 24	Jan 14 12:22:21 PM PST 24	2053314425 ps
T419	/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1602226039	Jan 14 12:17:20 PM PST 24	Jan 14 12:17:25 PM PST 24	2022215086 ps
T420	/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.643844252	Jan 14 12:23:12 PM PST 24	Jan 14 12:23:26 PM PST 24	2014277841 ps
T421	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3082190830	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:05 PM PST 24	2050575733 ps
T422	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.1503876970	Jan 14 12:23:00 PM PST 24	Jan 14 12:23:03 PM PST 24	2061235372 ps
T423	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1645451486	Jan 14 12:17:20 PM PST 24	Jan 14 12:17:29 PM PST 24	2047795370 ps
T329	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1127121866	Jan 14 12:22:01 PM PST 24	Jan 14 12:22:08 PM PST 24	22505181525 ps
T11	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.3073119900	Jan 14 12:29:01 PM PST 24	Jan 14 12:29:07 PM PST 24	4657155432 ps
T12	/workspace/coverage/default/33.sysrst_ctrl_edge_detect.2037503427	Jan 14 12:29:26 PM PST 24	Jan 14 12:29:28 PM PST 24	3162903413 ps
T13	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.792916271	Jan 14 12:28:50 PM PST 24	Jan 14 12:28:59 PM PST 24	2774765465 ps
T27	/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.895021046	Jan 14 12:29:41 PM PST 24	Jan 14 12:29:55 PM PST 24	2615643983 ps
T28	/workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.784019009	Jan 14 12:28:47 PM PST 24	Jan 14 12:28:54 PM PST 24	2550041108 ps
T29	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1725393427	Jan 14 12:28:36 PM PST 24	Jan 14 12:28:43 PM PST 24	2343541234 ps
T14	/workspace/coverage/default/29.sysrst_ctrl_edge_detect.535523503	Jan 14 12:29:13 PM PST 24	Jan 14 12:29:19 PM PST 24	5411083711 ps
T30	/workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3704595620	Jan 14 12:28:44 PM PST 24	Jan 14 12:28:50 PM PST 24	2614869761 ps
T31	/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.947836571	Jan 14 12:30:05 PM PST 24	Jan 14 12:30:29 PM PST 24	44042778241 ps
T15	/workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1226892901	Jan 14 12:29:16 PM PST 24	Jan 14 12:31:08 PM PST 24	84030299782 ps
T55	/workspace/coverage/default/49.sysrst_ctrl_smoke.2342884350	Jan 14 12:29:42 PM PST 24	Jan 14 12:29:54 PM PST 24	2128105727 ps
T16	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2496355098	Jan 14 12:29:46 PM PST 24	Jan 14 12:31:23 PM PST 24	70104036186 ps
T56	/workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1586208471	Jan 14 12:28:49 PM PST 24	Jan 14 12:28:56 PM PST 24	6051359210 ps
T46	/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1258750081	Jan 14 12:29:48 PM PST 24	Jan 14 12:30:28 PM PST 24	23838376839 ps
T57	/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.2092279556	Jan 14 12:29:43 PM PST 24	Jan 14 12:29:56 PM PST 24	2106453184 ps
T17	/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3441590801	Jan 14 12:29:39 PM PST 24	Jan 14 12:29:54 PM PST 24	3007381774 ps
T58	/workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.3102357629	Jan 14 12:29:01 PM PST 24	Jan 14 12:29:09 PM PST 24	2449180711 ps
T59	/workspace/coverage/default/17.sysrst_ctrl_alert_test.2951042636	Jan 14 12:28:46 PM PST 24	Jan 14 12:28:49 PM PST 24	2036485754 ps
T60	/workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.4244549187	Jan 14 12:29:11 PM PST 24	Jan 14 12:29:14 PM PST 24	5569329451 ps
T102	/workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.138074037	Jan 14 12:29:04 PM PST 24	Jan 14 12:29:07 PM PST 24	2632113047 ps
T424	/workspace/coverage/default/28.sysrst_ctrl_smoke.1863439457	Jan 14 12:29:17 PM PST 24	Jan 14 12:29:20 PM PST 24	2124301695 ps
T47	/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1623988072	Jan 14 12:30:05 PM PST 24	Jan 14 12:31:10 PM PST 24	24079896996 ps
T235	/workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2834535906	Jan 14 12:29:40 PM PST 24	Jan 14 12:29:52 PM PST 24	2532172010 ps
T72	/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3628720358	Jan 14 12:29:54 PM PST 24	Jan 14 12:29:59 PM PST 24	2484328065 ps
T425	/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.880965347	Jan 14 12:29:37 PM PST 24	Jan 14 12:29:43 PM PST 24	2744720629 ps
T356	/workspace/coverage/default/24.sysrst_ctrl_pin_access_test.39636846	Jan 14 12:29:01 PM PST 24	Jan 14 12:29:07 PM PST 24	2138289458 ps
T91	/workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1482075802	Jan 14 12:28:48 PM PST 24	Jan 14 12:28:59 PM PST 24	3485427991 ps
T426	/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1590480973	Jan 14 12:29:39 PM PST 24	Jan 14 12:29:55 PM PST 24	2160209634 ps
T18	/workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2980516907	Jan 14 12:29:14 PM PST 24	Jan 14 12:30:54 PM PST 24	154186037489 ps
T19	/workspace/coverage/default/29.sysrst_ctrl_stress_all.645362473	Jan 14 12:29:16 PM PST 24	Jan 14 12:29:22 PM PST 24	6569590697 ps
T66	/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.2271400331	Jan 14 12:29:46 PM PST 24	Jan 14 12:29:56 PM PST 24	3656389393 ps
T67	/workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2299615657	Jan 14 12:29:18 PM PST 24	Jan 14 12:29:26 PM PST 24	2247598965 ps
T68	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.2394617538	Jan 14 12:29:14 PM PST 24	Jan 14 12:29:24 PM PST 24	2610015443 ps
T69	/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.982387742	Jan 14 12:29:43 PM PST 24	Jan 14 12:29:58 PM PST 24	4021068863 ps
T70	/workspace/coverage/default/18.sysrst_ctrl_smoke.3141458357	Jan 14 12:28:54 PM PST 24	Jan 14 12:28:58 PM PST 24	2120552680 ps
T20	/workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1640386631	Jan 14 12:29:16 PM PST 24	Jan 14 12:29:25 PM PST 24	6729910108 ps
T43	/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1206458361	Jan 14 12:28:19 PM PST 24	Jan 14 12:32:11 PM PST 24	534880835909 ps
T71	/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1982442141	Jan 14 12:28:49 PM PST 24	Jan 14 12:40:48 PM PST 24	278300670082 ps
T308	/workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1119412117	Jan 14 12:28:45 PM PST 24	Jan 14 12:28:53 PM PST 24	2609688122 ps
T427	/workspace/coverage/default/2.sysrst_ctrl_smoke.2455807577	Jan 14 12:28:33 PM PST 24	Jan 14 12:28:36 PM PST 24	2127602306 ps
T428	/workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.1434017230	Jan 14 12:28:46 PM PST 24	Jan 14 12:28:55 PM PST 24	2489484330 ps
T364	/workspace/coverage/default/11.sysrst_ctrl_pin_override_test.1305254354	Jan 14 12:28:40 PM PST 24	Jan 14 12:28:45 PM PST 24	2518709646 ps
T38	/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3007172937	Jan 14 12:29:39 PM PST 24	Jan 14 12:30:22 PM PST 24	45972688861 ps
T103	/workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.2472889798	Jan 14 12:28:42 PM PST 24	Jan 14 12:29:20 PM PST 24	28086910286 ps
T429	/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.2631062922	Jan 14 12:29:30 PM PST 24	Jan 14 12:29:33 PM PST 24	2262314005 ps
T95	/workspace/coverage/default/31.sysrst_ctrl_combo_detect.2237225237	Jan 14 12:29:12 PM PST 24	Jan 14 12:32:15 PM PST 24	73666841066 ps
T127	/workspace/coverage/default/4.sysrst_ctrl_smoke.4135773233	Jan 14 12:28:31 PM PST 24	Jan 14 12:28:37 PM PST 24	2112746902 ps
T96	/workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3679412617	Jan 14 12:28:42 PM PST 24	Jan 14 12:28:45 PM PST 24	2270968777 ps
T128	/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.1562635377	Jan 14 12:28:49 PM PST 24	Jan 14 12:28:53 PM PST 24	4224390838 ps
T97	/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1735557450	Jan 14 12:28:23 PM PST 24	Jan 14 12:28:32 PM PST 24	3415104334 ps
T129	/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.2731136598	Jan 14 12:28:40 PM PST 24	Jan 14 12:28:47 PM PST 24	2197792135 ps
T51	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.2165850848	Jan 14 12:30:02 PM PST 24	Jan 14 12:30:07 PM PST 24	3117685154 ps
T131	/workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.839646185	Jan 14 12:29:14 PM PST 24	Jan 14 12:29:24 PM PST 24	5299212266 ps
T254	/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.335215086	Jan 14 12:29:37 PM PST 24	Jan 14 12:29:42 PM PST 24	2551391539 ps
T48	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.511101179	Jan 14 12:28:24 PM PST 24	Jan 14 12:28:25 PM PST 24	2329277755 ps
T272	/workspace/coverage/default/33.sysrst_ctrl_alert_test.2839433987	Jan 14 12:29:24 PM PST 24	Jan 14 12:29:28 PM PST 24	2015975884 ps
T430	/workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2031284296	Jan 14 12:28:48 PM PST 24	Jan 14 12:28:55 PM PST 24	2061463510 ps
T273	/workspace/coverage/default/10.sysrst_ctrl_alert_test.1495769197	Jan 14 12:28:44 PM PST 24	Jan 14 12:28:46 PM PST 24	2025983851 ps
T431	/workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3900974688	Jan 14 12:28:51 PM PST 24	Jan 14 12:28:54 PM PST 24	2630109754 ps
T432	/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1738236647	Jan 14 12:29:41 PM PST 24	Jan 14 12:30:01 PM PST 24	3433262210 ps
T104	/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1799343920	Jan 14 12:29:54 PM PST 24	Jan 14 12:30:04 PM PST 24	27401129972 ps
T433	/workspace/coverage/default/20.sysrst_ctrl_smoke.465866041	Jan 14 12:28:52 PM PST 24	Jan 14 12:28:59 PM PST 24	2113210863 ps
T434	/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.93536756	Jan 14 12:28:38 PM PST 24	Jan 14 12:28:46 PM PST 24	2609637108 ps
T39	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1104524348	Jan 14 12:29:14 PM PST 24	Jan 14 12:29:47 PM PST 24	226098188456 ps
T42	/workspace/coverage/default/16.sysrst_ctrl_combo_detect.721698875	Jan 14 12:28:48 PM PST 24	Jan 14 12:34:13 PM PST 24	125877915684 ps
T212	/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4235216939	Jan 14 12:29:36 PM PST 24	Jan 14 12:29:46 PM PST 24	2172388624 ps
T40	/workspace/coverage/default/32.sysrst_ctrl_combo_detect.1163983602	Jan 14 12:29:23 PM PST 24	Jan 14 12:30:21 PM PST 24	79623648290 ps
T213	/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1191878986	Jan 14 12:29:42 PM PST 24	Jan 14 12:29:56 PM PST 24	2184633395 ps
T214	/workspace/coverage/default/24.sysrst_ctrl_smoke.2585380285	Jan 14 12:29:05 PM PST 24	Jan 14 12:29:08 PM PST 24	2125468334 ps
T215	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.257410262	Jan 14 12:29:41 PM PST 24	Jan 14 12:29:57 PM PST 24	2513196794 ps
T45	/workspace/coverage/default/47.sysrst_ctrl_edge_detect.3129861920	Jan 14 12:29:58 PM PST 24	Jan 14 12:30:01 PM PST 24	4764706648 ps
T44	/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2668574263	Jan 14 12:28:42 PM PST 24	Jan 14 12:28:50 PM PST 24	2507198006 ps
T52	/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1384154988	Jan 14 12:29:38 PM PST 24	Jan 14 12:30:50 PM PST 24	89029067628 ps
T41	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.227323467	Jan 14 12:29:08 PM PST 24	Jan 14 12:30:30 PM PST 24	130164361494 ps
T173	/workspace/coverage/default/6.sysrst_ctrl_alert_test.4201566184	Jan 14 12:28:14 PM PST 24	Jan 14 12:28:17 PM PST 24	2032341546 ps
T174	/workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3260267284	Jan 14 12:29:10 PM PST 24	Jan 14 12:29:13 PM PST 24	2883855641 ps
T175	/workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1219906951	Jan 14 12:28:43 PM PST 24	Jan 14 12:28:46 PM PST 24	2624937089 ps
T98	/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3277478519	Jan 14 12:28:42 PM PST 24	Jan 14 12:29:29 PM PST 24	17850213345 ps
T37	/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.577899978	Jan 14 12:29:39 PM PST 24	Jan 14 12:29:51 PM PST 24	5748238200 ps
T135	/workspace/coverage/default/13.sysrst_ctrl_pin_access_test.2844673086	Jan 14 12:28:37 PM PST 24	Jan 14 12:28:44 PM PST 24	2233852529 ps
T125	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.1314094897	Jan 14 12:29:18 PM PST 24	Jan 14 12:32:00 PM PST 24	75735688668 ps
T435	/workspace/coverage/default/12.sysrst_ctrl_pin_access_test.812936944	Jan 14 12:28:38 PM PST 24	Jan 14 12:28:45 PM PST 24	2248337813 ps
T93	/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.2105529948	Jan 14 12:30:05 PM PST 24	Jan 14 12:30:20 PM PST 24	20099992352 ps
T49	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.4063330804	Jan 14 12:29:40 PM PST 24	Jan 14 12:30:28 PM PST 24	53977181400 ps
T257	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.26614212	Jan 14 12:28:38 PM PST 24	Jan 14 12:29:04 PM PST 24	18794889632 ps
T258	/workspace/coverage/default/11.sysrst_ctrl_alert_test.2014643126	Jan 14 12:28:39 PM PST 24	Jan 14 12:28:45 PM PST 24	2010936008 ps
T436	/workspace/coverage/default/5.sysrst_ctrl_alert_test.1113514462	Jan 14 12:28:34 PM PST 24	Jan 14 12:28:36 PM PST 24	2054855327 ps
T437	/workspace/coverage/default/25.sysrst_ctrl_pin_access_test.2867230287	Jan 14 12:29:12 PM PST 24	Jan 14 12:29:19 PM PST 24	2031095509 ps
T53	/workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1355299895	Jan 14 12:29:16 PM PST 24	Jan 14 12:29:25 PM PST 24	3634914395 ps
T130	/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.312057322	Jan 14 12:29:50 PM PST 24	Jan 14 12:31:37 PM PST 24	73785442809 ps
T136	/workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.891935240	Jan 14 12:28:27 PM PST 24	Jan 14 12:29:00 PM PST 24	47382337058 ps
T137	/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1773312332	Jan 14 12:29:52 PM PST 24	Jan 14 12:30:03 PM PST 24	2615454324 ps
T54	/workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1253190793	Jan 14 12:29:13 PM PST 24	Jan 14 12:29:17 PM PST 24	3459847508 ps
T74	/workspace/coverage/default/33.sysrst_ctrl_stress_all.1616466354	Jan 14 12:29:20 PM PST 24	Jan 14 12:31:04 PM PST 24	143444669560 ps
T138	/workspace/coverage/default/48.sysrst_ctrl_stress_all.563827699	Jan 14 12:29:53 PM PST 24	Jan 14 12:30:23 PM PST 24	10885294374 ps
T139	/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3242964472	Jan 14 12:29:37 PM PST 24	Jan 14 12:29:48 PM PST 24	2580244740 ps
T154	/workspace/coverage/default/48.sysrst_ctrl_combo_detect.3965253901	Jan 14 12:29:41 PM PST 24	Jan 14 12:31:32 PM PST 24	141920041981 ps
T155	/workspace/coverage/default/24.sysrst_ctrl_edge_detect.2477494919	Jan 14 12:29:11 PM PST 24	Jan 14 12:29:14 PM PST 24	2884074742 ps
T156	/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.763271644	Jan 14 12:29:40 PM PST 24	Jan 14 12:29:53 PM PST 24	2285813650 ps
T99	/workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3771291485	Jan 14 12:28:55 PM PST 24	Jan 14 12:28:59 PM PST 24	4047867659 ps
T61	/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3701227322	Jan 14 12:29:48 PM PST 24	Jan 14 12:30:00 PM PST 24	6192549213 ps
T438	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1164998568	Jan 14 12:29:39 PM PST 24	Jan 14 12:29:52 PM PST 24	2628353755 ps
T439	/workspace/coverage/default/14.sysrst_ctrl_alert_test.2930817733	Jan 14 12:28:47 PM PST 24	Jan 14 12:28:50 PM PST 24	2033501567 ps
T440	/workspace/coverage/default/20.sysrst_ctrl_alert_test.408525336	Jan 14 12:30:06 PM PST 24	Jan 14 12:30:13 PM PST 24	2009626318 ps
T365	/workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1236015803	Jan 14 12:28:49 PM PST 24	Jan 14 12:28:58 PM PST 24	2513940678 ps
T259	/workspace/coverage/default/1.sysrst_ctrl_combo_detect.3049488109	Jan 14 12:28:29 PM PST 24	Jan 14 12:31:49 PM PST 24	146881935696 ps
T441	/workspace/coverage/default/13.sysrst_ctrl_alert_test.2534195642	Jan 14 12:28:40 PM PST 24	Jan 14 12:28:44 PM PST 24	2016024209 ps
T442	/workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.741049872	Jan 14 12:28:36 PM PST 24	Jan 14 12:28:45 PM PST 24	2438830111 ps
T443	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.616549736	Jan 14 12:29:00 PM PST 24	Jan 14 12:29:04 PM PST 24	4755921965 ps
T82	/workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1144527451	Jan 14 12:28:48 PM PST 24	Jan 14 12:29:00 PM PST 24	39549244733 ps
T444	/workspace/coverage/default/36.sysrst_ctrl_smoke.2995931845	Jan 14 12:29:25 PM PST 24	Jan 14 12:29:27 PM PST 24	2150903266 ps
T445	/workspace/coverage/default/12.sysrst_ctrl_smoke.2517737902	Jan 14 12:28:47 PM PST 24	Jan 14 12:28:50 PM PST 24	2138653848 ps
T240	/workspace/coverage/default/3.sysrst_ctrl_stress_all.629552540	Jan 14 12:28:23 PM PST 24	Jan 14 12:39:49 PM PST 24	250936423706 ps
T94	/workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1125434727	Jan 14 12:28:46 PM PST 24	Jan 14 12:28:49 PM PST 24	2797227975 ps
T245	/workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4243492130	Jan 14 12:28:45 PM PST 24	Jan 14 12:28:50 PM PST 24	3428941839 ps
T62	/workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.144898758	Jan 14 12:28:45 PM PST 24	Jan 14 12:29:43 PM PST 24	27469771976 ps
T246	/workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.2949948496	Jan 14 12:29:08 PM PST 24	Jan 14 12:29:16 PM PST 24	2610028921 ps
T100	/workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2045700550	Jan 14 12:29:12 PM PST 24	Jan 14 12:29:17 PM PST 24	3684563172 ps
T247	/workspace/coverage/default/36.sysrst_ctrl_pin_override_test.2723298907	Jan 14 12:29:27 PM PST 24	Jan 14 12:29:32 PM PST 24	2514404260 ps
T63	/workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.422095351	Jan 14 12:29:34 PM PST 24	Jan 14 12:29:48 PM PST 24	8019111809 ps
T446	/workspace/coverage/default/47.sysrst_ctrl_alert_test.557362185	Jan 14 12:29:44 PM PST 24	Jan 14 12:29:57 PM PST 24	2012752149 ps
T101	/workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.3853383873	Jan 14 12:28:49 PM PST 24	Jan 14 12:28:53 PM PST 24	3267056634 ps
T366	/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2692262459	Jan 14 12:30:08 PM PST 24	Jan 14 12:30:11 PM PST 24	2568537492 ps
T83	/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1503308429	Jan 14 12:29:35 PM PST 24	Jan 14 12:31:13 PM PST 24	133378735376 ps
T309	/workspace/coverage/default/35.sysrst_ctrl_combo_detect.2838098695	Jan 14 12:29:34 PM PST 24	Jan 14 12:30:55 PM PST 24	58874306482 ps
T447	/workspace/coverage/default/16.sysrst_ctrl_stress_all.3004113335	Jan 14 12:28:49 PM PST 24	Jan 14 12:29:02 PM PST 24	14729728640 ps
T448	/workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.232997809	Jan 14 12:28:49 PM PST 24	Jan 14 12:28:58 PM PST 24	2670123870 ps
T126	/workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1888296379	Jan 14 12:29:09 PM PST 24	Jan 14 12:29:25 PM PST 24	21933288988 ps
T64	/workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.2393559718	Jan 14 12:28:52 PM PST 24	Jan 14 12:30:22 PM PST 24	1291776998851 ps
T157	/workspace/coverage/default/31.sysrst_ctrl_edge_detect.60346953	Jan 14 12:29:10 PM PST 24	Jan 14 12:29:23 PM PST 24	4907124124 ps
T449	/workspace/coverage/default/3.sysrst_ctrl_alert_test.3016745922	Jan 14 12:28:39 PM PST 24	Jan 14 12:28:41 PM PST 24	2035786615 ps
T450	/workspace/coverage/default/27.sysrst_ctrl_smoke.1844820826	Jan 14 12:29:14 PM PST 24	Jan 14 12:29:22 PM PST 24	2112547310 ps