Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
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Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
sysrst_ctrl_key_intr_status_cg 100.00 1 100 1 64 64




Group Instance : sysrst_ctrl_key_intr_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 28 0 28 100.00


Variables for Group Instance sysrst_ctrl_key_intr_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_ac_present_h2l 2 0 2 100.00 100 1 1 2
cp_ac_present_l2h 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_h2l 2 0 2 100.00 100 1 1 2
cp_ec_rst_l_l2h 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_h2l 2 0 2 100.00 100 1 1 2
cp_flash_wp_l_l2h 2 0 2 100.00 100 1 1 2
cp_key0_in_h2l 2 0 2 100.00 100 1 1 2
cp_key0_in_l2h 2 0 2 100.00 100 1 1 2
cp_key1_in_h2l 2 0 2 100.00 100 1 1 2
cp_key1_in_l2h 2 0 2 100.00 100 1 1 2
cp_key2_in_h2l 2 0 2 100.00 100 1 1 2
cp_key2_in_l2h 2 0 2 100.00 100 1 1 2
cp_pwrb_h2l 2 0 2 100.00 100 1 1 2
cp_pwrb_l2h 2 0 2 100.00 100 1 1 2


Summary for Variable cp_ac_present_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1150 1 T338 1 T337 1 T339 1
auto[1] 108 1 T14 3 T19 1 T41 1



Summary for Variable cp_ac_present_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1111 1 T338 1 T337 1 T339 1
auto[1] 147 1 T14 2 T41 7 T42 6



Summary for Variable cp_ec_rst_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1131 1 T338 1 T337 1 T339 1
auto[1] 127 1 T13 2 T43 2 T46 2



Summary for Variable cp_ec_rst_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ec_rst_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1148 1 T338 1 T337 1 T339 1
auto[1] 110 1 T14 1 T41 2 T42 1



Summary for Variable cp_flash_wp_l_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1122 1 T338 1 T337 1 T339 1
auto[1] 136 1 T44 2 T41 2 T42 3



Summary for Variable cp_flash_wp_l_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_flash_wp_l_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1180 1 T338 1 T337 1 T339 1
auto[1] 78 1 T19 2 T41 2 T42 4



Summary for Variable cp_key0_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1155 1 T338 1 T337 1 T339 1
auto[1] 103 1 T13 2 T44 4 T41 3



Summary for Variable cp_key0_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1128 1 T338 1 T337 1 T339 1
auto[1] 130 1 T44 2 T41 1 T42 3



Summary for Variable cp_key1_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1142 1 T338 1 T337 1 T339 1
auto[1] 116 1 T13 1 T19 1 T44 2



Summary for Variable cp_key1_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1123 1 T338 1 T337 1 T339 1
auto[1] 135 1 T13 3 T41 3 T42 2



Summary for Variable cp_key2_in_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1167 1 T338 1 T337 1 T339 1
auto[1] 91 1 T13 2 T14 1 T42 3



Summary for Variable cp_key2_in_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1128 1 T338 1 T337 1 T339 1
auto[1] 130 1 T14 3 T19 2 T44 3



Summary for Variable cp_pwrb_h2l

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_h2l

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1151 1 T338 1 T337 1 T339 1
auto[1] 107 1 T13 1 T19 1 T41 4



Summary for Variable cp_pwrb_l2h

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_l2h

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1119 1 T338 1 T337 1 T339 1
auto[1] 139 1 T19 2 T41 6 T42 5

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