Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1838

1

T13

4

T15

13

T17

17

auto[1]

632

1

T13

16

T18

10

T21

14

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1791

1

T13

14

T17

14

T18

28

auto[1]

679

1

T13

6

T15

13

T17

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1840

1

T13

20

T15

7

T17

2

auto[1]

630

1

T15

6

T17

15

T18

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1780

1

T13

14

T15

6

T17

15

auto[1]

690

1

T13

6

T15

7

T17

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2286

1

T13

20

T15

13

T17

17

auto[1]

184

1

T18

1

T20

9

T50

21

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2289

1

T13

20

T15

13

T17

17

auto[1]

181

1

T18

5

T20

2

T50

13

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2265

1

T13

20

T15

13

T17

17

auto[1]

205

1

T18

4

T20

5

T22

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2242

1

T13

20

T15

13

T17

17

auto[1]

228

1

T18

6

T20

9

T22

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2212

1

T13

20

T15

13

T17

17

auto[1]

258

1

T18

1

T22

3

T49

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1801

1

T13

18

T15

7

T17

15

auto[1]

669

1

T13

2

T15

6

T17

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1034	1			T13	20		T15	13		T17	17
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	61	1			T67	4		T77	1		T246	10
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	57	1			T245	7		T69	4		T321	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T50	8		T67	3		T322	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	69	1			T18	6		T22	1		T78	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	18	1			T20	6		T78	8		T323	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	57	1			T49	5		T67	1		T118	28
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T323	1		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	44	1			T78	4		T68	2		T258	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	17	1			T246	7		T323	4		T324	4
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	41	1			T22	3		T245	6		T118	12
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T325	2		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	20	1			T49	5		T64	2		T70	4
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T20	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	9	1			T326	2		T327	7		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	3	1			T328	1		T329	2		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	55	1			T68	2		T245	6		T246	12
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	32	1			T50	7		T247	6		T323	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	30	1			T78	1		T247	5		T330	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	6	1			T18	1		T118	2		T331	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	6	1			T64	2		T258	4		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	1	1			T266	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T61	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	27	1			T18	4		T20	2		T130	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T332	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	6	1			T50	6		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	6	1			T245	6		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T258	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

115

1

T13

9

T18

10

T49

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

164

1

T20

6

T41

1

T109

12

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

61

1

T21

10

T41

5

T246

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

135

1

T50

6

T67

3

T78

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

58

1

T13

5

T21

4

T22

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T17

2

T19

1

T20

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

27

1

T56

3

T68

2

T333

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

93

1

T17

12

T18

1

T50

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

43

1

T41

3

T64

2

T118

14

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

50

1

T266

1

T102

1

T247

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T58

3

T179

3

T172

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

79

1

T50

8

T57

5

T260

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

41

1

T108

4

T245

6

T313

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

42

1

T88

4

T246

12

T334

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T41

2

T272

3

T229

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

115

1

T13

4

T22

1

T88

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

60

1

T217

6

T117

5

T335

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T20

3

T109

5

T311

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

45

1

T13

1

T105

2

T78

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

65

1

T15

7

T67

4

T55

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T41

5

T60

2

T245

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T105

1

T78

4

T336

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T13

1

T335

1

T324

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T17

3

T49

5

T42

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

53

1

T272

2

T109

2

T217

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T15

6

T105

3

T60

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T139

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

41

1

T41

3

T272

2

T77

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T58

3

T336

1

T268

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

14

1

T108

3

T91

2

T269

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T144

2

T167

1

T222

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded