Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T13

8

T16

8

T19

34

auto[1]

1003

1

T13

12

T16

12

T19

26

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

494

1

T13

6

T16

6

T19

13

from_0to1

489

1

T13

6

T16

6

T19

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T13

11

T16

14

T19

36

auto[1]

1003

1

T13

9

T16

6

T19

24

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T13

10

T16

12

T19

33

auto[1]

971

1

T13

10

T16

8

T19

27

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T13

1

T16

1

T19

1

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T13

1

T16

3

T19

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T16

1

T19

3

T86

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T86

1

T87

1

T161

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T13

1

T19

2

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T13

1

T19

3

T160

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T13

2

T16

1

T19

3

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T19

2

T161

1

T162

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T13

1

T19

2

T85

3

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T13

2

T19

3

T160

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T16

1

T19

2

T86

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T13

1

T19

1

T85

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T13

1

T16

3

T19

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T16

1

T19

1

T160

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T85

1

T86

1

T87

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T13

1

T16

1

T19

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T13

7

T16

11

T19

35

auto[1]

1005

1

T13

13

T16

9

T19

25

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

463

1

T13

4

T16

6

T19

14

from_0to1

468

1

T13

4

T16

5

T19

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T13

10

T16

6

T19

27

auto[1]

1004

1

T13

10

T16

14

T19

33

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T13

12

T16

9

T19

37

auto[1]

1016

1

T13

8

T16

11

T19

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T19

3

T87

1

T162

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T16

1

T19

1

T85

1

auto[0]

from_1to0

auto[1]

auto[0]

45

1

T19

3

T85

1

T86

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T16

2

T85

1

T86

2

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T16

1

T19

5

T87

3

auto[0]

from_0to1

auto[0]

auto[1]

65

1

T19

1

T85

1

T86

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T16

2

T19

2

T85

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T13

1

T16

1

T19

1

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T13

2

T16

1

T19

3

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T13

1

T19

1

T85

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T13

1

T16

1

T19

3

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T16

1

T85

1

T87

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T13

1

T19

1

T86

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T13

1

T16

1

T19

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T13

1

T19

1

T85

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T19

2

T87

1

T41

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T13

12

T16

8

T19

31

auto[1]

1014

1

T13

8

T16

12

T19

29

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T13

7

T16

5

T19

14

from_0to1

494

1

T13

8

T16

4

T19

15

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

994

1

T13

8

T16

11

T19

35

auto[1]

1041

1

T13

12

T16

9

T19

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T13

7

T16

9

T19

32

auto[1]

1036

1

T13

13

T16

11

T19

28

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T13

1

T16

1

T19

2

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T13

1

T19

3

T86

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T85

1

T87

1

T41

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T13

2

T85

1

T41

4

auto[0]

from_0to1

auto[0]

auto[0]

52

1

T13

1

T19

1

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T13

2

T16

1

T19

2

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T13

1

T19

3

T41

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T13

1

T19

1

T85

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T16

2

T19

2

T85

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T19

3

T85

1

T160

2

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T16

1

T19

3

T86

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T13

3

T16

1

T19

1

auto[1]

from_0to1

auto[0]

auto[0]

37

1

T16

1

T19

2

T87

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T16

1

T19

2

T86

1

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T13

1

T19

3

T86

2

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T13

2

T16

1

T19

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1004

1

T13

9

T16

5

T19

30

auto[1]

1031

1

T13

11

T16

15

T19

30

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T13

6

T16

5

T19

13

from_0to1

495

1

T13

6

T16

4

T19

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T13

10

T16

10

T19

34

auto[1]

997

1

T13

10

T16

10

T19

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T13

12

T16

12

T19

33

auto[1]

1014

1

T13

8

T16

8

T19

27

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T19

1

T85

1

T86

2

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T13

2

T16

1

T19

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T19

2

T160

1

T41

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T13

1

T19

2

T86

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T16

1

T19

4

T85

2

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T19

1

T160

1

T41

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T13

2

T19

1

T87

1

auto[0]

from_0to1

auto[1]

auto[1]

44

1

T85

1

T86

1

T161

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T13

2

T16

1

T19

2

auto[1]

from_1to0

auto[0]

auto[1]

64

1

T16

1

T19

3

T162

2

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T16

1

T85

1

T87

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T13

1

T16

1

T19

1

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T13

2

T16

2

T19

3

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T19

1

T85

1

T86

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T13

2

T16

1

T19

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T19

2

T86

2

T160

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T13

10

T16

10

T19

33

auto[1]

987

1

T13

10

T16

10

T19

27

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

491

1

T13

6

T16

5

T19

14

from_0to1

477

1

T13

5

T16

5

T19

14

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T13

9

T16

13

T19

39

auto[1]

1013

1

T13

11

T16

7

T19

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1011

1

T13

7

T16

11

T19

32

auto[1]

1024

1

T13

13

T16

9

T19

28

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T16

1

T19

3

T162

2

auto[0]

from_1to0

auto[0]

auto[1]

51

1

T16

1

T19

2

T86

1

auto[0]

from_1to0

auto[1]

auto[0]

62

1

T19

2

T85

1

T86

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T13

3

T85

1

T87

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T16

3

T19

3

T86

2

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T13

1

T19

3

T87

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T16

1

T85

1

T86

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T19

1

T86

1

T87

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T13

2

T16

1

T19

3

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T19

2

T86

2

T87

3

auto[1]

from_1to0

auto[1]

auto[0]

67

1

T13

1

T86

1

T160

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T16

2

T19

2

T86

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T13

1

T16

1

T19

2

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T13

1

T19

4

T87

2

auto[1]

from_0to1

auto[1]

auto[0]

40

1

T13

1

T86

1

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T13

1

T19

1

T85

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1014

1

T13

7

T16

13

T19

33

auto[1]

1021

1

T13

13

T16

7

T19

27

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

504

1

T13

5

T16

5

T19

14

from_0to1

501

1

T13

6

T16

6

T19

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T13

10

T16

12

T19

28

auto[1]

1036

1

T13

10

T16

8

T19

32

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T13

13

T16

12

T19

24

auto[1]

1012

1

T13

7

T16

8

T19

36

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T13

1

T16

3

T19

3

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T13

1

T19

3

T85

1

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T19

1

T85

1

T87

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T13

1

T19

2

T86

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T13

1

T16

2

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T13

1

T16

2

T19

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T16

1

T19

3

T86

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T19

2

T86

1

T87

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T19

1

T86

1

T162

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T19

2

T85

2

T87

2

auto[1]

from_1to0

auto[1]

auto[0]

82

1

T13

1

T16

2

T19

2

auto[1]

from_1to0

auto[1]

auto[1]

68

1

T13

1

T86

1

T161

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T13

2

T16

1

T19

2

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T160

2

T41

3

T42

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T13

1

T19

1

T85

3

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T13

1

T19

3

T85

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T13

10

T16

7

T19

26

auto[1]

1016

1

T13

10

T16

13

T19

34

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T13

5

T16

3

T19

17

from_0to1

498

1

T13

5

T16

3

T19

17

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T13

7

T16

9

T19

25

auto[1]

1049

1

T13

13

T16

11

T19

35

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

986

1

T13

7

T16

8

T19

29

auto[1]

1049

1

T13

13

T16

12

T19

31

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T19

1

T85

2

T86

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T19

2

T85

1

T86

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T19

3

T86

2

T41

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T13

3

T16

1

T19

3

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T13

3

T19

2

T85

3

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T16

1

T19

1

T161

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T19

1

T85

1

T161

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T16

1

T19

1

T85

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T16

1

T19

2

T85

1

auto[1]

from_1to0

auto[0]

auto[1]

57

1

T13

1

T85

1

T87

2

auto[1]

from_1to0

auto[1]

auto[0]

72

1

T16

1

T19

3

T160

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T13

1

T19

3

T85

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T19

4

T85

1

T86

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T19

3

T85

1

T87

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T19

2

T86

1

T87

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T13

2

T16

1

T19

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T13

9

T16

8

T19

29

auto[1]

1000

1

T13

11

T16

12

T19

31

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T13

6

T16

4

T19

13

from_0to1

488

1

T13

7

T16

5

T19

13

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T13

8

T16

13

T19

34

auto[1]

1030

1

T13

12

T16

7

T19

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1018

1

T13

12

T16

7

T19

24

auto[1]

1017

1

T13

8

T16

13

T19

36

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T13

1

T160

1

T161

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T16

1

T19

2

T87

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T19

2

T85

1

T86

2

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T13

1

T16

1

T19

4

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T13

1

T19

2

T86

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T16

1

T85

1

T87

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T85

1

T86

2

T160

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T13

2

T19

2

T85

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T13

2

T16

1

T19

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T16

1

T19

3

T85

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T13

2

T19

1

T85

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T85

1

T87

2

T160

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T13

1

T19

2

T86

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T16

2

T19

2

T86

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T13

1

T16

1

T19

2

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T13

2

T16

1

T19

3