Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154479	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119064

1

T1

114

T6

14

T2

833

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141989	1			T1	156		T6	20		T2	403
values[0x0]	65331	1			T1	55		T6	10		T2	204
values[0x1]	66223	1			T1	45		T6	9		T2	226

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	124744	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148799

1

T1

146

T6

16

T2

833

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1089	1			T1	1		T3	4		T8	16
valid_sources[0x01]	1009	1			T1	2		T3	5		T8	9
valid_sources[0x02]	873	1			T1	1		T2	1		T3	4
valid_sources[0x03]	849	1			T6	3		T3	1		T23	1
valid_sources[0x04]	898	1			T1	2		T6	2		T2	6
valid_sources[0x05]	1722	1			T1	1		T6	1		T2	15
valid_sources[0x06]	1081	1			T2	15		T3	3		T23	1
valid_sources[0x07]	1290	1			T2	5		T3	5		T23	2
valid_sources[0x08]	871	1			T1	1		T2	11		T3	5
valid_sources[0x09]	981	1			T2	1		T3	3		T23	2
valid_sources[0x0a]	1034	1			T1	2		T2	7		T3	1
valid_sources[0x0b]	989	1			T2	9		T3	8		T7	1
valid_sources[0x0c]	938	1			T1	2		T2	7		T3	7
valid_sources[0x0d]	1671	1			T1	2		T3	6		T23	14
valid_sources[0x0e]	1006	1			T2	2		T3	10		T23	2
valid_sources[0x0f]	1051	1			T1	2		T2	7		T3	7
valid_sources[0x10]	1736	1			T1	1		T2	16		T3	5
valid_sources[0x11]	1069	1			T1	2		T2	18		T3	7
valid_sources[0x12]	989	1			T2	27		T3	3		T23	2
valid_sources[0x13]	1838	1			T2	1		T3	7		T8	12
valid_sources[0x14]	1846	1			T1	3		T3	3		T8	13
valid_sources[0x15]	943	1			T2	9		T3	3		T23	3
valid_sources[0x16]	1022	1			T1	1		T3	2		T7	1
valid_sources[0x17]	1284	1			T1	1		T2	5		T3	5
valid_sources[0x18]	1118	1			T1	1		T6	3		T3	5
valid_sources[0x19]	999	1			T1	5		T3	4		T8	13
valid_sources[0x1a]	1137	1			T1	3		T3	6		T23	4
valid_sources[0x1b]	1016	1			T1	3		T6	4		T2	1
valid_sources[0x1c]	1208	1			T3	1		T8	8		T9	3
valid_sources[0x1d]	901	1			T3	9		T8	7		T9	4
valid_sources[0x1e]	1022	1			T1	1		T6	1		T3	8
valid_sources[0x1f]	1253	1			T1	1		T2	19		T3	4
valid_sources[0x20]	798	1			T2	8		T3	3		T8	8
valid_sources[0x21]	922	1			T1	1		T3	4		T8	16
valid_sources[0x22]	1062	1			T1	1		T2	11		T3	4
valid_sources[0x23]	975	1			T1	2		T3	1		T8	12
valid_sources[0x24]	931	1			T1	1		T3	4		T7	3
valid_sources[0x25]	784	1			T1	1		T2	3		T3	5
valid_sources[0x26]	1663	1			T2	10		T3	3		T8	9
valid_sources[0x27]	920	1			T1	1		T3	6		T23	1
valid_sources[0x28]	848	1			T1	1		T2	10		T3	3
valid_sources[0x29]	993	1			T1	3		T3	3		T7	2
valid_sources[0x2a]	915	1			T1	1		T3	8		T7	4
valid_sources[0x2b]	862	1			T1	3		T3	4		T23	4
valid_sources[0x2c]	1753	1			T3	5		T8	5		T9	2
valid_sources[0x2d]	972	1			T1	1		T2	11		T3	5
valid_sources[0x2e]	1198	1			T1	3		T2	2		T3	7
valid_sources[0x2f]	979	1			T1	1		T2	5		T3	5
valid_sources[0x30]	980	1			T1	1		T3	4		T8	7
valid_sources[0x31]	937	1			T3	4		T23	1		T8	15
valid_sources[0x32]	1051	1			T1	2		T3	7		T23	12
valid_sources[0x33]	1061	1			T1	1		T3	6		T8	8
valid_sources[0x34]	955	1			T1	2		T3	3		T7	3
valid_sources[0x35]	908	1			T3	5		T8	19		T9	5
valid_sources[0x36]	728	1			T3	2		T23	5		T8	8
valid_sources[0x37]	905	1			T1	1		T3	3		T7	2
valid_sources[0x38]	1458	1			T1	2		T3	5		T23	7
valid_sources[0x39]	965	1			T1	1		T3	4		T8	2
valid_sources[0x3a]	834	1			T1	2		T2	13		T3	1
valid_sources[0x3b]	857	1			T3	8		T7	4		T8	14
valid_sources[0x3c]	939	1			T2	5		T3	5		T8	8
valid_sources[0x3d]	973	1			T1	2		T3	4		T23	2
valid_sources[0x3e]	1512	1			T1	3		T3	12		T23	2
valid_sources[0x3f]	964	1			T3	4		T23	7		T8	9
valid_sources[0x40]	832	1			T1	2		T3	4		T23	1
valid_sources[0x41]	885	1			T2	9		T3	4		T7	9
valid_sources[0x42]	951	1			T2	15		T3	3		T8	6
valid_sources[0x43]	1128	1			T1	2		T3	5		T23	1
valid_sources[0x44]	1178	1			T1	2		T3	5		T23	1
valid_sources[0x45]	827	1			T1	3		T3	2		T8	8
valid_sources[0x46]	920	1			T1	3		T2	6		T3	4
valid_sources[0x47]	903	1			T3	2		T23	2		T8	1
valid_sources[0x48]	842	1			T3	7		T8	11		T9	2
valid_sources[0x49]	1402	1			T6	5		T2	11		T3	1
valid_sources[0x4a]	880	1			T1	2		T3	10		T8	11
valid_sources[0x4b]	988	1			T1	2		T3	1		T8	6
valid_sources[0x4c]	1069	1			T1	1		T3	1		T23	1
valid_sources[0x4d]	1001	1			T3	3		T23	2		T8	7
valid_sources[0x4e]	857	1			T1	2		T2	3		T3	3
valid_sources[0x4f]	1092	1			T6	2		T3	3		T8	9
valid_sources[0x50]	747	1			T1	2		T3	3		T23	1
valid_sources[0x51]	817	1			T2	7		T3	4		T23	1
valid_sources[0x52]	1045	1			T2	1		T3	8		T23	6
valid_sources[0x53]	1479	1			T1	2		T2	2		T3	6
valid_sources[0x54]	1677	1			T1	3		T3	4		T23	5
valid_sources[0x55]	948	1			T6	4		T2	14		T3	2
valid_sources[0x56]	948	1			T1	1		T3	5		T23	1
valid_sources[0x57]	917	1			T1	1		T2	3		T3	3
valid_sources[0x58]	1043	1			T2	7		T3	4		T23	8
valid_sources[0x59]	888	1			T1	2		T3	7		T8	7
valid_sources[0x5a]	1144	1			T1	3		T3	1		T7	3
valid_sources[0x5b]	823	1			T2	5		T3	7		T8	3
valid_sources[0x5c]	1001	1			T2	2		T3	2		T7	5
valid_sources[0x5d]	2074	1			T3	1		T8	5		T9	1
valid_sources[0x5e]	906	1			T3	3		T23	1		T8	9
valid_sources[0x5f]	1111	1			T1	2		T2	3		T3	4
valid_sources[0x60]	1261	1			T3	4		T8	4		T9	6
valid_sources[0x61]	1338	1			T1	1		T3	5		T7	3
valid_sources[0x62]	1015	1			T1	1		T3	6		T23	2
valid_sources[0x63]	1227	1			T1	1		T3	5		T8	6
valid_sources[0x64]	1869	1			T1	1		T2	27		T3	5
valid_sources[0x65]	959	1			T3	6		T23	3		T8	7
valid_sources[0x66]	1091	1			T1	2		T3	6		T23	2
valid_sources[0x67]	1062	1			T1	1		T2	1		T3	3
valid_sources[0x68]	918	1			T3	7		T23	2		T8	16
valid_sources[0x69]	1506	1			T1	2		T2	4		T3	5
valid_sources[0x6a]	841	1			T1	2		T2	2		T3	5
valid_sources[0x6b]	875	1			T1	1		T2	9		T3	5
valid_sources[0x6c]	883	1			T1	1		T2	11		T3	5
valid_sources[0x6d]	912	1			T1	1		T3	3		T23	3
valid_sources[0x6e]	1241	1			T2	6		T3	7		T8	8
valid_sources[0x6f]	1165	1			T1	1		T2	8		T3	6
valid_sources[0x70]	1152	1			T3	3		T23	4		T8	8
valid_sources[0x71]	1136	1			T1	1		T3	6		T8	11
valid_sources[0x72]	922	1			T1	3		T2	9		T3	3
valid_sources[0x73]	1901	1			T1	2		T3	5		T23	2
valid_sources[0x74]	907	1			T1	1		T3	7		T8	19
valid_sources[0x75]	1075	1			T3	5		T8	22		T9	1
valid_sources[0x76]	1011	1			T1	2		T2	17		T3	1
valid_sources[0x77]	880	1			T1	2		T2	4		T3	2
valid_sources[0x78]	1420	1			T3	2		T8	12		T9	4
valid_sources[0x79]	817	1			T3	3		T7	1		T23	2
valid_sources[0x7a]	1069	1			T1	3		T6	4		T2	8
valid_sources[0x7b]	826	1			T2	5		T3	5		T8	17
valid_sources[0x7c]	1450	1			T1	1		T2	8		T3	5
valid_sources[0x7d]	722	1			T1	1		T2	2		T3	4
valid_sources[0x7e]	877	1			T1	2		T3	5		T23	1
valid_sources[0x7f]	1001	1			T1	3		T3	5		T23	3
valid_sources[0x80]	809	1			T3	3		T8	12		T9	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64358

1

T1

60

T6

9

T2

403

values[0x0]

all_enables

biggest_size

32041

1

T1

30

T6

3

T2

204

values[0x1]

all_enables

biggest_size

22665

1

T1

24

T6

2

T2

226