Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T27,T28
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T28
0	1	Covered	T42
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T28
0	1	Covered	T13,T27,T28
1	0	Covered	T62

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T27,T28
1	-	Covered	T13,T27,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T27,T28
0	1	Covered	T13,T27,T28
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T27,T28
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T27,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T42
DetectSt	-	-	-	-	0	1	-	Covered	T13,T27,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T27,T28
StableSt	-	-	-	-	-	-	0	Covered	T13,T27,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	259	0	0
CntIncr_A	7322997	202660	0	0
CntNoWrap_A	7322997	6654999	0	0
DetectStDropOut_A	7322997	1	0	0
DetectedOut_A	7322997	843	0	0
DetectedPulseOut_A	7322997	120	0	0
DisabledIdleSt_A	7322997	6376909	0	0
DisabledNoDetection_A	7322997	6379292	0	0
EnterDebounceSt_A	7322997	143	0	0
EnterDetectSt_A	7322997	121	0	0
EnterStableSt_A	7322997	120	0	0
PulseIsPulse_A	7322997	120	0	0
StayInStableSt	7322997	723	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7322997	7101	0	0
gen_low_level_sva.LowLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	119	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	259	0	0
T13	69834	11	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	6	0	0
T19	0	8	0	0
T26	522	0	0	0
T27	6406	5	0	0
T28	575	4	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T42	0	2	0	0
T79	0	2	0	0
T80	0	4	0	0
T81	0	2	0	0
T82	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	202660	0	0
T13	69834	2993	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	87	0	0
T19	0	230	0	0
T26	522	0	0	0
T27	6406	51	0	0
T28	575	36	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T42	0	58	0	0
T79	0	82	0	0
T80	0	113	0	0
T81	0	66	0	0
T82	0	87	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6654999	0	0
T13	69834	57759	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2422	0	0
T26	522	121	0	0
T27	6406	894	0	0
T28	575	170	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1	0	0
T42	15727	1	0	0
T43	871	0	0	0
T51	238858	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	843	0	0
T13	69834	26	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	9	0	0
T19	0	31	0	0
T26	522	0	0	0
T27	6406	18	0	0
T28	575	14	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T79	0	4	0	0
T80	0	10	0	0
T81	0	6	0	0
T82	0	23	0	0
T111	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	120	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	3	0	0
T19	0	4	0	0
T26	522	0	0	0
T27	6406	2	0	0
T28	575	2	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0
T111	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6376909	0	0
T13	69834	54527	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2235	0	0
T26	522	121	0	0
T27	6406	729	0	0
T28	575	52	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6379292	0	0
T13	69834	54557	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2248	0	0
T26	522	122	0	0
T27	6406	744	0	0
T28	575	53	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	143	0	0
T13	69834	7	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	3	0	0
T19	0	4	0	0
T26	522	0	0	0
T27	6406	3	0	0
T28	575	2	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T42	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	121	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	3	0	0
T19	0	4	0	0
T26	522	0	0	0
T27	6406	2	0	0
T28	575	2	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T42	0	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	120	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	3	0	0
T19	0	4	0	0
T26	522	0	0	0
T27	6406	2	0	0
T28	575	2	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0
T111	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	120	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	3	0	0
T19	0	4	0	0
T26	522	0	0	0
T27	6406	2	0	0
T28	575	2	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0
T111	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	723	0	0
T13	69834	21	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	6	0	0
T19	0	27	0	0
T26	522	0	0	0
T27	6406	16	0	0
T28	575	12	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T79	0	3	0	0
T80	0	8	0	0
T81	0	5	0	0
T82	0	21	0	0
T111	0	17	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	7101	0	0
T13	69834	88	0	0
T14	1004	1	0	0
T15	25490	9	0	0
T16	8605	34	0	0
T26	522	4	0	0
T27	6406	38	0	0
T28	575	3	0	0
T29	525	6	0	0
T30	521	5	0	0
T31	427	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	119	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	3	0	0
T19	0	4	0	0
T26	522	0	0	0
T27	6406	2	0	0
T28	575	2	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T79	0	1	0	0
T80	0	2	0	0
T81	0	1	0	0
T82	0	2	0	0
T111	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T16,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T16,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T16,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T19
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T16,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T19
0	1	Covered	T41,T75,T71
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T19
0	1	Unreachable
1	0	Covered	T13,T16,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T16,T19
0	1	Covered	T13,T16,T19
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T19
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T19
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T52,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T19
DetectSt	-	-	-	-	1	-	-	Covered	T41,T75,T71
DetectSt	-	-	-	-	0	1	-	Covered	T13,T16,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T16,T19
StableSt	-	-	-	-	-	-	0	Covered	T13,T16,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	150	0	0
CntIncr_A	7322997	256019	0	0
CntNoWrap_A	7322997	6655108	0	0
DetectStDropOut_A	7322997	10	0	0
DetectedOut_A	7322997	75198	0	0
DetectedPulseOut_A	7322997	41	0	0
DisabledIdleSt_A	7322997	6016875	0	0
DisabledNoDetection_A	7322997	6019314	0	0
EnterDebounceSt_A	7322997	99	0	0
EnterDetectSt_A	7322997	51	0	0
EnterStableSt_A	7322997	41	0	0
PulseIsPulse_A	7322997	41	0	0
StayInStableSt	7322997	75157	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7322997	7101	0	0
gen_low_level_sva.LowLevelEvent_A	7322997	6657698	0	0
gen_sticky_sva.StableStDropOut_A	7322997	261666	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	150	0	0
T13	69834	2	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	2	0	0
T19	0	2	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	8	0	0
T42	0	2	0	0
T51	0	2	0	0
T52	0	4	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	256019	0	0
T13	69834	23	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	67	0	0
T19	0	56	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	281	0	0
T42	0	17	0	0
T51	0	79428	0	0
T52	0	136	0	0
T53	0	62	0	0
T54	0	40	0	0
T55	0	75	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655108	0	0
T13	69834	57768	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2426	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	10	0	0
T41	50824	1	0	0
T42	15727	0	0	0
T43	871	0	0	0
T51	238858	0	0	0
T71	0	3	0	0
T75	7761	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	1	0	0
T117	55227	0	0	0
T118	27756	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	75198	0	0
T13	69834	123	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	180	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	447	0	0
T42	0	34	0	0
T53	0	135	0	0
T54	0	184	0	0
T55	0	186	0	0
T72	0	126	0	0
T75	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	41	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6016875	0	0
T13	69834	56876	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2298	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6019314	0	0
T13	69834	56909	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2313	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	99	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T51	0	2	0	0
T52	0	4	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	51	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	4	0	0
T42	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T71	0	3	0	0
T75	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	41	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	41	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T72	0	1	0	0
T75	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	75157	0	0
T13	69834	122	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T19	0	179	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	444	0	0
T42	0	33	0	0
T53	0	134	0	0
T54	0	183	0	0
T55	0	185	0	0
T72	0	125	0	0
T75	0	126	0	0
T119	0	554	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	7101	0	0
T13	69834	88	0	0
T14	1004	1	0	0
T15	25490	9	0	0
T16	8605	34	0	0
T26	522	4	0	0
T27	6406	38	0	0
T28	575	3	0	0
T29	525	6	0	0
T30	521	5	0	0
T31	427	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	261666	0	0
T13	69834	724	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	40	0	0
T19	0	43640	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	470	0	0
T42	0	214	0	0
T53	0	89	0	0
T54	0	177	0	0
T55	0	344	0	0
T72	0	390	0	0
T75	0	436	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T16,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T16,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T16,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T19
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T16,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T41
0	1	Covered	T13,T42,T53
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T19,T41
0	1	Unreachable
1	0	Covered	T16,T19,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T16,T19
0	1	Covered	T13,T16,T19
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T19
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T19
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T41,T52
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T19
DetectSt	-	-	-	-	1	-	-	Covered	T13,T42,T53
DetectSt	-	-	-	-	0	1	-	Covered	T16,T19,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T19,T41
StableSt	-	-	-	-	-	-	0	Covered	T16,T19,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	151	0	0
CntIncr_A	7322997	15949	0	0
CntNoWrap_A	7322997	6655107	0	0
DetectStDropOut_A	7322997	16	0	0
DetectedOut_A	7322997	42072	0	0
DetectedPulseOut_A	7322997	45	0	0
DisabledIdleSt_A	7322997	6016875	0	0
DisabledNoDetection_A	7322997	6019314	0	0
EnterDebounceSt_A	7322997	90	0	0
EnterDetectSt_A	7322997	61	0	0
EnterStableSt_A	7322997	45	0	0
PulseIsPulse_A	7322997	45	0	0
StayInStableSt	7322997	42027	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_sticky_sva.StableStDropOut_A	7322997	451743	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	151	0	0
T13	69834	9	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	2	0	0
T19	0	2	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	6	0	0
T42	0	4	0	0
T51	0	2	0	0
T52	0	3	0	0
T53	0	5	0	0
T54	0	3	0	0
T55	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	15949	0	0
T13	69834	395	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	74	0	0
T19	0	10630	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	169	0	0
T42	0	50	0	0
T51	0	78	0	0
T52	0	100	0	0
T53	0	135	0	0
T54	0	150	0	0
T55	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655107	0	0
T13	69834	57761	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2426	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	16	0	0
T13	69834	4	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T42	0	1	0	0
T53	0	2	0	0
T113	0	2	0	0
T116	0	1	0	0
T120	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	42072	0	0
T16	8605	1	0	0
T17	10613	0	0	0
T18	15803	0	0	0
T19	63708	33183	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	0	626	0	0
T42	0	1	0	0
T51	0	120	0	0
T52	0	103	0	0
T55	0	42	0	0
T71	0	640	0	0
T72	0	620	0	0
T75	0	44	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T112	425	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	45	0	0
T16	8605	1	0	0
T17	10613	0	0	0
T18	15803	0	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T75	0	1	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T112	425	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6016875	0	0
T13	69834	56876	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2298	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6019314	0	0
T13	69834	56909	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2313	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	90	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	4	0	0
T42	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	0	3	0	0
T54	0	3	0	0
T55	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	61	0	0
T13	69834	4	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T75	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	45	0	0
T16	8605	1	0	0
T17	10613	0	0	0
T18	15803	0	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T75	0	1	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T112	425	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	45	0	0
T16	8605	1	0	0
T17	10613	0	0	0
T18	15803	0	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	0	2	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T71	0	1	0	0
T72	0	2	0	0
T75	0	1	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T112	425	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	42027	0	0
T19	63708	33182	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	624	0	0
T42	15727	0	0	0
T51	0	119	0	0
T52	0	102	0	0
T55	0	41	0	0
T71	0	639	0	0
T72	0	618	0	0
T75	0	43	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T119	0	122	0	0
T124	0	238	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	451743	0	0
T16	8605	33	0	0
T17	10613	0	0	0
T18	15803	0	0	0
T19	63708	66	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	0	205	0	0
T42	0	99	0	0
T51	0	79283	0	0
T52	0	148	0	0
T55	0	547	0	0
T71	0	120	0	0
T72	0	330	0	0
T75	0	29	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T112	425	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T16,T19

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T16,T19

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T16,T19

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T16,T19
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T16,T19

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T19
0	1	Covered	T19,T71,T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T16,T19
0	1	Unreachable
1	0	Covered	T13,T16,T19

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T16,T19
0	1	Covered	T13,T16,T19
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T19
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T16,T19
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T16,T19
DebounceSt	-	0	1	0	-	-	-	Covered	T71,T72,T125
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T16,T19
DetectSt	-	-	-	-	1	-	-	Covered	T19,T71,T72
DetectSt	-	-	-	-	0	1	-	Covered	T13,T16,T19
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T16,T19
StableSt	-	-	-	-	-	-	0	Covered	T13,T16,T19
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	166	0	0
CntIncr_A	7322997	113615	0	0
CntNoWrap_A	7322997	6655092	0	0
DetectStDropOut_A	7322997	23	0	0
DetectedOut_A	7322997	137372	0	0
DetectedPulseOut_A	7322997	49	0	0
DisabledIdleSt_A	7322997	6016875	0	0
DisabledNoDetection_A	7322997	6019314	0	0
EnterDebounceSt_A	7322997	94	0	0
EnterDetectSt_A	7322997	72	0	0
EnterStableSt_A	7322997	49	0	0
PulseIsPulse_A	7322997	49	0	0
StayInStableSt	7322997	137323	0	0
gen_high_event_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_sticky_sva.StableStDropOut_A	7322997	281899	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	166	0	0
T13	69834	2	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	2	0	0
T19	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	6	0	0
T42	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	113615	0	0
T13	69834	87	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	50	0	0
T19	0	16892	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	212	0	0
T42	0	68	0	0
T51	0	30	0	0
T52	0	13	0	0
T53	0	53	0	0
T54	0	31	0	0
T55	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655092	0	0
T13	69834	57768	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2426	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	23	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T71	3421	1	0	0
T72	0	4	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T116	0	1	0	0
T120	0	6	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T129	0	4	0	0
T130	14980	0	0	0
T131	929	0	0	0
T132	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	137372	0	0
T13	69834	733	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	48	0	0
T19	0	8447	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	805	0	0
T42	0	172	0	0
T51	0	41	0	0
T52	0	78	0	0
T53	0	207	0	0
T54	0	148	0	0
T55	0	476	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	49	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6016875	0	0
T13	69834	56876	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2298	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6019314	0	0
T13	69834	56909	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2313	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	94	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	2	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	72	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	2	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	49	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	49	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	1	0	0
T19	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	3	0	0
T42	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	137323	0	0
T13	69834	732	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	47	0	0
T19	0	8446	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	802	0	0
T42	0	171	0	0
T51	0	40	0	0
T52	0	77	0	0
T53	0	206	0	0
T54	0	147	0	0
T55	0	475	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	281899	0	0
T13	69834	68	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	25	0	0
T19	0	12371	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	251	0	0
T42	0	35	0	0
T51	0	79414	0	0
T52	0	319	0	0
T53	0	39	0	0
T54	0	237	0	0
T55	0	43	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T19,T42,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T19,T42,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T19,T42,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T41,T42
1	0	Covered	T13,T26,T27
1	1	Covered	T19,T42,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T42,T48
0	1	Covered	T133,T134
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T42,T48
0	1	Covered	T42,T48,T135
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T42,T48
1	-	Covered	T42,T48,T135

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T42,T48
0	1	Covered	T19,T42,T48
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T42,T48
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T42,T48
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T42,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T136
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T42,T48
DetectSt	-	-	-	-	1	-	-	Covered	T133,T134
DetectSt	-	-	-	-	0	1	-	Covered	T19,T42,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T48,T135
StableSt	-	-	-	-	-	-	0	Covered	T19,T42,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	52	0	0
CntIncr_A	7322997	49878	0	0
CntNoWrap_A	7322997	6655206	0	0
DetectStDropOut_A	7322997	2	0	0
DetectedOut_A	7322997	1399	0	0
DetectedPulseOut_A	7322997	23	0	0
DisabledIdleSt_A	7322997	6542219	0	0
DisabledNoDetection_A	7322997	6544614	0	0
EnterDebounceSt_A	7322997	27	0	0
EnterDetectSt_A	7322997	25	0	0
EnterStableSt_A	7322997	23	0	0
PulseIsPulse_A	7322997	23	0	0
StayInStableSt	7322997	1366	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	52	0	0
T19	63708	2	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	2	0	0
T43	871	0	0	0
T48	0	2	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	4	0	0
T135	0	4	0	0
T137	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0
T140	0	2	0	0
T141	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	49878	0	0
T19	63708	10	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	77	0	0
T43	871	0	0	0
T48	0	64	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	136	0	0
T135	0	90	0	0
T137	0	17	0	0
T138	0	28	0	0
T139	0	16	0	0
T140	0	33	0	0
T141	0	124	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655206	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	2	0	0
T133	1044	1	0	0
T134	0	1	0	0
T139	33550	0	0	0
T142	745	0	0	0
T143	494	0	0	0
T144	21400	0	0	0
T145	18860	0	0	0
T146	502	0	0	0
T147	502	0	0	0
T148	6094	0	0	0
T149	429	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1399	0	0
T19	63708	41	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	118	0	0
T43	871	0	0	0
T48	0	43	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	35	0	0
T135	0	120	0	0
T137	0	64	0	0
T138	0	98	0	0
T139	0	40	0	0
T140	0	95	0	0
T141	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	23	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	1	0	0
T43	871	0	0	0
T48	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6542219	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6544614	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	27	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	1	0	0
T43	871	0	0	0
T48	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	25	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	1	0	0
T43	871	0	0	0
T48	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	2	0	0
T135	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	23	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	1	0	0
T43	871	0	0	0
T48	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	23	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	1	0	0
T43	871	0	0	0
T48	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	1	0	0
T135	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1366	0	0
T19	63708	39	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T42	15727	117	0	0
T43	871	0	0	0
T48	0	42	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T133	0	34	0	0
T135	0	117	0	0
T137	0	62	0	0
T138	0	96	0	0
T139	0	39	0	0
T140	0	94	0	0
T141	0	77	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	12	0	0
T42	15727	1	0	0
T43	871	0	0	0
T48	1025	1	0	0
T51	238858	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T152	425	0	0	0
T153	934	0	0	0
T154	405	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T44,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T44,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T44,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T44,T41,T42
1	0	Covered	T13,T26,T27
1	1	Covered	T44,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T41,T42
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T41,T42
0	1	Covered	T48,T155,T55
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T41,T42
1	-	Covered	T48,T155,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T44,T41,T42
0	1	Covered	T44,T41,T42
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T41,T42
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T44,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T44,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T156,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T44,T41,T42
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T44,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T155,T55
StableSt	-	-	-	-	-	-	0	Covered	T44,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	123	0	0
CntIncr_A	7322997	133670	0	0
CntNoWrap_A	7322997	6655135	0	0
DetectStDropOut_A	7322997	0	0	0
DetectedOut_A	7322997	71107	0	0
DetectedPulseOut_A	7322997	60	0	0
DisabledIdleSt_A	7322997	6376737	0	0
DisabledNoDetection_A	7322997	6379126	0	0
EnterDebounceSt_A	7322997	63	0	0
EnterDetectSt_A	7322997	60	0	0
EnterStableSt_A	7322997	60	0	0
PulseIsPulse_A	7322997	60	0	0
StayInStableSt	7322997	71017	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7322997	2764	0	0
gen_low_level_sva.LowLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	123	0	0
T41	50824	2	0	0
T42	15727	2	0	0
T43	871	0	0	0
T44	726	2	0	0
T46	0	2	0	0
T48	0	4	0	0
T50	17880	0	0	0
T55	0	2	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	2	0	0
T155	0	2	0	0
T158	0	4	0	0
T159	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	133670	0	0
T41	50824	28	0	0
T42	15727	55	0	0
T43	871	0	0	0
T44	726	62	0	0
T46	0	57	0	0
T48	0	128	0	0
T50	17880	0	0	0
T55	0	89	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	17	0	0
T155	0	80	0	0
T158	0	120	0	0
T159	0	23	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655135	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	71107	0	0
T41	50824	47	0	0
T42	15727	49	0	0
T43	871	0	0	0
T44	726	38	0	0
T46	0	357	0	0
T48	0	378	0	0
T50	17880	0	0	0
T55	0	18	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	44	0	0
T155	0	400	0	0
T158	0	172	0	0
T159	0	64	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	60	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	0	0	0
T44	726	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6376737	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6379126	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	63	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	0	0	0
T44	726	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	60	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	0	0	0
T44	726	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	60	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	0	0	0
T44	726	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	60	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	0	0	0
T44	726	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T159	0	1	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	71017	0	0
T41	50824	45	0	0
T42	15727	47	0	0
T43	871	0	0	0
T44	726	36	0	0
T46	0	355	0	0
T48	0	375	0	0
T50	17880	0	0	0
T55	0	17	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	43	0	0
T155	0	399	0	0
T158	0	169	0	0
T159	0	62	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	2764	0	0
T13	69834	43	0	0
T14	1004	2	0	0
T15	25490	0	0	0
T16	8605	24	0	0
T26	522	5	0	0
T27	6406	36	0	0
T28	575	0	0	0
T29	525	6	0	0
T30	521	6	0	0
T31	427	3	0	0
T83	0	2	0	0
T112	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	29	0	0
T48	1025	1	0	0
T55	0	1	0	0
T79	16846	0	0	0
T88	23683	0	0	0
T89	5416	0	0	0
T90	5682	0	0	0
T107	743	0	0	0
T108	21172	0	0	0
T135	0	2	0	0
T137	0	1	0	0
T139	0	1	0	0
T152	425	0	0	0
T153	934	0	0	0
T154	405	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0