Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T41,T42
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T41,T42
0	1	Covered	T203
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T41,T46
0	1	Covered	T42,T48,T155
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T41,T46
1	-	Covered	T42,T48,T155

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T41,T42
0	1	Covered	T13,T41,T42
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T41,T42
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T155,T219,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T203
DetectSt	-	-	-	-	0	1	-	Covered	T13,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T48,T155
StableSt	-	-	-	-	-	-	0	Covered	T13,T41,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	129	0	0
CntIncr_A	7322997	68684	0	0
CntNoWrap_A	7322997	6655129	0	0
DetectStDropOut_A	7322997	1	0	0
DetectedOut_A	7322997	5402	0	0
DetectedPulseOut_A	7322997	61	0	0
DisabledIdleSt_A	7322997	6375908	0	0
DisabledNoDetection_A	7322997	6378299	0	0
EnterDebounceSt_A	7322997	67	0	0
EnterDetectSt_A	7322997	62	0	0
EnterStableSt_A	7322997	61	0	0
PulseIsPulse_A	7322997	61	0	0
StayInStableSt	7322997	5318	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	129	0	0
T13	69834	2	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T55	0	2	0	0
T155	0	3	0	0
T158	0	6	0	0
T169	0	4	0	0
T187	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	68684	0	0
T13	69834	92	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	28	0	0
T42	0	76	0	0
T46	0	57	0	0
T48	0	64	0	0
T55	0	12	0	0
T155	0	160	0	0
T158	0	180	0	0
T169	0	92	0	0
T187	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655129	0	0
T13	69834	57768	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1	0	0
T114	1184	0	0	0
T203	945	1	0	0
T220	413	0	0	0
T221	596	0	0	0
T222	18468	0	0	0
T223	28257	0	0	0
T224	695	0	0	0
T225	404	0	0	0
T226	491	0	0	0
T227	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	5402	0	0
T13	69834	364	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	194	0	0
T42	0	1	0	0
T46	0	357	0	0
T48	0	135	0	0
T55	0	127	0	0
T155	0	53	0	0
T158	0	82	0	0
T169	0	86	0	0
T187	0	153	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	61	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	3	0	0
T169	0	2	0	0
T187	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6375908	0	0
T13	69834	57310	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6378299	0	0
T13	69834	57342	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	67	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	2	0	0
T158	0	3	0	0
T169	0	2	0	0
T187	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	62	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	3	0	0
T169	0	2	0	0
T187	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	61	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	3	0	0
T169	0	2	0	0
T187	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	61	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	3	0	0
T169	0	2	0	0
T187	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	5318	0	0
T13	69834	362	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	192	0	0
T46	0	355	0	0
T48	0	134	0	0
T55	0	125	0	0
T73	0	70	0	0
T155	0	52	0	0
T158	0	78	0	0
T169	0	83	0	0
T187	0	150	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	37	0	0
T42	15727	1	0	0
T43	871	0	0	0
T48	1025	1	0	0
T51	238858	0	0	0
T73	0	2	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T131	0	2	0	0
T135	0	2	0	0
T152	425	0	0	0
T153	934	0	0	0
T154	405	0	0	0
T155	0	1	0	0
T158	0	2	0	0
T169	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T44,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T44,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T44,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T19,T44
1	0	Covered	T13,T26,T27
1	1	Covered	T44,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T42,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T42,T43
0	1	Covered	T43,T169,T158
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T42,T43
1	-	Covered	T43,T169,T158

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T44,T42,T43
0	1	Covered	T44,T42,T43
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T42,T43
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T44,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T44,T42,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T44,T42,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T44,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T169,T158
StableSt	-	-	-	-	-	-	0	Covered	T44,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	87	0	0
CntIncr_A	7322997	2499	0	0
CntNoWrap_A	7322997	6655171	0	0
DetectStDropOut_A	7322997	0	0	0
DetectedOut_A	7322997	3017	0	0
DetectedPulseOut_A	7322997	43	0	0
DisabledIdleSt_A	7322997	6636037	0	0
DisabledNoDetection_A	7322997	6638424	0	0
EnterDebounceSt_A	7322997	45	0	0
EnterDetectSt_A	7322997	43	0	0
EnterStableSt_A	7322997	43	0	0
PulseIsPulse_A	7322997	43	0	0
StayInStableSt	7322997	2951	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7322997	6472	0	0
gen_low_level_sva.LowLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	87	0	0
T41	50824	0	0	0
T42	15727	2	0	0
T43	871	4	0	0
T44	726	2	0	0
T45	0	2	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	4	0	0
T133	0	2	0	0
T138	0	4	0	0
T158	0	4	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	2	0	0
T180	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	2499	0	0
T41	50824	0	0	0
T42	15727	76	0	0
T43	871	186	0	0
T44	726	62	0	0
T45	0	35	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	102	0	0
T133	0	68	0	0
T138	0	56	0	0
T158	0	120	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	46	0	0
T180	0	33	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655171	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	3017	0	0
T41	50824	0	0	0
T42	15727	256	0	0
T43	871	83	0	0
T44	726	120	0	0
T45	0	93	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	63	0	0
T133	0	145	0	0
T138	0	139	0	0
T158	0	148	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	34	0	0
T180	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	43	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T45	0	1	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	2	0	0
T133	0	1	0	0
T138	0	2	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	1	0	0
T180	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6636037	0	0
T13	69834	57310	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6638424	0	0
T13	69834	57342	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	45	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T45	0	1	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	2	0	0
T133	0	1	0	0
T138	0	2	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	1	0	0
T180	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	43	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T45	0	1	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	2	0	0
T133	0	1	0	0
T138	0	2	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	1	0	0
T180	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	43	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T45	0	1	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	2	0	0
T133	0	1	0	0
T138	0	2	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	1	0	0
T180	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	43	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T45	0	1	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	2	0	0
T133	0	1	0	0
T138	0	2	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	1	0	0
T180	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	2951	0	0
T41	50824	0	0	0
T42	15727	254	0	0
T43	871	80	0	0
T44	726	118	0	0
T45	0	91	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T131	0	60	0	0
T133	0	144	0	0
T138	0	136	0	0
T158	0	146	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	33	0	0
T180	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6472	0	0
T13	69834	54	0	0
T14	1004	1	0	0
T15	25490	10	0	0
T16	8605	30	0	0
T26	522	5	0	0
T27	6406	45	0	0
T28	575	0	0	0
T29	525	5	0	0
T30	521	6	0	0
T31	427	5	0	0
T112	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	19	0	0
T43	871	1	0	0
T51	238858	0	0	0
T55	20370	0	0	0
T64	11590	0	0	0
T81	639	0	0	0
T106	522	0	0	0
T131	0	1	0	0
T133	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T158	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	729	1	0	0
T228	0	1	0	0
T229	29213	0	0	0
T230	442	0	0	0
T231	407	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T44,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T44,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T44,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T44,T41,T42
1	0	Covered	T13,T26,T27
1	1	Covered	T44,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T42,T43
0	1	Covered	T157
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T42,T43
0	1	Covered	T44,T43,T48
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T42,T43
1	-	Covered	T44,T43,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T44,T42,T43
0	1	Covered	T44,T42,T43
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T44,T42,T43
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T44,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T44,T42,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T44,T42,T43
DetectSt	-	-	-	-	1	-	-	Covered	T157
DetectSt	-	-	-	-	0	1	-	Covered	T44,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T43,T48
StableSt	-	-	-	-	-	-	0	Covered	T44,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	117	0	0
CntIncr_A	7322997	133384	0	0
CntNoWrap_A	7322997	6655141	0	0
DetectStDropOut_A	7322997	1	0	0
DetectedOut_A	7322997	69847	0	0
DetectedPulseOut_A	7322997	56	0	0
DisabledIdleSt_A	7322997	6378097	0	0
DisabledNoDetection_A	7322997	6380489	0	0
EnterDebounceSt_A	7322997	60	0	0
EnterDetectSt_A	7322997	57	0	0
EnterStableSt_A	7322997	56	0	0
PulseIsPulse_A	7322997	56	0	0
StayInStableSt	7322997	69766	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	117	0	0
T41	50824	0	0	0
T42	15727	2	0	0
T43	871	4	0	0
T44	726	3	0	0
T48	0	4	0	0
T50	17880	0	0	0
T55	0	4	0	0
T91	0	2	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	2	0	0
T155	0	6	0	0
T158	0	4	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	133384	0	0
T41	50824	0	0	0
T42	15727	76	0	0
T43	871	186	0	0
T44	726	124	0	0
T48	0	128	0	0
T50	17880	0	0	0
T55	0	99	0	0
T91	0	38	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	17	0	0
T155	0	240	0	0
T158	0	120	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	92	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655141	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1	0	0
T157	931	1	0	0
T171	623	0	0	0
T172	15903	0	0	0
T173	502	0	0	0
T174	420	0	0	0
T175	562	0	0	0
T176	1065	0	0	0
T177	502	0	0	0
T178	514	0	0	0
T202	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	69847	0	0
T41	50824	0	0	0
T42	15727	333	0	0
T43	871	180	0	0
T44	726	18	0	0
T48	0	51	0	0
T50	17880	0	0	0
T55	0	24	0	0
T91	0	3	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	149	0	0
T155	0	124	0	0
T158	0	117	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	145	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	56	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	2	0	0
T91	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	3	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6378097	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6380489	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	60	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	2	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	2	0	0
T91	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	3	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	57	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	2	0	0
T91	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	3	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	56	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	2	0	0
T91	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	3	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	56	0	0
T41	50824	0	0	0
T42	15727	1	0	0
T43	871	2	0	0
T44	726	1	0	0
T48	0	2	0	0
T50	17880	0	0	0
T55	0	2	0	0
T91	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	1	0	0
T155	0	3	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	69766	0	0
T41	50824	0	0	0
T42	15727	331	0	0
T43	871	177	0	0
T44	726	17	0	0
T48	0	48	0	0
T50	17880	0	0	0
T55	0	22	0	0
T91	0	2	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T137	0	147	0	0
T155	0	120	0	0
T158	0	115	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	142	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	30	0	0
T41	50824	0	0	0
T42	15727	0	0	0
T43	871	1	0	0
T44	726	1	0	0
T48	0	1	0	0
T50	17880	0	0	0
T55	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T91	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T155	0	2	0	0
T158	0	2	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T169	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T44,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T44,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T44,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T44,T41
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T44,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T44,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T44,T41
0	1	Covered	T44,T46,T48
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T44,T41
1	-	Covered	T44,T46,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T44,T41
0	1	Covered	T13,T44,T41
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T44,T41
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T44,T41
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T44,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T155,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T44,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T13,T44,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T46,T48
StableSt	-	-	-	-	-	-	0	Covered	T13,T44,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	75	0	0
CntIncr_A	7322997	67221	0	0
CntNoWrap_A	7322997	6655183	0	0
DetectStDropOut_A	7322997	0	0	0
DetectedOut_A	7322997	3428	0	0
DetectedPulseOut_A	7322997	36	0	0
DisabledIdleSt_A	7322997	6377916	0	0
DisabledNoDetection_A	7322997	6380306	0	0
EnterDebounceSt_A	7322997	39	0	0
EnterDetectSt_A	7322997	36	0	0
EnterStableSt_A	7322997	36	0	0
PulseIsPulse_A	7322997	36	0	0
StayInStableSt	7322997	3371	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7322997	6436	0	0
gen_low_level_sva.LowLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	75	0	0
T13	69834	2	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	2	0	0
T44	0	4	0	0
T46	0	2	0	0
T48	0	2	0	0
T55	0	2	0	0
T155	0	3	0	0
T158	0	4	0	0
T163	0	2	0	0
T169	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	67221	0	0
T13	69834	92	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	28	0	0
T44	0	124	0	0
T46	0	57	0	0
T48	0	64	0	0
T55	0	89	0	0
T155	0	160	0	0
T158	0	120	0	0
T163	0	65057	0	0
T169	0	46	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655183	0	0
T13	69834	57768	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	3428	0	0
T13	69834	41	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	48	0	0
T44	0	81	0	0
T46	0	145	0	0
T48	0	371	0	0
T55	0	42	0	0
T155	0	51	0	0
T158	0	175	0	0
T163	0	206	0	0
T169	0	34	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	36	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T163	0	1	0	0
T169	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6377916	0	0
T13	69834	57310	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6380306	0	0
T13	69834	57342	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	39	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	2	0	0
T158	0	2	0	0
T163	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	36	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T163	0	1	0	0
T169	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	36	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T163	0	1	0	0
T169	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	36	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1	0	0
T44	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T55	0	1	0	0
T155	0	1	0	0
T158	0	2	0	0
T163	0	1	0	0
T169	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	3371	0	0
T13	69834	39	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	46	0	0
T44	0	78	0	0
T46	0	144	0	0
T48	0	370	0	0
T55	0	40	0	0
T155	0	50	0	0
T158	0	172	0	0
T163	0	205	0	0
T169	0	33	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6436	0	0
T13	69834	66	0	0
T14	1004	1	0	0
T15	25490	15	0	0
T16	8605	30	0	0
T26	522	4	0	0
T27	6406	39	0	0
T28	575	0	0	0
T29	525	3	0	0
T30	521	6	0	0
T31	427	2	0	0
T112	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	14	0	0
T41	50824	0	0	0
T42	15727	0	0	0
T43	871	0	0	0
T44	726	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T50	17880	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T139	0	1	0	0
T155	0	1	0	0
T158	0	1	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T163	0	1	0	0
T169	0	1	0	0
T197	0	1	0	0
T228	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T19,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T19,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T19,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T41,T42
1	0	Covered	T13,T26,T27
1	1	Covered	T19,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T41,T42
0	1	Covered	T73,T74,T210
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T41,T42
0	1	Covered	T41,T42,T158
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T41,T42
1	-	Covered	T41,T42,T158

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T41,T42
0	1	Covered	T19,T41,T42
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T41,T42
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T75,T73,T232
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T73,T74,T210
DetectSt	-	-	-	-	0	1	-	Covered	T19,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T158
StableSt	-	-	-	-	-	-	0	Covered	T19,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	132	0	0
CntIncr_A	7322997	68819	0	0
CntNoWrap_A	7322997	6655126	0	0
DetectStDropOut_A	7322997	4	0	0
DetectedOut_A	7322997	70913	0	0
DetectedPulseOut_A	7322997	57	0	0
DisabledIdleSt_A	7322997	6375878	0	0
DisabledNoDetection_A	7322997	6378264	0	0
EnterDebounceSt_A	7322997	71	0	0
EnterDetectSt_A	7322997	61	0	0
EnterStableSt_A	7322997	57	0	0
PulseIsPulse_A	7322997	57	0	0
StayInStableSt	7322997	70829	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	132	0	0
T19	63708	2	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	4	0	0
T42	15727	4	0	0
T45	0	2	0	0
T55	0	4	0	0
T73	0	4	0	0
T74	0	4	0	0
T75	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	4	0	0
T159	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	68819	0	0
T19	63708	10	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	82	0	0
T42	15727	131	0	0
T45	0	35	0	0
T55	0	101	0	0
T73	0	144	0	0
T74	0	192	0	0
T75	0	18	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	120	0	0
T159	0	23	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655126	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	4	0	0
T73	799	1	0	0
T74	955	1	0	0
T189	425	0	0	0
T190	793	0	0	0
T191	507	0	0	0
T192	23946	0	0	0
T193	534	0	0	0
T194	496	0	0	0
T196	0	1	0	0
T210	14895	1	0	0
T233	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	70913	0	0
T19	63708	44	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	247	0	0
T42	15727	90	0	0
T45	0	290	0	0
T55	0	209	0	0
T74	0	212	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	86	0	0
T159	0	128	0	0
T163	0	65550	0	0
T193	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	57	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	2	0	0
T42	15727	2	0	0
T45	0	1	0	0
T55	0	2	0	0
T74	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	2	0	0
T159	0	1	0	0
T163	0	1	0	0
T193	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6375878	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6378264	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	71	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	2	0	0
T42	15727	2	0	0
T45	0	1	0	0
T55	0	2	0	0
T73	0	3	0	0
T74	0	2	0	0
T75	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	2	0	0
T159	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	61	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	2	0	0
T42	15727	2	0	0
T45	0	1	0	0
T55	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	2	0	0
T159	0	1	0	0
T193	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	57	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	2	0	0
T42	15727	2	0	0
T45	0	1	0	0
T55	0	2	0	0
T74	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	2	0	0
T159	0	1	0	0
T163	0	1	0	0
T193	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	57	0	0
T19	63708	1	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	2	0	0
T42	15727	2	0	0
T45	0	1	0	0
T55	0	2	0	0
T74	0	1	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	2	0	0
T159	0	1	0	0
T163	0	1	0	0
T193	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	70829	0	0
T19	63708	42	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T41	50824	244	0	0
T42	15727	87	0	0
T45	0	288	0	0
T55	0	205	0	0
T74	0	210	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T158	0	84	0	0
T159	0	126	0	0
T163	0	65549	0	0
T193	0	80	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	29	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	0	0	0
T51	238858	0	0	0
T94	5369	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T131	0	2	0	0
T135	0	1	0	0
T140	0	1	0	0
T158	6466	2	0	0
T163	0	1	0	0
T166	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T234	453	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T41,T42,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T41,T42,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T41,T42,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T19,T41
1	0	Covered	T13,T26,T27
1	1	Covered	T41,T42,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T42,T43
0	1	Covered	T73,T179,T135
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T42,T43
1	-	Covered	T73,T179,T135

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T42,T43
0	1	Covered	T41,T42,T43
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T42,T43
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T42,T43
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T42,T43
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T41,T42,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T73,T179,T135
StableSt	-	-	-	-	-	-	0	Covered	T41,T42,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	79	0	0
CntIncr_A	7322997	67410	0	0
CntNoWrap_A	7322997	6655179	0	0
DetectStDropOut_A	7322997	0	0	0
DetectedOut_A	7322997	68101	0	0
DetectedPulseOut_A	7322997	39	0	0
DisabledIdleSt_A	7322997	6277191	0	0
DisabledNoDetection_A	7322997	6279577	0	0
EnterDebounceSt_A	7322997	40	0	0
EnterDetectSt_A	7322997	39	0	0
EnterStableSt_A	7322997	39	0	0
PulseIsPulse_A	7322997	39	0	0
StayInStableSt	7322997	68038	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7322997	7101	0	0
gen_low_level_sva.LowLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	79	0	0
T41	50824	2	0	0
T42	15727	2	0	0
T43	871	2	0	0
T47	770	2	0	0
T51	238858	0	0	0
T73	0	6	0	0
T77	8850	0	0	0
T102	0	2	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	2	0	0
T163	0	2	0	0
T179	0	6	0	0
T180	0	2	0	0
T198	2370	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	67410	0	0
T41	50824	54	0	0
T42	15727	77	0	0
T43	871	93	0	0
T47	770	76	0	0
T51	238858	0	0	0
T73	0	144	0	0
T77	8850	0	0	0
T102	0	78	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	45	0	0
T163	0	65057	0	0
T179	0	260	0	0
T180	0	33	0	0
T198	2370	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6655179	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	68101	0	0
T41	50824	50	0	0
T42	15727	122	0	0
T43	871	134	0	0
T47	770	119	0	0
T51	238858	0	0	0
T73	0	126	0	0
T77	8850	0	0	0
T102	0	84	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	111	0	0
T163	0	65305	0	0
T179	0	232	0	0
T180	0	42	0	0
T198	2370	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	39	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	1	0	0
T47	770	1	0	0
T51	238858	0	0	0
T73	0	3	0	0
T77	8850	0	0	0
T102	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	1	0	0
T163	0	1	0	0
T179	0	3	0	0
T180	0	1	0	0
T198	2370	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6277191	0	0
T13	69834	57310	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6279577	0	0
T13	69834	57342	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	40	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	1	0	0
T47	770	1	0	0
T51	238858	0	0	0
T73	0	3	0	0
T77	8850	0	0	0
T102	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	1	0	0
T163	0	1	0	0
T179	0	3	0	0
T180	0	1	0	0
T198	2370	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	39	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	1	0	0
T47	770	1	0	0
T51	238858	0	0	0
T73	0	3	0	0
T77	8850	0	0	0
T102	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	1	0	0
T163	0	1	0	0
T179	0	3	0	0
T180	0	1	0	0
T198	2370	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	39	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	1	0	0
T47	770	1	0	0
T51	238858	0	0	0
T73	0	3	0	0
T77	8850	0	0	0
T102	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	1	0	0
T163	0	1	0	0
T179	0	3	0	0
T180	0	1	0	0
T198	2370	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	39	0	0
T41	50824	1	0	0
T42	15727	1	0	0
T43	871	1	0	0
T47	770	1	0	0
T51	238858	0	0	0
T73	0	3	0	0
T77	8850	0	0	0
T102	0	1	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	1	0	0
T163	0	1	0	0
T179	0	3	0	0
T180	0	1	0	0
T198	2370	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	68038	0	0
T41	50824	48	0	0
T42	15727	120	0	0
T43	871	132	0	0
T47	770	117	0	0
T51	238858	0	0	0
T73	0	122	0	0
T77	8850	0	0	0
T102	0	82	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T135	0	110	0	0
T163	0	65303	0	0
T179	0	227	0	0
T180	0	40	0	0
T198	2370	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	7101	0	0
T13	69834	88	0	0
T14	1004	1	0	0
T15	25490	9	0	0
T16	8605	34	0	0
T26	522	4	0	0
T27	6406	38	0	0
T28	575	3	0	0
T29	525	6	0	0
T30	521	5	0	0
T31	427	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	14	0	0
T73	799	2	0	0
T135	0	1	0	0
T140	0	1	0	0
T150	0	1	0	0
T156	0	1	0	0
T165	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T179	30905	1	0	0
T186	0	1	0	0
T233	422	0	0	0
T235	657	0	0	0
T236	687	0	0	0
T237	3097	0	0	0
T238	720	0	0	0
T239	538	0	0	0
T240	445	0	0	0
T241	521	0	0	0