Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T20,T22
1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T22
1	0	Covered	T18,T20,T22
1	1	Covered	T18,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T22
0	1	Covered	T89,T90,T92
1	0	Covered	T77,T93,T99

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T22
0	1	Covered	T18,T20,T22
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T20,T22
1	-	Covered	T18,T20,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T20,T22
0	1	Covered	T18,T20,T22
0	0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T22
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T22
IdleSt	0	-	-	-	-	-	-	Covered	T18,T20,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T242,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T22
DetectSt	-	-	-	-	1	-	-	Covered	T77,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T18,T20,T22
DetectSt	-	-	-	-	0	0	-	Covered	T18,T20,T22
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T22
StableSt	-	-	-	-	-	-	0	Covered	T18,T20,T22
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	2913	0	0
CntIncr_A	7322997	97780	0	0
CntNoWrap_A	7322997	6652345	0	0
DetectStDropOut_A	7322997	494	0	0
DetectedOut_A	7322997	72494	0	0
DetectedPulseOut_A	7322997	774	0	0
DisabledIdleSt_A	7322997	6229289	0	0
DisabledNoDetection_A	7322997	6231535	0	0
EnterDebounceSt_A	7322997	1486	0	0
EnterDetectSt_A	7322997	1427	0	0
EnterStableSt_A	7322997	774	0	0
PulseIsPulse_A	7322997	774	0	0
StayInStableSt	7322997	71617	0	0
gen_high_event_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	670	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	2913	0	0
T18	15803	48	0	0
T19	63708	0	0	0
T20	25712	32	0	0
T21	19919	0	0	0
T22	18114	36	0	0
T49	0	20	0	0
T50	0	10	0	0
T67	0	52	0	0
T68	0	34	0	0
T77	0	10	0	0
T78	0	34	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	54	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	97780	0	0
T18	15803	1416	0	0
T19	63708	0	0	0
T20	25712	912	0	0
T21	19919	0	0	0
T22	18114	648	0	0
T49	0	890	0	0
T50	0	415	0	0
T67	0	858	0	0
T68	0	1139	0	0
T77	0	296	0	0
T78	0	1054	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	1515	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6652345	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	494	0	0
T57	21418	0	0	0
T79	16846	0	0	0
T89	5416	27	0	0
T90	5682	11	0	0
T92	0	23	0	0
T93	0	8	0	0
T94	0	31	0	0
T95	0	12	0	0
T97	0	6	0	0
T99	0	20	0	0
T100	0	11	0	0
T101	0	26	0	0
T107	743	0	0	0
T108	21172	0	0	0
T109	35269	0	0	0
T110	2049	0	0	0
T244	1063	0	0	0
T245	18885	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	72494	0	0
T18	15803	1815	0	0
T19	63708	0	0	0
T20	25712	2800	0	0
T21	19919	0	0	0
T22	18114	4233	0	0
T49	0	1476	0	0
T50	0	536	0	0
T67	0	2818	0	0
T68	0	1487	0	0
T78	0	2104	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	1590	0	0
T246	0	1264	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	774	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	18	0	0
T49	0	10	0	0
T50	0	5	0	0
T67	0	26	0	0
T68	0	17	0	0
T78	0	17	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	11	0	0
T246	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6229289	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6231535	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1486	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	18	0	0
T49	0	10	0	0
T50	0	5	0	0
T67	0	26	0	0
T68	0	17	0	0
T77	0	5	0	0
T78	0	17	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	27	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1427	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	18	0	0
T49	0	10	0	0
T50	0	5	0	0
T67	0	26	0	0
T68	0	17	0	0
T77	0	5	0	0
T78	0	17	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	27	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	774	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	18	0	0
T49	0	10	0	0
T50	0	5	0	0
T67	0	26	0	0
T68	0	17	0	0
T78	0	17	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	11	0	0
T246	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	774	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	18	0	0
T49	0	10	0	0
T50	0	5	0	0
T67	0	26	0	0
T68	0	17	0	0
T78	0	17	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	11	0	0
T246	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	71617	0	0
T18	15803	1787	0	0
T19	63708	0	0	0
T20	25712	2779	0	0
T21	19919	0	0	0
T22	18114	4212	0	0
T49	0	1466	0	0
T50	0	528	0	0
T67	0	2789	0	0
T68	0	1470	0	0
T78	0	2084	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	1577	0	0
T246	0	1234	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	670	0	0
T18	15803	20	0	0
T19	63708	0	0	0
T20	25712	11	0	0
T21	19919	0	0	0
T22	18114	15	0	0
T49	0	10	0	0
T50	0	2	0	0
T67	0	23	0	0
T68	0	17	0	0
T78	0	14	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	9	0	0
T246	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T15,T16
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T15,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T15,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T27,T15
1	1	Covered	T13,T15,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T19,T21,T88
1	0	Covered	T62,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
1	0	Covered	T64,T62,T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T17
1	-	Covered	T13,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T16
0	1	Covered	T13,T15,T16
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T16
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T16,T17
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T16
DetectSt	-	-	-	-	1	-	-	Covered	T19,T21,T88
DetectSt	-	-	-	-	0	1	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T13,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T13,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	1081	0	0
CntIncr_A	7322997	58682	0	0
CntNoWrap_A	7322997	6654177	0	0
DetectStDropOut_A	7322997	58	0	0
DetectedOut_A	7322997	18644	0	0
DetectedPulseOut_A	7322997	429	0	0
DisabledIdleSt_A	7322997	6242131	0	0
DisabledNoDetection_A	7322997	6243727	0	0
EnterDebounceSt_A	7322997	592	0	0
EnterDetectSt_A	7322997	491	0	0
EnterStableSt_A	7322997	429	0	0
PulseIsPulse_A	7322997	429	0	0
StayInStableSt	7322997	18188	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	397	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1081	0	0
T13	69834	32	0	0
T14	1004	0	0	0
T15	25490	6	0	0
T16	8605	1	0	0
T17	0	27	0	0
T18	0	8	0	0
T19	0	5	0	0
T20	0	8	0	0
T21	0	4	0	0
T22	0	6	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T49	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	58682	0	0
T13	69834	1676	0	0
T14	1004	0	0	0
T15	25490	396	0	0
T16	8605	20	0	0
T17	0	1227	0	0
T18	0	268	0	0
T19	0	272	0	0
T20	0	268	0	0
T21	0	246	0	0
T22	0	126	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T49	0	465	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6654177	0	0
T13	69834	57738	0	0
T14	1004	603	0	0
T15	25490	25018	0	0
T16	8605	2427	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	58	0	0
T19	63708	2	0	0
T20	25712	0	0	0
T21	19919	2	0	0
T55	0	3	0	0
T57	0	2	0	0
T79	16846	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T88	23683	5	0	0
T89	5416	0	0	0
T90	5682	0	0	0
T91	0	6	0	0
T96	0	1	0	0
T98	0	5	0	0
T102	0	1	0	0
T103	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	18644	0	0
T13	69834	604	0	0
T14	1004	0	0	0
T15	25490	34	0	0
T16	8605	0	0	0
T17	0	977	0	0
T18	0	209	0	0
T20	0	995	0	0
T22	0	819	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	236	0	0
T49	0	226	0	0
T50	0	212	0	0
T105	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	429	0	0
T13	69834	14	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	12	0	0
T18	0	4	0	0
T20	0	4	0	0
T22	0	3	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	6	0	0
T49	0	5	0	0
T50	0	3	0	0
T105	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6242131	0	0
T13	69834	50750	0	0
T14	1004	603	0	0
T15	25490	20148	0	0
T16	8605	2395	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6243727	0	0
T13	69834	50777	0	0
T14	1004	604	0	0
T15	25490	20148	0	0
T16	8605	2409	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	592	0	0
T13	69834	18	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	1	0	0
T17	0	15	0	0
T18	0	4	0	0
T19	0	3	0	0
T20	0	4	0	0
T21	0	2	0	0
T22	0	3	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T49	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	491	0	0
T13	69834	14	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	12	0	0
T18	0	4	0	0
T19	0	2	0	0
T20	0	4	0	0
T21	0	2	0	0
T22	0	3	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T49	0	5	0	0
T50	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	429	0	0
T13	69834	14	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	12	0	0
T18	0	4	0	0
T20	0	4	0	0
T22	0	3	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	6	0	0
T49	0	5	0	0
T50	0	3	0	0
T105	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	429	0	0
T13	69834	14	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	12	0	0
T18	0	4	0	0
T20	0	4	0	0
T22	0	3	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	6	0	0
T49	0	5	0	0
T50	0	3	0	0
T105	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	18188	0	0
T13	69834	590	0	0
T14	1004	0	0	0
T15	25490	31	0	0
T16	8605	0	0	0
T17	0	965	0	0
T18	0	203	0	0
T20	0	991	0	0
T22	0	813	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	230	0	0
T49	0	221	0	0
T50	0	209	0	0
T105	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	397	0	0
T13	69834	14	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	12	0	0
T18	0	2	0	0
T20	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	6	0	0
T49	0	5	0	0
T50	0	3	0	0
T67	0	2	0	0
T105	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T20,T22
1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T22
1	0	Covered	T18,T20,T22
1	1	Covered	T18,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T22
0	1	Covered	T67,T89,T90
1	0	Covered	T22,T67,T93

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T49
0	1	Covered	T18,T20,T49
1	0	Covered	T22,T247

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T20,T22
1	-	Covered	T18,T20,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T20,T22
0	1	Covered	T18,T20,T22
0	0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T22
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T22
IdleSt	0	-	-	-	-	-	-	Covered	T18,T20,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T242,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T22
DetectSt	-	-	-	-	1	-	-	Covered	T22,T67,T89
DetectSt	-	-	-	-	0	1	-	Covered	T18,T20,T22
DetectSt	-	-	-	-	0	0	-	Covered	T18,T20,T22
StableSt	-	-	-	-	-	-	1	Covered	T18,T20,T22
StableSt	-	-	-	-	-	-	0	Covered	T18,T20,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	2701	0	0
CntIncr_A	7322997	94664	0	0
CntNoWrap_A	7322997	6652557	0	0
DetectStDropOut_A	7322997	317	0	0
DetectedOut_A	7322997	76722	0	0
DetectedPulseOut_A	7322997	823	0	0
DisabledIdleSt_A	7322997	6224566	0	0
DisabledNoDetection_A	7322997	6226800	0	0
EnterDebounceSt_A	7322997	1377	0	0
EnterDetectSt_A	7322997	1324	0	0
EnterStableSt_A	7322997	823	0	0
PulseIsPulse_A	7322997	823	0	0
StayInStableSt	7322997	75784	0	0
gen_high_event_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	694	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	2701	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	26	0	0
T49	0	18	0	0
T50	0	28	0	0
T67	0	28	0	0
T68	0	40	0	0
T77	0	44	0	0
T78	0	64	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	94664	0	0
T18	15803	732	0	0
T19	63708	0	0	0
T20	25712	544	0	0
T21	19919	0	0	0
T22	18114	735	0	0
T49	0	540	0	0
T50	0	1176	0	0
T67	0	733	0	0
T68	0	1680	0	0
T77	0	880	0	0
T78	0	1792	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	331	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6652557	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	317	0	0
T52	845	0	0	0
T67	16620	4	0	0
T78	16369	0	0	0
T89	0	6	0	0
T90	0	10	0	0
T92	0	7	0	0
T94	0	21	0	0
T95	0	9	0	0
T97	0	30	0	0
T99	0	12	0	0
T100	0	3	0	0
T101	0	11	0	0
T248	402	0	0	0
T249	447	0	0	0
T250	407	0	0	0
T251	112318	0	0	0
T252	508	0	0	0
T253	13522	0	0	0
T254	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	76722	0	0
T18	15803	707	0	0
T19	63708	0	0	0
T20	25712	987	0	0
T21	19919	0	0	0
T22	18114	2	0	0
T49	0	1863	0	0
T50	0	2071	0	0
T68	0	1957	0	0
T77	0	1661	0	0
T78	0	2421	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	985	0	0
T246	0	1454	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	823	0	0
T18	15803	12	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	2	0	0
T49	0	9	0	0
T50	0	14	0	0
T68	0	20	0	0
T77	0	22	0	0
T78	0	32	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	8	0	0
T246	0	27	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6224566	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6226800	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1377	0	0
T18	15803	12	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	13	0	0
T49	0	9	0	0
T50	0	14	0	0
T67	0	14	0	0
T68	0	20	0	0
T77	0	22	0	0
T78	0	32	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1324	0	0
T18	15803	12	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	13	0	0
T49	0	9	0	0
T50	0	14	0	0
T67	0	14	0	0
T68	0	20	0	0
T77	0	22	0	0
T78	0	32	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	823	0	0
T18	15803	12	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	2	0	0
T49	0	9	0	0
T50	0	14	0	0
T68	0	20	0	0
T77	0	22	0	0
T78	0	32	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	8	0	0
T246	0	27	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	823	0	0
T18	15803	12	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	2	0	0
T49	0	9	0	0
T50	0	14	0	0
T68	0	20	0	0
T77	0	22	0	0
T78	0	32	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T245	0	8	0	0
T246	0	27	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	75784	0	0
T18	15803	693	0	0
T19	63708	0	0	0
T20	25712	977	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	1854	0	0
T50	0	2054	0	0
T68	0	1937	0	0
T77	0	1638	0	0
T78	0	2386	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T118	0	1120	0	0
T245	0	975	0	0
T246	0	1420	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	694	0	0
T18	15803	10	0	0
T19	63708	0	0	0
T20	25712	6	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	9	0	0
T50	0	11	0	0
T68	0	20	0	0
T77	0	21	0	0
T78	0	29	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T118	0	3	0	0
T245	0	6	0	0
T246	0	20	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T15,T17
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T27,T15
1	1	Covered	T13,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T60,T108,T109
1	0	Covered	T62,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
1	0	Covered	T49,T62

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T17
1	-	Covered	T13,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T21,T50
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T60,T108,T109
DetectSt	-	-	-	-	0	1	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T13,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T13,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	971	0	0
CntIncr_A	7322997	53237	0	0
CntNoWrap_A	7322997	6654287	0	0
DetectStDropOut_A	7322997	61	0	0
DetectedOut_A	7322997	20249	0	0
DetectedPulseOut_A	7322997	388	0	0
DisabledIdleSt_A	7322997	6265886	0	0
DisabledNoDetection_A	7322997	6267576	0	0
EnterDebounceSt_A	7322997	519	0	0
EnterDetectSt_A	7322997	453	0	0
EnterStableSt_A	7322997	388	0	0
PulseIsPulse_A	7322997	388	0	0
StayInStableSt	7322997	19824	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	348	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	971	0	0
T13	69834	2	0	0
T14	1004	0	0	0
T15	25490	6	0	0
T16	8605	0	0	0
T17	0	7	0	0
T18	0	4	0	0
T19	0	2	0	0
T20	0	4	0	0
T21	0	11	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	19	0	0
T49	0	10	0	0
T50	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	53237	0	0
T13	69834	174	0	0
T14	1004	0	0	0
T15	25490	399	0	0
T16	8605	0	0	0
T17	0	550	0	0
T18	0	88	0	0
T19	0	79	0	0
T20	0	124	0	0
T21	0	599	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1271	0	0
T49	0	400	0	0
T50	0	290	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6654287	0	0
T13	69834	57768	0	0
T14	1004	603	0	0
T15	25490	25018	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	61	0	0
T57	21418	0	0	0
T60	10067	3	0	0
T68	10505	0	0	0
T98	0	9	0	0
T102	0	2	0	0
T108	21172	7	0	0
T109	35269	2	0	0
T110	2049	0	0	0
T117	0	5	0	0
T179	0	5	0	0
T181	411	0	0	0
T182	422	0	0	0
T183	488	0	0	0
T222	0	15	0	0
T244	1063	0	0	0
T255	0	3	0	0
T256	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	20249	0	0
T13	69834	8	0	0
T14	1004	0	0	0
T15	25490	31	0	0
T16	8605	0	0	0
T17	0	18	0	0
T18	0	152	0	0
T19	0	47	0	0
T20	0	507	0	0
T21	0	99	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	525	0	0
T49	0	429	0	0
T50	0	390	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	388	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	5	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	9	0	0
T49	0	5	0	0
T50	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6265886	0	0
T13	69834	55483	0	0
T14	1004	603	0	0
T15	25490	20148	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6267576	0	0
T13	69834	55515	0	0
T14	1004	604	0	0
T15	25490	20148	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	519	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	4	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	6	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	10	0	0
T49	0	5	0	0
T50	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	453	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	5	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	9	0	0
T49	0	5	0	0
T50	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	388	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	5	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	9	0	0
T49	0	5	0	0
T50	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	388	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	5	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	9	0	0
T49	0	5	0	0
T50	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	19824	0	0
T13	69834	7	0	0
T14	1004	0	0	0
T15	25490	28	0	0
T16	8605	0	0	0
T17	0	15	0	0
T18	0	150	0	0
T19	0	46	0	0
T20	0	505	0	0
T21	0	94	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	516	0	0
T49	0	424	0	0
T50	0	385	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	348	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	3	0	0
T16	8605	0	0	0
T17	0	3	0	0
T18	0	2	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	0	5	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	9	0	0
T49	0	4	0	0
T50	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T20,T22
1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T22
1	0	Covered	T18,T20,T22
1	1	Covered	T18,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T22
0	1	Covered	T68,T77,T89
1	0	Covered	T20,T68,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T18,T22,T49
0	1	Covered	T18,T22,T49
1	0	Covered	T69,T70,T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T18,T22,T49
1	-	Covered	T18,T22,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T20,T22
0	1	Covered	T18,T20,T22
0	0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T22
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T22
IdleSt	0	-	-	-	-	-	-	Covered	T18,T20,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T242,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T22
DetectSt	-	-	-	-	1	-	-	Covered	T20,T68,T77
DetectSt	-	-	-	-	0	1	-	Covered	T18,T22,T49
DetectSt	-	-	-	-	0	0	-	Covered	T18,T20,T22
StableSt	-	-	-	-	-	-	1	Covered	T18,T22,T49
StableSt	-	-	-	-	-	-	0	Covered	T18,T22,T49
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	3034	0	0
CntIncr_A	7322997	105822	0	0
CntNoWrap_A	7322997	6652224	0	0
DetectStDropOut_A	7322997	533	0	0
DetectedOut_A	7322997	43917	0	0
DetectedPulseOut_A	7322997	684	0	0
DisabledIdleSt_A	7322997	6250694	0	0
DisabledNoDetection_A	7322997	6252976	0	0
EnterDebounceSt_A	7322997	1549	0	0
EnterDetectSt_A	7322997	1485	0	0
EnterStableSt_A	7322997	684	0	0
PulseIsPulse_A	7322997	684	0	0
StayInStableSt	7322997	43166	0	0
gen_high_event_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	608	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	3034	0	0
T18	15803	4	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	50	0	0
T49	0	8	0	0
T50	0	12	0	0
T67	0	16	0	0
T68	0	50	0	0
T77	0	26	0	0
T78	0	28	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	105822	0	0
T18	15803	110	0	0
T19	63708	0	0	0
T20	25712	546	0	0
T21	19919	0	0	0
T22	18114	1075	0	0
T49	0	304	0	0
T50	0	426	0	0
T67	0	320	0	0
T68	0	3296	0	0
T77	0	770	0	0
T78	0	938	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	724	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6652224	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	533	0	0
T48	1025	0	0	0
T64	0	5	0	0
T68	10505	2	0	0
T77	8850	7	0	0
T88	23683	0	0	0
T89	5416	13	0	0
T90	0	18	0	0
T92	0	12	0	0
T93	0	5	0	0
T94	0	20	0	0
T95	0	11	0	0
T97	0	10	0	0
T152	425	0	0	0
T153	934	0	0	0
T154	405	0	0	0
T199	733	0	0	0
T200	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	43917	0	0
T18	15803	159	0	0
T19	63708	0	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T22	18114	1047	0	0
T49	0	117	0	0
T50	0	219	0	0
T67	0	1433	0	0
T78	0	192	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T118	0	1449	0	0
T245	0	2668	0	0
T246	0	1405	0	0
T258	0	1449	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	684	0	0
T18	15803	2	0	0
T19	63708	0	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T22	18114	25	0	0
T49	0	4	0	0
T50	0	6	0	0
T67	0	8	0	0
T78	0	14	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T118	0	11	0	0
T245	0	24	0	0
T246	0	24	0	0
T258	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6250694	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6252976	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1549	0	0
T18	15803	2	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	25	0	0
T49	0	4	0	0
T50	0	6	0	0
T67	0	8	0	0
T68	0	25	0	0
T77	0	13	0	0
T78	0	14	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1485	0	0
T18	15803	2	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	25	0	0
T49	0	4	0	0
T50	0	6	0	0
T67	0	8	0	0
T68	0	25	0	0
T77	0	13	0	0
T78	0	14	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	684	0	0
T18	15803	2	0	0
T19	63708	0	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T22	18114	25	0	0
T49	0	4	0	0
T50	0	6	0	0
T67	0	8	0	0
T78	0	14	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T118	0	11	0	0
T245	0	24	0	0
T246	0	24	0	0
T258	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	684	0	0
T18	15803	2	0	0
T19	63708	0	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T22	18114	25	0	0
T49	0	4	0	0
T50	0	6	0	0
T67	0	8	0	0
T78	0	14	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T118	0	11	0	0
T245	0	24	0	0
T246	0	24	0	0
T258	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	43166	0	0
T18	15803	157	0	0
T19	63708	0	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T22	18114	1021	0	0
T49	0	113	0	0
T50	0	213	0	0
T67	0	1424	0	0
T78	0	177	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T118	0	1430	0	0
T245	0	2642	0	0
T246	0	1376	0	0
T258	0	1432	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	608	0	0
T18	15803	2	0	0
T19	63708	0	0	0
T20	25712	0	0	0
T21	19919	0	0	0
T22	18114	24	0	0
T49	0	4	0	0
T50	0	6	0	0
T67	0	7	0	0
T78	0	13	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T118	0	3	0	0
T245	0	22	0	0
T246	0	19	0	0
T258	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T15,T17
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T15,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T27,T15
1	1	Covered	T13,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T60,T259,T117
1	0	Covered	T62,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T15,T17
1	-	Covered	T13,T15,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T15,T17
0	1	Covered	T13,T15,T17
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T15,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T17,T21
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T60,T259,T117
DetectSt	-	-	-	-	0	1	-	Covered	T13,T15,T17
DetectSt	-	-	-	-	0	0	-	Covered	T13,T15,T17
StableSt	-	-	-	-	-	-	1	Covered	T13,T15,T17
StableSt	-	-	-	-	-	-	0	Covered	T13,T15,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	795	0	0
CntIncr_A	7322997	44717	0	0
CntNoWrap_A	7322997	6654463	0	0
DetectStDropOut_A	7322997	39	0	0
DetectedOut_A	7322997	14032	0	0
DetectedPulseOut_A	7322997	329	0	0
DisabledIdleSt_A	7322997	6280132	0	0
DisabledNoDetection_A	7322997	6281831	0	0
EnterDebounceSt_A	7322997	423	0	0
EnterDetectSt_A	7322997	372	0	0
EnterStableSt_A	7322997	329	0	0
PulseIsPulse_A	7322997	329	0	0
StayInStableSt	7322997	13672	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	297	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	795	0	0
T13	69834	12	0	0
T14	1004	0	0	0
T15	25490	14	0	0
T16	8605	0	0	0
T17	0	5	0	0
T18	0	2	0	0
T21	0	11	0	0
T22	0	2	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	14	0	0
T42	0	1	0	0
T67	0	2	0	0
T105	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	44717	0	0
T13	69834	850	0	0
T14	1004	0	0	0
T15	25490	651	0	0
T16	8605	0	0	0
T17	0	355	0	0
T18	0	59	0	0
T21	0	669	0	0
T22	0	35	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	665	0	0
T42	0	93	0	0
T67	0	41	0	0
T105	0	280	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6654463	0	0
T13	69834	57758	0	0
T14	1004	603	0	0
T15	25490	25010	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	39	0	0
T60	10067	2	0	0
T68	10505	0	0	0
T117	0	3	0	0
T145	0	1	0	0
T169	729	0	0	0
T181	411	0	0	0
T182	422	0	0	0
T183	488	0	0	0
T229	29213	0	0	0
T230	442	0	0	0
T255	0	3	0	0
T259	11859	1	0	0
T260	0	2	0	0
T261	0	2	0	0
T262	0	4	0	0
T263	0	1	0	0
T264	0	8	0	0
T265	1801	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	14032	0	0
T13	69834	27	0	0
T14	1004	0	0	0
T15	25490	356	0	0
T16	8605	0	0	0
T17	0	48	0	0
T18	0	61	0	0
T21	0	29	0	0
T22	0	283	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	401	0	0
T67	0	170	0	0
T78	0	57	0	0
T105	0	108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	329	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	7	0	0
T16	8605	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	7	0	0
T67	0	1	0	0
T78	0	1	0	0
T105	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6280132	0	0
T13	69834	50922	0	0
T14	1004	603	0	0
T15	25490	20148	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6281831	0	0
T13	69834	50952	0	0
T14	1004	604	0	0
T15	25490	20148	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	423	0	0
T13	69834	7	0	0
T14	1004	0	0	0
T15	25490	7	0	0
T16	8605	0	0	0
T17	0	3	0	0
T18	0	1	0	0
T21	0	6	0	0
T22	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	7	0	0
T42	0	1	0	0
T67	0	1	0	0
T105	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	372	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	7	0	0
T16	8605	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	7	0	0
T67	0	1	0	0
T78	0	1	0	0
T105	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	329	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	7	0	0
T16	8605	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	7	0	0
T67	0	1	0	0
T78	0	1	0	0
T105	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	329	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	7	0	0
T16	8605	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	7	0	0
T67	0	1	0	0
T78	0	1	0	0
T105	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	13672	0	0
T13	69834	22	0	0
T14	1004	0	0	0
T15	25490	349	0	0
T16	8605	0	0	0
T17	0	46	0	0
T18	0	60	0	0
T21	0	24	0	0
T22	0	282	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	394	0	0
T67	0	168	0	0
T78	0	56	0	0
T105	0	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	297	0	0
T13	69834	5	0	0
T14	1004	0	0	0
T15	25490	7	0	0
T16	8605	0	0	0
T17	0	2	0	0
T18	0	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	7	0	0
T78	0	1	0	0
T105	0	2	0	0
T253	0	2	0	0