Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T20,T22
1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T18,T20,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T20,T22
1	0	Covered	T18,T20,T22
1	1	Covered	T18,T20,T22

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T20,T22
0	1	Covered	T22,T89,T90
1	0	Covered	T18,T22,T77

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T20,T49,T50
0	1	Covered	T20,T49,T50
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T20,T49,T50
1	-	Covered	T20,T49,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T20,T22
0	1	Covered	T18,T20,T22
0	0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T20,T22
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T20,T22
IdleSt	0	-	-	-	-	-	-	Covered	T18,T20,T22
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T20,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T76,T242,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T20,T22
DetectSt	-	-	-	-	1	-	-	Covered	T18,T22,T77
DetectSt	-	-	-	-	0	1	-	Covered	T20,T49,T50
DetectSt	-	-	-	-	0	0	-	Covered	T18,T20,T22
StableSt	-	-	-	-	-	-	1	Covered	T20,T49,T50
StableSt	-	-	-	-	-	-	0	Covered	T20,T49,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	3150	0	0
CntIncr_A	7322997	102556	0	0
CntNoWrap_A	7322997	6652108	0	0
DetectStDropOut_A	7322997	461	0	0
DetectedOut_A	7322997	72989	0	0
DetectedPulseOut_A	7322997	882	0	0
DisabledIdleSt_A	7322997	6233878	0	0
DisabledNoDetection_A	7322997	6236128	0	0
EnterDebounceSt_A	7322997	1601	0	0
EnterDetectSt_A	7322997	1549	0	0
EnterStableSt_A	7322997	882	0	0
PulseIsPulse_A	7322997	882	0	0
StayInStableSt	7322997	72009	0	0
gen_high_event_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	784	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	3150	0	0
T18	15803	48	0	0
T19	63708	0	0	0
T20	25712	16	0	0
T21	19919	0	0	0
T22	18114	28	0	0
T49	0	10	0	0
T50	0	28	0	0
T67	0	30	0	0
T68	0	52	0	0
T77	0	26	0	0
T78	0	58	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	102556	0	0
T18	15803	1585	0	0
T19	63708	0	0	0
T20	25712	408	0	0
T21	19919	0	0	0
T22	18114	792	0	0
T49	0	475	0	0
T50	0	784	0	0
T67	0	450	0	0
T68	0	1976	0	0
T77	0	777	0	0
T78	0	1624	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	1400	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6652108	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	461	0	0
T22	18114	3	0	0
T41	50824	0	0	0
T44	726	0	0	0
T49	9268	0	0	0
T50	17880	0	0	0
T87	509	0	0	0
T89	0	25	0	0
T90	0	26	0	0
T92	0	21	0	0
T94	0	12	0	0
T95	0	23	0	0
T97	0	7	0	0
T100	0	19	0	0
T101	0	9	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T266	0	5	0	0
T267	1330	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	72989	0	0
T20	25712	3035	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	52	0	0
T50	17880	1277	0	0
T64	0	821	0	0
T67	0	1489	0	0
T68	0	1633	0	0
T78	0	1605	0	0
T85	502	0	0	0
T86	513	0	0	0
T93	0	1386	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T245	0	2724	0	0
T246	0	629	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	882	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	5	0	0
T50	17880	14	0	0
T64	0	11	0	0
T67	0	15	0	0
T68	0	26	0	0
T78	0	29	0	0
T85	502	0	0	0
T86	513	0	0	0
T93	0	26	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T245	0	25	0	0
T246	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6233878	0	0
T13	69834	57770	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6236128	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1601	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	14	0	0
T49	0	5	0	0
T50	0	14	0	0
T67	0	15	0	0
T68	0	26	0	0
T77	0	13	0	0
T78	0	29	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	1549	0	0
T18	15803	24	0	0
T19	63708	0	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T22	18114	14	0	0
T49	0	5	0	0
T50	0	14	0	0
T67	0	15	0	0
T68	0	26	0	0
T77	0	13	0	0
T78	0	29	0	0
T83	426	0	0	0
T84	491	0	0	0
T85	502	0	0	0
T86	513	0	0	0
T87	509	0	0	0
T89	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	882	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	5	0	0
T50	17880	14	0	0
T64	0	11	0	0
T67	0	15	0	0
T68	0	26	0	0
T78	0	29	0	0
T85	502	0	0	0
T86	513	0	0	0
T93	0	26	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T245	0	25	0	0
T246	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	882	0	0
T20	25712	8	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	5	0	0
T50	17880	14	0	0
T64	0	11	0	0
T67	0	15	0	0
T68	0	26	0	0
T78	0	29	0	0
T85	502	0	0	0
T86	513	0	0	0
T93	0	26	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T245	0	25	0	0
T246	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	72009	0	0
T20	25712	3025	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	47	0	0
T50	17880	1259	0	0
T64	0	808	0	0
T67	0	1472	0	0
T68	0	1607	0	0
T78	0	1574	0	0
T85	502	0	0	0
T86	513	0	0	0
T93	0	1360	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T245	0	2696	0	0
T246	0	615	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	784	0	0
T20	25712	6	0	0
T21	19919	0	0	0
T44	726	0	0	0
T49	9268	5	0	0
T50	17880	10	0	0
T64	0	9	0	0
T67	0	13	0	0
T68	0	26	0	0
T78	0	27	0	0
T85	502	0	0	0
T86	513	0	0	0
T93	0	26	0	0
T160	503	0	0	0
T161	507	0	0	0
T162	504	0	0	0
T245	0	22	0	0
T246	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T13,T15,T17
1	Covered	T13,T26,T27

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T26,T27
1	1	Covered	T13,T26,T27

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T17,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T13,T26,T27	VC_COV_UNR
1	Covered	T13,T17,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T13,T26,T27
1	Covered	T13,T20,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T27,T15
1	1	Covered	T13,T17,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T20,T21
0	1	Covered	T41,T55,T268
1	0	Covered	T61,T62,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T20,T21
0	1	Covered	T13,T20,T21
1	0	Covered	T63

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T20,T21
1	-	Covered	T13,T20,T21

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1
DetectSt	168	Covered	T1
IdleSt	163	Covered	T1
StableSt	191	Covered	T1

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1
DebounceSt->IdleSt	163	Covered	T1
DetectSt->IdleSt	186	Covered	T1
DetectSt->StableSt	191	Covered	T1
IdleSt->DebounceSt	148	Covered	T1
StableSt->IdleSt	206	Covered	T1

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T17,T20
0	1	Covered	T13,T17,T20
0	0	Excluded	T13,T26,T27	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T20,T21
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T17,T20
IdleSt	0	-	-	-	-	-	-	Covered	T13,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T62,T63
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T20,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T17,T41,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T17,T20
DetectSt	-	-	-	-	1	-	-	Covered	T41,T55,T268
DetectSt	-	-	-	-	0	1	-	Covered	T13,T20,T21
DetectSt	-	-	-	-	0	0	-	Covered	T13,T20,T21
StableSt	-	-	-	-	-	-	1	Covered	T13,T20,T21
StableSt	-	-	-	-	-	-	0	Covered	T13,T20,T21
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T13,T26,T27

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7322997	832	0	0
CntIncr_A	7322997	46778	0	0
CntNoWrap_A	7322997	6654426	0	0
DetectStDropOut_A	7322997	61	0	0
DetectedOut_A	7322997	14848	0	0
DetectedPulseOut_A	7322997	325	0	0
DisabledIdleSt_A	7322997	6242855	0	0
DisabledNoDetection_A	7322997	6244511	0	0
EnterDebounceSt_A	7322997	443	0	0
EnterDetectSt_A	7322997	391	0	0
EnterStableSt_A	7322997	325	0	0
PulseIsPulse_A	7322997	325	0	0
StayInStableSt	7322997	14488	0	0
gen_high_level_sva.HighLevelEvent_A	7322997	6657698	0	0
gen_not_sticky_sva.StableStDropOut_A	7322997	288	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	832	0	0
T13	69834	2	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T17	0	1	0	0
T20	0	4	0	0
T21	0	8	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	15	0	0
T42	0	1	0	0
T50	0	2	0	0
T67	0	4	0	0
T78	0	4	0	0
T105	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	46778	0	0
T13	69834	130	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T17	0	73	0	0
T20	0	138	0	0
T21	0	448	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	1124	0	0
T42	0	93	0	0
T50	0	62	0	0
T67	0	104	0	0
T78	0	140	0	0
T105	0	564	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6654426	0	0
T13	69834	57768	0	0
T14	1004	603	0	0
T15	25490	25024	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	61	0	0
T41	50824	4	0	0
T42	15727	0	0	0
T43	871	0	0	0
T51	238858	0	0	0
T55	20370	4	0	0
T61	0	4	0	0
T64	11590	0	0	0
T81	639	0	0	0
T104	203555	0	0	0
T105	32333	0	0	0
T106	522	0	0	0
T139	0	9	0	0
T262	0	4	0	0
T264	0	9	0	0
T268	0	2	0	0
T269	0	1	0	0
T270	0	2	0	0
T271	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	14848	0	0
T13	69834	15	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T20	0	492	0	0
T21	0	47	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	10	0	0
T50	0	66	0	0
T60	0	66	0	0
T67	0	323	0	0
T78	0	148	0	0
T105	0	16	0	0
T272	0	98	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	325	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	2	0	0
T50	0	1	0	0
T60	0	2	0	0
T67	0	2	0	0
T78	0	2	0	0
T105	0	3	0	0
T272	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6242855	0	0
T13	69834	50922	0	0
T14	1004	603	0	0
T15	25490	20148	0	0
T16	8605	2428	0	0
T26	522	121	0	0
T27	6406	899	0	0
T28	575	174	0	0
T29	525	124	0	0
T30	521	120	0	0
T31	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6244511	0	0
T13	69834	50952	0	0
T14	1004	604	0	0
T15	25490	20148	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	443	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T17	0	1	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	9	0	0
T42	0	1	0	0
T50	0	1	0	0
T67	0	2	0	0
T78	0	2	0	0
T105	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	391	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	6	0	0
T50	0	1	0	0
T60	0	2	0	0
T67	0	2	0	0
T78	0	2	0	0
T105	0	3	0	0
T272	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	325	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	2	0	0
T50	0	1	0	0
T60	0	2	0	0
T67	0	2	0	0
T78	0	2	0	0
T105	0	3	0	0
T272	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	325	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	2	0	0
T50	0	1	0	0
T60	0	2	0	0
T67	0	2	0	0
T78	0	2	0	0
T105	0	3	0	0
T272	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	14488	0	0
T13	69834	14	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T20	0	490	0	0
T21	0	43	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	8	0	0
T50	0	65	0	0
T60	0	64	0	0
T67	0	321	0	0
T78	0	146	0	0
T105	0	13	0	0
T272	0	96	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	6657698	0	0
T13	69834	57803	0	0
T14	1004	604	0	0
T15	25490	25034	0	0
T16	8605	2443	0	0
T26	522	122	0	0
T27	6406	915	0	0
T28	575	175	0	0
T29	525	125	0	0
T30	521	121	0	0
T31	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7322997	288	0	0
T13	69834	1	0	0
T14	1004	0	0	0
T15	25490	0	0	0
T16	8605	0	0	0
T20	0	2	0	0
T21	0	4	0	0
T26	522	0	0	0
T27	6406	0	0	0
T28	575	0	0	0
T29	525	0	0	0
T30	521	0	0	0
T31	427	0	0	0
T41	0	2	0	0
T50	0	1	0	0
T60	0	2	0	0
T67	0	2	0	0
T78	0	2	0	0
T105	0	3	0	0
T272	0	2	0	0