Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.34	100.00	96.72	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1394268916	11915	0	0
auto_block_debounce_ctl_rd_A	1394268916	1975	0	0
auto_block_out_ctl_rd_A	1394268916	2501	0	0
com_det_ctl_0_rd_A	1394268916	3976	0	0
com_det_ctl_1_rd_A	1394268916	4133	0	0
com_det_ctl_2_rd_A	1394268916	4201	0	0
com_det_ctl_3_rd_A	1394268916	4176	0	0
com_out_ctl_0_rd_A	1394268916	4775	0	0
com_out_ctl_1_rd_A	1394268916	4701	0	0
com_out_ctl_2_rd_A	1394268916	4504	0	0
com_out_ctl_3_rd_A	1394268916	4706	0	0
com_pre_det_ctl_0_rd_A	1394268916	1481	0	0
com_pre_det_ctl_1_rd_A	1394268916	1387	0	0
com_pre_det_ctl_2_rd_A	1394268916	1428	0	0
com_pre_det_ctl_3_rd_A	1394268916	1565	0	0
com_pre_sel_ctl_0_rd_A	1394268916	4995	0	0
com_pre_sel_ctl_1_rd_A	1394268916	5091	0	0
com_pre_sel_ctl_2_rd_A	1394268916	5192	0	0
com_pre_sel_ctl_3_rd_A	1394268916	4885	0	0
com_sel_ctl_0_rd_A	1394268916	4953	0	0
com_sel_ctl_1_rd_A	1394268916	4661	0	0
com_sel_ctl_2_rd_A	1394268916	5005	0	0
com_sel_ctl_3_rd_A	1394268916	5055	0	0
ec_rst_ctl_rd_A	1394268916	2726	0	0
intr_enable_rd_A	1394268916	2102	0	0
key_intr_ctl_rd_A	1394268916	4462	0	0
key_intr_debounce_ctl_rd_A	1394268916	1371	0	0
key_invert_ctl_rd_A	1394268916	5163	0	0
pin_allowed_ctl_rd_A	1394268916	6131	0	0
pin_out_ctl_rd_A	1394268916	4416	0	0
pin_out_value_rd_A	1394268916	4467	0	0
regwen_rd_A	1394268916	1619	0	0
ulp_ac_debounce_ctl_rd_A	1394268916	1406	0	0
ulp_ctl_rd_A	1394268916	1587	0	0
ulp_lid_debounce_ctl_rd_A	1394268916	1521	0	0
ulp_pwrb_debounce_ctl_rd_A	1394268916	1573	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	11915	0	0
T1	53006	7	0	0
T2	728643	0	0	0
T3	111531	4	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	2	0	0
T9	213101	4	0	0
T11	0	5	0	0
T12	0	5	0	0
T23	228433	0	0	0
T24	101921	5	0	0
T25	95240	0	0	0
T39	0	1	0	0
T291	0	5	0	0
T292	0	2	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1975	0	0
T1	53006	23	0	0
T2	728643	0	0	0
T3	111531	42	0	0
T4	0	2	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	7	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	79	0	0
T33	0	338	0	0
T277	0	18	0	0
T292	0	4	0	0
T293	0	2	0	0
T294	0	8	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	2501	0	0
T1	53006	10	0	0
T2	728643	0	0	0
T3	111531	68	0	0
T4	0	31	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	8	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	54	0	0
T33	0	298	0	0
T277	0	8	0	0
T292	0	4	0	0
T293	0	3	0	0
T294	0	17	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	3976	0	0
T1	53006	12	0	0
T2	728643	0	0	0
T3	111531	24	0	0
T4	0	8	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	27	0	0
T33	0	330	0	0
T277	0	13	0	0
T292	0	7	0	0
T293	0	2	0	0
T294	0	4	0	0
T295	0	13	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4133	0	0
T1	53006	9	0	0
T2	728643	0	0	0
T3	111531	32	0	0
T4	0	11	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	9	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	24	0	0
T33	0	304	0	0
T277	0	16	0	0
T292	0	1	0	0
T293	0	3	0	0
T294	0	8	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4201	0	0
T1	53006	24	0	0
T2	728643	0	0	0
T3	111531	36	0	0
T4	0	9	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	6	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	16	0	0
T33	0	305	0	0
T277	0	11	0	0
T279	0	15	0	0
T293	0	12	0	0
T294	0	5	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4176	0	0
T1	53006	10	0	0
T2	728643	0	0	0
T3	111531	41	0	0
T4	0	7	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	44	0	0
T33	0	309	0	0
T277	0	23	0	0
T292	0	3	0	0
T293	0	9	0	0
T294	0	2	0	0
T295	0	4	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4775	0	0
T1	53006	18	0	0
T2	728643	0	0	0
T3	111531	125	0	0
T4	0	23	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	4	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	46	0	0
T33	0	339	0	0
T277	0	4	0	0
T292	0	9	0	0
T293	0	6	0	0
T294	0	13	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4701	0	0
T1	53006	23	0	0
T2	728643	0	0	0
T3	111531	73	0	0
T4	0	9	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	1	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	59	0	0
T33	0	297	0	0
T277	0	17	0	0
T292	0	8	0	0
T293	0	9	0	0
T294	0	13	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4504	0	0
T1	53006	18	0	0
T2	728643	0	0	0
T3	111531	69	0	0
T4	0	16	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	10	0	0
T33	0	279	0	0
T277	0	13	0	0
T279	0	11	0	0
T292	0	9	0	0
T293	0	10	0	0
T295	0	30	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4706	0	0
T1	53006	12	0	0
T2	728643	0	0	0
T3	111531	65	0	0
T4	0	27	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	3	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	41	0	0
T33	0	284	0	0
T277	0	8	0	0
T293	0	4	0	0
T294	0	18	0	0
T295	0	24	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1481	0	0
T1	53006	18	0	0
T2	728643	0	0	0
T3	111531	42	0	0
T4	0	4	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	6	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	76	0	0
T33	0	314	0	0
T277	0	10	0	0
T292	0	3	0	0
T293	0	10	0	0
T294	0	3	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1387	0	0
T1	53006	29	0	0
T2	728643	0	0	0
T3	111531	33	0	0
T4	0	10	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	28	0	0
T33	0	293	0	0
T277	0	14	0	0
T293	0	4	0	0
T294	0	7	0	0
T295	0	7	0	0
T296	0	80	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1428	0	0
T1	53006	8	0	0
T2	728643	0	0	0
T3	111531	28	0	0
T4	0	7	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	3	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	47	0	0
T33	0	303	0	0
T277	0	10	0	0
T292	0	7	0	0
T293	0	7	0	0
T294	0	5	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1565	0	0
T1	53006	17	0	0
T2	728643	0	0	0
T3	111531	23	0	0
T4	0	7	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	46	0	0
T33	0	338	0	0
T277	0	14	0	0
T279	0	4	0	0
T292	0	8	0	0
T293	0	5	0	0
T294	0	6	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4995	0	0
T1	53006	15	0	0
T2	728643	0	0	0
T3	111531	67	0	0
T4	0	17	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	1	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	12	0	0
T33	0	295	0	0
T277	0	14	0	0
T293	0	7	0	0
T294	0	13	0	0
T295	0	16	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	5091	0	0
T1	53006	30	0	0
T2	728643	0	0	0
T3	111531	89	0	0
T4	0	5	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	14	0	0
T33	0	324	0	0
T277	0	22	0	0
T292	0	15	0	0
T293	0	7	0	0
T294	0	4	0	0
T295	0	32	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	5192	0	0
T1	53006	18	0	0
T2	728643	0	0	0
T3	111531	94	0	0
T4	0	8	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	2	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	38	0	0
T33	0	313	0	0
T277	0	19	0	0
T279	0	9	0	0
T293	0	15	0	0
T294	0	22	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4885	0	0
T1	53006	19	0	0
T2	728643	0	0	0
T3	111531	162	0	0
T4	0	19	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	1	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	33	0	0
T33	0	309	0	0
T279	0	10	0	0
T292	0	9	0	0
T293	0	13	0	0
T294	0	3	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4953	0	0
T1	53006	18	0	0
T2	728643	0	0	0
T3	111531	72	0	0
T4	0	16	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	43	0	0
T33	0	316	0	0
T292	0	3	0	0
T293	0	8	0	0
T294	0	11	0	0
T295	0	38	0	0
T296	0	292	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4661	0	0
T1	53006	2	0	0
T2	728643	0	0	0
T3	111531	58	0	0
T4	0	38	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	5	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	52	0	0
T33	0	316	0	0
T277	0	4	0	0
T292	0	2	0	0
T293	0	4	0	0
T294	0	19	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	5005	0	0
T1	53006	12	0	0
T2	728643	0	0	0
T3	111531	73	0	0
T4	0	11	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	47	0	0
T33	0	344	0	0
T277	0	11	0	0
T279	0	5	0	0
T292	0	18	0	0
T293	0	15	0	0
T294	0	14	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	5055	0	0
T1	53006	19	0	0
T2	728643	0	0	0
T3	111531	78	0	0
T4	0	27	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	1	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	12	0	0
T33	0	303	0	0
T277	0	4	0	0
T292	0	11	0	0
T293	0	4	0	0
T294	0	5	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	2726	0	0
T1	53006	9	0	0
T2	728643	0	0	0
T3	111531	28	0	0
T4	0	8	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	9	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	77	0	0
T33	0	328	0	0
T277	0	4	0	0
T292	0	8	0	0
T293	0	8	0	0
T294	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	2102	0	0
T2	728643	0	0	0
T3	111531	26	0	0
T4	0	6	0	0
T6	25268	18	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T10	201197	0	0	0
T23	228433	234	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	51	0	0
T33	0	345	0	0
T277	0	7	0	0
T292	0	2	0	0
T293	0	16	0	0
T294	0	5	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4462	0	0
T1	53006	26	0	0
T2	728643	0	0	0
T3	111531	397	0	0
T4	0	115	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	23	0	0
T33	0	337	0	0
T277	0	26	0	0
T292	0	9	0	0
T293	0	14	0	0
T294	0	34	0	0
T295	0	96	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1371	0	0
T1	53006	8	0	0
T2	728643	0	0	0
T3	111531	37	0	0
T4	0	13	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	49	0	0
T33	0	326	0	0
T277	0	18	0	0
T279	0	8	0	0
T292	0	7	0	0
T293	0	16	0	0
T294	0	2	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	5163	0	0
T1	53006	23	0	0
T2	728643	0	0	0
T3	111531	238	0	0
T4	0	11	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	4	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	40	0	0
T33	0	336	0	0
T277	0	20	0	0
T292	0	10	0	0
T293	0	3	0	0
T295	0	59	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	6131	0	0
T1	53006	10	0	0
T2	728643	0	0	0
T3	111531	273	0	0
T4	0	13	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	9	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	47	0	0
T33	0	313	0	0
T277	0	9	0	0
T279	0	13	0	0
T293	0	4	0	0
T295	0	136	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4416	0	0
T1	53006	18	0	0
T2	728643	0	0	0
T3	111531	161	0	0
T4	0	39	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	39	0	0
T33	0	316	0	0
T277	0	29	0	0
T279	0	1	0	0
T292	0	8	0	0
T293	0	12	0	0
T294	0	3	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	4467	0	0
T1	53006	21	0	0
T2	728643	0	0	0
T3	111531	147	0	0
T4	0	59	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	12	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	20	0	0
T33	0	289	0	0
T277	0	24	0	0
T279	0	1	0	0
T293	0	10	0	0
T294	0	9	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1619	0	0
T1	53006	19	0	0
T2	728643	0	0	0
T3	111531	47	0	0
T4	0	5	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	222	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	86	0	0
T33	0	290	0	0
T277	0	19	0	0
T292	0	6	0	0
T293	0	5	0	0
T294	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1406	0	0
T1	53006	24	0	0
T2	728643	0	0	0
T3	111531	33	0	0
T4	0	4	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	1	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	62	0	0
T33	0	255	0	0
T277	0	12	0	0
T279	0	5	0	0
T292	0	17	0	0
T293	0	11	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1587	0	0
T1	53006	11	0	0
T2	728643	0	0	0
T3	111531	25	0	0
T4	0	4	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	23	0	0
T33	0	358	0	0
T277	0	10	0	0
T292	0	4	0	0
T293	0	11	0	0
T294	0	6	0	0
T295	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1521	0	0
T1	53006	19	0	0
T2	728643	0	0	0
T3	111531	32	0	0
T4	0	7	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	59	0	0
T33	0	283	0	0
T277	0	7	0	0
T279	0	4	0	0
T292	0	7	0	0
T293	0	2	0	0
T295	0	7	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1394268916	1573	0	0
T1	53006	17	0	0
T2	728643	0	0	0
T3	111531	42	0	0
T4	0	8	0	0
T6	25268	0	0	0
T7	194913	0	0	0
T8	415376	0	0	0
T9	213101	0	0	0
T23	228433	0	0	0
T24	101921	0	0	0
T25	95240	0	0	0
T32	0	42	0	0
T33	0	347	0	0
T277	0	11	0	0
T279	0	1	0	0
T292	0	3	0	0
T293	0	3	0	0
T294	0	8	0	0