| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.54 | 98.96 | 96.49 | 100.00 | 97.44 | 98.33 | 99.72 | 91.87 |
| T763 | /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1924814361 | Jan 21 12:30:03 PM PST 24 | Jan 21 12:30:07 PM PST 24 | 2483490807 ps | ||
| T764 | /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.155931333 | Jan 21 12:30:10 PM PST 24 | Jan 21 12:30:20 PM PST 24 | 3179803761 ps | ||
| T765 | /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2003337381 | Jan 21 12:30:07 PM PST 24 | Jan 21 12:30:11 PM PST 24 | 2633795219 ps | ||
| T766 | /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.632003194 | Jan 21 12:29:22 PM PST 24 | Jan 21 12:29:30 PM PST 24 | 2511309417 ps | ||
| T767 | /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1112993253 | Jan 21 12:27:59 PM PST 24 | Jan 21 12:28:11 PM PST 24 | 3266132739 ps | ||
| T768 | /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1919417525 | Jan 21 12:27:16 PM PST 24 | Jan 21 12:27:20 PM PST 24 | 4228512285 ps | ||
| T769 | /workspace/coverage/default/0.sysrst_ctrl_alert_test.1837152115 | Jan 21 12:26:40 PM PST 24 | Jan 21 12:26:43 PM PST 24 | 2071945972 ps | ||
| T770 | /workspace/coverage/default/17.sysrst_ctrl_stress_all.4176947169 | Jan 21 12:28:00 PM PST 24 | Jan 21 12:28:04 PM PST 24 | 13949890229 ps | ||
| T771 | /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1834732191 | Jan 21 12:30:17 PM PST 24 | Jan 21 12:30:51 PM PST 24 | 50810262504 ps | ||
| T772 | /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.920818078 | Jan 21 12:29:32 PM PST 24 | Jan 21 12:29:42 PM PST 24 | 3413309177 ps | ||
| T773 | /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2592102492 | Jan 21 12:28:17 PM PST 24 | Jan 21 12:28:19 PM PST 24 | 3456359164 ps | ||
| T774 | /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1309743511 | Jan 21 12:27:59 PM PST 24 | Jan 21 12:28:04 PM PST 24 | 4359892558 ps | ||
| T366 | /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3835027957 | Jan 21 12:28:55 PM PST 24 | Jan 21 12:30:12 PM PST 24 | 290851050393 ps | ||
| T775 | /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1963790166 | Jan 21 12:31:31 PM PST 24 | Jan 21 12:32:23 PM PST 24 | 70368871971 ps | ||
| T776 | /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.4164938975 | Jan 21 12:31:38 PM PST 24 | Jan 21 12:33:46 PM PST 24 | 47350556267 ps | ||
| T777 | /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.4217669672 | Jan 21 12:28:00 PM PST 24 | Jan 21 12:28:03 PM PST 24 | 4326763544 ps | ||
| T778 | /workspace/coverage/default/47.sysrst_ctrl_alert_test.3366374844 | Jan 21 12:31:11 PM PST 24 | Jan 21 12:31:14 PM PST 24 | 2038821422 ps | ||
| T779 | /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3671523079 | Jan 21 12:29:51 PM PST 24 | Jan 21 12:29:58 PM PST 24 | 3013316284 ps | ||
| T780 | /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.924857263 | Jan 21 12:29:55 PM PST 24 | Jan 21 12:31:28 PM PST 24 | 33290848164 ps | ||
| T334 | /workspace/coverage/default/20.sysrst_ctrl_stress_all.3507168993 | Jan 21 12:28:42 PM PST 24 | Jan 21 12:36:30 PM PST 24 | 172670211497 ps | ||
| T781 | /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.735819888 | Jan 21 12:31:16 PM PST 24 | Jan 21 12:31:20 PM PST 24 | 3040188286 ps | ||
| T782 | /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.547706287 | Jan 21 12:28:37 PM PST 24 | Jan 21 12:28:39 PM PST 24 | 2627717736 ps | ||
| T783 | /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2679646568 | Jan 21 12:30:11 PM PST 24 | Jan 21 12:30:20 PM PST 24 | 2610869899 ps | ||
| T183 | /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1081951964 | Jan 21 12:29:41 PM PST 24 | Jan 21 12:30:43 PM PST 24 | 21329581820 ps | ||
| T784 | /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.420302785 | Jan 21 12:28:19 PM PST 24 | Jan 21 12:28:26 PM PST 24 | 2187641536 ps | ||
| T785 | /workspace/coverage/default/24.sysrst_ctrl_smoke.1197027318 | Jan 21 12:28:59 PM PST 24 | Jan 21 12:29:08 PM PST 24 | 2108851719 ps | ||
| T786 | /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1750628722 | Jan 21 12:28:21 PM PST 24 | Jan 21 12:28:23 PM PST 24 | 3047109803 ps | ||
| T787 | /workspace/coverage/default/15.sysrst_ctrl_combo_detect.268598317 | Jan 21 12:28:11 PM PST 24 | Jan 21 12:29:18 PM PST 24 | 100453055523 ps | ||
| T788 | /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3503126994 | Jan 21 12:30:13 PM PST 24 | Jan 21 12:30:18 PM PST 24 | 2517576436 ps | ||
| T789 | /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1229783938 | Jan 21 12:30:27 PM PST 24 | Jan 21 12:31:01 PM PST 24 | 66693934802 ps | ||
| T279 | /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.359492163 | Jan 21 12:30:11 PM PST 24 | Jan 21 12:30:59 PM PST 24 | 37588688190 ps | ||
| T790 | /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3972290686 | Jan 21 12:28:59 PM PST 24 | Jan 21 12:37:10 PM PST 24 | 197197930310 ps | ||
| T791 | /workspace/coverage/default/22.sysrst_ctrl_stress_all.2848036921 | Jan 21 12:29:04 PM PST 24 | Jan 21 12:29:37 PM PST 24 | 9130659873 ps | ||
| T792 | /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2134528933 | Jan 21 12:28:59 PM PST 24 | Jan 21 12:29:30 PM PST 24 | 42768652657 ps | ||
| T793 | /workspace/coverage/default/15.sysrst_ctrl_edge_detect.744784807 | Jan 21 12:28:07 PM PST 24 | Jan 21 12:29:32 PM PST 24 | 192862123887 ps | ||
| T794 | /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2723969895 | Jan 21 12:26:52 PM PST 24 | Jan 21 12:26:55 PM PST 24 | 2324982476 ps | ||
| T795 | /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3524922395 | Jan 21 12:27:42 PM PST 24 | Jan 21 12:27:48 PM PST 24 | 2613541817 ps | ||
| T796 | /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2618309478 | Jan 21 12:28:51 PM PST 24 | Jan 21 12:28:57 PM PST 24 | 2447357483 ps | ||
| T265 | /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1393249293 | Jan 21 12:30:51 PM PST 24 | Jan 21 12:31:55 PM PST 24 | 99894349449 ps | ||
| T797 | /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.822612704 | Jan 21 01:22:05 PM PST 24 | Jan 21 01:22:12 PM PST 24 | 3935142946 ps | ||
| T798 | /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3039127943 | Jan 21 12:31:10 PM PST 24 | Jan 21 12:31:23 PM PST 24 | 26790279342 ps | ||
| T799 | /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.895665450 | Jan 21 12:28:59 PM PST 24 | Jan 21 12:29:03 PM PST 24 | 2625418621 ps | ||
| T800 | /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3094142642 | Jan 21 12:31:19 PM PST 24 | Jan 21 12:31:21 PM PST 24 | 2122914737 ps | ||
| T801 | /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3100709085 | Jan 21 12:28:41 PM PST 24 | Jan 21 12:28:49 PM PST 24 | 4272091663 ps | ||
| T802 | /workspace/coverage/default/2.sysrst_ctrl_smoke.4190815109 | Jan 21 12:26:59 PM PST 24 | Jan 21 12:27:08 PM PST 24 | 2112864577 ps | ||
| T803 | /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2969919249 | Jan 21 12:31:35 PM PST 24 | Jan 21 12:32:48 PM PST 24 | 27084821437 ps | ||
| T804 | /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2560406073 | Jan 21 12:28:58 PM PST 24 | Jan 21 12:29:01 PM PST 24 | 2536405704 ps | ||
| T805 | /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1699646432 | Jan 21 12:30:34 PM PST 24 | Jan 21 01:03:52 PM PST 24 | 768978753799 ps | ||
| T806 | /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2310725044 | Jan 21 12:30:03 PM PST 24 | Jan 21 12:30:10 PM PST 24 | 2515467190 ps | ||
| T807 | /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1283437529 | Jan 21 12:27:59 PM PST 24 | Jan 21 12:28:04 PM PST 24 | 2469045147 ps | ||
| T808 | /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3899810263 | Jan 21 12:31:06 PM PST 24 | Jan 21 12:31:08 PM PST 24 | 7009723842 ps | ||
| T325 | /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1406356764 | Jan 21 12:27:16 PM PST 24 | Jan 21 12:28:18 PM PST 24 | 128710858530 ps | ||
| T809 | /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3945093890 | Jan 21 12:29:47 PM PST 24 | Jan 21 12:30:53 PM PST 24 | 49383756885 ps | ||
| T810 | /workspace/coverage/default/34.sysrst_ctrl_combo_detect.3909406231 | Jan 21 12:30:01 PM PST 24 | Jan 21 12:30:33 PM PST 24 | 117918750443 ps | ||
| T811 | /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.140497441 | Jan 21 12:26:45 PM PST 24 | Jan 21 12:26:50 PM PST 24 | 2365439071 ps | ||
| T812 | /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.956424432 | Jan 21 12:30:50 PM PST 24 | Jan 21 12:30:58 PM PST 24 | 2610105432 ps | ||
| T813 | /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1182382456 | Jan 21 12:29:50 PM PST 24 | Jan 21 12:29:56 PM PST 24 | 10620689202 ps | ||
| T814 | /workspace/coverage/default/44.sysrst_ctrl_edge_detect.525303041 | Jan 21 12:30:54 PM PST 24 | Jan 21 12:31:02 PM PST 24 | 4783378467 ps | ||
| T815 | /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.4186362928 | Jan 21 12:31:13 PM PST 24 | Jan 21 12:31:17 PM PST 24 | 3843337937 ps | ||
| T816 | /workspace/coverage/default/25.sysrst_ctrl_alert_test.2642127122 | Jan 21 12:29:08 PM PST 24 | Jan 21 12:29:20 PM PST 24 | 2010389408 ps | ||
| T817 | /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2018728899 | Jan 21 12:30:28 PM PST 24 | Jan 21 12:30:37 PM PST 24 | 3106439147 ps | ||
| T818 | /workspace/coverage/default/15.sysrst_ctrl_smoke.1789049554 | Jan 21 12:28:06 PM PST 24 | Jan 21 12:28:10 PM PST 24 | 2116975395 ps | ||
| T819 | /workspace/coverage/default/37.sysrst_ctrl_alert_test.1734615477 | Jan 21 12:30:16 PM PST 24 | Jan 21 12:30:21 PM PST 24 | 2016094939 ps | ||
| T820 | /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.364442036 | Jan 21 12:28:30 PM PST 24 | Jan 21 12:28:37 PM PST 24 | 2513012215 ps | ||
| T821 | /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2902154288 | Jan 21 12:29:02 PM PST 24 | Jan 21 12:30:49 PM PST 24 | 40681445833 ps | ||
| T261 | /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1897141051 | Jan 21 12:27:15 PM PST 24 | Jan 21 12:27:49 PM PST 24 | 47842405824 ps | ||
| T822 | /workspace/coverage/default/16.sysrst_ctrl_alert_test.1676617348 | Jan 21 12:28:17 PM PST 24 | Jan 21 12:28:23 PM PST 24 | 2009975289 ps | ||
| T823 | /workspace/coverage/default/18.sysrst_ctrl_alert_test.53829479 | Jan 21 12:28:19 PM PST 24 | Jan 21 12:28:22 PM PST 24 | 2037359375 ps | ||
| T824 | /workspace/coverage/default/44.sysrst_ctrl_alert_test.2866030401 | Jan 21 12:30:50 PM PST 24 | Jan 21 12:30:57 PM PST 24 | 2010355847 ps | ||
| T825 | /workspace/coverage/default/36.sysrst_ctrl_alert_test.1137208767 | Jan 21 12:30:21 PM PST 24 | Jan 21 12:30:28 PM PST 24 | 2009743020 ps | ||
| T826 | /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1093773092 | Jan 21 12:29:47 PM PST 24 | Jan 21 12:29:54 PM PST 24 | 3581328201 ps | ||
| T827 | /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2633433825 | Jan 21 12:30:10 PM PST 24 | Jan 21 12:30:20 PM PST 24 | 3055593043 ps | ||
| T828 | /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.167049457 | Jan 21 12:31:37 PM PST 24 | Jan 21 12:32:21 PM PST 24 | 64682144824 ps | ||
| T829 | /workspace/coverage/default/12.sysrst_ctrl_combo_detect.4189440338 | Jan 21 12:27:55 PM PST 24 | Jan 21 12:33:13 PM PST 24 | 128183588403 ps | ||
| T830 | /workspace/coverage/default/31.sysrst_ctrl_combo_detect.175474637 | Jan 21 12:29:40 PM PST 24 | Jan 21 12:39:05 PM PST 24 | 205333123342 ps | ||
| T831 | /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2816667475 | Jan 21 12:30:16 PM PST 24 | Jan 21 12:30:27 PM PST 24 | 3804410450 ps | ||
| T832 | /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.4259069382 | Jan 21 12:29:50 PM PST 24 | Jan 21 12:29:56 PM PST 24 | 3525666054 ps | ||
| T833 | /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1184220314 | Jan 21 12:29:34 PM PST 24 | Jan 21 12:29:38 PM PST 24 | 2478685692 ps | ||
| T834 | /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1673729045 | Jan 21 12:31:02 PM PST 24 | Jan 21 12:31:13 PM PST 24 | 3817529415 ps | ||
| T338 | /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.482183645 | Jan 21 12:28:11 PM PST 24 | Jan 21 12:30:58 PM PST 24 | 66764240809 ps | ||
| T835 | /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4025629296 | Jan 21 12:31:33 PM PST 24 | Jan 21 12:34:12 PM PST 24 | 61061472985 ps | ||
| T836 | /workspace/coverage/default/38.sysrst_ctrl_stress_all.140478505 | Jan 21 12:30:11 PM PST 24 | Jan 21 12:31:47 PM PST 24 | 97063215491 ps | ||
| T837 | /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1653405541 | Jan 21 12:32:00 PM PST 24 | Jan 21 12:35:18 PM PST 24 | 65347839327 ps | ||
| T838 | /workspace/coverage/default/17.sysrst_ctrl_alert_test.2164011256 | Jan 21 12:28:11 PM PST 24 | Jan 21 12:28:18 PM PST 24 | 2015078097 ps | ||
| T839 | /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.116366034 | Jan 21 12:27:11 PM PST 24 | Jan 21 12:27:16 PM PST 24 | 2996227372 ps | ||
| T840 | /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2494497004 | Jan 21 12:27:10 PM PST 24 | Jan 21 12:27:18 PM PST 24 | 3427966859 ps | ||
| T841 | /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3945867082 | Jan 21 12:28:17 PM PST 24 | Jan 21 12:28:19 PM PST 24 | 2473707298 ps | ||
| T842 | /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.623977672 | Jan 21 12:27:03 PM PST 24 | Jan 21 12:27:11 PM PST 24 | 10070437130 ps | ||
| T843 | /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.78321185 | Jan 21 12:28:26 PM PST 24 | Jan 21 12:28:44 PM PST 24 | 26100548793 ps | ||
| T149 | /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2813753839 | Jan 21 12:26:49 PM PST 24 | Jan 21 12:29:18 PM PST 24 | 855850709549 ps | ||
| T844 | /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1801969783 | Jan 21 12:27:16 PM PST 24 | Jan 21 12:28:06 PM PST 24 | 82884694859 ps | ||
| T845 | /workspace/coverage/default/0.sysrst_ctrl_stress_all.3045826001 | Jan 21 12:26:45 PM PST 24 | Jan 21 12:27:24 PM PST 24 | 14613249837 ps | ||
| T846 | /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1089050004 | Jan 21 12:27:56 PM PST 24 | Jan 21 12:28:04 PM PST 24 | 2474123434 ps | ||
| T847 | /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1354058126 | Jan 21 12:27:02 PM PST 24 | Jan 21 12:27:11 PM PST 24 | 4951859072 ps | ||
| T848 | /workspace/coverage/default/3.sysrst_ctrl_alert_test.2678009094 | Jan 21 12:27:07 PM PST 24 | Jan 21 12:27:14 PM PST 24 | 2026043300 ps | ||
| T849 | /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3660608678 | Jan 21 12:30:03 PM PST 24 | Jan 21 12:30:08 PM PST 24 | 2250026877 ps | ||
| T850 | /workspace/coverage/default/27.sysrst_ctrl_stress_all.3883401246 | Jan 21 12:29:17 PM PST 24 | Jan 21 12:29:35 PM PST 24 | 8341776536 ps | ||
| T851 | /workspace/coverage/default/4.sysrst_ctrl_smoke.1279857827 | Jan 21 12:27:08 PM PST 24 | Jan 21 12:27:17 PM PST 24 | 2111627081 ps | ||
| T852 | /workspace/coverage/default/21.sysrst_ctrl_alert_test.826219150 | Jan 21 12:28:46 PM PST 24 | Jan 21 12:28:52 PM PST 24 | 2011477782 ps | ||
| T853 | /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.830181223 | Jan 21 12:30:20 PM PST 24 | Jan 21 12:30:23 PM PST 24 | 2632850465 ps | ||
| T854 | /workspace/coverage/default/25.sysrst_ctrl_stress_all.2822483300 | Jan 21 12:29:02 PM PST 24 | Jan 21 12:29:13 PM PST 24 | 8778861373 ps | ||
| T855 | /workspace/coverage/default/32.sysrst_ctrl_stress_all.1336182000 | Jan 21 12:30:03 PM PST 24 | Jan 21 12:30:15 PM PST 24 | 16685419966 ps | ||
| T856 | /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2464959569 | Jan 21 12:27:52 PM PST 24 | Jan 21 12:27:57 PM PST 24 | 2522373559 ps | ||
| T857 | /workspace/coverage/default/11.sysrst_ctrl_alert_test.3106585681 | Jan 21 12:27:47 PM PST 24 | Jan 21 12:27:49 PM PST 24 | 2027945645 ps | ||
| T858 | /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.56752930 | Jan 21 12:28:08 PM PST 24 | Jan 21 12:28:10 PM PST 24 | 2555493626 ps | ||
| T859 | /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1830945255 | Jan 21 12:26:58 PM PST 24 | Jan 21 12:27:00 PM PST 24 | 2692174495 ps | ||
| T860 | /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2488481229 | Jan 21 12:26:57 PM PST 24 | Jan 21 12:27:02 PM PST 24 | 2415877633 ps | ||
| T861 | /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.990664490 | Jan 21 12:29:09 PM PST 24 | Jan 21 12:29:19 PM PST 24 | 2027909372 ps | ||
| T862 | /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1872646854 | Jan 21 12:27:16 PM PST 24 | Jan 21 12:32:21 PM PST 24 | 854207687976 ps | ||
| T275 | /workspace/coverage/default/38.sysrst_ctrl_combo_detect.996620009 | Jan 21 12:30:13 PM PST 24 | Jan 21 12:31:35 PM PST 24 | 36371013894 ps | ||
| T863 | /workspace/coverage/default/17.sysrst_ctrl_smoke.681399350 | Jan 21 12:28:11 PM PST 24 | Jan 21 12:28:13 PM PST 24 | 2234124123 ps | ||
| T864 | /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.838734510 | Jan 21 12:28:52 PM PST 24 | Jan 21 12:28:57 PM PST 24 | 3709985217 ps | ||
| T150 | /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.3599320205 | Jan 21 12:29:08 PM PST 24 | Jan 21 12:29:23 PM PST 24 | 5961407953 ps | ||
| T865 | /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1612591731 | Jan 21 12:27:16 PM PST 24 | Jan 21 12:27:21 PM PST 24 | 2515348391 ps | ||
| T866 | /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.151800640 | Jan 21 12:27:24 PM PST 24 | Jan 21 12:27:30 PM PST 24 | 2017320460 ps | ||
| T867 | /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.220243775 | Jan 21 12:30:59 PM PST 24 | Jan 21 12:31:08 PM PST 24 | 2512779600 ps | ||
| T868 | /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.463539868 | Jan 21 12:26:49 PM PST 24 | Jan 21 12:26:54 PM PST 24 | 2489793937 ps | ||
| T869 | /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2606059069 | Jan 21 12:24:52 PM PST 24 | Jan 21 12:26:49 PM PST 24 | 42438180416 ps | ||
| T870 | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.577503300 | Jan 21 12:24:23 PM PST 24 | Jan 21 12:24:28 PM PST 24 | 2141537472 ps | ||
| T871 | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3886733371 | Jan 21 12:55:53 PM PST 24 | Jan 21 12:56:49 PM PST 24 | 22249463700 ps | ||
| T872 | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1242154578 | Jan 21 12:23:22 PM PST 24 | Jan 21 12:24:01 PM PST 24 | 10145900278 ps | ||
| T873 | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3249756559 | Jan 21 12:24:40 PM PST 24 | Jan 21 12:25:28 PM PST 24 | 59637528967 ps | ||
| T874 | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3655507542 | Jan 21 12:24:47 PM PST 24 | Jan 21 12:24:56 PM PST 24 | 2505064797 ps | ||
| T339 | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1577179324 | Jan 21 12:20:44 PM PST 24 | Jan 21 12:21:17 PM PST 24 | 42808167715 ps | ||
| T875 | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942161220 | Jan 21 12:24:33 PM PST 24 | Jan 21 12:24:36 PM PST 24 | 2115030535 ps | ||
| T876 | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.534593055 | Jan 21 12:52:15 PM PST 24 | Jan 21 12:52:17 PM PST 24 | 2333564354 ps | ||
| T877 | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1973447611 | Jan 21 12:24:49 PM PST 24 | Jan 21 12:25:07 PM PST 24 | 22447259793 ps | ||
| T878 | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3192139719 | Jan 21 12:49:00 PM PST 24 | Jan 21 12:49:07 PM PST 24 | 2057608400 ps | ||
| T879 | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.814806851 | Jan 21 12:24:53 PM PST 24 | Jan 21 12:25:52 PM PST 24 | 42525964567 ps | ||
| T880 | /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272343999 | Jan 21 01:10:20 PM PST 24 | Jan 21 01:10:28 PM PST 24 | 2082458635 ps | ||
| T881 | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.795319197 | Jan 21 12:38:19 PM PST 24 | Jan 21 12:38:22 PM PST 24 | 2216346546 ps | ||
| T882 | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2338426054 | Jan 21 12:40:54 PM PST 24 | Jan 21 12:41:01 PM PST 24 | 2055880395 ps | ||
| T883 | /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4167432468 | Jan 21 12:25:02 PM PST 24 | Jan 21 12:25:11 PM PST 24 | 2010451723 ps | ||
| T884 | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3076396111 | Jan 21 12:53:26 PM PST 24 | Jan 21 12:53:30 PM PST 24 | 2071730983 ps | ||
| T885 | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4177180807 | Jan 21 12:53:56 PM PST 24 | Jan 21 12:54:07 PM PST 24 | 8332420122 ps | ||
| T886 | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2190184408 | Jan 21 12:21:49 PM PST 24 | Jan 21 12:22:03 PM PST 24 | 2048820332 ps | ||
| T887 | /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.160594222 | Jan 21 12:22:49 PM PST 24 | Jan 21 12:22:51 PM PST 24 | 2033794886 ps | ||
| T888 | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3686059347 | Jan 21 12:29:45 PM PST 24 | Jan 21 12:29:51 PM PST 24 | 2107217587 ps | ||
| T889 | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.896393600 | Jan 21 12:33:56 PM PST 24 | Jan 21 12:35:13 PM PST 24 | 64538236217 ps | ||
| T890 | /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2276282414 | Jan 21 01:13:17 PM PST 24 | Jan 21 01:14:16 PM PST 24 | 42425986889 ps | ||
| T891 | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3043695211 | Jan 21 12:51:45 PM PST 24 | Jan 21 12:51:52 PM PST 24 | 2010901850 ps | ||
| T892 | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1399088329 | Jan 21 12:24:37 PM PST 24 | Jan 21 12:24:40 PM PST 24 | 2084564633 ps | ||
| T893 | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3092991725 | Jan 21 12:21:20 PM PST 24 | Jan 21 12:22:10 PM PST 24 | 8778871002 ps | ||
| T894 | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2341820279 | Jan 21 12:24:33 PM PST 24 | Jan 21 12:24:39 PM PST 24 | 2315585451 ps | ||
| T895 | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1566888412 | Jan 21 12:24:45 PM PST 24 | Jan 21 12:24:52 PM PST 24 | 2039592625 ps | ||
| T896 | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2444609158 | Jan 21 12:24:46 PM PST 24 | Jan 21 12:24:52 PM PST 24 | 2060828775 ps | ||
| T897 | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1198432115 | Jan 21 12:24:26 PM PST 24 | Jan 21 12:26:27 PM PST 24 | 42370803495 ps | ||
| T898 | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2536758539 | Jan 21 01:02:46 PM PST 24 | Jan 21 01:02:51 PM PST 24 | 8637406115 ps | ||
| T899 | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3748945294 | Jan 21 01:27:52 PM PST 24 | Jan 21 01:27:55 PM PST 24 | 2171184492 ps | ||
| T900 | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3774085523 | Jan 21 12:24:43 PM PST 24 | Jan 21 12:24:47 PM PST 24 | 2023496491 ps | ||
| T901 | /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1044474067 | Jan 21 12:47:05 PM PST 24 | Jan 21 12:47:11 PM PST 24 | 2014583800 ps | ||
| T902 | /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.617205868 | Jan 21 12:46:42 PM PST 24 | Jan 21 12:46:45 PM PST 24 | 2030285252 ps | ||
| T903 | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1160605891 | Jan 21 01:57:19 PM PST 24 | Jan 21 01:57:23 PM PST 24 | 2095934985 ps | ||
| T904 | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3544275494 | Jan 21 12:21:49 PM PST 24 | Jan 21 12:21:58 PM PST 24 | 2052485530 ps | ||
| T905 | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2189915104 | Jan 21 01:11:03 PM PST 24 | Jan 21 01:11:09 PM PST 24 | 2458518980 ps | ||
| T906 | /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2350210391 | Jan 21 12:22:10 PM PST 24 | Jan 21 12:22:15 PM PST 24 | 2029900058 ps | ||
| T907 | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2189439605 | Jan 21 12:49:27 PM PST 24 | Jan 21 12:49:30 PM PST 24 | 2111736139 ps | ||
| T908 | /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1301379209 | Jan 21 01:23:04 PM PST 24 | Jan 21 01:23:11 PM PST 24 | 2013476325 ps | ||
| T909 | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3755583896 | Jan 21 12:24:47 PM PST 24 | Jan 21 12:24:54 PM PST 24 | 2051073639 ps | ||
| T910 | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1956860770 | Jan 21 12:24:24 PM PST 24 | Jan 21 12:24:30 PM PST 24 | 2160602921 ps | ||
| T911 | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1016013162 | Jan 21 02:12:17 PM PST 24 | Jan 21 02:12:22 PM PST 24 | 2077429251 ps | ||
| T912 | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2396174145 | Jan 21 12:45:57 PM PST 24 | Jan 21 12:46:37 PM PST 24 | 8921095213 ps | ||
| T913 | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2427172857 | Jan 21 12:24:53 PM PST 24 | Jan 21 12:24:57 PM PST 24 | 2041055603 ps | ||
| T914 | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.929666311 | Jan 21 12:24:43 PM PST 24 | Jan 21 12:24:46 PM PST 24 | 2095742184 ps | ||
| T915 | /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1844938794 | Jan 21 12:49:17 PM PST 24 | Jan 21 12:49:34 PM PST 24 | 43720619671 ps | ||
| T916 | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2047268247 | Jan 21 12:25:01 PM PST 24 | Jan 21 12:25:06 PM PST 24 | 2756915509 ps |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3200331034 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4017545215 ps |
| CPU time | 7.72 seconds |
| Started | Jan 21 12:42:10 PM PST 24 |
| Finished | Jan 21 12:42:19 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-8d5fa7c1-ab10-4671-8ac3-e0df7be3d51d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200331034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl _csr_hw_reset.3200331034 |
| Directory | /workspace/1.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2344218520 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 42877426512 ps |
| CPU time | 31.02 seconds |
| Started | Jan 21 12:47:31 PM PST 24 |
| Finished | Jan 21 12:48:02 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-91e4fda7-4442-4f6d-8cbd-e01421a4678d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344218520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ ctrl_tl_intg_err.2344218520 |
| Directory | /workspace/14.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3214254499 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 73920515645 ps |
| CPU time | 97.21 seconds |
| Started | Jan 21 12:30:12 PM PST 24 |
| Finished | Jan 21 12:31:51 PM PST 24 |
| Peak memory | 213668 kb |
| Host | smart-012e8dc2-d5dc-41ce-b21c-061840693537 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214254499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.3214254499 |
| Directory | /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1463951853 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 87159244270 ps |
| CPU time | 112.74 seconds |
| Started | Jan 21 12:31:26 PM PST 24 |
| Finished | Jan 21 12:33:20 PM PST 24 |
| Peak memory | 201216 kb |
| Host | smart-376f9abd-13a3-49bb-80ec-fcfdb855d1a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1463951853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w ith_pre_cond.1463951853 |
| Directory | /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_stress_all.3873431667 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 259173462588 ps |
| CPU time | 292.78 seconds |
| Started | Jan 21 12:31:15 PM PST 24 |
| Finished | Jan 21 12:36:08 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-cf536ac9-c529-4234-aef1-5e9254ecc437 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873431667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s tress_all.3873431667 |
| Directory | /workspace/47.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1670886217 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 197322395701 ps |
| CPU time | 133.79 seconds |
| Started | Jan 21 12:28:00 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 217572 kb |
| Host | smart-42c9d4f5-9ebd-4a8d-a04f-95c732f6ec94 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670886217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1670886217 |
| Directory | /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1306451763 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 134281809536 ps |
| CPU time | 74.27 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:28:24 PM PST 24 |
| Peak memory | 209608 kb |
| Host | smart-42108bfc-fe32-4bf2-b92f-65d34b03cf5b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306451763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1306451763 |
| Directory | /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2320364380 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 37840894855 ps |
| CPU time | 171.37 seconds |
| Started | Jan 21 12:21:27 PM PST 24 |
| Finished | Jan 21 12:24:19 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-ea9287ed-d382-44c3-870a-20374d5108ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320364380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl _csr_bit_bash.2320364380 |
| Directory | /workspace/1.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.1430965613 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 161550815166 ps |
| CPU time | 200.61 seconds |
| Started | Jan 21 12:29:10 PM PST 24 |
| Finished | Jan 21 12:32:37 PM PST 24 |
| Peak memory | 209576 kb |
| Host | smart-bd3e798a-cfc2-403e-b9a1-5c74bb6e2455 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430965613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.1430965613 |
| Directory | /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.595350892 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 2043375751 ps |
| CPU time | 1.9 seconds |
| Started | Jan 21 12:24:46 PM PST 24 |
| Finished | Jan 21 12:24:49 PM PST 24 |
| Peak memory | 200548 kb |
| Host | smart-de63ad0d-5d8b-4300-b42d-f48a1c43f9e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595350892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_tes t.595350892 |
| Directory | /workspace/22.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_stress_all.2429783088 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 275112721091 ps |
| CPU time | 727.67 seconds |
| Started | Jan 21 12:27:58 PM PST 24 |
| Finished | Jan 21 12:40:06 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-a74b1be8-34d2-46e5-bc23-befed8e07289 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429783088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s tress_all.2429783088 |
| Directory | /workspace/10.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1851941120 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 39854754259 ps |
| CPU time | 96.36 seconds |
| Started | Jan 21 12:26:47 PM PST 24 |
| Finished | Jan 21 12:28:27 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-c18e6fa8-5195-49f0-b9ec-e1201e206a0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851941120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1851941120 |
| Directory | /workspace/1.sysrst_ctrl_feature_disable/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.466373323 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 2028646465 ps |
| CPU time | 6.58 seconds |
| Started | Jan 21 12:53:23 PM PST 24 |
| Finished | Jan 21 12:53:33 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-b6b1a624-5157-479f-a6b0-c6e1b810171d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466373323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_error s.466373323 |
| Directory | /workspace/12.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.626854856 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 233691780380 ps |
| CPU time | 212.71 seconds |
| Started | Jan 21 12:31:05 PM PST 24 |
| Finished | Jan 21 12:34:39 PM PST 24 |
| Peak memory | 209584 kb |
| Host | smart-480e67cb-2b8b-4325-9427-15b27c063c29 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626854856 -assert n opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.626854856 |
| Directory | /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2891975240 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 8960310434 ps |
| CPU time | 32.33 seconds |
| Started | Jan 21 12:53:28 PM PST 24 |
| Finished | Jan 21 12:54:03 PM PST 24 |
| Peak memory | 201120 kb |
| Host | smart-3d5e3272-60ce-471f-be78-2e75de025260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891975240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0 .sysrst_ctrl_same_csr_outstanding.2891975240 |
| Directory | /workspace/0.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2885347169 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 189513853033 ps |
| CPU time | 59.31 seconds |
| Started | Jan 21 12:28:55 PM PST 24 |
| Finished | Jan 21 12:29:55 PM PST 24 |
| Peak memory | 209508 kb |
| Host | smart-73e012e9-5112-4e62-960e-2120241f6266 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885347169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2885347169 |
| Directory | /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2677877311 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 42013755076 ps |
| CPU time | 112.43 seconds |
| Started | Jan 21 12:26:42 PM PST 24 |
| Finished | Jan 21 12:28:40 PM PST 24 |
| Peak memory | 220468 kb |
| Host | smart-a8c708fc-7a39-4f51-9f23-220700a03615 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677877311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.2677877311 |
| Directory | /workspace/0.sysrst_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.900959539 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 212914833619 ps |
| CPU time | 140.86 seconds |
| Started | Jan 21 12:27:20 PM PST 24 |
| Finished | Jan 21 12:29:41 PM PST 24 |
| Peak memory | 218080 kb |
| Host | smart-0cbe6f6f-ea76-4130-8dda-708a606831f4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900959539 -assert n opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.900959539 |
| Directory | /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1102916690 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 131190397925 ps |
| CPU time | 91.34 seconds |
| Started | Jan 21 12:31:27 PM PST 24 |
| Finished | Jan 21 12:32:59 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-86ae1a1d-a22d-4aca-b43a-7c3ac173abc8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1102916690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w ith_pre_cond.1102916690 |
| Directory | /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3577459090 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2511610321 ps |
| CPU time | 7.33 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:30 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-41f99ad2-a629-44a9-9bdc-73f5078574aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577459090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3577459090 |
| Directory | /workspace/29.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2813753839 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 855850709549 ps |
| CPU time | 146.27 seconds |
| Started | Jan 21 12:26:49 PM PST 24 |
| Finished | Jan 21 12:29:18 PM PST 24 |
| Peak memory | 217716 kb |
| Host | smart-8c8cfd13-0567-4dc7-b0ac-35ddb7fb01cb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813753839 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2813753839 |
| Directory | /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1140875427 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 69329224614 ps |
| CPU time | 44.53 seconds |
| Started | Jan 21 12:28:46 PM PST 24 |
| Finished | Jan 21 12:29:31 PM PST 24 |
| Peak memory | 201200 kb |
| Host | smart-a503cf5b-8ab8-4fab-beeb-f65d30fe43ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140875427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w ith_pre_cond.1140875427 |
| Directory | /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_stress_all.677163415 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 18196229819 ps |
| CPU time | 11.9 seconds |
| Started | Jan 21 12:30:50 PM PST 24 |
| Finished | Jan 21 12:31:03 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-294a69ed-156c-4dcc-a0e4-5fbc3e29cd83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677163415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_st ress_all.677163415 |
| Directory | /workspace/42.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.4205400539 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 171161476105 ps |
| CPU time | 66.94 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:31:28 PM PST 24 |
| Peak memory | 217816 kb |
| Host | smart-e59a3bfe-601f-42de-9c83-f570bc2ee03b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205400539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.4205400539 |
| Directory | /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3172603810 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 93582778596 ps |
| CPU time | 42.37 seconds |
| Started | Jan 21 12:31:38 PM PST 24 |
| Finished | Jan 21 12:32:22 PM PST 24 |
| Peak memory | 201276 kb |
| Host | smart-ce6285e2-0488-4516-8a7c-234b0714f2c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172603810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w ith_pre_cond.3172603810 |
| Directory | /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3385675475 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 78696605085 ps |
| CPU time | 199.46 seconds |
| Started | Jan 21 12:26:58 PM PST 24 |
| Finished | Jan 21 12:30:18 PM PST 24 |
| Peak memory | 214104 kb |
| Host | smart-4de50c31-e15f-4117-bf18-7f924e477874 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385675475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3385675475 |
| Directory | /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1409973803 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 122390571695 ps |
| CPU time | 284.45 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:34:56 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-95aff7aa-6a67-45dd-ba7c-2dc093e5b1e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1409973803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w ith_pre_cond.1409973803 |
| Directory | /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2447380577 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 192425031797 ps |
| CPU time | 264.77 seconds |
| Started | Jan 21 12:28:17 PM PST 24 |
| Finished | Jan 21 12:32:42 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-e4da880f-c3e0-4dba-ae0c-6d967779cef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2447380577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_w ith_pre_cond.2447380577 |
| Directory | /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.307649013 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2525502133 ps |
| CPU time | 2.26 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:14 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-9cc84533-428e-4091-b379-f5454d3c9a9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=307649013 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.307649013 |
| Directory | /workspace/18.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_stress_all.3507168993 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 172670211497 ps |
| CPU time | 467.64 seconds |
| Started | Jan 21 12:28:42 PM PST 24 |
| Finished | Jan 21 12:36:30 PM PST 24 |
| Peak memory | 201616 kb |
| Host | smart-49731cb2-58c5-4927-910c-9a640b85e044 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507168993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s tress_all.3507168993 |
| Directory | /workspace/20.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1197464119 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 70197880556 ps |
| CPU time | 41.33 seconds |
| Started | Jan 21 12:30:47 PM PST 24 |
| Finished | Jan 21 12:31:29 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-9bfa4d54-e4a1-4121-bb56-e057c3846105 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197464119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c trl_combo_detect.1197464119 |
| Directory | /workspace/41.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1566888733 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2334057337 ps |
| CPU time | 3.9 seconds |
| Started | Jan 21 12:26:26 PM PST 24 |
| Finished | Jan 21 12:26:33 PM PST 24 |
| Peak memory | 209176 kb |
| Host | smart-ab8c96e8-391e-4840-84c1-d0a6da8fdc4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566888733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error s.1566888733 |
| Directory | /workspace/8.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_stress_all.1353091021 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 15859384643 ps |
| CPU time | 18.2 seconds |
| Started | Jan 21 12:28:00 PM PST 24 |
| Finished | Jan 21 12:28:20 PM PST 24 |
| Peak memory | 200960 kb |
| Host | smart-cce9d856-7fec-4d7b-8981-64a7dbc679b0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353091021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s tress_all.1353091021 |
| Directory | /workspace/11.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2598297542 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4935225299 ps |
| CPU time | 4.67 seconds |
| Started | Jan 21 12:29:36 PM PST 24 |
| Finished | Jan 21 12:29:42 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-ee4c9749-9abe-4064-b560-7a813d1fb7f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598297542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct rl_edge_detect.2598297542 |
| Directory | /workspace/31.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1081951964 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 21329581820 ps |
| CPU time | 58.32 seconds |
| Started | Jan 21 12:29:41 PM PST 24 |
| Finished | Jan 21 12:30:43 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-dabccc74-2b45-4f4e-9c14-87bfa2fdd350 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081951964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1081951964 |
| Directory | /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2364976972 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 42453819959 ps |
| CPU time | 113.1 seconds |
| Started | Jan 21 12:59:07 PM PST 24 |
| Finished | Jan 21 01:01:01 PM PST 24 |
| Peak memory | 201128 kb |
| Host | smart-6294455c-8dcd-42a9-841d-4a07a9418be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364976972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ ctrl_tl_intg_err.2364976972 |
| Directory | /workspace/19.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.714842853 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 129998732976 ps |
| CPU time | 331.42 seconds |
| Started | Jan 21 12:30:21 PM PST 24 |
| Finished | Jan 21 12:35:54 PM PST 24 |
| Peak memory | 201232 kb |
| Host | smart-ec8fc0da-b8c9-405a-b4dc-381a868cf6db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714842853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_wi th_pre_cond.714842853 |
| Directory | /workspace/37.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3901105206 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 40224254182 ps |
| CPU time | 56.86 seconds |
| Started | Jan 21 12:27:58 PM PST 24 |
| Finished | Jan 21 12:28:55 PM PST 24 |
| Peak memory | 209528 kb |
| Host | smart-6f11ea78-e07c-4743-807d-3dc0f1009b89 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901105206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.3901105206 |
| Directory | /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.2984095362 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 4590349383037 ps |
| CPU time | 988.08 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:44:23 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-623065fe-f835-477e-8808-ef3c9b624009 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984095362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ ctrl_ultra_low_pwr.2984095362 |
| Directory | /workspace/11.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3196567681 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 35528825085 ps |
| CPU time | 99.43 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:28:28 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-db804804-c436-44a2-b3c8-b8a121d07152 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3196567681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.3196567681 |
| Directory | /workspace/0.sysrst_ctrl_feature_disable/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.281622149 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2018232961 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 12:24:43 PM PST 24 |
| Finished | Jan 21 12:24:47 PM PST 24 |
| Peak memory | 200136 kb |
| Host | smart-6b7f1fbe-a396-4e61-a71e-ae6174502484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281622149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_tes t.281622149 |
| Directory | /workspace/14.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1286105722 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 56741255467 ps |
| CPU time | 142.77 seconds |
| Started | Jan 21 12:29:00 PM PST 24 |
| Finished | Jan 21 12:31:25 PM PST 24 |
| Peak memory | 201200 kb |
| Host | smart-d1ba05c5-b312-4985-b52c-41aa135d1a2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286105722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_w ith_pre_cond.1286105722 |
| Directory | /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3961744702 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 103083387204 ps |
| CPU time | 61.85 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:31:06 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-b7e33e44-2269-4206-92cd-2b1e9c3d0a8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961744702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c trl_combo_detect.3961744702 |
| Directory | /workspace/32.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3598484643 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 25381555384 ps |
| CPU time | 31.9 seconds |
| Started | Jan 21 12:30:21 PM PST 24 |
| Finished | Jan 21 12:30:54 PM PST 24 |
| Peak memory | 201204 kb |
| Host | smart-d1d272bc-1bcd-4952-b5d9-ffdc44a3f744 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598484643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c trl_combo_detect.3598484643 |
| Directory | /workspace/37.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3947209982 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 70591631259 ps |
| CPU time | 190.96 seconds |
| Started | Jan 21 12:27:25 PM PST 24 |
| Finished | Jan 21 12:30:37 PM PST 24 |
| Peak memory | 200980 kb |
| Host | smart-b13ae48c-06ae-48e3-8e4f-926976a83259 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3947209982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wi th_pre_cond.3947209982 |
| Directory | /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.359492163 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 37588688190 ps |
| CPU time | 46.78 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:30:59 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-7d0d0c19-6c03-4b57-bb87-54768afadc2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359492163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_wi th_pre_cond.359492163 |
| Directory | /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1319377772 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 117096716020 ps |
| CPU time | 324.73 seconds |
| Started | Jan 21 12:31:38 PM PST 24 |
| Finished | Jan 21 12:37:04 PM PST 24 |
| Peak memory | 200840 kb |
| Host | smart-2e7b31a7-127e-410f-b0a9-e17509f77156 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1319377772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_w ith_pre_cond.1319377772 |
| Directory | /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3062193810 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 94348054993 ps |
| CPU time | 77.81 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:28:06 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-b981f85c-1312-4cdc-9f0c-27e8deaf2be8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062193810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi th_pre_cond.3062193810 |
| Directory | /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1763872528 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 3358226847 ps |
| CPU time | 2.81 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:12 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-1ea2429c-903f-4b69-a0ca-7ef9f60d8a23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763872528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.1763872528 |
| Directory | /workspace/1.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1215681783 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 76510927190 ps |
| CPU time | 71.83 seconds |
| Started | Jan 21 12:26:47 PM PST 24 |
| Finished | Jan 21 12:28:03 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-7d1ac77b-ee98-4f12-a0bf-1425c419d440 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215681783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi th_pre_cond.1215681783 |
| Directory | /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3813972699 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 122953442270 ps |
| CPU time | 79.51 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:29:15 PM PST 24 |
| Peak memory | 201280 kb |
| Host | smart-7a88bcd7-9b93-4498-94a3-a6c505b38968 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3813972699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w ith_pre_cond.3813972699 |
| Directory | /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.482183645 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 66764240809 ps |
| CPU time | 165.47 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:30:58 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-7d405223-6fae-4c1e-b971-0904dffc45ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=482183645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_wi th_pre_cond.482183645 |
| Directory | /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2487519086 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 98321438640 ps |
| CPU time | 64.48 seconds |
| Started | Jan 21 12:29:02 PM PST 24 |
| Finished | Jan 21 12:30:08 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-f4555d37-172c-4f6c-8fa5-e9f5aafe5953 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2487519086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w ith_pre_cond.2487519086 |
| Directory | /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1639748638 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 141396078701 ps |
| CPU time | 358.37 seconds |
| Started | Jan 21 12:29:11 PM PST 24 |
| Finished | Jan 21 12:35:15 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-5d9469a9-9f8b-4bb7-b82d-9cc9ebc5e471 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639748638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w ith_pre_cond.1639748638 |
| Directory | /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3274266434 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 33707013570 ps |
| CPU time | 60.61 seconds |
| Started | Jan 21 12:29:18 PM PST 24 |
| Finished | Jan 21 12:30:23 PM PST 24 |
| Peak memory | 209540 kb |
| Host | smart-a574bec1-c68e-4803-83dc-f7c9c23df386 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274266434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.3274266434 |
| Directory | /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3123714470 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 95157381565 ps |
| CPU time | 32.65 seconds |
| Started | Jan 21 12:30:17 PM PST 24 |
| Finished | Jan 21 12:30:51 PM PST 24 |
| Peak memory | 201116 kb |
| Host | smart-dfa14ac5-42c9-4898-94f5-64cc2117a000 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123714470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c trl_combo_detect.3123714470 |
| Directory | /workspace/40.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2993542387 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 40902355474 ps |
| CPU time | 10.23 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:31:31 PM PST 24 |
| Peak memory | 201344 kb |
| Host | smart-f220abe4-348d-4e00-a04d-1a2518bc4995 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2993542387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w ith_pre_cond.2993542387 |
| Directory | /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.4018928038 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 87159143649 ps |
| CPU time | 63.53 seconds |
| Started | Jan 21 12:31:18 PM PST 24 |
| Finished | Jan 21 12:32:23 PM PST 24 |
| Peak memory | 201200 kb |
| Host | smart-214ecd34-1d86-4aa7-bb3b-2c485043086b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018928038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w ith_pre_cond.4018928038 |
| Directory | /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3486326821 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 108361109978 ps |
| CPU time | 73.46 seconds |
| Started | Jan 21 12:31:19 PM PST 24 |
| Finished | Jan 21 12:32:33 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-dee31b5b-9945-4f2f-8eae-7099aca82c9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3486326821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w ith_pre_cond.3486326821 |
| Directory | /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2157513275 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 85497158590 ps |
| CPU time | 58.24 seconds |
| Started | Jan 21 12:31:48 PM PST 24 |
| Finished | Jan 21 12:33:05 PM PST 24 |
| Peak memory | 201208 kb |
| Host | smart-1fe0ed07-0e81-4d57-a9c4-aa261fb6e09c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157513275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_w ith_pre_cond.2157513275 |
| Directory | /workspace/96.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1203057106 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 5401083188 ps |
| CPU time | 3.38 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:28:00 PM PST 24 |
| Peak memory | 201120 kb |
| Host | smart-13f81a36-ddf8-473f-998f-7191975ea88b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203057106 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct rl_edge_detect.1203057106 |
| Directory | /workspace/11.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3175609390 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4633269883 ps |
| CPU time | 5.42 seconds |
| Started | Jan 21 12:28:26 PM PST 24 |
| Finished | Jan 21 12:28:32 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-3c24683b-1f58-4d12-8f06-5d1c0cb5fb11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175609390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct rl_edge_detect.3175609390 |
| Directory | /workspace/19.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_edge_detect.8105738 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4034705419 ps |
| CPU time | 8.82 seconds |
| Started | Jan 21 12:27:53 PM PST 24 |
| Finished | Jan 21 12:28:03 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-7a61f7d3-52ef-49d2-9339-57bd8afa91f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8105738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_e dge_detect.8105738 |
| Directory | /workspace/9.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_alert_test.90479044 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 2040279524 ps |
| CPU time | 1.97 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:11 PM PST 24 |
| Peak memory | 200864 kb |
| Host | smart-280ea308-61e4-41d8-80f2-8bb94e65e2c1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90479044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.90479044 |
| Directory | /workspace/1.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1897141051 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 47842405824 ps |
| CPU time | 32.64 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:27:49 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-085be5a2-d4dc-480f-b416-3d2af63f0e45 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1897141051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_wi th_pre_cond.1897141051 |
| Directory | /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3655507542 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2505064797 ps |
| CPU time | 8.34 seconds |
| Started | Jan 21 12:24:47 PM PST 24 |
| Finished | Jan 21 12:24:56 PM PST 24 |
| Peak memory | 200964 kb |
| Host | smart-9d9c8430-7096-483e-b8a4-83163be05f66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655507542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl _csr_aliasing.3655507542 |
| Directory | /workspace/0.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3249756559 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 59637528967 ps |
| CPU time | 47.41 seconds |
| Started | Jan 21 12:24:40 PM PST 24 |
| Finished | Jan 21 12:25:28 PM PST 24 |
| Peak memory | 199372 kb |
| Host | smart-c99ac2db-72e6-479a-8301-dfa445436b1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249756559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl _csr_bit_bash.3249756559 |
| Directory | /workspace/0.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.692948848 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 4017158007 ps |
| CPU time | 11.28 seconds |
| Started | Jan 21 12:24:40 PM PST 24 |
| Finished | Jan 21 12:24:52 PM PST 24 |
| Peak memory | 199204 kb |
| Host | smart-0cdcea03-7b49-46b0-8365-220d130ea782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692948848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ csr_hw_reset.692948848 |
| Directory | /workspace/0.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3755583896 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 2051073639 ps |
| CPU time | 6.51 seconds |
| Started | Jan 21 12:24:47 PM PST 24 |
| Finished | Jan 21 12:24:54 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-8f83b67c-73e8-48fc-bc65-fb8a666aa491 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755583896 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3755583896 |
| Directory | /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2816405025 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 2058355957 ps |
| CPU time | 6.32 seconds |
| Started | Jan 21 12:23:12 PM PST 24 |
| Finished | Jan 21 12:23:19 PM PST 24 |
| Peak memory | 200808 kb |
| Host | smart-762589a3-5e0c-4952-9d40-92290a567fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816405025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r w.2816405025 |
| Directory | /workspace/0.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.197820926 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2015254132 ps |
| CPU time | 5.61 seconds |
| Started | Jan 21 12:54:16 PM PST 24 |
| Finished | Jan 21 12:54:22 PM PST 24 |
| Peak memory | 200684 kb |
| Host | smart-7acbd37f-3d97-4e40-9d4a-6b3e5af40788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197820926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test .197820926 |
| Directory | /workspace/0.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2379890719 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2203743128 ps |
| CPU time | 2.61 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:06 PM PST 24 |
| Peak memory | 200972 kb |
| Host | smart-48ceb902-5401-4051-89eb-6f8dd6922d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379890719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error s.2379890719 |
| Directory | /workspace/0.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2860275498 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 22238764151 ps |
| CPU time | 47.32 seconds |
| Started | Jan 21 12:24:40 PM PST 24 |
| Finished | Jan 21 12:25:28 PM PST 24 |
| Peak memory | 199340 kb |
| Host | smart-66d1628e-7e7c-478f-ba48-9c97ad982667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860275498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c trl_tl_intg_err.2860275498 |
| Directory | /workspace/0.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.594371879 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 3178976710 ps |
| CPU time | 10.61 seconds |
| Started | Jan 21 12:38:45 PM PST 24 |
| Finished | Jan 21 12:38:57 PM PST 24 |
| Peak memory | 200956 kb |
| Host | smart-2c5cfb6b-e470-4d06-8501-37d2ae919556 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594371879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ csr_aliasing.594371879 |
| Directory | /workspace/1.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942161220 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2115030535 ps |
| CPU time | 2.02 seconds |
| Started | Jan 21 12:24:33 PM PST 24 |
| Finished | Jan 21 12:24:36 PM PST 24 |
| Peak memory | 199020 kb |
| Host | smart-c7670eff-2e70-44f9-a5db-8dc9a21e3a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942161220 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942161220 |
| Directory | /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2444609158 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 2060828775 ps |
| CPU time | 4.94 seconds |
| Started | Jan 21 12:24:46 PM PST 24 |
| Finished | Jan 21 12:24:52 PM PST 24 |
| Peak memory | 200596 kb |
| Host | smart-b50c1bcf-1c19-40c5-93ff-c0e9a343f607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444609158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r w.2444609158 |
| Directory | /workspace/1.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.577503300 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 2141537472 ps |
| CPU time | 1.12 seconds |
| Started | Jan 21 12:24:23 PM PST 24 |
| Finished | Jan 21 12:24:28 PM PST 24 |
| Peak memory | 199332 kb |
| Host | smart-67e036d5-aec2-476a-b8b4-de3410d89c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577503300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test .577503300 |
| Directory | /workspace/1.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4177180807 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 8332420122 ps |
| CPU time | 10.34 seconds |
| Started | Jan 21 12:53:56 PM PST 24 |
| Finished | Jan 21 12:54:07 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-19f78563-ec1a-4759-8b81-e20adafa0f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177180807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .sysrst_ctrl_same_csr_outstanding.4177180807 |
| Directory | /workspace/1.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2341820279 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2315585451 ps |
| CPU time | 4.93 seconds |
| Started | Jan 21 12:24:33 PM PST 24 |
| Finished | Jan 21 12:24:39 PM PST 24 |
| Peak memory | 199852 kb |
| Host | smart-456da262-5eb5-4c75-bb96-96085fcb7065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341820279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error s.2341820279 |
| Directory | /workspace/1.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.814806851 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 42525964567 ps |
| CPU time | 57.09 seconds |
| Started | Jan 21 12:24:53 PM PST 24 |
| Finished | Jan 21 12:25:52 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-741f02bd-3c94-4bb6-86ab-e7fc516bf35b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814806851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ct rl_tl_intg_err.814806851 |
| Directory | /workspace/1.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3192139719 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2057608400 ps |
| CPU time | 6.09 seconds |
| Started | Jan 21 12:49:00 PM PST 24 |
| Finished | Jan 21 12:49:07 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-fa4a1084-64c3-42a5-aa7b-3a1fa8bb20ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192139719 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3192139719 |
| Directory | /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1403072299 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2136803947 ps |
| CPU time | 1.62 seconds |
| Started | Jan 21 01:01:08 PM PST 24 |
| Finished | Jan 21 01:01:11 PM PST 24 |
| Peak memory | 200800 kb |
| Host | smart-7815596e-b6a6-4728-a708-faad32f0c562 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403072299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_ rw.1403072299 |
| Directory | /workspace/10.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3544275494 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 2052485530 ps |
| CPU time | 1.4 seconds |
| Started | Jan 21 12:21:49 PM PST 24 |
| Finished | Jan 21 12:21:58 PM PST 24 |
| Peak memory | 200404 kb |
| Host | smart-bb7a6650-a8ed-4c3c-a1e5-d0a0aabd0b47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544275494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te st.3544275494 |
| Directory | /workspace/10.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1298531861 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 7733971185 ps |
| CPU time | 6.44 seconds |
| Started | Jan 21 12:21:51 PM PST 24 |
| Finished | Jan 21 12:22:04 PM PST 24 |
| Peak memory | 201184 kb |
| Host | smart-06a5914c-c51a-45f9-b909-5414f5bede3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298531861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 0.sysrst_ctrl_same_csr_outstanding.1298531861 |
| Directory | /workspace/10.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2190184408 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 2048820332 ps |
| CPU time | 6.63 seconds |
| Started | Jan 21 12:21:49 PM PST 24 |
| Finished | Jan 21 12:22:03 PM PST 24 |
| Peak memory | 200904 kb |
| Host | smart-5c0bdb07-505f-4b06-82e3-0d88203c29c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190184408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro rs.2190184408 |
| Directory | /workspace/10.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1198432115 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 42370803495 ps |
| CPU time | 119.11 seconds |
| Started | Jan 21 12:24:26 PM PST 24 |
| Finished | Jan 21 12:26:27 PM PST 24 |
| Peak memory | 199968 kb |
| Host | smart-c5741d6c-b63e-43f3-a6bc-f4a0f264e59e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198432115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ ctrl_tl_intg_err.1198432115 |
| Directory | /workspace/10.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3887386278 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2105193366 ps |
| CPU time | 2.19 seconds |
| Started | Jan 21 12:36:11 PM PST 24 |
| Finished | Jan 21 12:36:14 PM PST 24 |
| Peak memory | 200852 kb |
| Host | smart-8f912f88-6283-4e68-a5c4-d7bdd17413e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887386278 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3887386278 |
| Directory | /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2513392378 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 2043406153 ps |
| CPU time | 3.32 seconds |
| Started | Jan 21 12:24:17 PM PST 24 |
| Finished | Jan 21 12:24:22 PM PST 24 |
| Peak memory | 199568 kb |
| Host | smart-7aaff0c9-9808-46e6-8720-21c222b2fb2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513392378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_ rw.2513392378 |
| Directory | /workspace/11.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.902192947 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2025867739 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 12:23:10 PM PST 24 |
| Finished | Jan 21 12:23:13 PM PST 24 |
| Peak memory | 200696 kb |
| Host | smart-c7515525-a70f-4036-8b10-2bbe3e6fa216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902192947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes t.902192947 |
| Directory | /workspace/11.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2649898511 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4811724500 ps |
| CPU time | 3.76 seconds |
| Started | Jan 21 12:24:43 PM PST 24 |
| Finished | Jan 21 12:24:47 PM PST 24 |
| Peak memory | 200768 kb |
| Host | smart-59c2fa5f-728e-4152-86a6-1626e17b2a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649898511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 1.sysrst_ctrl_same_csr_outstanding.2649898511 |
| Directory | /workspace/11.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4036300001 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 2026534622 ps |
| CPU time | 6.47 seconds |
| Started | Jan 21 12:21:49 PM PST 24 |
| Finished | Jan 21 12:22:03 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-ebb065d9-314b-4297-a9a6-bed5a62c35c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036300001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro rs.4036300001 |
| Directory | /workspace/11.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1582508070 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 22229972044 ps |
| CPU time | 59.32 seconds |
| Started | Jan 21 12:21:49 PM PST 24 |
| Finished | Jan 21 12:22:56 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-9ac4d28e-ca44-44fc-90f9-35e1afe2b9e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582508070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ ctrl_tl_intg_err.1582508070 |
| Directory | /workspace/11.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3791196161 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2071307971 ps |
| CPU time | 6.02 seconds |
| Started | Jan 21 12:21:49 PM PST 24 |
| Finished | Jan 21 12:22:03 PM PST 24 |
| Peak memory | 200648 kb |
| Host | smart-baa378b0-25e0-489e-9892-54c1524aac67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791196161 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3791196161 |
| Directory | /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.538500155 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2032720146 ps |
| CPU time | 3.62 seconds |
| Started | Jan 21 12:35:13 PM PST 24 |
| Finished | Jan 21 12:35:27 PM PST 24 |
| Peak memory | 200636 kb |
| Host | smart-6bf46b1a-8d3e-4534-91d3-b5cf9bdf5183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538500155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_r w.538500155 |
| Directory | /workspace/12.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2025772463 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2012648465 ps |
| CPU time | 5.51 seconds |
| Started | Jan 21 01:10:23 PM PST 24 |
| Finished | Jan 21 01:10:29 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-b39c1323-11fc-4cab-8573-554e2542a82c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025772463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te st.2025772463 |
| Directory | /workspace/12.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1759660749 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 10536655477 ps |
| CPU time | 27.98 seconds |
| Started | Jan 21 12:21:22 PM PST 24 |
| Finished | Jan 21 12:21:53 PM PST 24 |
| Peak memory | 201164 kb |
| Host | smart-8f1db90f-e02e-4d4a-978e-0f4b3ab834b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759660749 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 2.sysrst_ctrl_same_csr_outstanding.1759660749 |
| Directory | /workspace/12.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2606059069 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 42438180416 ps |
| CPU time | 114.47 seconds |
| Started | Jan 21 12:24:52 PM PST 24 |
| Finished | Jan 21 12:26:49 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-be157145-3b7e-4396-99ac-6c79af484703 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606059069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ ctrl_tl_intg_err.2606059069 |
| Directory | /workspace/12.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.929666311 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 2095742184 ps |
| CPU time | 2.24 seconds |
| Started | Jan 21 12:24:43 PM PST 24 |
| Finished | Jan 21 12:24:46 PM PST 24 |
| Peak memory | 200756 kb |
| Host | smart-f79ec4e5-2f5d-4774-92b4-bbd7c6dd92e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929666311 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.929666311 |
| Directory | /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.42617686 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2082608922 ps |
| CPU time | 2.09 seconds |
| Started | Jan 21 12:53:33 PM PST 24 |
| Finished | Jan 21 12:53:37 PM PST 24 |
| Peak memory | 200656 kb |
| Host | smart-c6d37375-f5fe-4ee4-bc15-5e3553b5e681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42617686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw .42617686 |
| Directory | /workspace/13.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3043695211 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2010901850 ps |
| CPU time | 5.78 seconds |
| Started | Jan 21 12:51:45 PM PST 24 |
| Finished | Jan 21 12:51:52 PM PST 24 |
| Peak memory | 200544 kb |
| Host | smart-d5340a4a-b252-4d90-bb91-df0cd8cba656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043695211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te st.3043695211 |
| Directory | /workspace/13.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2396174145 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 8921095213 ps |
| CPU time | 37.67 seconds |
| Started | Jan 21 12:45:57 PM PST 24 |
| Finished | Jan 21 12:46:37 PM PST 24 |
| Peak memory | 201108 kb |
| Host | smart-5587fe1e-8bf9-45c8-909a-e58f4dfeb3e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396174145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 3.sysrst_ctrl_same_csr_outstanding.2396174145 |
| Directory | /workspace/13.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1607190654 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2624647328 ps |
| CPU time | 3.84 seconds |
| Started | Jan 21 12:57:50 PM PST 24 |
| Finished | Jan 21 12:57:55 PM PST 24 |
| Peak memory | 201220 kb |
| Host | smart-a019807f-b0e3-4c7b-8b67-a3a9d83bb347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607190654 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro rs.1607190654 |
| Directory | /workspace/13.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2063774298 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 22420044317 ps |
| CPU time | 16.89 seconds |
| Started | Jan 21 12:58:46 PM PST 24 |
| Finished | Jan 21 12:59:03 PM PST 24 |
| Peak memory | 201512 kb |
| Host | smart-fae3e371-1513-4dac-a00d-59864615297a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063774298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ ctrl_tl_intg_err.2063774298 |
| Directory | /workspace/13.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2338426054 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 2055880395 ps |
| CPU time | 6.03 seconds |
| Started | Jan 21 12:40:54 PM PST 24 |
| Finished | Jan 21 12:41:01 PM PST 24 |
| Peak memory | 200820 kb |
| Host | smart-b6c418b9-eb06-4196-bf27-c35e8e9f13ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338426054 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2338426054 |
| Directory | /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.646047800 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2057901613 ps |
| CPU time | 5.38 seconds |
| Started | Jan 21 01:13:54 PM PST 24 |
| Finished | Jan 21 01:14:01 PM PST 24 |
| Peak memory | 200732 kb |
| Host | smart-5efc6134-0e6d-4fac-9e4a-240f3cf9aaa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646047800 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_r w.646047800 |
| Directory | /workspace/14.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.203682752 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4685084320 ps |
| CPU time | 5.55 seconds |
| Started | Jan 21 12:24:43 PM PST 24 |
| Finished | Jan 21 12:24:49 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-6bd46b80-ae17-4b09-acb5-302952c4105f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203682752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .sysrst_ctrl_same_csr_outstanding.203682752 |
| Directory | /workspace/14.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1956860770 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 2160602921 ps |
| CPU time | 3.35 seconds |
| Started | Jan 21 12:24:24 PM PST 24 |
| Finished | Jan 21 12:24:30 PM PST 24 |
| Peak memory | 208252 kb |
| Host | smart-853fc1b9-ec1a-4732-a329-826af78e2a70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956860770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro rs.1956860770 |
| Directory | /workspace/14.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3748945294 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2171184492 ps |
| CPU time | 2.41 seconds |
| Started | Jan 21 01:27:52 PM PST 24 |
| Finished | Jan 21 01:27:55 PM PST 24 |
| Peak memory | 200916 kb |
| Host | smart-23c80890-efcc-4c79-bb0b-e5a261452e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748945294 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3748945294 |
| Directory | /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3118224499 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 2043165857 ps |
| CPU time | 2.07 seconds |
| Started | Jan 21 12:21:03 PM PST 24 |
| Finished | Jan 21 12:21:08 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-539f38d3-2107-4c5a-8010-8d13393feede |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118224499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_ rw.3118224499 |
| Directory | /workspace/15.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2427172857 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2041055603 ps |
| CPU time | 2.02 seconds |
| Started | Jan 21 12:24:53 PM PST 24 |
| Finished | Jan 21 12:24:57 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-a74d22ac-b882-458d-9a1b-342312377b69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427172857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te st.2427172857 |
| Directory | /workspace/15.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.319161765 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 8534328311 ps |
| CPU time | 12.35 seconds |
| Started | Jan 21 12:21:05 PM PST 24 |
| Finished | Jan 21 12:21:20 PM PST 24 |
| Peak memory | 201224 kb |
| Host | smart-0a93ab60-4cbb-49b5-bfbb-d7863770ec95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319161765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15 .sysrst_ctrl_same_csr_outstanding.319161765 |
| Directory | /workspace/15.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3773238103 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2136668888 ps |
| CPU time | 4.12 seconds |
| Started | Jan 21 12:37:18 PM PST 24 |
| Finished | Jan 21 12:37:23 PM PST 24 |
| Peak memory | 209252 kb |
| Host | smart-641e5379-ea7d-4a23-893a-9c311d6fe2f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773238103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro rs.3773238103 |
| Directory | /workspace/15.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.388078732 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 22382145207 ps |
| CPU time | 8.52 seconds |
| Started | Jan 21 12:53:52 PM PST 24 |
| Finished | Jan 21 12:54:01 PM PST 24 |
| Peak memory | 201224 kb |
| Host | smart-6a7f17a0-8d51-4cee-a3db-b757fed50f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388078732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_c trl_tl_intg_err.388078732 |
| Directory | /workspace/15.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1706800882 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 2136241028 ps |
| CPU time | 1.75 seconds |
| Started | Jan 21 01:10:33 PM PST 24 |
| Finished | Jan 21 01:10:37 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-d67ed0d5-df5f-4ab0-b343-a023da3909a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706800882 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1706800882 |
| Directory | /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2189439605 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2111736139 ps |
| CPU time | 2.18 seconds |
| Started | Jan 21 12:49:27 PM PST 24 |
| Finished | Jan 21 12:49:30 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-1c00e4a6-8e69-4886-8490-f2b078149185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189439605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_ rw.2189439605 |
| Directory | /workspace/16.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4182298636 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2056542037 ps |
| CPU time | 1.5 seconds |
| Started | Jan 21 01:49:47 PM PST 24 |
| Finished | Jan 21 01:49:55 PM PST 24 |
| Peak memory | 200636 kb |
| Host | smart-e1adafea-ee42-4a69-ada3-f1d2a40bda09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182298636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te st.4182298636 |
| Directory | /workspace/16.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3092991725 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 8778871002 ps |
| CPU time | 46.58 seconds |
| Started | Jan 21 12:21:20 PM PST 24 |
| Finished | Jan 21 12:22:10 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-712f167f-3d21-4810-8032-b9d85e105ffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092991725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 6.sysrst_ctrl_same_csr_outstanding.3092991725 |
| Directory | /workspace/16.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1016013162 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 2077429251 ps |
| CPU time | 4.7 seconds |
| Started | Jan 21 02:12:17 PM PST 24 |
| Finished | Jan 21 02:12:22 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-ea411be7-78f3-48f1-86fc-40423c232c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016013162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro rs.1016013162 |
| Directory | /workspace/16.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.946224107 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 22250463056 ps |
| CPU time | 55.85 seconds |
| Started | Jan 21 12:47:46 PM PST 24 |
| Finished | Jan 21 12:48:42 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-ba07c7ed-2b5f-4ecb-a456-3aaf1ca63776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946224107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_c trl_tl_intg_err.946224107 |
| Directory | /workspace/16.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.360614424 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2090344520 ps |
| CPU time | 2.01 seconds |
| Started | Jan 21 12:45:04 PM PST 24 |
| Finished | Jan 21 12:45:06 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-6e0cb241-05fe-42a1-98ee-f31825dd6eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360614424 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.360614424 |
| Directory | /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3741186431 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2051010089 ps |
| CPU time | 3.67 seconds |
| Started | Jan 21 12:21:25 PM PST 24 |
| Finished | Jan 21 12:21:30 PM PST 24 |
| Peak memory | 200796 kb |
| Host | smart-a3cc6f6b-a0b0-4766-9ecd-ddd2f480513a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741186431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_ rw.3741186431 |
| Directory | /workspace/17.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.424543434 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2011382932 ps |
| CPU time | 5.96 seconds |
| Started | Jan 21 12:24:40 PM PST 24 |
| Finished | Jan 21 12:24:47 PM PST 24 |
| Peak memory | 199308 kb |
| Host | smart-eb45b22d-a3ff-4fcc-9cdf-66b9dd638bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424543434 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_tes t.424543434 |
| Directory | /workspace/17.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1879322715 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 9011624969 ps |
| CPU time | 13.4 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:16 PM PST 24 |
| Peak memory | 200928 kb |
| Host | smart-8ca5120a-d46e-43cd-a215-5622848e0ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879322715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 7.sysrst_ctrl_same_csr_outstanding.1879322715 |
| Directory | /workspace/17.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3848460687 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2242492291 ps |
| CPU time | 4.79 seconds |
| Started | Jan 21 12:48:07 PM PST 24 |
| Finished | Jan 21 12:48:16 PM PST 24 |
| Peak memory | 200956 kb |
| Host | smart-3b18d79d-516c-4fe3-a333-b4b5a794495e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848460687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro rs.3848460687 |
| Directory | /workspace/17.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1844938794 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 43720619671 ps |
| CPU time | 16.48 seconds |
| Started | Jan 21 12:49:17 PM PST 24 |
| Finished | Jan 21 12:49:34 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-ec77cba6-abab-4553-8dcf-423ef8cf73e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844938794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ ctrl_tl_intg_err.1844938794 |
| Directory | /workspace/17.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2882343185 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 2081971750 ps |
| CPU time | 6.82 seconds |
| Started | Jan 21 12:21:51 PM PST 24 |
| Finished | Jan 21 12:22:05 PM PST 24 |
| Peak memory | 200824 kb |
| Host | smart-051c4c5f-7d13-4596-ab7f-4ebb2c749888 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882343185 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2882343185 |
| Directory | /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3114425616 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2039068162 ps |
| CPU time | 3.4 seconds |
| Started | Jan 21 12:42:54 PM PST 24 |
| Finished | Jan 21 12:42:58 PM PST 24 |
| Peak memory | 200796 kb |
| Host | smart-1511c983-fbe5-442c-9251-8003d3aa95c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114425616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_ rw.3114425616 |
| Directory | /workspace/18.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2433712211 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2020354548 ps |
| CPU time | 2.87 seconds |
| Started | Jan 21 12:50:10 PM PST 24 |
| Finished | Jan 21 12:50:14 PM PST 24 |
| Peak memory | 200352 kb |
| Host | smart-4f750bf6-6824-40f2-8181-5f1386561ce5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433712211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_te st.2433712211 |
| Directory | /workspace/18.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.536576659 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5677738466 ps |
| CPU time | 8.59 seconds |
| Started | Jan 21 12:22:09 PM PST 24 |
| Finished | Jan 21 12:22:21 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-291afb67-78c0-4ac7-8fab-a6ce6fcaf3b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536576659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .sysrst_ctrl_same_csr_outstanding.536576659 |
| Directory | /workspace/18.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2681632746 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 2048382311 ps |
| CPU time | 6.76 seconds |
| Started | Jan 21 01:00:32 PM PST 24 |
| Finished | Jan 21 01:00:41 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-f2bdc12f-07e8-4235-9cbc-a0955482f512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681632746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro rs.2681632746 |
| Directory | /workspace/18.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2276282414 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 42425986889 ps |
| CPU time | 58.24 seconds |
| Started | Jan 21 01:13:17 PM PST 24 |
| Finished | Jan 21 01:14:16 PM PST 24 |
| Peak memory | 201244 kb |
| Host | smart-5ff0511c-cc1d-41b4-a1d2-c2771b69f695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276282414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ ctrl_tl_intg_err.2276282414 |
| Directory | /workspace/18.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272343999 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 2082458635 ps |
| CPU time | 6.36 seconds |
| Started | Jan 21 01:10:20 PM PST 24 |
| Finished | Jan 21 01:10:28 PM PST 24 |
| Peak memory | 200952 kb |
| Host | smart-7e0b58bc-67b6-4a15-bcdd-d5488fd081ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272343999 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272343999 |
| Directory | /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1208196782 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2033510349 ps |
| CPU time | 6.16 seconds |
| Started | Jan 21 12:22:04 PM PST 24 |
| Finished | Jan 21 12:22:12 PM PST 24 |
| Peak memory | 201132 kb |
| Host | smart-a3e151f1-88de-45d8-af75-e0ca01dace02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208196782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_ rw.1208196782 |
| Directory | /workspace/19.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.394267563 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2010243158 ps |
| CPU time | 5.51 seconds |
| Started | Jan 21 12:22:02 PM PST 24 |
| Finished | Jan 21 12:22:08 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-7c6a0482-10aa-4261-94d7-e2f4a7675e1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394267563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_tes t.394267563 |
| Directory | /workspace/19.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4093033948 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 5243987407 ps |
| CPU time | 13.28 seconds |
| Started | Jan 21 01:01:38 PM PST 24 |
| Finished | Jan 21 01:01:52 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-b3789d95-dcd9-4ca8-ae5e-c0aad863ece9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093033948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 9.sysrst_ctrl_same_csr_outstanding.4093033948 |
| Directory | /workspace/19.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2052964166 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2138216953 ps |
| CPU time | 4.37 seconds |
| Started | Jan 21 01:05:39 PM PST 24 |
| Finished | Jan 21 01:05:45 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-bff29458-c60f-4309-9fc2-d0a19a622276 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052964166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro rs.2052964166 |
| Directory | /workspace/19.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2914410648 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 2523298466 ps |
| CPU time | 5.57 seconds |
| Started | Jan 21 12:22:21 PM PST 24 |
| Finished | Jan 21 12:22:28 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-2c4e130e-8994-4ce0-8f1e-c36dd87649ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914410648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl _csr_aliasing.2914410648 |
| Directory | /workspace/2.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2905394092 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 34685255752 ps |
| CPU time | 67.81 seconds |
| Started | Jan 21 12:24:22 PM PST 24 |
| Finished | Jan 21 12:25:35 PM PST 24 |
| Peak memory | 200088 kb |
| Host | smart-8c67336f-bb62-485f-bed9-b0f13dc7161a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905394092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl _csr_bit_bash.2905394092 |
| Directory | /workspace/2.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1747505142 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 4016650719 ps |
| CPU time | 11.17 seconds |
| Started | Jan 21 12:54:38 PM PST 24 |
| Finished | Jan 21 12:54:50 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-dffa7540-f236-440d-a849-5a2b356c64ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747505142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl _csr_hw_reset.1747505142 |
| Directory | /workspace/2.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.446993428 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2120704221 ps |
| CPU time | 2.58 seconds |
| Started | Jan 21 12:24:19 PM PST 24 |
| Finished | Jan 21 12:24:23 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-e25bc7c7-39cf-4d1d-b124-19b3fe0a135c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446993428 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.446993428 |
| Directory | /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1399088329 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2084564633 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 12:24:37 PM PST 24 |
| Finished | Jan 21 12:24:40 PM PST 24 |
| Peak memory | 200728 kb |
| Host | smart-b14fce5b-6c44-46fe-b52f-e1bb850e67fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399088329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r w.1399088329 |
| Directory | /workspace/2.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3760984165 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 2023898693 ps |
| CPU time | 3.16 seconds |
| Started | Jan 21 12:24:49 PM PST 24 |
| Finished | Jan 21 12:24:53 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-ab5caf37-db3d-4a5e-b692-255c4c4daef3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760984165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes t.3760984165 |
| Directory | /workspace/2.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3892389436 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 4567049758 ps |
| CPU time | 16.23 seconds |
| Started | Jan 21 12:24:49 PM PST 24 |
| Finished | Jan 21 12:25:06 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-e870e467-ebbf-4997-81eb-a0858c900c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892389436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2 .sysrst_ctrl_same_csr_outstanding.3892389436 |
| Directory | /workspace/2.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1038099337 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2351688958 ps |
| CPU time | 3.31 seconds |
| Started | Jan 21 12:24:53 PM PST 24 |
| Finished | Jan 21 12:24:58 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-4483b06c-a3e8-4efd-b83b-ea37e68a2822 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038099337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_error s.1038099337 |
| Directory | /workspace/2.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1577179324 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 42808167715 ps |
| CPU time | 32.12 seconds |
| Started | Jan 21 12:20:44 PM PST 24 |
| Finished | Jan 21 12:21:17 PM PST 24 |
| Peak memory | 201464 kb |
| Host | smart-d4a8d6c1-2382-4bad-8bfb-922489b8d3ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577179324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c trl_tl_intg_err.1577179324 |
| Directory | /workspace/2.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2802483188 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2014485973 ps |
| CPU time | 5.47 seconds |
| Started | Jan 21 12:58:06 PM PST 24 |
| Finished | Jan 21 12:58:13 PM PST 24 |
| Peak memory | 200304 kb |
| Host | smart-bc04a418-2196-4233-9d86-b7fcc06aab4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802483188 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_te st.2802483188 |
| Directory | /workspace/20.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2330877721 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 2012325908 ps |
| CPU time | 5.79 seconds |
| Started | Jan 21 01:01:22 PM PST 24 |
| Finished | Jan 21 01:01:29 PM PST 24 |
| Peak memory | 200532 kb |
| Host | smart-94c256ff-efb0-4417-adef-dd79ec22156e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330877721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te st.2330877721 |
| Directory | /workspace/21.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1044474067 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2014583800 ps |
| CPU time | 5.81 seconds |
| Started | Jan 21 12:47:05 PM PST 24 |
| Finished | Jan 21 12:47:11 PM PST 24 |
| Peak memory | 200544 kb |
| Host | smart-7a8e79d2-3220-460c-9152-5635aeeec1d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044474067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_te st.1044474067 |
| Directory | /workspace/23.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4278932405 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2015203840 ps |
| CPU time | 5.56 seconds |
| Started | Jan 21 12:24:46 PM PST 24 |
| Finished | Jan 21 12:24:52 PM PST 24 |
| Peak memory | 200572 kb |
| Host | smart-7d03c904-5944-4c1a-ac56-b822ff221394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278932405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_te st.4278932405 |
| Directory | /workspace/24.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2350210391 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 2029900058 ps |
| CPU time | 2.06 seconds |
| Started | Jan 21 12:22:10 PM PST 24 |
| Finished | Jan 21 12:22:15 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-cd8eead3-67d3-4c00-a302-61fbe5449cfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350210391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te st.2350210391 |
| Directory | /workspace/25.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3423510556 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2060402630 ps |
| CPU time | 1.55 seconds |
| Started | Jan 21 12:22:58 PM PST 24 |
| Finished | Jan 21 12:23:00 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-a0c1f301-5639-461d-b2fe-47dd98976db9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423510556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te st.3423510556 |
| Directory | /workspace/26.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3377054006 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2135014958 ps |
| CPU time | 1 seconds |
| Started | Jan 21 12:24:53 PM PST 24 |
| Finished | Jan 21 12:24:56 PM PST 24 |
| Peak memory | 200400 kb |
| Host | smart-af2728c7-b7e7-4f44-8972-0977b13e7b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377054006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te st.3377054006 |
| Directory | /workspace/27.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2471598043 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2023718065 ps |
| CPU time | 3.36 seconds |
| Started | Jan 21 12:22:44 PM PST 24 |
| Finished | Jan 21 12:22:48 PM PST 24 |
| Peak memory | 200376 kb |
| Host | smart-2e0ba80c-b394-4313-9d6b-c07a0513b102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471598043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te st.2471598043 |
| Directory | /workspace/28.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.617205868 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 2030285252 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 12:46:42 PM PST 24 |
| Finished | Jan 21 12:46:45 PM PST 24 |
| Peak memory | 200524 kb |
| Host | smart-59daa929-3b7f-432c-a5cc-144d277d9379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617205868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_tes t.617205868 |
| Directory | /workspace/29.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.3079620722 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 2705821771 ps |
| CPU time | 10.69 seconds |
| Started | Jan 21 12:24:18 PM PST 24 |
| Finished | Jan 21 12:24:30 PM PST 24 |
| Peak memory | 199772 kb |
| Host | smart-b612a21d-2b66-4c87-9beb-ca5fd27657ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079620722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl _csr_aliasing.3079620722 |
| Directory | /workspace/3.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.896393600 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 64538236217 ps |
| CPU time | 76.2 seconds |
| Started | Jan 21 12:33:56 PM PST 24 |
| Finished | Jan 21 12:35:13 PM PST 24 |
| Peak memory | 200984 kb |
| Host | smart-e02989f6-79f5-44d0-a183-936762327bbb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896393600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ csr_bit_bash.896393600 |
| Directory | /workspace/3.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.597809967 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6031030543 ps |
| CPU time | 8.66 seconds |
| Started | Jan 21 12:48:48 PM PST 24 |
| Finished | Jan 21 12:48:58 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-4f27d886-11f7-41a5-977c-ded30534f133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597809967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ csr_hw_reset.597809967 |
| Directory | /workspace/3.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3686059347 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 2107217587 ps |
| CPU time | 2.6 seconds |
| Started | Jan 21 12:29:45 PM PST 24 |
| Finished | Jan 21 12:29:51 PM PST 24 |
| Peak memory | 210140 kb |
| Host | smart-d74cdbf1-8039-4bca-827c-8621c84839c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686059347 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.3686059347 |
| Directory | /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2018794102 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 2100686586 ps |
| CPU time | 1.69 seconds |
| Started | Jan 21 12:43:01 PM PST 24 |
| Finished | Jan 21 12:43:04 PM PST 24 |
| Peak memory | 200828 kb |
| Host | smart-6175f8b7-3625-4301-a465-8cb769c09dde |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018794102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r w.2018794102 |
| Directory | /workspace/3.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1809496853 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2036682883 ps |
| CPU time | 2.03 seconds |
| Started | Jan 21 12:47:12 PM PST 24 |
| Finished | Jan 21 12:47:14 PM PST 24 |
| Peak memory | 200376 kb |
| Host | smart-982c599d-d18e-4294-83f5-297388b1bbba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809496853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes t.1809496853 |
| Directory | /workspace/3.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.1242154578 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 10145900278 ps |
| CPU time | 39.02 seconds |
| Started | Jan 21 12:23:22 PM PST 24 |
| Finished | Jan 21 12:24:01 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-5feef085-65d3-4a10-a962-a5b968560e30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242154578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3 .sysrst_ctrl_same_csr_outstanding.1242154578 |
| Directory | /workspace/3.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.2047268247 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2756915509 ps |
| CPU time | 1.97 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:06 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-f1e27db8-f46f-4121-8fb4-1bd5764b1d32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047268247 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error s.2047268247 |
| Directory | /workspace/3.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2674016043 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 22247600512 ps |
| CPU time | 53.69 seconds |
| Started | Jan 21 12:47:47 PM PST 24 |
| Finished | Jan 21 12:48:41 PM PST 24 |
| Peak memory | 201140 kb |
| Host | smart-e8990662-9f19-4a8d-b788-a9ed3446a98c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674016043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c trl_tl_intg_err.2674016043 |
| Directory | /workspace/3.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.1853166463 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2061022459 ps |
| CPU time | 1.48 seconds |
| Started | Jan 21 12:24:52 PM PST 24 |
| Finished | Jan 21 12:24:56 PM PST 24 |
| Peak memory | 200568 kb |
| Host | smart-ec488551-9664-4a1d-a59d-e3eb4de38368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853166463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te st.1853166463 |
| Directory | /workspace/30.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2337683083 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2047662979 ps |
| CPU time | 2.03 seconds |
| Started | Jan 21 12:22:58 PM PST 24 |
| Finished | Jan 21 12:23:01 PM PST 24 |
| Peak memory | 200816 kb |
| Host | smart-b39edbed-2807-4ca8-b702-16eec8849127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337683083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te st.2337683083 |
| Directory | /workspace/31.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.160594222 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 2033794886 ps |
| CPU time | 2.02 seconds |
| Started | Jan 21 12:22:49 PM PST 24 |
| Finished | Jan 21 12:22:51 PM PST 24 |
| Peak memory | 200704 kb |
| Host | smart-04a4928e-3a25-4462-b9c7-fc5c012d74c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160594222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_tes t.160594222 |
| Directory | /workspace/32.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3789874493 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2022553665 ps |
| CPU time | 2 seconds |
| Started | Jan 21 12:22:42 PM PST 24 |
| Finished | Jan 21 12:22:45 PM PST 24 |
| Peak memory | 200856 kb |
| Host | smart-8e25a9d9-fa6b-427d-be3a-fa1c270432fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789874493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te st.3789874493 |
| Directory | /workspace/33.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1883899108 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2014680447 ps |
| CPU time | 6.21 seconds |
| Started | Jan 21 12:22:43 PM PST 24 |
| Finished | Jan 21 12:22:50 PM PST 24 |
| Peak memory | 200392 kb |
| Host | smart-1d461aa3-37b6-4093-b2cd-b5ee9595f145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883899108 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te st.1883899108 |
| Directory | /workspace/34.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1082354682 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2024540470 ps |
| CPU time | 1.81 seconds |
| Started | Jan 21 12:40:21 PM PST 24 |
| Finished | Jan 21 12:40:23 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-d5b52eb5-6e59-469a-bdcd-448da8ccea19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082354682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te st.1082354682 |
| Directory | /workspace/35.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.4099971795 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 2011887776 ps |
| CPU time | 5.92 seconds |
| Started | Jan 21 12:32:20 PM PST 24 |
| Finished | Jan 21 12:32:35 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-c44a5745-9de8-4801-83e2-3efa219bf1ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099971795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te st.4099971795 |
| Directory | /workspace/36.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3497015882 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2049873708 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 12:25:02 PM PST 24 |
| Finished | Jan 21 12:25:07 PM PST 24 |
| Peak memory | 200572 kb |
| Host | smart-9a795412-fbf1-41d7-b405-fee2744cc64d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497015882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_te st.3497015882 |
| Directory | /workspace/37.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2739277480 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2030318326 ps |
| CPU time | 2.02 seconds |
| Started | Jan 21 12:22:53 PM PST 24 |
| Finished | Jan 21 12:22:56 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-5942344c-dbb6-46c2-a74f-18e7153f54bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739277480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_te st.2739277480 |
| Directory | /workspace/38.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1848378176 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 2017069125 ps |
| CPU time | 5.96 seconds |
| Started | Jan 21 12:22:58 PM PST 24 |
| Finished | Jan 21 12:23:05 PM PST 24 |
| Peak memory | 200472 kb |
| Host | smart-69a5bcaf-5450-4f5c-b8df-b2a318760fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848378176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te st.1848378176 |
| Directory | /workspace/39.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2246954219 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2444476624 ps |
| CPU time | 3.71 seconds |
| Started | Jan 21 12:53:29 PM PST 24 |
| Finished | Jan 21 12:53:35 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-c4373384-dcea-4838-847a-6c875768f296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246954219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl _csr_aliasing.2246954219 |
| Directory | /workspace/4.sysrst_ctrl_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1428163008 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 40557595976 ps |
| CPU time | 79.96 seconds |
| Started | Jan 21 12:24:19 PM PST 24 |
| Finished | Jan 21 12:25:40 PM PST 24 |
| Peak memory | 200652 kb |
| Host | smart-0e1f9e51-6636-4570-84dc-a18e8395671c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428163008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl _csr_bit_bash.1428163008 |
| Directory | /workspace/4.sysrst_ctrl_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2095640668 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 4044243481 ps |
| CPU time | 2.94 seconds |
| Started | Jan 21 01:50:09 PM PST 24 |
| Finished | Jan 21 01:50:18 PM PST 24 |
| Peak memory | 200796 kb |
| Host | smart-47d07fe4-4589-443b-ad43-27b09cee481c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095640668 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl _csr_hw_reset.2095640668 |
| Directory | /workspace/4.sysrst_ctrl_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3546153232 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2032086527 ps |
| CPU time | 5.84 seconds |
| Started | Jan 21 01:00:27 PM PST 24 |
| Finished | Jan 21 01:00:35 PM PST 24 |
| Peak memory | 200780 kb |
| Host | smart-74045b0d-9bf6-4175-9654-5fe0b4a61c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546153232 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.3546153232 |
| Directory | /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1566888412 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2039592625 ps |
| CPU time | 5.61 seconds |
| Started | Jan 21 12:24:45 PM PST 24 |
| Finished | Jan 21 12:24:52 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-f54ea34e-40f8-44aa-bf7b-f2cc8c198f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566888412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r w.1566888412 |
| Directory | /workspace/4.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2663583052 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2073945900 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 01:08:00 PM PST 24 |
| Finished | Jan 21 01:08:04 PM PST 24 |
| Peak memory | 200612 kb |
| Host | smart-8b2911c6-b456-4c12-a513-77b81dff34b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663583052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes t.2663583052 |
| Directory | /workspace/4.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.4046922896 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 8652826010 ps |
| CPU time | 23.61 seconds |
| Started | Jan 21 12:23:22 PM PST 24 |
| Finished | Jan 21 12:23:46 PM PST 24 |
| Peak memory | 200976 kb |
| Host | smart-42c27524-71ae-4f0a-be76-22e7680fbd85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046922896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4 .sysrst_ctrl_same_csr_outstanding.4046922896 |
| Directory | /workspace/4.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1275580321 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2032622933 ps |
| CPU time | 7.22 seconds |
| Started | Jan 21 12:21:25 PM PST 24 |
| Finished | Jan 21 12:21:34 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-0afb3e09-b4e1-4d79-a645-71574d302023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275580321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_error s.1275580321 |
| Directory | /workspace/4.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1973447611 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 22447259793 ps |
| CPU time | 16.71 seconds |
| Started | Jan 21 12:24:49 PM PST 24 |
| Finished | Jan 21 12:25:07 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-7af12b6c-457e-42a1-aa56-00e29417489c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973447611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_c trl_tl_intg_err.1973447611 |
| Directory | /workspace/4.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1301379209 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 2013476325 ps |
| CPU time | 5.64 seconds |
| Started | Jan 21 01:23:04 PM PST 24 |
| Finished | Jan 21 01:23:11 PM PST 24 |
| Peak memory | 200628 kb |
| Host | smart-568ba7a3-ed95-4869-84da-a79cccd32b8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301379209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_te st.1301379209 |
| Directory | /workspace/40.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.899356132 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2012281886 ps |
| CPU time | 5.67 seconds |
| Started | Jan 21 12:25:02 PM PST 24 |
| Finished | Jan 21 12:25:10 PM PST 24 |
| Peak memory | 200540 kb |
| Host | smart-ef9d62e1-0852-4b72-bf63-6b368dfd5f88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899356132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_tes t.899356132 |
| Directory | /workspace/41.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.3784617023 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2009425348 ps |
| CPU time | 5.83 seconds |
| Started | Jan 21 12:25:02 PM PST 24 |
| Finished | Jan 21 12:25:10 PM PST 24 |
| Peak memory | 200436 kb |
| Host | smart-36dbecb6-291a-4898-92b5-96889ff3941b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784617023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te st.3784617023 |
| Directory | /workspace/42.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3263107470 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 2016828388 ps |
| CPU time | 3.4 seconds |
| Started | Jan 21 12:59:56 PM PST 24 |
| Finished | Jan 21 01:00:00 PM PST 24 |
| Peak memory | 200440 kb |
| Host | smart-ff426873-8e0b-407b-8597-94fdd474de66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263107470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te st.3263107470 |
| Directory | /workspace/43.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.4167432468 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 2010451723 ps |
| CPU time | 5.8 seconds |
| Started | Jan 21 12:25:02 PM PST 24 |
| Finished | Jan 21 12:25:11 PM PST 24 |
| Peak memory | 200500 kb |
| Host | smart-abba8724-1948-41bc-8123-e9a3fd18b3e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167432468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te st.4167432468 |
| Directory | /workspace/44.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.970699765 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2026801350 ps |
| CPU time | 3.25 seconds |
| Started | Jan 21 12:22:58 PM PST 24 |
| Finished | Jan 21 12:23:02 PM PST 24 |
| Peak memory | 200536 kb |
| Host | smart-65e529ea-780b-4104-baea-8d2ff9dff461 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970699765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_tes t.970699765 |
| Directory | /workspace/45.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.436721208 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 2012835929 ps |
| CPU time | 6.33 seconds |
| Started | Jan 21 12:22:58 PM PST 24 |
| Finished | Jan 21 12:23:05 PM PST 24 |
| Peak memory | 200344 kb |
| Host | smart-386ce190-71d1-46d6-9816-7d519e4800fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436721208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_tes t.436721208 |
| Directory | /workspace/46.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.698069956 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2033522741 ps |
| CPU time | 1.89 seconds |
| Started | Jan 21 12:46:42 PM PST 24 |
| Finished | Jan 21 12:46:45 PM PST 24 |
| Peak memory | 200552 kb |
| Host | smart-1ee91d40-ce66-4289-9606-e284caa1895a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698069956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_tes t.698069956 |
| Directory | /workspace/47.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3218539371 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2108919720 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:25:01 PM PST 24 |
| Finished | Jan 21 12:25:05 PM PST 24 |
| Peak memory | 200572 kb |
| Host | smart-782900a5-673b-4f13-b4be-4239e27db6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218539371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_te st.3218539371 |
| Directory | /workspace/48.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2990557723 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2083609874 ps |
| CPU time | 1.43 seconds |
| Started | Jan 21 12:24:36 PM PST 24 |
| Finished | Jan 21 12:24:39 PM PST 24 |
| Peak memory | 199376 kb |
| Host | smart-db4393c8-8a9b-41e4-8deb-5a2907ecf40d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990557723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_te st.2990557723 |
| Directory | /workspace/49.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.795319197 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2216346546 ps |
| CPU time | 1.29 seconds |
| Started | Jan 21 12:38:19 PM PST 24 |
| Finished | Jan 21 12:38:22 PM PST 24 |
| Peak memory | 200804 kb |
| Host | smart-c729ead3-e869-4893-a689-d8cac64c0922 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795319197 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.795319197 |
| Directory | /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.407516555 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2035915330 ps |
| CPU time | 6.36 seconds |
| Started | Jan 21 12:22:42 PM PST 24 |
| Finished | Jan 21 12:22:50 PM PST 24 |
| Peak memory | 200640 kb |
| Host | smart-4a822a2e-7069-4fec-8a66-44da01232076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407516555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw .407516555 |
| Directory | /workspace/5.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3076396111 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2071730983 ps |
| CPU time | 1.21 seconds |
| Started | Jan 21 12:53:26 PM PST 24 |
| Finished | Jan 21 12:53:30 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-2f1dff11-12d1-4e0a-b392-d1fc43d671a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076396111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes t.3076396111 |
| Directory | /workspace/5.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.2531941028 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 8592980518 ps |
| CPU time | 23.12 seconds |
| Started | Jan 21 01:08:49 PM PST 24 |
| Finished | Jan 21 01:09:14 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-75d3a117-64e2-4647-b1cd-d4b2c56ea482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531941028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5 .sysrst_ctrl_same_csr_outstanding.2531941028 |
| Directory | /workspace/5.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.270120932 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 2050456378 ps |
| CPU time | 6.68 seconds |
| Started | Jan 21 02:30:38 PM PST 24 |
| Finished | Jan 21 02:30:45 PM PST 24 |
| Peak memory | 201216 kb |
| Host | smart-d298af4a-7bb2-4ce5-ae9e-a71763739e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270120932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors .270120932 |
| Directory | /workspace/5.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.166535678 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 42636470824 ps |
| CPU time | 55.84 seconds |
| Started | Jan 21 12:42:03 PM PST 24 |
| Finished | Jan 21 12:42:59 PM PST 24 |
| Peak memory | 201216 kb |
| Host | smart-994715f0-e696-4449-a1d8-53e64fcf271e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166535678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ct rl_tl_intg_err.166535678 |
| Directory | /workspace/5.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2189915104 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2458518980 ps |
| CPU time | 1.52 seconds |
| Started | Jan 21 01:11:03 PM PST 24 |
| Finished | Jan 21 01:11:09 PM PST 24 |
| Peak memory | 200952 kb |
| Host | smart-f2d842e5-e349-4fba-a550-6e86d32739fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189915104 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.2189915104 |
| Directory | /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1298431784 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2037884719 ps |
| CPU time | 6.16 seconds |
| Started | Jan 21 12:24:46 PM PST 24 |
| Finished | Jan 21 12:24:53 PM PST 24 |
| Peak memory | 200700 kb |
| Host | smart-6a5641f7-800f-484d-a6f4-7d7f56e0d22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298431784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_r w.1298431784 |
| Directory | /workspace/6.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1881715655 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 2075560784 ps |
| CPU time | 0.98 seconds |
| Started | Jan 21 12:58:03 PM PST 24 |
| Finished | Jan 21 12:58:05 PM PST 24 |
| Peak memory | 200556 kb |
| Host | smart-0c54530e-700c-4bef-9d32-7e04fea8bea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881715655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes t.1881715655 |
| Directory | /workspace/6.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.788418074 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4807995562 ps |
| CPU time | 3.97 seconds |
| Started | Jan 21 12:58:10 PM PST 24 |
| Finished | Jan 21 12:58:15 PM PST 24 |
| Peak memory | 200844 kb |
| Host | smart-4b921ab0-32c3-4d4c-be80-fab38c95fcdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788418074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ =sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6. sysrst_ctrl_same_csr_outstanding.788418074 |
| Directory | /workspace/6.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1160605891 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2095934985 ps |
| CPU time | 2.65 seconds |
| Started | Jan 21 01:57:19 PM PST 24 |
| Finished | Jan 21 01:57:23 PM PST 24 |
| Peak memory | 201096 kb |
| Host | smart-296b1cc1-2a47-48c7-a29c-a30af2f17548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160605891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_error s.1160605891 |
| Directory | /workspace/6.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2804986841 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 42746241185 ps |
| CPU time | 20.71 seconds |
| Started | Jan 21 12:22:42 PM PST 24 |
| Finished | Jan 21 12:23:04 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-64b0a03f-6a02-4995-abca-a73ccd2eefaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804986841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c trl_tl_intg_err.2804986841 |
| Directory | /workspace/6.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2355397234 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 2044039663 ps |
| CPU time | 5.46 seconds |
| Started | Jan 21 12:42:25 PM PST 24 |
| Finished | Jan 21 12:42:31 PM PST 24 |
| Peak memory | 200760 kb |
| Host | smart-0418af48-cc24-47f7-91ea-7c1198bbb436 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355397234 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.2355397234 |
| Directory | /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.156698672 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2062733022 ps |
| CPU time | 3.79 seconds |
| Started | Jan 21 12:37:18 PM PST 24 |
| Finished | Jan 21 12:37:23 PM PST 24 |
| Peak memory | 200736 kb |
| Host | smart-b9e0330c-4793-4662-9cc4-768356794d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156698672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw .156698672 |
| Directory | /workspace/7.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2705923326 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 2013635103 ps |
| CPU time | 5.12 seconds |
| Started | Jan 21 12:44:53 PM PST 24 |
| Finished | Jan 21 12:44:59 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-9c3a6f2e-87c9-4ffb-af27-2c8ef5f50e0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705923326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes t.2705923326 |
| Directory | /workspace/7.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1831239728 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 8202361276 ps |
| CPU time | 20.53 seconds |
| Started | Jan 21 01:00:22 PM PST 24 |
| Finished | Jan 21 01:00:44 PM PST 24 |
| Peak memory | 201232 kb |
| Host | smart-d2bfddd0-48cb-4c56-8e6f-0a9346f44d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831239728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7 .sysrst_ctrl_same_csr_outstanding.1831239728 |
| Directory | /workspace/7.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2699693997 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 2236068192 ps |
| CPU time | 2.7 seconds |
| Started | Jan 21 01:25:54 PM PST 24 |
| Finished | Jan 21 01:25:57 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-3179fc77-8a5c-44fb-9908-146b01acecaa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699693997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_error s.2699693997 |
| Directory | /workspace/7.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.534476789 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 42398183396 ps |
| CPU time | 113.23 seconds |
| Started | Jan 21 12:48:07 PM PST 24 |
| Finished | Jan 21 12:50:05 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-5c2360b1-c6f3-4404-baa8-c47ec406d85f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534476789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ct rl_tl_intg_err.534476789 |
| Directory | /workspace/7.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2279343677 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2068286853 ps |
| CPU time | 4.13 seconds |
| Started | Jan 21 12:19:39 PM PST 24 |
| Finished | Jan 21 12:19:44 PM PST 24 |
| Peak memory | 201168 kb |
| Host | smart-13997c18-d6f9-45aa-9d2d-795ddb862096 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279343677 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2279343677 |
| Directory | /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.841012914 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2097174428 ps |
| CPU time | 1.88 seconds |
| Started | Jan 21 12:20:27 PM PST 24 |
| Finished | Jan 21 12:20:29 PM PST 24 |
| Peak memory | 200708 kb |
| Host | smart-0c6180c8-5c21-4cb8-b25e-df587964347d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841012914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw .841012914 |
| Directory | /workspace/8.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.937982686 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2027288999 ps |
| CPU time | 3.29 seconds |
| Started | Jan 21 12:26:58 PM PST 24 |
| Finished | Jan 21 12:27:02 PM PST 24 |
| Peak memory | 200444 kb |
| Host | smart-ef65e7fa-9387-491d-8c6a-8a7dc9253940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937982686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test .937982686 |
| Directory | /workspace/8.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2063802870 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 9717517651 ps |
| CPU time | 27.27 seconds |
| Started | Jan 21 12:23:10 PM PST 24 |
| Finished | Jan 21 12:23:38 PM PST 24 |
| Peak memory | 201212 kb |
| Host | smart-1f76838e-80ea-425f-a77e-8a006dc4e381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063802870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8 .sysrst_ctrl_same_csr_outstanding.2063802870 |
| Directory | /workspace/8.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3079641975 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 22194198698 ps |
| CPU time | 56.87 seconds |
| Started | Jan 21 12:53:42 PM PST 24 |
| Finished | Jan 21 12:54:42 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-95c4954f-bb67-4465-8904-aa07ab66e5f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079641975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c trl_tl_intg_err.3079641975 |
| Directory | /workspace/8.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.534593055 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 2333564354 ps |
| CPU time | 1.54 seconds |
| Started | Jan 21 12:52:15 PM PST 24 |
| Finished | Jan 21 12:52:17 PM PST 24 |
| Peak memory | 200864 kb |
| Host | smart-038c134b-8026-4848-a0a5-3c5b45ea7efb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534593055 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.534593055 |
| Directory | /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.246675021 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2083240376 ps |
| CPU time | 2.01 seconds |
| Started | Jan 21 12:21:49 PM PST 24 |
| Finished | Jan 21 12:21:59 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-8687a88c-f6dd-450c-b30d-c749cefd63fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246675021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw .246675021 |
| Directory | /workspace/9.sysrst_ctrl_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3774085523 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 2023496491 ps |
| CPU time | 3.28 seconds |
| Started | Jan 21 12:24:43 PM PST 24 |
| Finished | Jan 21 12:24:47 PM PST 24 |
| Peak memory | 199996 kb |
| Host | smart-95cde632-801a-419a-b6ec-4b3585624d04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774085523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_tes t.3774085523 |
| Directory | /workspace/9.sysrst_ctrl_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2536758539 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 8637406115 ps |
| CPU time | 3.71 seconds |
| Started | Jan 21 01:02:46 PM PST 24 |
| Finished | Jan 21 01:02:51 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-63b472d8-00ea-42c3-8faf-39be8433d3a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536758539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9 .sysrst_ctrl_same_csr_outstanding.2536758539 |
| Directory | /workspace/9.sysrst_ctrl_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2492889024 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2025490388 ps |
| CPU time | 6.59 seconds |
| Started | Jan 21 12:21:49 PM PST 24 |
| Finished | Jan 21 12:22:04 PM PST 24 |
| Peak memory | 200844 kb |
| Host | smart-c586c165-7392-4dc0-a0d5-c99722205df6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492889024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error s.2492889024 |
| Directory | /workspace/9.sysrst_ctrl_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3886733371 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 22249463700 ps |
| CPU time | 54.49 seconds |
| Started | Jan 21 12:55:53 PM PST 24 |
| Finished | Jan 21 12:56:49 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-aef8f540-1595-4eb5-a8ba-e1e927b57624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886733371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c trl_tl_intg_err.3886733371 |
| Directory | /workspace/9.sysrst_ctrl_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_alert_test.1837152115 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 2071945972 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 12:26:40 PM PST 24 |
| Finished | Jan 21 12:26:43 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-9f6a82f9-c185-4c08-bc40-d6d8c91e66f5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837152115 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes t.1837152115 |
| Directory | /workspace/0.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3435683755 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3284449561 ps |
| CPU time | 8.69 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:26:57 PM PST 24 |
| Peak memory | 201116 kb |
| Host | smart-97bd497e-984e-4890-b17c-193711045b73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3435683755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.3435683755 |
| Directory | /workspace/0.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_combo_detect.2671586409 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 100480495129 ps |
| CPU time | 66.76 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:27:55 PM PST 24 |
| Peak memory | 201192 kb |
| Host | smart-339f625f-74eb-4b04-b7ae-6162e5bc5427 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671586409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct rl_combo_detect.2671586409 |
| Directory | /workspace/0.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.1296873698 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2406814361 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 12:26:25 PM PST 24 |
| Finished | Jan 21 12:26:30 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-ae88999b-c71b-4fd9-aabb-2a89d8b58799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1296873698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.1296873698 |
| Directory | /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.140497441 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 2365439071 ps |
| CPU time | 2.16 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:26:50 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-2a79a0b7-aaef-458b-8a1a-73faf55ccef7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140497441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_ cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det ect_ec_rst_with_pre_cond.140497441 |
| Directory | /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.2679531961 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 2962604295 ps |
| CPU time | 3.07 seconds |
| Started | Jan 21 12:26:25 PM PST 24 |
| Finished | Jan 21 12:26:28 PM PST 24 |
| Peak memory | 201088 kb |
| Host | smart-5fae590e-8491-47cf-b9d7-33728d9642ac |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679531961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c trl_ec_pwr_on_rst.2679531961 |
| Directory | /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_edge_detect.298420143 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 438320534969 ps |
| CPU time | 264.32 seconds |
| Started | Jan 21 12:26:43 PM PST 24 |
| Finished | Jan 21 12:31:12 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-b32e3faf-94aa-49b6-a0c9-ffcafc2f2c6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298420143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl _edge_detect.298420143 |
| Directory | /workspace/0.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.634576745 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2613663429 ps |
| CPU time | 7.63 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:26:56 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-779f0f31-f527-4c0d-aff8-1c14fc95a611 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634576745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.634576745 |
| Directory | /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.327407934 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2462917257 ps |
| CPU time | 2.57 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:26:51 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-d0a8ab16-fc3d-4252-b09f-f4a778214d67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=327407934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.327407934 |
| Directory | /workspace/0.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.2752399418 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2212729696 ps |
| CPU time | 6.39 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:26:54 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-dd2cc219-0b67-49f3-89e0-63487b9b887e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752399418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.2752399418 |
| Directory | /workspace/0.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3599633005 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 2517457506 ps |
| CPU time | 3.29 seconds |
| Started | Jan 21 12:26:25 PM PST 24 |
| Finished | Jan 21 12:26:29 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-e70816d7-5837-4566-80d6-8a3859f26c9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599633005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3599633005 |
| Directory | /workspace/0.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_smoke.2276952672 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2123129721 ps |
| CPU time | 3.17 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:26:51 PM PST 24 |
| Peak memory | 200980 kb |
| Host | smart-15234764-784f-4611-810c-e2915b8be970 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2276952672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2276952672 |
| Directory | /workspace/0.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_stress_all.3045826001 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 14613249837 ps |
| CPU time | 35.64 seconds |
| Started | Jan 21 12:26:45 PM PST 24 |
| Finished | Jan 21 12:27:24 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-f246657d-4b58-4ec6-b5b8-7b76bacf2fdd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045826001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st ress_all.3045826001 |
| Directory | /workspace/0.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.3051257762 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 42852890767 ps |
| CPU time | 30.28 seconds |
| Started | Jan 21 12:26:42 PM PST 24 |
| Finished | Jan 21 12:27:18 PM PST 24 |
| Peak memory | 209284 kb |
| Host | smart-be80dd4d-d976-4fb0-9456-c7c6e2c1883d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051257762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.3051257762 |
| Directory | /workspace/0.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.648959611 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 5397152371 ps |
| CPU time | 1.95 seconds |
| Started | Jan 21 12:26:28 PM PST 24 |
| Finished | Jan 21 12:26:33 PM PST 24 |
| Peak memory | 201484 kb |
| Host | smart-a78d3e05-e105-41de-b852-bad1117daac8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648959611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct rl_ultra_low_pwr.648959611 |
| Directory | /workspace/0.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2580432570 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 163716756257 ps |
| CPU time | 425.83 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:34:15 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-eb7ac519-bd9d-4bcf-9745-67e07e0e5c8b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580432570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct rl_combo_detect.2580432570 |
| Directory | /workspace/1.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.1078718262 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2209268523 ps |
| CPU time | 3.56 seconds |
| Started | Jan 21 12:26:34 PM PST 24 |
| Finished | Jan 21 12:26:38 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-ce39dfcd-ba13-4bc2-b341-1a7d4ede168d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078718262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.1078718262 |
| Directory | /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1172651537 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2531321085 ps |
| CPU time | 6.85 seconds |
| Started | Jan 21 12:26:37 PM PST 24 |
| Finished | Jan 21 12:26:44 PM PST 24 |
| Peak memory | 200964 kb |
| Host | smart-2777e85b-8efa-4e87-8876-86b7800b561f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1172651537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre _cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de tect_ec_rst_with_pre_cond.1172651537 |
| Directory | /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1728739540 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 4356227752 ps |
| CPU time | 11.27 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:21 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-a8d9d5aa-4584-4c0c-81e4-14ee3155368c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728739540 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c trl_ec_pwr_on_rst.1728739540 |
| Directory | /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_edge_detect.4029088720 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 156346051153 ps |
| CPU time | 171.88 seconds |
| Started | Jan 21 12:26:49 PM PST 24 |
| Finished | Jan 21 12:29:44 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-ae3f31c3-e9e1-4411-9ab2-1ce5414ea19d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029088720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr l_edge_detect.4029088720 |
| Directory | /workspace/1.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.377334852 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2630774847 ps |
| CPU time | 2.55 seconds |
| Started | Jan 21 12:26:47 PM PST 24 |
| Finished | Jan 21 12:26:54 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-9379cb15-e2f5-48b5-9ef8-95db0accca67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=377334852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.377334852 |
| Directory | /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2125466522 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2479163929 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 12:26:41 PM PST 24 |
| Finished | Jan 21 12:26:48 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-41545527-012f-4761-a58a-697075ffe7fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2125466522 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2125466522 |
| Directory | /workspace/1.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.497880625 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 2159415653 ps |
| CPU time | 2.11 seconds |
| Started | Jan 21 12:26:42 PM PST 24 |
| Finished | Jan 21 12:26:49 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-beaa712c-0294-4d19-9862-084f4ce62ef6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497880625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.497880625 |
| Directory | /workspace/1.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.567752604 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2531166269 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:12 PM PST 24 |
| Peak memory | 200984 kb |
| Host | smart-c6868877-86b3-4a58-937f-6b8e444192eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567752604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.567752604 |
| Directory | /workspace/1.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_sec_cm.790775719 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 42223469683 ps |
| CPU time | 15.11 seconds |
| Started | Jan 21 12:26:44 PM PST 24 |
| Finished | Jan 21 12:27:03 PM PST 24 |
| Peak memory | 220644 kb |
| Host | smart-308fdb5a-f63b-4e44-ba17-1e495de651f7 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790775719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.790775719 |
| Directory | /workspace/1.sysrst_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_smoke.2822270795 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 2120860835 ps |
| CPU time | 3.31 seconds |
| Started | Jan 21 12:26:41 PM PST 24 |
| Finished | Jan 21 12:26:50 PM PST 24 |
| Peak memory | 200968 kb |
| Host | smart-fe7fa62f-c726-4113-9869-3ee1f0d47e3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822270795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2822270795 |
| Directory | /workspace/1.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_stress_all.2183572196 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 15605058136 ps |
| CPU time | 32.95 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:42 PM PST 24 |
| Peak memory | 201144 kb |
| Host | smart-94c78b8f-152b-4204-9c3e-5f27373f0797 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183572196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st ress_all.2183572196 |
| Directory | /workspace/1.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.623977672 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 10070437130 ps |
| CPU time | 1.62 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:11 PM PST 24 |
| Peak memory | 200884 kb |
| Host | smart-561ce9cb-96ad-4555-b59a-165dbeced99e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623977672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct rl_ultra_low_pwr.623977672 |
| Directory | /workspace/1.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_alert_test.2125718454 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2022349304 ps |
| CPU time | 2.76 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:03 PM PST 24 |
| Peak memory | 200972 kb |
| Host | smart-78008330-e086-443b-bbd2-ffef01d54777 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125718454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te st.2125718454 |
| Directory | /workspace/10.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.1165212109 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3233778759 ps |
| CPU time | 3.75 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:28:00 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-407f1e0c-4e36-4abf-9a80-0d9f7d50ef50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165212109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.1 165212109 |
| Directory | /workspace/10.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_combo_detect.1708585723 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 154925657490 ps |
| CPU time | 24.86 seconds |
| Started | Jan 21 12:27:53 PM PST 24 |
| Finished | Jan 21 12:28:19 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-32081c0e-633a-4fac-a2a3-03898e3c5dbd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708585723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c trl_combo_detect.1708585723 |
| Directory | /workspace/10.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.117780118 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 79228122063 ps |
| CPU time | 104.41 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:29:45 PM PST 24 |
| Peak memory | 200596 kb |
| Host | smart-3ef73b35-e2e1-46db-8455-cd4aae180a76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=117780118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_wi th_pre_cond.117780118 |
| Directory | /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1821850272 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 3161668274 ps |
| CPU time | 8.57 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:09 PM PST 24 |
| Peak memory | 200384 kb |
| Host | smart-8ffddbb6-d30c-46a5-bb63-1ec3384a5524 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821850272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ ctrl_ec_pwr_on_rst.1821850272 |
| Directory | /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1309743511 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4359892558 ps |
| CPU time | 4.15 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-7b4896c2-d334-4c15-9af5-0f1437144107 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309743511 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct rl_edge_detect.1309743511 |
| Directory | /workspace/10.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3524922395 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 2613541817 ps |
| CPU time | 4.96 seconds |
| Started | Jan 21 12:27:42 PM PST 24 |
| Finished | Jan 21 12:27:48 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-674cb5af-e7ed-4127-ae4a-e41c552503c9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524922395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3524922395 |
| Directory | /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.3178647195 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2468136053 ps |
| CPU time | 2.33 seconds |
| Started | Jan 21 12:27:52 PM PST 24 |
| Finished | Jan 21 12:27:55 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-310f2587-feb8-4247-88ce-3372027cf610 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3178647195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.3178647195 |
| Directory | /workspace/10.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.125143255 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2038319108 ps |
| CPU time | 1.79 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:27:58 PM PST 24 |
| Peak memory | 200920 kb |
| Host | smart-2337cb4f-2a49-418f-bd94-ccd966cc7e13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125143255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.125143255 |
| Directory | /workspace/10.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.2464959569 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2522373559 ps |
| CPU time | 3.92 seconds |
| Started | Jan 21 12:27:52 PM PST 24 |
| Finished | Jan 21 12:27:57 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-563bc50b-3ed4-4cc8-8065-b501502cd564 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464959569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.2464959569 |
| Directory | /workspace/10.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_smoke.574507413 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2115581173 ps |
| CPU time | 3.36 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:28:00 PM PST 24 |
| Peak memory | 200964 kb |
| Host | smart-5c58a61d-aa48-4b84-b4c0-60798ace7ea7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=574507413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.574507413 |
| Directory | /workspace/10.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.372884501 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 717858878095 ps |
| CPU time | 51.57 seconds |
| Started | Jan 21 12:27:44 PM PST 24 |
| Finished | Jan 21 12:28:36 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-d85b5042-8f3a-4e16-bb10-0d1211a3c0e8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372884501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c trl_ultra_low_pwr.372884501 |
| Directory | /workspace/10.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_alert_test.3106585681 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 2027945645 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 12:27:47 PM PST 24 |
| Finished | Jan 21 12:27:49 PM PST 24 |
| Peak memory | 200988 kb |
| Host | smart-6fca2ff3-6d78-41dc-8759-5b3b843650c9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106585681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te st.3106585681 |
| Directory | /workspace/11.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2966691116 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3329425296 ps |
| CPU time | 8.81 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-2f4e6632-0d01-49a4-a97b-391416763fd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2966691116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2 966691116 |
| Directory | /workspace/11.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2921446994 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 105670949348 ps |
| CPU time | 71.5 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:29:12 PM PST 24 |
| Peak memory | 200964 kb |
| Host | smart-1614a928-8488-4162-9acc-be23e1f9454b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921446994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c trl_combo_detect.2921446994 |
| Directory | /workspace/11.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3430869605 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 3196428456 ps |
| CPU time | 2.78 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-31684740-56e0-475e-b662-953d7deffc06 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430869605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ ctrl_ec_pwr_on_rst.3430869605 |
| Directory | /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.3945284436 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2618321742 ps |
| CPU time | 5.4 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:06 PM PST 24 |
| Peak memory | 200792 kb |
| Host | smart-dec23eaf-378e-4ec4-9287-04ea29f07c21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945284436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.3945284436 |
| Directory | /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1089050004 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2474123434 ps |
| CPU time | 7.33 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 200980 kb |
| Host | smart-62aa12a9-8509-4f96-9cfb-60f8deff492c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1089050004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1089050004 |
| Directory | /workspace/11.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.1904470451 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2133953055 ps |
| CPU time | 6.39 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:08 PM PST 24 |
| Peak memory | 200320 kb |
| Host | smart-4063b8da-8e74-4ffc-b411-3c7a834ce14c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1904470451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1904470451 |
| Directory | /workspace/11.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2088797065 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2526140262 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:27:59 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-2d89780b-8b0c-4213-852a-58448d4d6f40 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088797065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2088797065 |
| Directory | /workspace/11.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_smoke.2007461239 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 2206439032 ps |
| CPU time | 0.86 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:02 PM PST 24 |
| Peak memory | 200952 kb |
| Host | smart-1472e956-2c7f-4bc6-bff0-9d6d41f0ea12 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2007461239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2007461239 |
| Directory | /workspace/11.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1556394709 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 77590690877 ps |
| CPU time | 49.34 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:28:45 PM PST 24 |
| Peak memory | 217768 kb |
| Host | smart-e5ea3244-3792-45bc-b420-8ae6180c4a9e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556394709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.1556394709 |
| Directory | /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_alert_test.3682820816 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 2025243675 ps |
| CPU time | 2.81 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:27:58 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-34741a2c-bdf1-4d83-869b-16e66b364f4a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682820816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_te st.3682820816 |
| Directory | /workspace/12.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1112993253 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3266132739 ps |
| CPU time | 9.07 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:11 PM PST 24 |
| Peak memory | 200388 kb |
| Host | smart-83bc1d39-7fc7-4c8f-8e15-e207aea66814 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112993253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1 112993253 |
| Directory | /workspace/12.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_combo_detect.4189440338 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 128183588403 ps |
| CPU time | 317.5 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:33:13 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-3e34bdfe-67d9-4f0c-8872-2c2865aa81d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189440338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c trl_combo_detect.4189440338 |
| Directory | /workspace/12.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3096930310 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 63752264636 ps |
| CPU time | 183.17 seconds |
| Started | Jan 21 12:27:57 PM PST 24 |
| Finished | Jan 21 12:31:01 PM PST 24 |
| Peak memory | 201244 kb |
| Host | smart-d0df6cb2-1c20-44ac-8b80-21af81e80451 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3096930310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w ith_pre_cond.3096930310 |
| Directory | /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.861727039 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 4049579273 ps |
| CPU time | 3.47 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:27:59 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-143dddff-95a1-4d98-bfdf-1b485ee938d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861727039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c trl_ec_pwr_on_rst.861727039 |
| Directory | /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_edge_detect.1472984999 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3116748763 ps |
| CPU time | 2.43 seconds |
| Started | Jan 21 12:28:00 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-cf3b1437-5bc8-494d-9b78-b51f99807212 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472984999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct rl_edge_detect.1472984999 |
| Directory | /workspace/12.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2494997279 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2665440526 ps |
| CPU time | 1.4 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:27:57 PM PST 24 |
| Peak memory | 201076 kb |
| Host | smart-2f9bd20e-6f58-47c4-b056-abf37f9dac9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494997279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2494997279 |
| Directory | /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.1298065926 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2636985669 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:27:56 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-eb513bdf-2ec3-4992-8b5e-8d592d8c186d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1298065926 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.1298065926 |
| Directory | /workspace/12.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.3144890412 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2123458012 ps |
| CPU time | 2 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:03 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-613c0ee4-2090-4192-af52-12136c638d0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3144890412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3144890412 |
| Directory | /workspace/12.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.1751776131 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 2508820670 ps |
| CPU time | 5.85 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:07 PM PST 24 |
| Peak memory | 200868 kb |
| Host | smart-d8980860-32e3-4760-8918-702245b921cd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1751776131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1751776131 |
| Directory | /workspace/12.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_smoke.4224944480 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2112081226 ps |
| CPU time | 5.9 seconds |
| Started | Jan 21 12:27:47 PM PST 24 |
| Finished | Jan 21 12:27:54 PM PST 24 |
| Peak memory | 200960 kb |
| Host | smart-b637acf6-d815-485d-bdee-48bf213ac736 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4224944480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.4224944480 |
| Directory | /workspace/12.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_stress_all.1274124578 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 6242085117 ps |
| CPU time | 14.05 seconds |
| Started | Jan 21 12:28:02 PM PST 24 |
| Finished | Jan 21 12:28:16 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-1eabc229-f817-4c6b-abd6-06630b537aab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274124578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_s tress_all.1274124578 |
| Directory | /workspace/12.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.2560037674 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 111134824880 ps |
| CPU time | 279.79 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:32:37 PM PST 24 |
| Peak memory | 209468 kb |
| Host | smart-86eea1d0-d8b8-431a-b44f-690aafbb0eef |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560037674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.2560037674 |
| Directory | /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3827053741 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 3575678755 ps |
| CPU time | 6.35 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:28:02 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-443f1265-d8c1-48f9-ad68-d611daf170fb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827053741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ ctrl_ultra_low_pwr.3827053741 |
| Directory | /workspace/12.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_alert_test.3803910985 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 2012001660 ps |
| CPU time | 6.09 seconds |
| Started | Jan 21 12:27:44 PM PST 24 |
| Finished | Jan 21 12:27:50 PM PST 24 |
| Peak memory | 200964 kb |
| Host | smart-bb57943e-734f-43e5-88a8-d51ac16b9af6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803910985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te st.3803910985 |
| Directory | /workspace/13.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2282135272 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 3201831515 ps |
| CPU time | 2.38 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:27:58 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-7d6013fb-2e77-454e-8d52-e824f18ccb4a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2282135272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2 282135272 |
| Directory | /workspace/13.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_combo_detect.4119351826 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 53863440331 ps |
| CPU time | 137.72 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-77f017d3-e376-4a88-8e5c-a0b6c2e9d999 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119351826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c trl_combo_detect.4119351826 |
| Directory | /workspace/13.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1803081741 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 65244846728 ps |
| CPU time | 181.25 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:31:03 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-257d495e-f23b-403c-9823-59eabca8717a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1803081741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_w ith_pre_cond.1803081741 |
| Directory | /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3156083611 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3181607896 ps |
| CPU time | 2.8 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:27:59 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-3295e57c-f194-495d-912c-a818d870ee64 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156083611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ ctrl_ec_pwr_on_rst.3156083611 |
| Directory | /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_edge_detect.328836099 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3798978338 ps |
| CPU time | 2.23 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:02 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-8e540954-bb09-41d4-9937-512d9f573bf9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328836099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctr l_edge_detect.328836099 |
| Directory | /workspace/13.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1579165266 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 2619147366 ps |
| CPU time | 4.1 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-f26d13de-e134-4c4c-ab54-144ee1f12ac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1579165266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1579165266 |
| Directory | /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.2696945600 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 2456668745 ps |
| CPU time | 7.06 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:28:02 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-ca0b8127-72d0-46f8-a252-292e2e126290 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2696945600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.2696945600 |
| Directory | /workspace/13.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.3795459255 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2157928589 ps |
| CPU time | 1.06 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:27:57 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-2cbaf1c2-b7ad-497c-a919-d9b5286f7019 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795459255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.3795459255 |
| Directory | /workspace/13.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.3200674935 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2512989978 ps |
| CPU time | 7.27 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:28:03 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-37b408af-e715-40f4-9c57-b7c2abdd2f18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3200674935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3200674935 |
| Directory | /workspace/13.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_smoke.2576429548 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 2139551296 ps |
| CPU time | 1.89 seconds |
| Started | Jan 21 12:27:55 PM PST 24 |
| Finished | Jan 21 12:27:57 PM PST 24 |
| Peak memory | 201076 kb |
| Host | smart-9e69bef1-fd01-43d8-8c63-3142e444f9d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576429548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2576429548 |
| Directory | /workspace/13.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_stress_all.591450154 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 15336923986 ps |
| CPU time | 36.2 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:37 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-79126c6f-7f4c-41d6-a1d0-f91196b8fb10 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591450154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_st ress_all.591450154 |
| Directory | /workspace/13.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3317666489 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 12880064942 ps |
| CPU time | 10 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:12 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-66877718-a3de-4a33-a442-e39f571e8795 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317666489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ ctrl_ultra_low_pwr.3317666489 |
| Directory | /workspace/13.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_alert_test.4028775694 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2013919028 ps |
| CPU time | 5.87 seconds |
| Started | Jan 21 12:28:06 PM PST 24 |
| Finished | Jan 21 12:28:13 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-f110566c-c482-4493-a86b-a184a0cebef4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028775694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te st.4028775694 |
| Directory | /workspace/14.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.1862850856 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3876113705 ps |
| CPU time | 2.98 seconds |
| Started | Jan 21 12:28:06 PM PST 24 |
| Finished | Jan 21 12:28:10 PM PST 24 |
| Peak memory | 201540 kb |
| Host | smart-8362ca99-416b-494c-89fe-d2b993637bea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1862850856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.1 862850856 |
| Directory | /workspace/14.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_combo_detect.101984442 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 94740142910 ps |
| CPU time | 192.89 seconds |
| Started | Jan 21 12:28:02 PM PST 24 |
| Finished | Jan 21 12:31:15 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-f7122d21-6529-4438-a21f-f586eb1ba895 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101984442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ct rl_combo_detect.101984442 |
| Directory | /workspace/14.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.4217669672 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 4326763544 ps |
| CPU time | 1.39 seconds |
| Started | Jan 21 12:28:00 PM PST 24 |
| Finished | Jan 21 12:28:03 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-12962d19-f8d1-4845-ba1c-bcfa91954850 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217669672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ ctrl_ec_pwr_on_rst.4217669672 |
| Directory | /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_edge_detect.138963680 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2619870974 ps |
| CPU time | 2.18 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:27:57 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-8f16cf05-a8e6-4041-94d0-35a7d7fd1219 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138963680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr l_edge_detect.138963680 |
| Directory | /workspace/14.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2949317602 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2614470950 ps |
| CPU time | 7.93 seconds |
| Started | Jan 21 12:27:58 PM PST 24 |
| Finished | Jan 21 12:28:08 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-9a230136-1ad2-4d30-964c-aac1187d4294 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2949317602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2949317602 |
| Directory | /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1283437529 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 2469045147 ps |
| CPU time | 2.57 seconds |
| Started | Jan 21 12:27:59 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-b7e7f90f-6240-4af3-a72d-6b3bea981d03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283437529 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.1283437529 |
| Directory | /workspace/14.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1068923466 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2040321127 ps |
| CPU time | 1.89 seconds |
| Started | Jan 21 12:27:58 PM PST 24 |
| Finished | Jan 21 12:28:00 PM PST 24 |
| Peak memory | 200952 kb |
| Host | smart-79f65ed1-f161-4cf6-a407-72ebb27f3962 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068923466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.1068923466 |
| Directory | /workspace/14.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1308446739 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2522797675 ps |
| CPU time | 2.43 seconds |
| Started | Jan 21 12:27:58 PM PST 24 |
| Finished | Jan 21 12:28:01 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-a895abb5-22a2-45ab-8d19-a337ce73a518 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308446739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1308446739 |
| Directory | /workspace/14.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_smoke.3879385464 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2110306427 ps |
| CPU time | 5.91 seconds |
| Started | Jan 21 12:27:58 PM PST 24 |
| Finished | Jan 21 12:28:05 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-443faf26-5642-4a72-802b-7a29aa2e9aeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3879385464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3879385464 |
| Directory | /workspace/14.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_stress_all.2456384712 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 13044616909 ps |
| CPU time | 6.07 seconds |
| Started | Jan 21 12:28:04 PM PST 24 |
| Finished | Jan 21 12:28:11 PM PST 24 |
| Peak memory | 201212 kb |
| Host | smart-e5d8aa57-a04e-4024-8ee9-0bbf41849e2b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456384712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s tress_all.2456384712 |
| Directory | /workspace/14.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3837565157 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 86995985844 ps |
| CPU time | 109.35 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:29:45 PM PST 24 |
| Peak memory | 209652 kb |
| Host | smart-4ab4bf3c-2ab8-4264-94ff-5ac7c7f17e08 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837565157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.3837565157 |
| Directory | /workspace/14.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.2903817411 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4246239276 ps |
| CPU time | 2.33 seconds |
| Started | Jan 21 12:28:03 PM PST 24 |
| Finished | Jan 21 12:28:07 PM PST 24 |
| Peak memory | 201192 kb |
| Host | smart-8535069d-2303-47ba-bb8a-f2042e4f064e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903817411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ ctrl_ultra_low_pwr.2903817411 |
| Directory | /workspace/14.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_alert_test.2603421802 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 2019608017 ps |
| CPU time | 3.4 seconds |
| Started | Jan 21 12:28:17 PM PST 24 |
| Finished | Jan 21 12:28:21 PM PST 24 |
| Peak memory | 200160 kb |
| Host | smart-fb4e8569-7277-4dcd-893f-dd90bca5725f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603421802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te st.2603421802 |
| Directory | /workspace/15.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3109984312 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 3702903610 ps |
| CPU time | 3.07 seconds |
| Started | Jan 21 12:28:10 PM PST 24 |
| Finished | Jan 21 12:28:14 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-f805ee8c-3574-4c65-994c-cde09542fe3d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3109984312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.3 109984312 |
| Directory | /workspace/15.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_combo_detect.268598317 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 100453055523 ps |
| CPU time | 65.87 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:29:18 PM PST 24 |
| Peak memory | 201200 kb |
| Host | smart-70b03c8d-0fb6-4e5b-807e-223c0ba80c70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268598317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct rl_combo_detect.268598317 |
| Directory | /workspace/15.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.4074912395 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 4330897958 ps |
| CPU time | 3.33 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:15 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-ff8f5d33-6733-42d1-b439-0d14ff519d7e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074912395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ ctrl_ec_pwr_on_rst.4074912395 |
| Directory | /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_edge_detect.744784807 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 192862123887 ps |
| CPU time | 84.85 seconds |
| Started | Jan 21 12:28:07 PM PST 24 |
| Finished | Jan 21 12:29:32 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-47e1837e-6780-4a27-9441-bda47eb356d4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744784807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctr l_edge_detect.744784807 |
| Directory | /workspace/15.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3080026942 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2628146759 ps |
| CPU time | 2.37 seconds |
| Started | Jan 21 12:28:08 PM PST 24 |
| Finished | Jan 21 12:28:11 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-a4a500d1-b9df-4461-ad82-d2a83476308f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3080026942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.3080026942 |
| Directory | /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2250975171 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 2435657104 ps |
| CPU time | 7.27 seconds |
| Started | Jan 21 12:28:06 PM PST 24 |
| Finished | Jan 21 12:28:14 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-dc4b19ad-ce6d-4fa3-a4a8-5aac71d0fbc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2250975171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2250975171 |
| Directory | /workspace/15.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.739095946 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2040084560 ps |
| CPU time | 1.95 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:27:56 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-a2057fa1-1e52-466c-b9db-817b15daf2f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739095946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.739095946 |
| Directory | /workspace/15.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2424572360 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 2511522734 ps |
| CPU time | 5.64 seconds |
| Started | Jan 21 12:27:54 PM PST 24 |
| Finished | Jan 21 12:28:00 PM PST 24 |
| Peak memory | 201164 kb |
| Host | smart-9a3b7037-d8ce-426f-94ca-0ddb2c920cdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424572360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2424572360 |
| Directory | /workspace/15.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_smoke.1789049554 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 2116975395 ps |
| CPU time | 3.41 seconds |
| Started | Jan 21 12:28:06 PM PST 24 |
| Finished | Jan 21 12:28:10 PM PST 24 |
| Peak memory | 201368 kb |
| Host | smart-85c9bd3f-58ef-4947-af40-f386c956e2c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1789049554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.1789049554 |
| Directory | /workspace/15.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_stress_all.257453085 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 7645869345 ps |
| CPU time | 6.04 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:18 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-d3df17de-5a87-4175-a2ba-7de019b9d980 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257453085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_st ress_all.257453085 |
| Directory | /workspace/15.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.4289509174 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 38621861688 ps |
| CPU time | 53.08 seconds |
| Started | Jan 21 12:28:04 PM PST 24 |
| Finished | Jan 21 12:28:58 PM PST 24 |
| Peak memory | 209528 kb |
| Host | smart-3d9e966d-c51c-4818-8ef3-3efee2f98173 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289509174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.4289509174 |
| Directory | /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_alert_test.1676617348 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 2009975289 ps |
| CPU time | 5.89 seconds |
| Started | Jan 21 12:28:17 PM PST 24 |
| Finished | Jan 21 12:28:23 PM PST 24 |
| Peak memory | 200292 kb |
| Host | smart-233df185-fa67-4629-bd37-7efb87c3c66c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676617348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te st.1676617348 |
| Directory | /workspace/16.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3219909907 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 59279551568 ps |
| CPU time | 76.31 seconds |
| Started | Jan 21 12:28:10 PM PST 24 |
| Finished | Jan 21 12:29:27 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-a32424c2-ed6d-4064-a3ef-b7b0798e9458 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3219909907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3 219909907 |
| Directory | /workspace/16.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_combo_detect.3497193916 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 106359563135 ps |
| CPU time | 141.11 seconds |
| Started | Jan 21 12:28:18 PM PST 24 |
| Finished | Jan 21 12:30:39 PM PST 24 |
| Peak memory | 201184 kb |
| Host | smart-0853b781-0c79-4850-b0f1-e332e3a872c2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497193916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c trl_combo_detect.3497193916 |
| Directory | /workspace/16.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2429713201 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 77481102716 ps |
| CPU time | 54.54 seconds |
| Started | Jan 21 12:28:07 PM PST 24 |
| Finished | Jan 21 12:29:02 PM PST 24 |
| Peak memory | 201228 kb |
| Host | smart-b7d0d9cf-8f40-4bf2-8ab6-da9e1462e9fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429713201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w ith_pre_cond.2429713201 |
| Directory | /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.4225769948 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 5383015473 ps |
| CPU time | 7.4 seconds |
| Started | Jan 21 12:28:10 PM PST 24 |
| Finished | Jan 21 12:28:18 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-0fe35f43-8829-4678-8c7b-48f2a5d673c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225769948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ ctrl_ec_pwr_on_rst.4225769948 |
| Directory | /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2039085544 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 5687371278 ps |
| CPU time | 9 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:21 PM PST 24 |
| Peak memory | 200420 kb |
| Host | smart-4762a4f7-43e0-4f9b-b8be-6c835c4b3629 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039085544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct rl_edge_detect.2039085544 |
| Directory | /workspace/16.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.1366098501 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2615232917 ps |
| CPU time | 3.98 seconds |
| Started | Jan 21 12:28:08 PM PST 24 |
| Finished | Jan 21 12:28:13 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-cbe059fc-5455-4c2b-84ee-a4d33ea0afa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1366098501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.1366098501 |
| Directory | /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.3945867082 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 2473707298 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 12:28:17 PM PST 24 |
| Finished | Jan 21 12:28:19 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-35158c50-c06e-4cdf-8f79-7c8af6ae6415 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945867082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.3945867082 |
| Directory | /workspace/16.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.3847649110 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2076131027 ps |
| CPU time | 6.14 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:18 PM PST 24 |
| Peak memory | 200972 kb |
| Host | smart-620cf219-8d6f-4960-bcd1-53a9a44c08a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3847649110 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3847649110 |
| Directory | /workspace/16.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.56752930 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2555493626 ps |
| CPU time | 1.38 seconds |
| Started | Jan 21 12:28:08 PM PST 24 |
| Finished | Jan 21 12:28:10 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-2542fa96-31ec-4df0-8f1c-8dd5962cba53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=56752930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.56752930 |
| Directory | /workspace/16.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_smoke.1562497625 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2110509440 ps |
| CPU time | 6.24 seconds |
| Started | Jan 21 12:28:17 PM PST 24 |
| Finished | Jan 21 12:28:23 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-b8c45e27-05f0-4b05-8a65-6b2e788107b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1562497625 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.1562497625 |
| Directory | /workspace/16.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_stress_all.3681039548 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 9883988803 ps |
| CPU time | 23.24 seconds |
| Started | Jan 21 12:28:10 PM PST 24 |
| Finished | Jan 21 12:28:34 PM PST 24 |
| Peak memory | 201116 kb |
| Host | smart-8ffae137-0863-4868-8065-89f9e4a018ce |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681039548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s tress_all.3681039548 |
| Directory | /workspace/16.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4101518404 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 35605972746 ps |
| CPU time | 90.98 seconds |
| Started | Jan 21 12:28:07 PM PST 24 |
| Finished | Jan 21 12:29:38 PM PST 24 |
| Peak memory | 217680 kb |
| Host | smart-f23629aa-e5b1-4e40-b80d-7526efc2ac5c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101518404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.4101518404 |
| Directory | /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3442748513 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 5388736944 ps |
| CPU time | 1.6 seconds |
| Started | Jan 21 12:28:09 PM PST 24 |
| Finished | Jan 21 12:28:11 PM PST 24 |
| Peak memory | 201192 kb |
| Host | smart-f8492eb1-8529-47dd-8500-0b9a49fa294c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442748513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ ctrl_ultra_low_pwr.3442748513 |
| Directory | /workspace/16.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_alert_test.2164011256 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 2015078097 ps |
| CPU time | 6.11 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:18 PM PST 24 |
| Peak memory | 200908 kb |
| Host | smart-b861c98a-09a1-4c4f-99b7-2dfa5a2d070d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164011256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te st.2164011256 |
| Directory | /workspace/17.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.2192803783 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 3425585239 ps |
| CPU time | 7.93 seconds |
| Started | Jan 21 12:28:08 PM PST 24 |
| Finished | Jan 21 12:28:16 PM PST 24 |
| Peak memory | 201236 kb |
| Host | smart-8c728a4b-80ab-4586-a5a8-bf8bc93e7afa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2192803783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.2 192803783 |
| Directory | /workspace/17.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_combo_detect.3818057379 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 88484276810 ps |
| CPU time | 58.46 seconds |
| Started | Jan 21 12:28:12 PM PST 24 |
| Finished | Jan 21 12:29:11 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-24edf5ad-9bab-49c0-a670-1b1e4ab1501a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818057379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c trl_combo_detect.3818057379 |
| Directory | /workspace/17.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.3952880577 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 3852503119 ps |
| CPU time | 3.43 seconds |
| Started | Jan 21 12:28:12 PM PST 24 |
| Finished | Jan 21 12:28:16 PM PST 24 |
| Peak memory | 200988 kb |
| Host | smart-118c5893-ea2c-4fb3-ab5d-0402292e7551 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952880577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ ctrl_ec_pwr_on_rst.3952880577 |
| Directory | /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_edge_detect.3856172982 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4280299544 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 12:28:09 PM PST 24 |
| Finished | Jan 21 12:28:11 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-32d48e7e-0682-409b-986d-46a7a6b65581 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856172982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ct rl_edge_detect.3856172982 |
| Directory | /workspace/17.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3438617533 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 2611282123 ps |
| CPU time | 7.42 seconds |
| Started | Jan 21 12:28:12 PM PST 24 |
| Finished | Jan 21 12:28:20 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-a443f178-40df-4de3-872a-35950cbed4bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438617533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3438617533 |
| Directory | /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.2635802031 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 2470436838 ps |
| CPU time | 7.11 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:19 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-66c463e2-17ba-49d2-ada1-ba065519363f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2635802031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.2635802031 |
| Directory | /workspace/17.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.2157450295 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2150984191 ps |
| CPU time | 6.2 seconds |
| Started | Jan 21 12:28:09 PM PST 24 |
| Finished | Jan 21 12:28:16 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-e8bff9ac-b447-4b19-b440-ad6a8f110cdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2157450295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.2157450295 |
| Directory | /workspace/17.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.2842993065 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 2509814704 ps |
| CPU time | 7.17 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:19 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-6c30ad37-2db6-43a7-8bcf-645562cf8812 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842993065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.2842993065 |
| Directory | /workspace/17.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_smoke.681399350 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 2234124123 ps |
| CPU time | 0.94 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:13 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-c0e1ba6b-4c09-40ee-ba98-09d8cc3029d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=681399350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.681399350 |
| Directory | /workspace/17.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_stress_all.4176947169 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 13949890229 ps |
| CPU time | 2.66 seconds |
| Started | Jan 21 12:28:00 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-a8388ece-ebec-471d-9b1f-5fa5061fec32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176947169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_s tress_all.4176947169 |
| Directory | /workspace/17.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1413382479 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5512986555 ps |
| CPU time | 3.42 seconds |
| Started | Jan 21 12:28:07 PM PST 24 |
| Finished | Jan 21 12:28:11 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-a02e8fa9-e554-45c4-b1e5-3b9276113e3d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413382479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ ctrl_ultra_low_pwr.1413382479 |
| Directory | /workspace/17.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_alert_test.53829479 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 2037359375 ps |
| CPU time | 1.83 seconds |
| Started | Jan 21 12:28:19 PM PST 24 |
| Finished | Jan 21 12:28:22 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-7d0d1b14-4802-41e5-9084-c382e0008d6d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53829479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test .53829479 |
| Directory | /workspace/18.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1675980062 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 222660952199 ps |
| CPU time | 583.45 seconds |
| Started | Jan 21 12:28:14 PM PST 24 |
| Finished | Jan 21 12:37:58 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-7ce5d95c-668e-486c-9162-84e3e61d5c81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1675980062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1 675980062 |
| Directory | /workspace/18.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2220796787 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 24189644681 ps |
| CPU time | 61.91 seconds |
| Started | Jan 21 12:28:12 PM PST 24 |
| Finished | Jan 21 12:29:15 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-077fe342-1cf8-4cc4-8361-d1e582a7cb8c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220796787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c trl_combo_detect.2220796787 |
| Directory | /workspace/18.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1921641468 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 69334144748 ps |
| CPU time | 86.69 seconds |
| Started | Jan 21 12:28:20 PM PST 24 |
| Finished | Jan 21 12:29:48 PM PST 24 |
| Peak memory | 201276 kb |
| Host | smart-b13638e2-ce60-4fba-9961-0010c494a4fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921641468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w ith_pre_cond.1921641468 |
| Directory | /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2561109822 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3596480386 ps |
| CPU time | 9.28 seconds |
| Started | Jan 21 12:28:14 PM PST 24 |
| Finished | Jan 21 12:28:24 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-1864b580-0b88-4d66-81c8-0dc2c48a1c6e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561109822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ ctrl_ec_pwr_on_rst.2561109822 |
| Directory | /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1750628722 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3047109803 ps |
| CPU time | 1.38 seconds |
| Started | Jan 21 12:28:21 PM PST 24 |
| Finished | Jan 21 12:28:23 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-1a3fa775-47a1-4b74-ae53-b3b698c54656 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750628722 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct rl_edge_detect.1750628722 |
| Directory | /workspace/18.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3968700481 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2691021131 ps |
| CPU time | 1.32 seconds |
| Started | Jan 21 12:28:24 PM PST 24 |
| Finished | Jan 21 12:28:26 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-f3376345-76ba-4a85-bcc4-14d977df11f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968700481 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.3968700481 |
| Directory | /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.3161191827 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2476014808 ps |
| CPU time | 3.97 seconds |
| Started | Jan 21 12:28:19 PM PST 24 |
| Finished | Jan 21 12:28:24 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-845db814-1f8c-4aff-8288-4d725df74a64 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161191827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.3161191827 |
| Directory | /workspace/18.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3979068305 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 2209430321 ps |
| CPU time | 2.07 seconds |
| Started | Jan 21 12:28:19 PM PST 24 |
| Finished | Jan 21 12:28:21 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-3107a58f-a877-4650-9838-d09461e861c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979068305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3979068305 |
| Directory | /workspace/18.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_smoke.1220090569 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2113632688 ps |
| CPU time | 6.45 seconds |
| Started | Jan 21 12:28:11 PM PST 24 |
| Finished | Jan 21 12:28:19 PM PST 24 |
| Peak memory | 200896 kb |
| Host | smart-4433bda8-f47b-4b79-b55f-eb2a407a0d70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1220090569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.1220090569 |
| Directory | /workspace/18.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_stress_all.2125372368 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 166951223188 ps |
| CPU time | 67.89 seconds |
| Started | Jan 21 12:28:24 PM PST 24 |
| Finished | Jan 21 12:29:33 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-1e86bb76-3a17-4496-9010-2def170133f7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125372368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s tress_all.2125372368 |
| Directory | /workspace/18.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.1881597154 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 1813099625117 ps |
| CPU time | 80.54 seconds |
| Started | Jan 21 12:28:13 PM PST 24 |
| Finished | Jan 21 12:29:34 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-efdb2269-b9b6-4c47-9c51-9bb072b3787e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881597154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ ctrl_ultra_low_pwr.1881597154 |
| Directory | /workspace/18.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_alert_test.1585129004 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2026454553 ps |
| CPU time | 2.2 seconds |
| Started | Jan 21 12:28:30 PM PST 24 |
| Finished | Jan 21 12:28:33 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-ac27a68c-c491-4149-ac6f-10cb8840ce52 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585129004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te st.1585129004 |
| Directory | /workspace/19.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3646409215 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 81760949506 ps |
| CPU time | 53.53 seconds |
| Started | Jan 21 12:28:26 PM PST 24 |
| Finished | Jan 21 12:29:21 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-bf81165f-7598-4c08-9320-e8efda10fd4e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646409215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3 646409215 |
| Directory | /workspace/19.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_combo_detect.2657852146 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 108867673540 ps |
| CPU time | 292.07 seconds |
| Started | Jan 21 12:28:31 PM PST 24 |
| Finished | Jan 21 12:33:24 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-24fc85b8-9cbf-4bd8-af8d-b28b8eea6b8e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657852146 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c trl_combo_detect.2657852146 |
| Directory | /workspace/19.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.78321185 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 26100548793 ps |
| CPU time | 17.58 seconds |
| Started | Jan 21 12:28:26 PM PST 24 |
| Finished | Jan 21 12:28:44 PM PST 24 |
| Peak memory | 201268 kb |
| Host | smart-61ea4064-4379-4094-9583-9ac0d5c7a347 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=78321185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wit h_pre_cond.78321185 |
| Directory | /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2592102492 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 3456359164 ps |
| CPU time | 1.24 seconds |
| Started | Jan 21 12:28:17 PM PST 24 |
| Finished | Jan 21 12:28:19 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-8744b32c-b7f8-4abc-acef-3c602d6a644e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592102492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ ctrl_ec_pwr_on_rst.2592102492 |
| Directory | /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3696609423 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2613627566 ps |
| CPU time | 4.82 seconds |
| Started | Jan 21 12:28:24 PM PST 24 |
| Finished | Jan 21 12:28:29 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-14490364-4193-45e5-9abe-97c22ea39df8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3696609423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3696609423 |
| Directory | /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.655452592 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2483481591 ps |
| CPU time | 2.19 seconds |
| Started | Jan 21 12:28:15 PM PST 24 |
| Finished | Jan 21 12:28:18 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-f0bf3f66-cb83-4ddc-ab62-375a494c0c73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=655452592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.655452592 |
| Directory | /workspace/19.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.420302785 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2187641536 ps |
| CPU time | 6.58 seconds |
| Started | Jan 21 12:28:19 PM PST 24 |
| Finished | Jan 21 12:28:26 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-767d5cdc-d7e9-4705-a358-775e2c3c9d50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=420302785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.420302785 |
| Directory | /workspace/19.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.364442036 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2513012215 ps |
| CPU time | 7.25 seconds |
| Started | Jan 21 12:28:30 PM PST 24 |
| Finished | Jan 21 12:28:37 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-caa60623-8c7b-4cae-a57d-28b6e6261d98 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364442036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.364442036 |
| Directory | /workspace/19.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_smoke.1833838967 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2138110934 ps |
| CPU time | 1.96 seconds |
| Started | Jan 21 12:28:19 PM PST 24 |
| Finished | Jan 21 12:28:22 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-b7bfa015-1f20-4c4e-be1b-ea9b2dee75db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833838967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.1833838967 |
| Directory | /workspace/19.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_stress_all.16252272 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 6209995618 ps |
| CPU time | 17.97 seconds |
| Started | Jan 21 12:28:30 PM PST 24 |
| Finished | Jan 21 12:28:48 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-8888773d-dc5b-4cb5-be7b-2b037dee728d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_str ess_all.16252272 |
| Directory | /workspace/19.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.3301534879 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 42830864305 ps |
| CPU time | 26.2 seconds |
| Started | Jan 21 12:28:25 PM PST 24 |
| Finished | Jan 21 12:28:51 PM PST 24 |
| Peak memory | 209624 kb |
| Host | smart-adbe7a96-bc51-4570-a894-f9de3fbd36ce |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301534879 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.3301534879 |
| Directory | /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.701449542 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3213423511 ps |
| CPU time | 2.29 seconds |
| Started | Jan 21 12:28:32 PM PST 24 |
| Finished | Jan 21 12:28:35 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-e845dc64-80f0-459f-a920-51802ba0385a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701449542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c trl_ultra_low_pwr.701449542 |
| Directory | /workspace/19.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_alert_test.3298456370 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 2024892012 ps |
| CPU time | 1.74 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:03 PM PST 24 |
| Peak memory | 200840 kb |
| Host | smart-7579376c-0d87-4c87-805c-95b10e5f88d0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298456370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes t.3298456370 |
| Directory | /workspace/2.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.2673475888 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 3601529482 ps |
| CPU time | 1.14 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:11 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-545a7524-db44-4785-9555-b088a49012f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2673475888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.2673475888 |
| Directory | /workspace/2.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_combo_detect.738898260 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 109435297754 ps |
| CPU time | 42.51 seconds |
| Started | Jan 21 12:26:58 PM PST 24 |
| Finished | Jan 21 12:27:41 PM PST 24 |
| Peak memory | 201148 kb |
| Host | smart-4f5e5738-50db-4e4f-9b9e-4d5e937b5875 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738898260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr l_combo_detect.738898260 |
| Directory | /workspace/2.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3373951719 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2419353733 ps |
| CPU time | 1.98 seconds |
| Started | Jan 21 12:26:57 PM PST 24 |
| Finished | Jan 21 12:27:00 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-3023ef7e-94b3-40aa-9362-bce51f39c9d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3373951719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3373951719 |
| Directory | /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2723969895 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 2324982476 ps |
| CPU time | 2.16 seconds |
| Started | Jan 21 12:26:52 PM PST 24 |
| Finished | Jan 21 12:26:55 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-0d6aef0d-e860-4e5d-a310-0b5429fcf99e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723969895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre _cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de tect_ec_rst_with_pre_cond.2723969895 |
| Directory | /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2194161789 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 71438833847 ps |
| CPU time | 39.71 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:49 PM PST 24 |
| Peak memory | 201144 kb |
| Host | smart-5371f462-8cf8-4d93-9310-5ff15942cfb4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194161789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi th_pre_cond.2194161789 |
| Directory | /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.2385327353 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 2969774816 ps |
| CPU time | 8.85 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:10 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-0a858826-1409-4be3-8b5e-28b3fe6d5061 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385327353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c trl_ec_pwr_on_rst.2385327353 |
| Directory | /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_edge_detect.4173478908 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2371104837 ps |
| CPU time | 6.41 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:08 PM PST 24 |
| Peak memory | 201108 kb |
| Host | smart-76a20493-6477-4abe-be22-666dc8d159eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173478908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr l_edge_detect.4173478908 |
| Directory | /workspace/2.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1830945255 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2692174495 ps |
| CPU time | 1.34 seconds |
| Started | Jan 21 12:26:58 PM PST 24 |
| Finished | Jan 21 12:27:00 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-8d8f26e8-dfe3-48a9-b3b3-6e02b1d34290 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830945255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1830945255 |
| Directory | /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.711124347 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2446536626 ps |
| CPU time | 3.68 seconds |
| Started | Jan 21 12:26:55 PM PST 24 |
| Finished | Jan 21 12:26:59 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-68480ce8-ca8b-4c26-bc6f-b148328f35b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711124347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.711124347 |
| Directory | /workspace/2.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2311382420 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 2056603729 ps |
| CPU time | 4.84 seconds |
| Started | Jan 21 12:26:44 PM PST 24 |
| Finished | Jan 21 12:26:53 PM PST 24 |
| Peak memory | 200984 kb |
| Host | smart-94fddce4-6914-420f-b7b9-83ad00be9ca4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2311382420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2311382420 |
| Directory | /workspace/2.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.586158992 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2689660699 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:10 PM PST 24 |
| Peak memory | 201140 kb |
| Host | smart-6f46ca7b-8bdd-4115-b653-cde24e272fce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=586158992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.586158992 |
| Directory | /workspace/2.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_sec_cm.803218117 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 42568789122 ps |
| CPU time | 12 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:22 PM PST 24 |
| Peak memory | 220924 kb |
| Host | smart-b7761967-31ba-4065-9a9a-b1b362267116 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803218117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.803218117 |
| Directory | /workspace/2.sysrst_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_smoke.4190815109 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 2112864577 ps |
| CPU time | 6.18 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:08 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-0b717183-63a6-4ad1-922f-1ef3f9dc7676 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4190815109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.4190815109 |
| Directory | /workspace/2.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_stress_all.964542406 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 204301916306 ps |
| CPU time | 119.58 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:29:01 PM PST 24 |
| Peak memory | 200684 kb |
| Host | smart-cfbe78b0-d8b0-4107-9ccd-081b49bea3bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964542406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_str ess_all.964542406 |
| Directory | /workspace/2.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.1354058126 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 4951859072 ps |
| CPU time | 1.94 seconds |
| Started | Jan 21 12:27:02 PM PST 24 |
| Finished | Jan 21 12:27:11 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-343c5c7c-152c-46fb-85ec-a5bbdb93a219 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354058126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c trl_ultra_low_pwr.1354058126 |
| Directory | /workspace/2.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_alert_test.2132516039 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2022412736 ps |
| CPU time | 2.61 seconds |
| Started | Jan 21 12:28:41 PM PST 24 |
| Finished | Jan 21 12:28:44 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-0997d060-0aa3-4256-8365-eabc2d24f86c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132516039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te st.2132516039 |
| Directory | /workspace/20.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3678592908 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3269300635 ps |
| CPU time | 4.85 seconds |
| Started | Jan 21 12:28:37 PM PST 24 |
| Finished | Jan 21 12:28:42 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-10fd671f-4e39-40bb-817d-9881079a08eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678592908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3 678592908 |
| Directory | /workspace/20.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_combo_detect.3387721927 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 157559566370 ps |
| CPU time | 395.82 seconds |
| Started | Jan 21 12:28:41 PM PST 24 |
| Finished | Jan 21 12:35:18 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-ac5d84a0-c0ae-4456-8676-3fb45b42d629 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387721927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c trl_combo_detect.3387721927 |
| Directory | /workspace/20.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2183898596 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 85501684326 ps |
| CPU time | 102.06 seconds |
| Started | Jan 21 12:28:43 PM PST 24 |
| Finished | Jan 21 12:30:25 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-ff8d8b12-7005-402c-8c1e-7551655b86f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2183898596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w ith_pre_cond.2183898596 |
| Directory | /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1521222664 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 4682701408 ps |
| CPU time | 12.92 seconds |
| Started | Jan 21 12:28:45 PM PST 24 |
| Finished | Jan 21 12:28:59 PM PST 24 |
| Peak memory | 201200 kb |
| Host | smart-b39722ef-e0cd-4563-a3ed-45f088dbb492 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521222664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ ctrl_ec_pwr_on_rst.1521222664 |
| Directory | /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_edge_detect.787886291 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3967863754 ps |
| CPU time | 5.25 seconds |
| Started | Jan 21 12:28:44 PM PST 24 |
| Finished | Jan 21 12:28:50 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-e1f11447-d4ce-40c8-8aa4-b18dff371da9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787886291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctr l_edge_detect.787886291 |
| Directory | /workspace/20.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.547706287 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 2627717736 ps |
| CPU time | 2.42 seconds |
| Started | Jan 21 12:28:37 PM PST 24 |
| Finished | Jan 21 12:28:39 PM PST 24 |
| Peak memory | 201096 kb |
| Host | smart-2dfe828d-b215-4a43-b9d6-5cc0b0ea4311 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547706287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.547706287 |
| Directory | /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.1934376377 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2469426710 ps |
| CPU time | 3.84 seconds |
| Started | Jan 21 12:28:44 PM PST 24 |
| Finished | Jan 21 12:28:48 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-aaee4e44-fdfb-41e2-816b-95f3f4f81782 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1934376377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.1934376377 |
| Directory | /workspace/20.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.4071658312 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 2102149124 ps |
| CPU time | 1.34 seconds |
| Started | Jan 21 12:28:45 PM PST 24 |
| Finished | Jan 21 12:28:47 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-6977dd52-cb52-4509-856e-843a21ad9489 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071658312 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.4071658312 |
| Directory | /workspace/20.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3185261509 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2513501741 ps |
| CPU time | 7 seconds |
| Started | Jan 21 12:28:36 PM PST 24 |
| Finished | Jan 21 12:28:43 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-a2133143-8b8b-4a48-9c8c-9412ef4cc05a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185261509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.3185261509 |
| Directory | /workspace/20.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_smoke.1132442133 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 2135129293 ps |
| CPU time | 1.64 seconds |
| Started | Jan 21 12:28:33 PM PST 24 |
| Finished | Jan 21 12:28:35 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-659f20af-8cbe-4a00-8ccf-741fdcdc5b33 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132442133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1132442133 |
| Directory | /workspace/20.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.2165430151 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 10077472759 ps |
| CPU time | 24.72 seconds |
| Started | Jan 21 12:28:45 PM PST 24 |
| Finished | Jan 21 12:29:11 PM PST 24 |
| Peak memory | 201184 kb |
| Host | smart-9f95eebb-5e0e-4d2c-a2f8-294b32a37dd9 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165430151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.2165430151 |
| Directory | /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.4154594067 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4764055194 ps |
| CPU time | 4.54 seconds |
| Started | Jan 21 12:28:38 PM PST 24 |
| Finished | Jan 21 12:28:43 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-b1fd6afe-2aaf-4298-ab15-66a9b51928d2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154594067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ ctrl_ultra_low_pwr.4154594067 |
| Directory | /workspace/20.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_alert_test.826219150 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 2011477782 ps |
| CPU time | 5.91 seconds |
| Started | Jan 21 12:28:46 PM PST 24 |
| Finished | Jan 21 12:28:52 PM PST 24 |
| Peak memory | 200980 kb |
| Host | smart-a98c05b8-7e7c-4f28-9e68-48a858239631 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826219150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_tes t.826219150 |
| Directory | /workspace/21.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3068819351 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 3361455685 ps |
| CPU time | 4.77 seconds |
| Started | Jan 21 12:28:39 PM PST 24 |
| Finished | Jan 21 12:28:45 PM PST 24 |
| Peak memory | 201148 kb |
| Host | smart-745b5068-dd05-4db3-b7a2-8da368ec07a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3068819351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3 068819351 |
| Directory | /workspace/21.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3972290686 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 197197930310 ps |
| CPU time | 489.48 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:37:10 PM PST 24 |
| Peak memory | 201176 kb |
| Host | smart-9b34ea85-292c-42f2-946b-3a5336df7b22 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972290686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c trl_combo_detect.3972290686 |
| Directory | /workspace/21.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3100709085 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4272091663 ps |
| CPU time | 6.74 seconds |
| Started | Jan 21 12:28:41 PM PST 24 |
| Finished | Jan 21 12:28:49 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-2e3a693e-f074-443b-96b0-f0e4147e3603 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100709085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ ctrl_ec_pwr_on_rst.3100709085 |
| Directory | /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_edge_detect.1081511542 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3567366649 ps |
| CPU time | 2.03 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:04 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-1d7a2770-e76f-4fde-8acd-6d3c8902e485 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081511542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct rl_edge_detect.1081511542 |
| Directory | /workspace/21.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.4130719995 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2620627191 ps |
| CPU time | 4.04 seconds |
| Started | Jan 21 12:28:46 PM PST 24 |
| Finished | Jan 21 12:28:50 PM PST 24 |
| Peak memory | 201168 kb |
| Host | smart-16a91bb6-550f-47d5-8f3c-736ce6686212 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130719995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.4130719995 |
| Directory | /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.3519843070 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2475834565 ps |
| CPU time | 6.08 seconds |
| Started | Jan 21 12:28:39 PM PST 24 |
| Finished | Jan 21 12:28:45 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-b88c2361-32df-41ce-8e28-72d5d983357d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3519843070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.3519843070 |
| Directory | /workspace/21.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.3627860185 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2090445538 ps |
| CPU time | 3.44 seconds |
| Started | Jan 21 12:28:45 PM PST 24 |
| Finished | Jan 21 12:28:49 PM PST 24 |
| Peak memory | 200976 kb |
| Host | smart-f84e02b5-664b-47f2-af2a-06ae5c370ac9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3627860185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3627860185 |
| Directory | /workspace/21.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.638891234 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2511616124 ps |
| CPU time | 6 seconds |
| Started | Jan 21 12:28:43 PM PST 24 |
| Finished | Jan 21 12:28:49 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-49e44f4d-9118-4cc0-8c22-ea3eb076fcdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=638891234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.638891234 |
| Directory | /workspace/21.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_smoke.2603952581 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 2175546361 ps |
| CPU time | 1.03 seconds |
| Started | Jan 21 12:28:41 PM PST 24 |
| Finished | Jan 21 12:28:43 PM PST 24 |
| Peak memory | 201140 kb |
| Host | smart-26c850b6-7bdf-47dd-8a72-fc83458747e6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2603952581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2603952581 |
| Directory | /workspace/21.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_stress_all.4088275121 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 14407332267 ps |
| CPU time | 27.83 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:42 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-8e11291a-03ff-49c6-b02d-d0565bd34cdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088275121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s tress_all.4088275121 |
| Directory | /workspace/21.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.237541500 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 23607480555 ps |
| CPU time | 62.88 seconds |
| Started | Jan 21 12:28:54 PM PST 24 |
| Finished | Jan 21 12:29:57 PM PST 24 |
| Peak memory | 211060 kb |
| Host | smart-8bda9bd7-f319-4478-babc-3e9789d819e6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237541500 -assert n opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.237541500 |
| Directory | /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_alert_test.2926664361 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2025686120 ps |
| CPU time | 1.77 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:03 PM PST 24 |
| Peak memory | 200964 kb |
| Host | smart-874f48d7-9802-4d1b-a7cf-3fbcc2acc748 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926664361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te st.2926664361 |
| Directory | /workspace/22.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.4246197078 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 3286613187 ps |
| CPU time | 2.87 seconds |
| Started | Jan 21 12:28:46 PM PST 24 |
| Finished | Jan 21 12:28:49 PM PST 24 |
| Peak memory | 201128 kb |
| Host | smart-b34f601e-6b7b-4738-b68a-eb2d204653fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4246197078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.4 246197078 |
| Directory | /workspace/22.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_combo_detect.1940836376 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 55231878845 ps |
| CPU time | 70.82 seconds |
| Started | Jan 21 12:28:54 PM PST 24 |
| Finished | Jan 21 12:30:06 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-d15be781-9f35-436a-bb93-eec53d17cb48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940836376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c trl_combo_detect.1940836376 |
| Directory | /workspace/22.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.2134528933 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 42768652657 ps |
| CPU time | 28.8 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:30 PM PST 24 |
| Peak memory | 201276 kb |
| Host | smart-667b7b38-19fd-4826-9c09-c8dd4943af83 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2134528933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w ith_pre_cond.2134528933 |
| Directory | /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3832157177 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 3690682279 ps |
| CPU time | 9.73 seconds |
| Started | Jan 21 12:28:58 PM PST 24 |
| Finished | Jan 21 12:29:09 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-3fb7ea78-b314-4f39-a391-ffe7e963c3c5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832157177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ ctrl_ec_pwr_on_rst.3832157177 |
| Directory | /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_edge_detect.501882258 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2380811005 ps |
| CPU time | 3.64 seconds |
| Started | Jan 21 12:29:04 PM PST 24 |
| Finished | Jan 21 12:29:18 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-9e87aa3b-e8fe-4304-a689-0ab69821eca4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501882258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctr l_edge_detect.501882258 |
| Directory | /workspace/22.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.895665450 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 2625418621 ps |
| CPU time | 2.42 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:03 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-53264490-635e-4608-ad0d-f2d2c6db6cf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=895665450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.895665450 |
| Directory | /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2618309478 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 2447357483 ps |
| CPU time | 6.29 seconds |
| Started | Jan 21 12:28:51 PM PST 24 |
| Finished | Jan 21 12:28:57 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-51974a6d-5372-4b0d-8717-ddc3af1e67ab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2618309478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2618309478 |
| Directory | /workspace/22.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.2488670403 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2198205771 ps |
| CPU time | 2.04 seconds |
| Started | Jan 21 12:28:51 PM PST 24 |
| Finished | Jan 21 12:28:54 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-c210efeb-c804-4b09-ba81-0e74f6120386 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488670403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.2488670403 |
| Directory | /workspace/22.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.2560406073 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 2536405704 ps |
| CPU time | 2.26 seconds |
| Started | Jan 21 12:28:58 PM PST 24 |
| Finished | Jan 21 12:29:01 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-adc9c453-3178-4a06-b643-5bcbb676d367 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560406073 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2560406073 |
| Directory | /workspace/22.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_smoke.2195506360 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2123242559 ps |
| CPU time | 3.44 seconds |
| Started | Jan 21 12:29:04 PM PST 24 |
| Finished | Jan 21 12:29:17 PM PST 24 |
| Peak memory | 200980 kb |
| Host | smart-fb3eb02d-760e-416a-9374-3ab74bcf6019 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2195506360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.2195506360 |
| Directory | /workspace/22.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_stress_all.2848036921 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 9130659873 ps |
| CPU time | 23.19 seconds |
| Started | Jan 21 12:29:04 PM PST 24 |
| Finished | Jan 21 12:29:37 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-c9aed25a-0a07-4698-bb4b-8eeba67b3913 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848036921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s tress_all.2848036921 |
| Directory | /workspace/22.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.4055202229 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 7223719203 ps |
| CPU time | 3.44 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:17 PM PST 24 |
| Peak memory | 200680 kb |
| Host | smart-8bc242bb-90d9-4663-810c-ca0cb9d59ebb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055202229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ ctrl_ultra_low_pwr.4055202229 |
| Directory | /workspace/22.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_alert_test.2419290155 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2022208016 ps |
| CPU time | 3.26 seconds |
| Started | Jan 21 12:29:01 PM PST 24 |
| Finished | Jan 21 12:29:06 PM PST 24 |
| Peak memory | 201420 kb |
| Host | smart-345af276-de5c-4d02-af19-5c9c3979325b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419290155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_te st.2419290155 |
| Directory | /workspace/23.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.838734510 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 3709985217 ps |
| CPU time | 4.93 seconds |
| Started | Jan 21 12:28:52 PM PST 24 |
| Finished | Jan 21 12:28:57 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-4a64137b-fb8d-4619-8d23-7c9d937b9170 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838734510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.838734510 |
| Directory | /workspace/23.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_combo_detect.4020963111 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 92905024876 ps |
| CPU time | 67.11 seconds |
| Started | Jan 21 12:28:53 PM PST 24 |
| Finished | Jan 21 12:30:01 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-9591f5f6-0565-4f07-ae89-16d232f81b9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020963111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c trl_combo_detect.4020963111 |
| Directory | /workspace/23.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2851524756 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 75752861127 ps |
| CPU time | 104.9 seconds |
| Started | Jan 21 12:29:02 PM PST 24 |
| Finished | Jan 21 12:30:48 PM PST 24 |
| Peak memory | 201352 kb |
| Host | smart-31e53145-c8c7-4236-bf41-510f263ffeab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851524756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w ith_pre_cond.2851524756 |
| Directory | /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2660293616 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2984299036 ps |
| CPU time | 2.27 seconds |
| Started | Jan 21 12:29:04 PM PST 24 |
| Finished | Jan 21 12:29:16 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-2abb4191-e40c-4206-9318-f2224c6e026f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660293616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ ctrl_ec_pwr_on_rst.2660293616 |
| Directory | /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_edge_detect.233711525 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4494175399 ps |
| CPU time | 2.96 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:17 PM PST 24 |
| Peak memory | 200624 kb |
| Host | smart-f92f6956-f23c-40f3-87e9-e335b4e61793 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233711525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctr l_edge_detect.233711525 |
| Directory | /workspace/23.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3673234831 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2612645231 ps |
| CPU time | 4.82 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:19 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-41951eeb-07f5-4072-8a46-b51400675d2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3673234831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.3673234831 |
| Directory | /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.4113002305 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2472572824 ps |
| CPU time | 3.87 seconds |
| Started | Jan 21 12:28:54 PM PST 24 |
| Finished | Jan 21 12:28:59 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-b8ef35ec-0d54-4f8f-ad91-fd3654bd1bb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4113002305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.4113002305 |
| Directory | /workspace/23.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1769483317 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2047774294 ps |
| CPU time | 5.67 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:20 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-b0b4058d-b5bc-4df8-9fa7-aafda620e119 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769483317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1769483317 |
| Directory | /workspace/23.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2201266886 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2522067980 ps |
| CPU time | 2.35 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:16 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-48ceafe1-7a3d-42c8-8318-9e2287641e91 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2201266886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2201266886 |
| Directory | /workspace/23.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_smoke.2777043483 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2109222073 ps |
| CPU time | 5.56 seconds |
| Started | Jan 21 12:28:58 PM PST 24 |
| Finished | Jan 21 12:29:05 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-93b85f53-3928-4c7a-944d-a28dc921a19c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2777043483 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2777043483 |
| Directory | /workspace/23.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_stress_all.3307875947 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 16463026027 ps |
| CPU time | 17.33 seconds |
| Started | Jan 21 12:29:10 PM PST 24 |
| Finished | Jan 21 12:29:34 PM PST 24 |
| Peak memory | 200724 kb |
| Host | smart-f5ba1621-3eb8-4488-8a47-3493adf0feb7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307875947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s tress_all.3307875947 |
| Directory | /workspace/23.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.3835027957 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 290851050393 ps |
| CPU time | 76.95 seconds |
| Started | Jan 21 12:28:55 PM PST 24 |
| Finished | Jan 21 12:30:12 PM PST 24 |
| Peak memory | 209560 kb |
| Host | smart-75c9d8f1-42e5-4854-b2a2-80f70cbd5e45 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835027957 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.3835027957 |
| Directory | /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.814418036 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2052248837725 ps |
| CPU time | 118.43 seconds |
| Started | Jan 21 12:29:01 PM PST 24 |
| Finished | Jan 21 12:31:01 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-09df4b12-e797-4386-a89e-138c2c2672f0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814418036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_c trl_ultra_low_pwr.814418036 |
| Directory | /workspace/23.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_alert_test.835026398 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 2010697779 ps |
| CPU time | 5.8 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:20 PM PST 24 |
| Peak memory | 200408 kb |
| Host | smart-371ddeb2-66fc-47af-9e2f-75f975fce331 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835026398 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_tes t.835026398 |
| Directory | /workspace/24.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.783284793 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 3471600197 ps |
| CPU time | 2.14 seconds |
| Started | Jan 21 12:29:01 PM PST 24 |
| Finished | Jan 21 12:29:05 PM PST 24 |
| Peak memory | 201508 kb |
| Host | smart-62e31fcf-7e58-4174-b422-a337b1938f8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=783284793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.783284793 |
| Directory | /workspace/24.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_combo_detect.126249282 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 59140650299 ps |
| CPU time | 11.94 seconds |
| Started | Jan 21 12:28:53 PM PST 24 |
| Finished | Jan 21 12:29:06 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-e768d5b5-040d-482a-9713-e35b03d251a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126249282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct rl_combo_detect.126249282 |
| Directory | /workspace/24.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.3318589156 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 3605049141 ps |
| CPU time | 3.88 seconds |
| Started | Jan 21 12:29:10 PM PST 24 |
| Finished | Jan 21 12:29:20 PM PST 24 |
| Peak memory | 200748 kb |
| Host | smart-b6976c52-8718-4d63-b6f1-844ab8301349 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318589156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ ctrl_ec_pwr_on_rst.3318589156 |
| Directory | /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_edge_detect.3049845374 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 3390797263 ps |
| CPU time | 2.22 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:03 PM PST 24 |
| Peak memory | 201096 kb |
| Host | smart-36dbf317-b2ac-4860-914f-477b80c1ab19 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049845374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct rl_edge_detect.3049845374 |
| Directory | /workspace/24.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.4274896507 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2620326744 ps |
| CPU time | 3.87 seconds |
| Started | Jan 21 12:28:55 PM PST 24 |
| Finished | Jan 21 12:28:59 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-c580ba8f-4b01-4753-b726-18a700ba0356 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274896507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.4274896507 |
| Directory | /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1651200528 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2460106065 ps |
| CPU time | 6.93 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:21 PM PST 24 |
| Peak memory | 200628 kb |
| Host | smart-622c0ed0-0733-44e7-ae63-16f7a097cef9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1651200528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.1651200528 |
| Directory | /workspace/24.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.3115404843 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 2068251141 ps |
| CPU time | 2.1 seconds |
| Started | Jan 21 12:28:57 PM PST 24 |
| Finished | Jan 21 12:29:00 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-a9311d24-ee17-4253-ae4d-017ce06ad2c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3115404843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.3115404843 |
| Directory | /workspace/24.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2683779424 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 2527076597 ps |
| CPU time | 2.19 seconds |
| Started | Jan 21 12:28:57 PM PST 24 |
| Finished | Jan 21 12:29:00 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-2a322aed-38cc-4450-b43f-defb61d043f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2683779424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2683779424 |
| Directory | /workspace/24.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_smoke.1197027318 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 2108851719 ps |
| CPU time | 6.55 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:08 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-5b44a2b7-e68f-45e3-9eb1-3c569bd3fd87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1197027318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1197027318 |
| Directory | /workspace/24.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_stress_all.3786171236 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 19456444771 ps |
| CPU time | 22.59 seconds |
| Started | Jan 21 12:28:57 PM PST 24 |
| Finished | Jan 21 12:29:21 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-8688a3fe-09ca-450c-aa36-73cb97b20591 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786171236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s tress_all.3786171236 |
| Directory | /workspace/24.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3576651134 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 91917704571 ps |
| CPU time | 127.84 seconds |
| Started | Jan 21 12:28:55 PM PST 24 |
| Finished | Jan 21 12:31:03 PM PST 24 |
| Peak memory | 217700 kb |
| Host | smart-d52872fd-fe1b-4fc3-a069-2344290f6b3f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576651134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.3576651134 |
| Directory | /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.3835083733 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3262919295 ps |
| CPU time | 2.03 seconds |
| Started | Jan 21 12:28:57 PM PST 24 |
| Finished | Jan 21 12:29:00 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-648d6a5b-2b75-4db3-a62d-df945c52e091 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835083733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ ctrl_ultra_low_pwr.3835083733 |
| Directory | /workspace/24.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_alert_test.2642127122 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 2010389408 ps |
| CPU time | 5.76 seconds |
| Started | Jan 21 12:29:08 PM PST 24 |
| Finished | Jan 21 12:29:20 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-5c0f96d2-c0d7-4ff5-99bc-36f2f281bb5f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642127122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te st.2642127122 |
| Directory | /workspace/25.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4254329727 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 3909270626 ps |
| CPU time | 5.93 seconds |
| Started | Jan 21 12:29:02 PM PST 24 |
| Finished | Jan 21 12:29:14 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-2171ba7e-c6ad-4d94-97b1-f1c46cac4687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4254329727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.4 254329727 |
| Directory | /workspace/25.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_combo_detect.3224649282 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 30032336893 ps |
| CPU time | 21.62 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:23 PM PST 24 |
| Peak memory | 201116 kb |
| Host | smart-30423529-33a6-4cb1-8162-4d94f78d4805 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224649282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c trl_combo_detect.3224649282 |
| Directory | /workspace/25.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.2902154288 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 40681445833 ps |
| CPU time | 105.68 seconds |
| Started | Jan 21 12:29:02 PM PST 24 |
| Finished | Jan 21 12:30:49 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-18be2e40-6e16-4d07-86bd-44cc94f49a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2902154288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w ith_pre_cond.2902154288 |
| Directory | /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.1702575139 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3227805991 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 12:29:09 PM PST 24 |
| Finished | Jan 21 12:29:18 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-e4cd3143-1f5c-47a1-99c4-cc222b314739 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702575139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ ctrl_ec_pwr_on_rst.1702575139 |
| Directory | /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_edge_detect.2176877430 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3187420487 ps |
| CPU time | 1.36 seconds |
| Started | Jan 21 12:29:08 PM PST 24 |
| Finished | Jan 21 12:29:16 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-97ae824f-178a-4338-a1b2-2dcd6185c91a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176877430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct rl_edge_detect.2176877430 |
| Directory | /workspace/25.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.815732431 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2632433741 ps |
| CPU time | 2.36 seconds |
| Started | Jan 21 12:29:05 PM PST 24 |
| Finished | Jan 21 12:29:16 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-3c68695f-8911-4cb2-af01-292eea4d36c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=815732431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.815732431 |
| Directory | /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1190288081 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 2485297979 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:03 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-c683c118-045c-4a75-97ac-576b1dc5cc11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1190288081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1190288081 |
| Directory | /workspace/25.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.981818476 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2077804165 ps |
| CPU time | 2.1 seconds |
| Started | Jan 21 12:29:02 PM PST 24 |
| Finished | Jan 21 12:29:05 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-0f04db21-fd58-49bb-bedb-7d6d99892da1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=981818476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.981818476 |
| Directory | /workspace/25.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.927563020 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2537452433 ps |
| CPU time | 2.43 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:03 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-af970257-89aa-4d83-8130-196c4b50f157 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=927563020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.927563020 |
| Directory | /workspace/25.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_smoke.1672759102 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2161934451 ps |
| CPU time | 1.1 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:02 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-ee42bd08-ddee-43ee-9d1a-048dcfbc2cdb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672759102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1672759102 |
| Directory | /workspace/25.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_stress_all.2822483300 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 8778861373 ps |
| CPU time | 9.87 seconds |
| Started | Jan 21 12:29:02 PM PST 24 |
| Finished | Jan 21 12:29:13 PM PST 24 |
| Peak memory | 200956 kb |
| Host | smart-6f345026-f8ea-4ba5-9974-7691f8bdaa1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822483300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s tress_all.2822483300 |
| Directory | /workspace/25.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3726473105 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 10076345962 ps |
| CPU time | 3.02 seconds |
| Started | Jan 21 12:29:09 PM PST 24 |
| Finished | Jan 21 12:29:20 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-b9a419ff-26a8-42ac-90e1-fcbecb8c09dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726473105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ ctrl_ultra_low_pwr.3726473105 |
| Directory | /workspace/25.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_alert_test.3152539239 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2011688343 ps |
| CPU time | 6.06 seconds |
| Started | Jan 21 12:29:08 PM PST 24 |
| Finished | Jan 21 12:29:20 PM PST 24 |
| Peak memory | 200988 kb |
| Host | smart-ef4aba6c-b769-45c3-8381-7cd5c58391bd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152539239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te st.3152539239 |
| Directory | /workspace/26.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2464357519 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 101135939400 ps |
| CPU time | 68.93 seconds |
| Started | Jan 21 12:29:06 PM PST 24 |
| Finished | Jan 21 12:30:23 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-93e22d20-2ffd-43de-b9cf-7627d64835de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2464357519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2 464357519 |
| Directory | /workspace/26.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_combo_detect.995457980 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 50046880332 ps |
| CPU time | 70.66 seconds |
| Started | Jan 21 12:29:13 PM PST 24 |
| Finished | Jan 21 12:30:27 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-ec0102ce-e105-496a-92f5-d7dd6615f015 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995457980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct rl_combo_detect.995457980 |
| Directory | /workspace/26.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1590726107 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 3257153828 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 12:29:01 PM PST 24 |
| Finished | Jan 21 12:29:05 PM PST 24 |
| Peak memory | 201088 kb |
| Host | smart-61a8d28c-2e29-43ff-b648-d72b0de605fa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590726107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ ctrl_ec_pwr_on_rst.1590726107 |
| Directory | /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_edge_detect.3067388911 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3229969089 ps |
| CPU time | 1.92 seconds |
| Started | Jan 21 12:29:08 PM PST 24 |
| Finished | Jan 21 12:29:16 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-9c3fb07a-7ecd-43b6-a9ee-c20696abe1dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067388911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct rl_edge_detect.3067388911 |
| Directory | /workspace/26.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3003728937 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 2636572589 ps |
| CPU time | 2.3 seconds |
| Started | Jan 21 12:29:10 PM PST 24 |
| Finished | Jan 21 12:29:19 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-798355c5-508f-42e4-9edc-b8885ed1e503 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3003728937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3003728937 |
| Directory | /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.3934802585 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2463373148 ps |
| CPU time | 6.04 seconds |
| Started | Jan 21 12:29:04 PM PST 24 |
| Finished | Jan 21 12:29:20 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-2ab5a3f4-bb9c-41af-8089-b385db33a8c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934802585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.3934802585 |
| Directory | /workspace/26.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.2366909967 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2213306212 ps |
| CPU time | 6.46 seconds |
| Started | Jan 21 12:29:08 PM PST 24 |
| Finished | Jan 21 12:29:21 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-9289e5e3-6ee9-4090-b5ee-1cce9ed71d96 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2366909967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.2366909967 |
| Directory | /workspace/26.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3355913067 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2508212890 ps |
| CPU time | 7.62 seconds |
| Started | Jan 21 12:29:06 PM PST 24 |
| Finished | Jan 21 12:29:22 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-a55ad4c9-35ff-4889-97a5-2c0826d62673 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355913067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3355913067 |
| Directory | /workspace/26.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_smoke.3705632590 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2112819611 ps |
| CPU time | 6.21 seconds |
| Started | Jan 21 12:28:59 PM PST 24 |
| Finished | Jan 21 12:29:08 PM PST 24 |
| Peak memory | 200924 kb |
| Host | smart-566af98a-39f8-430c-a7eb-d564f3bdcf94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3705632590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3705632590 |
| Directory | /workspace/26.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_stress_all.1788855594 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 96720147300 ps |
| CPU time | 131.22 seconds |
| Started | Jan 21 12:29:07 PM PST 24 |
| Finished | Jan 21 12:31:25 PM PST 24 |
| Peak memory | 201552 kb |
| Host | smart-0509641e-3407-44ef-8b2e-cb2f270ccb26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788855594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s tress_all.1788855594 |
| Directory | /workspace/26.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.3599320205 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 5961407953 ps |
| CPU time | 8.29 seconds |
| Started | Jan 21 12:29:08 PM PST 24 |
| Finished | Jan 21 12:29:23 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-d1ed55a9-7004-4a19-9ccb-48f895117b20 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599320205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ ctrl_ultra_low_pwr.3599320205 |
| Directory | /workspace/26.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_alert_test.3252850047 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2024908400 ps |
| CPU time | 3.13 seconds |
| Started | Jan 21 12:29:16 PM PST 24 |
| Finished | Jan 21 12:29:25 PM PST 24 |
| Peak memory | 200956 kb |
| Host | smart-3d86c334-fdbf-48e0-b896-3f2bf0461aff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252850047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te st.3252850047 |
| Directory | /workspace/27.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3180655805 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 2941710360 ps |
| CPU time | 7.62 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:30 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-b57aa885-eccc-4347-906c-e251dbd7822a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180655805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3 180655805 |
| Directory | /workspace/27.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_combo_detect.1793083436 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 65369244086 ps |
| CPU time | 162.73 seconds |
| Started | Jan 21 12:29:15 PM PST 24 |
| Finished | Jan 21 12:32:04 PM PST 24 |
| Peak memory | 201088 kb |
| Host | smart-f8f7a7b3-7bca-4816-9ffc-e8df6a78b3c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793083436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_c trl_combo_detect.1793083436 |
| Directory | /workspace/27.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2863435036 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 32834739894 ps |
| CPU time | 94.01 seconds |
| Started | Jan 21 12:29:27 PM PST 24 |
| Finished | Jan 21 12:31:02 PM PST 24 |
| Peak memory | 201236 kb |
| Host | smart-ad730477-a620-47a7-b71c-cef185dbdced |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863435036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w ith_pre_cond.2863435036 |
| Directory | /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3697488447 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2616772201 ps |
| CPU time | 7.47 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:30 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-44e30157-01d9-4cd7-91d2-e2f57a434c92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697488447 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ ctrl_ec_pwr_on_rst.3697488447 |
| Directory | /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1466334510 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 5350381225 ps |
| CPU time | 9.99 seconds |
| Started | Jan 21 12:29:27 PM PST 24 |
| Finished | Jan 21 12:29:38 PM PST 24 |
| Peak memory | 200976 kb |
| Host | smart-4f733e89-feb9-42fe-a808-551a52d5e732 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466334510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct rl_edge_detect.1466334510 |
| Directory | /workspace/27.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.3275781309 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2652605649 ps |
| CPU time | 1.61 seconds |
| Started | Jan 21 12:29:18 PM PST 24 |
| Finished | Jan 21 12:29:24 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-653fa28d-166c-4fad-b02c-1f122e029d8e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275781309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.3275781309 |
| Directory | /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.3968734831 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2481992283 ps |
| CPU time | 2.33 seconds |
| Started | Jan 21 12:29:07 PM PST 24 |
| Finished | Jan 21 12:29:16 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-8b93da06-0846-4c23-aaec-b47a0667fa61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3968734831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3968734831 |
| Directory | /workspace/27.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.990664490 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 2027909372 ps |
| CPU time | 1.97 seconds |
| Started | Jan 21 12:29:09 PM PST 24 |
| Finished | Jan 21 12:29:19 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-40d50dff-a363-4857-a25e-be1c7bc38b62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=990664490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.990664490 |
| Directory | /workspace/27.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.2713204651 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 2518629274 ps |
| CPU time | 4.27 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:27 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-e5f4365a-156a-4d32-862d-efc5dda12d21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713204651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.2713204651 |
| Directory | /workspace/27.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_smoke.3424159361 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2117509415 ps |
| CPU time | 2.36 seconds |
| Started | Jan 21 12:29:07 PM PST 24 |
| Finished | Jan 21 12:29:17 PM PST 24 |
| Peak memory | 200904 kb |
| Host | smart-ec79af67-2a75-4dbd-8356-8afafa289f48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3424159361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3424159361 |
| Directory | /workspace/27.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_stress_all.3883401246 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 8341776536 ps |
| CPU time | 13.07 seconds |
| Started | Jan 21 12:29:17 PM PST 24 |
| Finished | Jan 21 12:29:35 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-ab1b9cdd-cefc-4b94-954c-ecd9cf847567 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883401246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s tress_all.3883401246 |
| Directory | /workspace/27.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3622740180 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 79726108349 ps |
| CPU time | 103.42 seconds |
| Started | Jan 21 12:29:22 PM PST 24 |
| Finished | Jan 21 12:31:07 PM PST 24 |
| Peak memory | 209564 kb |
| Host | smart-b5d8c453-d637-45bd-8550-06dc473da5b2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622740180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.3622740180 |
| Directory | /workspace/27.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.1335200611 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 6160228003 ps |
| CPU time | 2.33 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:25 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-939b2323-126b-4509-97d9-de33d6ab2d9b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335200611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ ctrl_ultra_low_pwr.1335200611 |
| Directory | /workspace/27.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_alert_test.4237121705 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2011652930 ps |
| CPU time | 5.69 seconds |
| Started | Jan 21 12:29:21 PM PST 24 |
| Finished | Jan 21 12:29:28 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-0f03c28d-c3d1-47fb-9e19-375449df962d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237121705 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te st.4237121705 |
| Directory | /workspace/28.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3273231541 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3886246874 ps |
| CPU time | 1.92 seconds |
| Started | Jan 21 12:29:27 PM PST 24 |
| Finished | Jan 21 12:29:30 PM PST 24 |
| Peak memory | 201148 kb |
| Host | smart-7f40739e-447c-483e-a476-ffadfb6e1ba5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3273231541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3 273231541 |
| Directory | /workspace/28.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_combo_detect.1295394921 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 179289535606 ps |
| CPU time | 440.58 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:36:43 PM PST 24 |
| Peak memory | 201168 kb |
| Host | smart-7d637c41-9ee2-4689-bcf3-06e275d835c1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295394921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c trl_combo_detect.1295394921 |
| Directory | /workspace/28.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3465070148 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 4498589076 ps |
| CPU time | 11.94 seconds |
| Started | Jan 21 12:29:13 PM PST 24 |
| Finished | Jan 21 12:29:29 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-b62c316c-f36b-44cc-8b9c-df203a44e596 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465070148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ ctrl_ec_pwr_on_rst.3465070148 |
| Directory | /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3397897707 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3097785100 ps |
| CPU time | 3.39 seconds |
| Started | Jan 21 12:29:16 PM PST 24 |
| Finished | Jan 21 12:29:25 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-24ef6876-72f4-46e0-adf5-722063370036 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397897707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct rl_edge_detect.3397897707 |
| Directory | /workspace/28.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1158727494 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2676821161 ps |
| CPU time | 1.45 seconds |
| Started | Jan 21 12:29:27 PM PST 24 |
| Finished | Jan 21 12:29:29 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-e732c100-5298-4310-9dd9-c2113661e556 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1158727494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1158727494 |
| Directory | /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.1354605246 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 2471136396 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 12:29:22 PM PST 24 |
| Finished | Jan 21 12:29:26 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-e3faa1c2-fa03-48f1-a0ed-34554b127f5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1354605246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.1354605246 |
| Directory | /workspace/28.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1645752681 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 2103459161 ps |
| CPU time | 3.2 seconds |
| Started | Jan 21 12:29:20 PM PST 24 |
| Finished | Jan 21 12:29:26 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-a301d340-da43-4d01-a0cf-98a9d7f45d78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1645752681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.1645752681 |
| Directory | /workspace/28.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.632003194 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2511309417 ps |
| CPU time | 7.13 seconds |
| Started | Jan 21 12:29:22 PM PST 24 |
| Finished | Jan 21 12:29:30 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-d708f25e-22aa-4d63-883f-f06174a96700 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632003194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.632003194 |
| Directory | /workspace/28.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_smoke.1291335135 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2155885344 ps |
| CPU time | 1.3 seconds |
| Started | Jan 21 12:29:15 PM PST 24 |
| Finished | Jan 21 12:29:23 PM PST 24 |
| Peak memory | 200952 kb |
| Host | smart-7f40251b-81fd-44c3-be86-75bf84ee0b53 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291335135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1291335135 |
| Directory | /workspace/28.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_stress_all.1853027829 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 9429376828 ps |
| CPU time | 8.49 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:31 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-9ca6277d-8f02-432b-a14b-996e13a775e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853027829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s tress_all.1853027829 |
| Directory | /workspace/28.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.720851874 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3302007718 ps |
| CPU time | 1.11 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:23 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-71cb5607-2a01-4bf9-9f4b-72b5deb2dac8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720851874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c trl_ultra_low_pwr.720851874 |
| Directory | /workspace/28.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_alert_test.98079665 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2027492473 ps |
| CPU time | 1.79 seconds |
| Started | Jan 21 12:29:33 PM PST 24 |
| Finished | Jan 21 12:29:36 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-fd61ad0d-2ee0-4cc3-92bb-a423ce3d6434 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98079665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test .98079665 |
| Directory | /workspace/29.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.4220121883 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2930124134 ps |
| CPU time | 4.06 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:26 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-e9d130a2-f2d0-41f2-8ab1-f446b96acc61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220121883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.4 220121883 |
| Directory | /workspace/29.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_combo_detect.507626821 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 27840495662 ps |
| CPU time | 68.88 seconds |
| Started | Jan 21 12:29:22 PM PST 24 |
| Finished | Jan 21 12:30:32 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-ba2511d6-7bb1-4fe9-9b2c-b8677f888328 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507626821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct rl_combo_detect.507626821 |
| Directory | /workspace/29.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.406691707 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 25828362699 ps |
| CPU time | 67.26 seconds |
| Started | Jan 21 12:29:24 PM PST 24 |
| Finished | Jan 21 12:30:32 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-9a0714fa-1d04-4e00-b431-9a2bb765c032 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406691707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_wi th_pre_cond.406691707 |
| Directory | /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.478421814 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2858090658 ps |
| CPU time | 7.53 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:30 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-9da7706f-d780-4bf7-8b52-ccebdd4a970a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478421814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c trl_ec_pwr_on_rst.478421814 |
| Directory | /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_edge_detect.1888486320 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2603288534 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:29:29 PM PST 24 |
| Finished | Jan 21 12:29:31 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-f1de45cf-f40a-4cd0-94e8-09edd4554100 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888486320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct rl_edge_detect.1888486320 |
| Directory | /workspace/29.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3619855967 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2833356909 ps |
| CPU time | 1.01 seconds |
| Started | Jan 21 12:29:16 PM PST 24 |
| Finished | Jan 21 12:29:23 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-0477a4cd-579a-4ff4-9541-e27fc34ef108 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3619855967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.3619855967 |
| Directory | /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.3579629132 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2479405645 ps |
| CPU time | 2.29 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:25 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-2ee2fe03-3bac-4d9d-a5c5-35607a06ea4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3579629132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.3579629132 |
| Directory | /workspace/29.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.2500667562 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2126676569 ps |
| CPU time | 1.5 seconds |
| Started | Jan 21 12:29:17 PM PST 24 |
| Finished | Jan 21 12:29:23 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-d3652681-c58c-4d17-9006-b6e073c88e15 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2500667562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.2500667562 |
| Directory | /workspace/29.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_smoke.1871661216 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2111042366 ps |
| CPU time | 6.06 seconds |
| Started | Jan 21 12:29:27 PM PST 24 |
| Finished | Jan 21 12:29:34 PM PST 24 |
| Peak memory | 200948 kb |
| Host | smart-eb6ebf73-164d-44a3-8492-91829230e6f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1871661216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.1871661216 |
| Directory | /workspace/29.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_stress_all.1228464790 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 11179848271 ps |
| CPU time | 9.26 seconds |
| Started | Jan 21 12:29:19 PM PST 24 |
| Finished | Jan 21 12:29:32 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-06599928-7f31-49d8-8fae-9f0f88839203 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228464790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s tress_all.1228464790 |
| Directory | /workspace/29.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1660059148 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 59570520761 ps |
| CPU time | 37.57 seconds |
| Started | Jan 21 12:29:13 PM PST 24 |
| Finished | Jan 21 12:29:57 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-0e62a72d-bc58-42c2-a95b-62b7c0ee4163 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660059148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1660059148 |
| Directory | /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.449148586 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 3050875140 ps |
| CPU time | 2.02 seconds |
| Started | Jan 21 12:29:24 PM PST 24 |
| Finished | Jan 21 12:29:26 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-f704aa71-4143-42b6-b371-db5bc75ae0b6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449148586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c trl_ultra_low_pwr.449148586 |
| Directory | /workspace/29.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_alert_test.2678009094 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 2026043300 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 12:27:07 PM PST 24 |
| Finished | Jan 21 12:27:14 PM PST 24 |
| Peak memory | 200952 kb |
| Host | smart-e91d6064-b12a-4a88-bc94-fbbc29ad35da |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678009094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes t.2678009094 |
| Directory | /workspace/3.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1589393516 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 3338783046 ps |
| CPU time | 4.82 seconds |
| Started | Jan 21 12:27:07 PM PST 24 |
| Finished | Jan 21 12:27:17 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-7c434711-a19f-4728-8607-a30bb021b4e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589393516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1589393516 |
| Directory | /workspace/3.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_combo_detect.1406356764 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 128710858530 ps |
| CPU time | 60.43 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:28:18 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-9916a0a2-ee31-4b5c-b707-9d1134539e8a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406356764 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct rl_combo_detect.1406356764 |
| Directory | /workspace/3.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.2488481229 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 2415877633 ps |
| CPU time | 3.9 seconds |
| Started | Jan 21 12:26:57 PM PST 24 |
| Finished | Jan 21 12:27:02 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-2707a0f1-bc6b-490a-bafc-1c54ce7fac8b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2488481229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.2488481229 |
| Directory | /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2006580991 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2382851593 ps |
| CPU time | 2.27 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:04 PM PST 24 |
| Peak memory | 200692 kb |
| Host | smart-5d257d17-88da-4855-a3bf-b14b5d54403a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006580991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre _cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de tect_ec_rst_with_pre_cond.2006580991 |
| Directory | /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2306938880 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 3172445598 ps |
| CPU time | 2.6 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:04 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-66c31d14-3738-478a-a3f0-3acd913c20e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306938880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c trl_ec_pwr_on_rst.2306938880 |
| Directory | /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3134354131 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4945264258 ps |
| CPU time | 10.13 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:27 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-da686116-aacb-4aeb-af81-9f8837c1245f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134354131 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr l_edge_detect.3134354131 |
| Directory | /workspace/3.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.837243914 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2613753687 ps |
| CPU time | 4.34 seconds |
| Started | Jan 21 12:27:04 PM PST 24 |
| Finished | Jan 21 12:27:14 PM PST 24 |
| Peak memory | 201148 kb |
| Host | smart-f7b5052f-0711-4944-8510-e905a9c60c1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837243914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.837243914 |
| Directory | /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.463539868 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 2489793937 ps |
| CPU time | 2.34 seconds |
| Started | Jan 21 12:26:49 PM PST 24 |
| Finished | Jan 21 12:26:54 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-e6bf0607-6a11-4488-8f5e-07c8e0dc82cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=463539868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.463539868 |
| Directory | /workspace/3.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.4122130838 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2212342667 ps |
| CPU time | 1.26 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:27:15 PM PST 24 |
| Peak memory | 200740 kb |
| Host | smart-a8d46b92-bd06-4519-8c13-3811d5e80101 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4122130838 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.4122130838 |
| Directory | /workspace/3.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.832876389 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2563037118 ps |
| CPU time | 1.33 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:27:14 PM PST 24 |
| Peak memory | 200912 kb |
| Host | smart-5802490a-0723-4f33-84b5-28ec10b6ddac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=832876389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.832876389 |
| Directory | /workspace/3.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3919325236 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 42014133445 ps |
| CPU time | 97.72 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:28:55 PM PST 24 |
| Peak memory | 220540 kb |
| Host | smart-1e63e921-d55a-4c9f-b359-91b36b3f147d |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919325236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3919325236 |
| Directory | /workspace/3.sysrst_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_smoke.2092448030 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 2168927686 ps |
| CPU time | 1.22 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:11 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-e471623b-29e3-44cd-9791-1df6ce11a134 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2092448030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2092448030 |
| Directory | /workspace/3.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_stress_all.1117806228 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 14142844456 ps |
| CPU time | 29.01 seconds |
| Started | Jan 21 12:27:01 PM PST 24 |
| Finished | Jan 21 12:27:33 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-ba163d8d-927c-407d-a2e3-92685027a184 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117806228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st ress_all.1117806228 |
| Directory | /workspace/3.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.1351787193 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 56992922870 ps |
| CPU time | 145.84 seconds |
| Started | Jan 21 12:27:01 PM PST 24 |
| Finished | Jan 21 12:29:29 PM PST 24 |
| Peak memory | 209500 kb |
| Host | smart-bea32dfa-b0f3-4a58-ba3f-d52569d453cb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351787193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.1351787193 |
| Directory | /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.449500884 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 5389055106 ps |
| CPU time | 7.29 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:24 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-78d57196-17eb-4f1f-9bf9-3fc6f4145d1b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449500884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct rl_ultra_low_pwr.449500884 |
| Directory | /workspace/3.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_alert_test.101045417 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2014430801 ps |
| CPU time | 5.89 seconds |
| Started | Jan 21 12:29:38 PM PST 24 |
| Finished | Jan 21 12:29:51 PM PST 24 |
| Peak memory | 201096 kb |
| Host | smart-b006573a-1b9d-469c-9347-6ce99078a51e |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101045417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_tes t.101045417 |
| Directory | /workspace/30.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.889778428 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 3740794920 ps |
| CPU time | 5.51 seconds |
| Started | Jan 21 12:29:33 PM PST 24 |
| Finished | Jan 21 12:29:39 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-53e07cde-0de8-4cea-b600-fa6bd50f4dae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=889778428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.889778428 |
| Directory | /workspace/30.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2378662325 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 176294245490 ps |
| CPU time | 89.89 seconds |
| Started | Jan 21 12:29:31 PM PST 24 |
| Finished | Jan 21 12:31:02 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-d57df672-58a7-4799-8012-6bb26ec35f3c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378662325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c trl_combo_detect.2378662325 |
| Directory | /workspace/30.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.3098840423 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 73781052402 ps |
| CPU time | 104.05 seconds |
| Started | Jan 21 12:29:37 PM PST 24 |
| Finished | Jan 21 12:31:27 PM PST 24 |
| Peak memory | 201416 kb |
| Host | smart-2664ed38-b901-4af8-b7d5-7434b634d4d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098840423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_w ith_pre_cond.3098840423 |
| Directory | /workspace/30.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.804125750 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 4132968833 ps |
| CPU time | 3.13 seconds |
| Started | Jan 21 12:29:28 PM PST 24 |
| Finished | Jan 21 12:29:32 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-66613c2a-44ed-4e15-8649-5f70df791775 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804125750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c trl_ec_pwr_on_rst.804125750 |
| Directory | /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_edge_detect.4280417041 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 3001139004 ps |
| CPU time | 2.08 seconds |
| Started | Jan 21 12:29:34 PM PST 24 |
| Finished | Jan 21 12:29:38 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-23ea3dd2-b3a9-4f0c-a0a2-97db073804b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280417041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct rl_edge_detect.4280417041 |
| Directory | /workspace/30.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1156334184 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 2613393383 ps |
| CPU time | 7.63 seconds |
| Started | Jan 21 12:29:30 PM PST 24 |
| Finished | Jan 21 12:29:39 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-7eb88923-4b8e-499b-885e-3d5c957038a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156334184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1156334184 |
| Directory | /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.3416104726 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 2481614811 ps |
| CPU time | 2.01 seconds |
| Started | Jan 21 12:29:30 PM PST 24 |
| Finished | Jan 21 12:29:33 PM PST 24 |
| Peak memory | 201448 kb |
| Host | smart-1afa8e7f-a74c-423d-b9e2-3612203d77c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3416104726 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3416104726 |
| Directory | /workspace/30.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3906393319 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2196818681 ps |
| CPU time | 6.52 seconds |
| Started | Jan 21 12:29:28 PM PST 24 |
| Finished | Jan 21 12:29:35 PM PST 24 |
| Peak memory | 201088 kb |
| Host | smart-b77bf3a6-8fd8-437f-b97a-4979e04a6b8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906393319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3906393319 |
| Directory | /workspace/30.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2932282284 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2508273733 ps |
| CPU time | 7.25 seconds |
| Started | Jan 21 12:29:33 PM PST 24 |
| Finished | Jan 21 12:29:41 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-1d6a4016-0d8b-46fe-ac7a-d755f048d6b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932282284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.2932282284 |
| Directory | /workspace/30.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_smoke.2279764644 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2139602114 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 12:29:30 PM PST 24 |
| Finished | Jan 21 12:29:33 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-c62ded3a-3609-4f39-af30-6ceeb61d2537 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2279764644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.2279764644 |
| Directory | /workspace/30.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_stress_all.2361655698 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 8920207266 ps |
| CPU time | 18.73 seconds |
| Started | Jan 21 12:29:36 PM PST 24 |
| Finished | Jan 21 12:29:56 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-a856e599-3cd7-4dc3-8fd5-ab7cc1f4cae5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361655698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s tress_all.2361655698 |
| Directory | /workspace/30.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.722330571 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 3770264907547 ps |
| CPU time | 745.68 seconds |
| Started | Jan 21 12:29:28 PM PST 24 |
| Finished | Jan 21 12:41:54 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-4027e4f5-8572-43ea-be70-f30b3b0d8040 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722330571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c trl_ultra_low_pwr.722330571 |
| Directory | /workspace/30.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_alert_test.1688875030 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2020981292 ps |
| CPU time | 2.72 seconds |
| Started | Jan 21 12:29:54 PM PST 24 |
| Finished | Jan 21 12:29:57 PM PST 24 |
| Peak memory | 201144 kb |
| Host | smart-fc0d63f8-32b5-4f4c-82a9-caace602a54a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688875030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te st.1688875030 |
| Directory | /workspace/31.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.607782864 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3416738575 ps |
| CPU time | 2.88 seconds |
| Started | Jan 21 12:29:38 PM PST 24 |
| Finished | Jan 21 12:29:48 PM PST 24 |
| Peak memory | 201144 kb |
| Host | smart-aba16143-576a-4a8c-9b34-3e770f4776d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607782864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.607782864 |
| Directory | /workspace/31.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_combo_detect.175474637 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 205333123342 ps |
| CPU time | 560.63 seconds |
| Started | Jan 21 12:29:40 PM PST 24 |
| Finished | Jan 21 12:39:05 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-a7153e8c-925c-4a44-bfa6-47f639b69e0a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175474637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct rl_combo_detect.175474637 |
| Directory | /workspace/31.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3945093890 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 49383756885 ps |
| CPU time | 63.56 seconds |
| Started | Jan 21 12:29:47 PM PST 24 |
| Finished | Jan 21 12:30:53 PM PST 24 |
| Peak memory | 201208 kb |
| Host | smart-985e4799-bd71-4e78-b886-7c9e5a366217 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3945093890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w ith_pre_cond.3945093890 |
| Directory | /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.920818078 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3413309177 ps |
| CPU time | 8.82 seconds |
| Started | Jan 21 12:29:32 PM PST 24 |
| Finished | Jan 21 12:29:42 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-068f5c8a-3a13-41ae-8897-14c04a8ed486 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920818078 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c trl_ec_pwr_on_rst.920818078 |
| Directory | /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2711423149 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2619633693 ps |
| CPU time | 4.17 seconds |
| Started | Jan 21 12:29:36 PM PST 24 |
| Finished | Jan 21 12:29:42 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-d1468e37-c87e-410d-bb7b-913fa90c7813 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2711423149 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2711423149 |
| Directory | /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1184220314 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 2478685692 ps |
| CPU time | 2.29 seconds |
| Started | Jan 21 12:29:34 PM PST 24 |
| Finished | Jan 21 12:29:38 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-96cba324-d8c2-43a9-9fe6-8442ad794aa8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1184220314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1184220314 |
| Directory | /workspace/31.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2985028339 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2245488845 ps |
| CPU time | 6.53 seconds |
| Started | Jan 21 12:29:42 PM PST 24 |
| Finished | Jan 21 12:29:51 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-0f1409da-acd2-4801-862d-5d8ef955ee69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985028339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2985028339 |
| Directory | /workspace/31.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.214413286 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2538055377 ps |
| CPU time | 1.85 seconds |
| Started | Jan 21 12:29:36 PM PST 24 |
| Finished | Jan 21 12:29:39 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-06ae5af1-0a8d-4deb-a3ec-5170f36bd4a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=214413286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.214413286 |
| Directory | /workspace/31.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_smoke.980617771 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2137014557 ps |
| CPU time | 1.82 seconds |
| Started | Jan 21 12:29:35 PM PST 24 |
| Finished | Jan 21 12:29:39 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-a667ca9f-085a-4ffd-ace6-c7fc632f6046 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980617771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.980617771 |
| Directory | /workspace/31.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_stress_all.3762982934 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 15190877081 ps |
| CPU time | 19.06 seconds |
| Started | Jan 21 12:29:55 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 201324 kb |
| Host | smart-9720fe7e-2fdf-4fbf-a8a8-b83cdcc99479 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762982934 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s tress_all.3762982934 |
| Directory | /workspace/31.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2145228270 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 6480558053 ps |
| CPU time | 2.42 seconds |
| Started | Jan 21 12:29:37 PM PST 24 |
| Finished | Jan 21 12:29:45 PM PST 24 |
| Peak memory | 201236 kb |
| Host | smart-acacf35e-42f3-4fc7-81a2-d3430bee75d8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145228270 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ ctrl_ultra_low_pwr.2145228270 |
| Directory | /workspace/31.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_alert_test.3288007000 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2014828798 ps |
| CPU time | 6.23 seconds |
| Started | Jan 21 12:29:51 PM PST 24 |
| Finished | Jan 21 12:29:58 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-ef123371-8b4f-42a1-a36a-594d87a4da00 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288007000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_te st.3288007000 |
| Directory | /workspace/32.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1078592867 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3623253282 ps |
| CPU time | 3.16 seconds |
| Started | Jan 21 12:29:46 PM PST 24 |
| Finished | Jan 21 12:29:52 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-3014adba-9328-46e5-b572-cfd5ef68a3b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1078592867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.1 078592867 |
| Directory | /workspace/32.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.192885822 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 24353269783 ps |
| CPU time | 15.26 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:20 PM PST 24 |
| Peak memory | 201164 kb |
| Host | smart-276615d0-48a6-4d30-9b21-d3e2b36fec0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=192885822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_wi th_pre_cond.192885822 |
| Directory | /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1093773092 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3581328201 ps |
| CPU time | 5.25 seconds |
| Started | Jan 21 12:29:47 PM PST 24 |
| Finished | Jan 21 12:29:54 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-1213c203-6a53-468e-836f-1f70204fcbbf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093773092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ ctrl_ec_pwr_on_rst.1093773092 |
| Directory | /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_edge_detect.795244231 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 2660703288 ps |
| CPU time | 4.3 seconds |
| Started | Jan 21 12:29:47 PM PST 24 |
| Finished | Jan 21 12:29:53 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-25f637dd-99eb-4db9-b7da-549e1dd60c2c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795244231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctr l_edge_detect.795244231 |
| Directory | /workspace/32.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3285476054 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2610238458 ps |
| CPU time | 6.68 seconds |
| Started | Jan 21 12:29:54 PM PST 24 |
| Finished | Jan 21 12:30:02 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-9aa5ed95-d8cf-4107-b284-fa7b64fe8453 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3285476054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.3285476054 |
| Directory | /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.1924814361 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 2483490807 ps |
| CPU time | 2.6 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:07 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-5c9bf9b8-7cac-4403-8537-c2bddb954b8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924814361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.1924814361 |
| Directory | /workspace/32.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.3660608678 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 2250026877 ps |
| CPU time | 3.5 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:08 PM PST 24 |
| Peak memory | 200988 kb |
| Host | smart-3bf4f7ac-1ac7-46bc-865d-4ef3cafcb138 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3660608678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3660608678 |
| Directory | /workspace/32.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.386571944 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2519923228 ps |
| CPU time | 4.01 seconds |
| Started | Jan 21 12:29:54 PM PST 24 |
| Finished | Jan 21 12:29:58 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-ea7f0980-82c1-4335-acc7-59684b6b9c63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=386571944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.386571944 |
| Directory | /workspace/32.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_smoke.537461308 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 2119049899 ps |
| CPU time | 3.17 seconds |
| Started | Jan 21 12:29:46 PM PST 24 |
| Finished | Jan 21 12:29:52 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-e7ca1f71-aedc-4a95-837c-714aa958f407 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537461308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.537461308 |
| Directory | /workspace/32.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_stress_all.1336182000 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 16685419966 ps |
| CPU time | 10.86 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-12fd010f-4834-455a-b66c-ae630debe36a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336182000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s tress_all.1336182000 |
| Directory | /workspace/32.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.822786906 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 3163964389 ps |
| CPU time | 6.47 seconds |
| Started | Jan 21 12:29:40 PM PST 24 |
| Finished | Jan 21 12:29:51 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-3e977572-87e9-4599-97d3-42f4b933ccdf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822786906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c trl_ultra_low_pwr.822786906 |
| Directory | /workspace/32.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_alert_test.1588232671 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 2041087349 ps |
| CPU time | 1.92 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:07 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-a40dad6e-46a0-4027-8767-ded3f6f35cd0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588232671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te st.1588232671 |
| Directory | /workspace/33.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.4259069382 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3525666054 ps |
| CPU time | 5.28 seconds |
| Started | Jan 21 12:29:50 PM PST 24 |
| Finished | Jan 21 12:29:56 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-c2a517b1-d780-49bb-936a-13c3cfe55a7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4259069382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.4 259069382 |
| Directory | /workspace/33.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_combo_detect.4101097915 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 49983630928 ps |
| CPU time | 33.33 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:39 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-849fa05c-50ac-43f3-a074-b07d7b956a3a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101097915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c trl_combo_detect.4101097915 |
| Directory | /workspace/33.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.149137862 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 27332324453 ps |
| CPU time | 77.18 seconds |
| Started | Jan 21 12:29:48 PM PST 24 |
| Finished | Jan 21 12:31:06 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-9641eb26-3241-4699-a550-5d2573f27b77 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149137862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_wi th_pre_cond.149137862 |
| Directory | /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.822612704 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 3935142946 ps |
| CPU time | 6.14 seconds |
| Started | Jan 21 01:22:05 PM PST 24 |
| Finished | Jan 21 01:22:12 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-27671ae2-1802-4c55-b1a6-f7dcbfc3128c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822612704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c trl_ec_pwr_on_rst.822612704 |
| Directory | /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3671523079 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3013316284 ps |
| CPU time | 5.89 seconds |
| Started | Jan 21 12:29:51 PM PST 24 |
| Finished | Jan 21 12:29:58 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-830f60f6-7613-4bb7-b084-09bfb1c53d8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671523079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct rl_edge_detect.3671523079 |
| Directory | /workspace/33.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.3591870630 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2608936845 ps |
| CPU time | 7.06 seconds |
| Started | Jan 21 12:29:52 PM PST 24 |
| Finished | Jan 21 12:30:00 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-b796bdb0-b076-41a2-9fe6-4e6932f18c18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3591870630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.3591870630 |
| Directory | /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2895098744 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2466177379 ps |
| CPU time | 6.65 seconds |
| Started | Jan 21 12:29:55 PM PST 24 |
| Finished | Jan 21 12:30:03 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-34b53d1c-10a3-4728-ac76-57f2f170d67f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2895098744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.2895098744 |
| Directory | /workspace/33.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3886025658 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2100186087 ps |
| CPU time | 1.04 seconds |
| Started | Jan 21 12:29:55 PM PST 24 |
| Finished | Jan 21 12:29:56 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-0e4edaee-b80b-4ff0-814d-728d9dd481e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3886025658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3886025658 |
| Directory | /workspace/33.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.2310725044 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2515467190 ps |
| CPU time | 4.18 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:10 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-dd6a243e-aaba-4264-acff-b8cf9133bb6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310725044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.2310725044 |
| Directory | /workspace/33.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_smoke.1496871226 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2130352303 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:07 PM PST 24 |
| Peak memory | 200920 kb |
| Host | smart-a5cdf56d-0f39-44d7-9087-91bb9ab4fb25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496871226 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1496871226 |
| Directory | /workspace/33.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_stress_all.3885319882 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 11566451622 ps |
| CPU time | 15.13 seconds |
| Started | Jan 21 12:29:52 PM PST 24 |
| Finished | Jan 21 12:30:08 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-be4a7333-8a65-4125-b13e-53978ec1ebb8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885319882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_s tress_all.3885319882 |
| Directory | /workspace/33.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3606660455 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 90639935120 ps |
| CPU time | 249.97 seconds |
| Started | Jan 21 12:29:49 PM PST 24 |
| Finished | Jan 21 12:34:00 PM PST 24 |
| Peak memory | 214444 kb |
| Host | smart-f5a08506-f0d4-4037-ae05-6fd7ac384541 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606660455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3606660455 |
| Directory | /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1182382456 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 10620689202 ps |
| CPU time | 4.87 seconds |
| Started | Jan 21 12:29:50 PM PST 24 |
| Finished | Jan 21 12:29:56 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-72ffe204-7e76-42f0-b4f8-45a1915d07b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182382456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ ctrl_ultra_low_pwr.1182382456 |
| Directory | /workspace/33.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_alert_test.280579395 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2028044821 ps |
| CPU time | 2.08 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 200984 kb |
| Host | smart-052a5764-920b-4c70-8d9b-aa77940a4872 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280579395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes t.280579395 |
| Directory | /workspace/34.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.397756174 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 213862662476 ps |
| CPU time | 533.91 seconds |
| Started | Jan 21 12:29:55 PM PST 24 |
| Finished | Jan 21 12:38:50 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-765cbc1a-41a6-44ba-be6a-878d26a7719f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=397756174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.397756174 |
| Directory | /workspace/34.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_combo_detect.3909406231 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 117918750443 ps |
| CPU time | 29.75 seconds |
| Started | Jan 21 12:30:01 PM PST 24 |
| Finished | Jan 21 12:30:33 PM PST 24 |
| Peak memory | 201176 kb |
| Host | smart-ab50202c-a527-490e-9ccb-448cfb9286eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909406231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c trl_combo_detect.3909406231 |
| Directory | /workspace/34.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.924857263 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 33290848164 ps |
| CPU time | 91.74 seconds |
| Started | Jan 21 12:29:55 PM PST 24 |
| Finished | Jan 21 12:31:28 PM PST 24 |
| Peak memory | 201208 kb |
| Host | smart-42be8ea4-cbc8-43bc-8cdb-c66d28fbbe75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=924857263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_wi th_pre_cond.924857263 |
| Directory | /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.3038348784 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 3567861785 ps |
| CPU time | 2.75 seconds |
| Started | Jan 21 12:29:59 PM PST 24 |
| Finished | Jan 21 12:30:05 PM PST 24 |
| Peak memory | 201088 kb |
| Host | smart-14306ae2-d684-4062-a8f8-99f490068c3e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038348784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ ctrl_ec_pwr_on_rst.3038348784 |
| Directory | /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_edge_detect.266297954 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2964223715 ps |
| CPU time | 2.17 seconds |
| Started | Jan 21 12:29:56 PM PST 24 |
| Finished | Jan 21 12:29:59 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-9f05bddf-cd76-4720-9d8f-64be81a2649f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266297954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctr l_edge_detect.266297954 |
| Directory | /workspace/34.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1487497089 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2608133886 ps |
| CPU time | 7.05 seconds |
| Started | Jan 21 12:30:01 PM PST 24 |
| Finished | Jan 21 12:30:10 PM PST 24 |
| Peak memory | 201076 kb |
| Host | smart-7467af5e-9602-4a24-9de8-ca5bf4a5dfb6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487497089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1487497089 |
| Directory | /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.1915112321 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 2465335561 ps |
| CPU time | 7.94 seconds |
| Started | Jan 21 12:29:52 PM PST 24 |
| Finished | Jan 21 12:30:01 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-b66ff54b-dbaa-4d6c-b5a9-943573e32d9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915112321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.1915112321 |
| Directory | /workspace/34.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.2803421428 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 2158497450 ps |
| CPU time | 1.32 seconds |
| Started | Jan 21 12:30:03 PM PST 24 |
| Finished | Jan 21 12:30:06 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-68de5c5a-1737-4839-93dd-f1eada18e693 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2803421428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2803421428 |
| Directory | /workspace/34.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.945476099 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2525094700 ps |
| CPU time | 2.65 seconds |
| Started | Jan 21 12:29:55 PM PST 24 |
| Finished | Jan 21 12:29:58 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-fab64e80-d9f1-4f40-aabd-3dbe899dd475 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=945476099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.945476099 |
| Directory | /workspace/34.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_smoke.2052772351 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2110541269 ps |
| CPU time | 5.94 seconds |
| Started | Jan 21 12:29:49 PM PST 24 |
| Finished | Jan 21 12:29:56 PM PST 24 |
| Peak memory | 200968 kb |
| Host | smart-c21b0104-7be8-4c51-9d83-ba669f8cf07c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2052772351 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.2052772351 |
| Directory | /workspace/34.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_stress_all.2944559920 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 223049116711 ps |
| CPU time | 553.49 seconds |
| Started | Jan 21 12:29:55 PM PST 24 |
| Finished | Jan 21 12:39:10 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-a98eccf4-5e79-4060-b47f-679c48752587 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944559920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s tress_all.2944559920 |
| Directory | /workspace/34.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2162947663 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 86196591088 ps |
| CPU time | 237.35 seconds |
| Started | Jan 21 12:29:58 PM PST 24 |
| Finished | Jan 21 12:33:56 PM PST 24 |
| Peak memory | 217652 kb |
| Host | smart-9b61bc44-8b5e-4d8b-a8e1-b67d12762a1b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162947663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2162947663 |
| Directory | /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.2470025784 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 4994465230 ps |
| CPU time | 6.46 seconds |
| Started | Jan 21 12:29:58 PM PST 24 |
| Finished | Jan 21 12:30:05 PM PST 24 |
| Peak memory | 201492 kb |
| Host | smart-4c9d4722-8d89-4447-8c17-f1281072522b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470025784 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ ctrl_ultra_low_pwr.2470025784 |
| Directory | /workspace/34.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_alert_test.4289784629 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2016537054 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 12:30:08 PM PST 24 |
| Finished | Jan 21 12:30:12 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-f658a106-696b-4a59-a2d3-98e0dfa14478 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289784629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te st.4289784629 |
| Directory | /workspace/35.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1033269930 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 410295011608 ps |
| CPU time | 1020.51 seconds |
| Started | Jan 21 12:30:05 PM PST 24 |
| Finished | Jan 21 12:47:08 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-072a784b-683a-4033-a173-f0a4c29df3f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1033269930 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1 033269930 |
| Directory | /workspace/35.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_combo_detect.2745524937 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 28993042274 ps |
| CPU time | 19.76 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:31 PM PST 24 |
| Peak memory | 201212 kb |
| Host | smart-264b36b9-865a-4595-ad46-277bbe1ece99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745524937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c trl_combo_detect.2745524937 |
| Directory | /workspace/35.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.10886696 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 78242376803 ps |
| CPU time | 196.67 seconds |
| Started | Jan 21 12:30:02 PM PST 24 |
| Finished | Jan 21 12:33:21 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-f228ff45-8dc7-461a-babf-324166729293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10886696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_wit h_pre_cond.10886696 |
| Directory | /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2633433825 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 3055593043 ps |
| CPU time | 8.26 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:20 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-f1ae3c7f-33bc-4543-8c17-30aed632747b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633433825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ ctrl_ec_pwr_on_rst.2633433825 |
| Directory | /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_edge_detect.4045920823 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4330924165 ps |
| CPU time | 3.38 seconds |
| Started | Jan 21 12:30:02 PM PST 24 |
| Finished | Jan 21 12:30:07 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-d4562380-a6d9-4a7d-9249-0bac9811f502 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045920823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct rl_edge_detect.4045920823 |
| Directory | /workspace/35.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1074809604 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2609124932 ps |
| CPU time | 6.8 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:18 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-9f389bda-7c39-43b9-9cec-7ada15fafd3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1074809604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.1074809604 |
| Directory | /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.2574186709 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 2496598779 ps |
| CPU time | 1.72 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:13 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-cb699b2a-9be1-45b2-b82d-b31443adc840 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2574186709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.2574186709 |
| Directory | /workspace/35.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.1864510797 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 2099024367 ps |
| CPU time | 2.03 seconds |
| Started | Jan 21 12:29:59 PM PST 24 |
| Finished | Jan 21 12:30:04 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-e1a57a73-fdec-467c-8f7a-6e73c2b503d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1864510797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.1864510797 |
| Directory | /workspace/35.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.1171206568 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 2536258394 ps |
| CPU time | 2.37 seconds |
| Started | Jan 21 12:30:00 PM PST 24 |
| Finished | Jan 21 12:30:05 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-de4f8253-efb9-4ba7-9604-5d9897100be9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1171206568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1171206568 |
| Directory | /workspace/35.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_smoke.2586181421 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2110446758 ps |
| CPU time | 5.68 seconds |
| Started | Jan 21 12:30:15 PM PST 24 |
| Finished | Jan 21 12:30:22 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-b252f6c9-af66-46f3-a731-acc7bd10b86c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586181421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2586181421 |
| Directory | /workspace/35.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_stress_all.1776067637 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 122918195857 ps |
| CPU time | 312.22 seconds |
| Started | Jan 21 12:30:05 PM PST 24 |
| Finished | Jan 21 12:35:19 PM PST 24 |
| Peak memory | 201560 kb |
| Host | smart-b2fad38a-85ff-4bd1-b739-abef279a3585 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776067637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s tress_all.1776067637 |
| Directory | /workspace/35.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1354200733 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 40381528023 ps |
| CPU time | 103.3 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:31:54 PM PST 24 |
| Peak memory | 209536 kb |
| Host | smart-d9c79d88-38f2-418d-b923-fe4e51d5912e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354200733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1354200733 |
| Directory | /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2427597928 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 5890945854 ps |
| CPU time | 2.07 seconds |
| Started | Jan 21 12:30:02 PM PST 24 |
| Finished | Jan 21 12:30:06 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-d2c66214-95c2-43a8-a3b9-f722419efcb5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427597928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ ctrl_ultra_low_pwr.2427597928 |
| Directory | /workspace/35.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_alert_test.1137208767 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 2009743020 ps |
| CPU time | 5.89 seconds |
| Started | Jan 21 12:30:21 PM PST 24 |
| Finished | Jan 21 12:30:28 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-cc1961a0-2c62-4d46-b139-6363abaffca9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137208767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_te st.1137208767 |
| Directory | /workspace/36.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1086038799 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 3442111660 ps |
| CPU time | 2.07 seconds |
| Started | Jan 21 12:30:06 PM PST 24 |
| Finished | Jan 21 12:30:09 PM PST 24 |
| Peak memory | 201244 kb |
| Host | smart-04ecba45-0df5-4399-a0e8-ba2034ea096a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1086038799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1 086038799 |
| Directory | /workspace/36.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_combo_detect.3635241329 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 47881348194 ps |
| CPU time | 120.12 seconds |
| Started | Jan 21 12:30:06 PM PST 24 |
| Finished | Jan 21 12:32:08 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-0829b5c2-c3f4-4046-8b34-7c7ce71166b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635241329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c trl_combo_detect.3635241329 |
| Directory | /workspace/36.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.4177960495 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3154704080 ps |
| CPU time | 4.48 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-79debbcc-e91c-4a83-8cb6-1074b554c99a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177960495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ ctrl_ec_pwr_on_rst.4177960495 |
| Directory | /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_edge_detect.2702215269 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2851117807 ps |
| CPU time | 8.34 seconds |
| Started | Jan 21 12:30:14 PM PST 24 |
| Finished | Jan 21 12:30:24 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-5f4e0f4f-af58-4ac8-b97e-f85f40d4a441 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702215269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct rl_edge_detect.2702215269 |
| Directory | /workspace/36.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2003337381 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2633795219 ps |
| CPU time | 2.45 seconds |
| Started | Jan 21 12:30:07 PM PST 24 |
| Finished | Jan 21 12:30:11 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-ce276c88-0e3a-4572-b017-784b2ebe0667 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2003337381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2003337381 |
| Directory | /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.2605396950 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 2481853348 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:13 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-a540ce27-2222-42b2-a25f-310d3fb3a4d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2605396950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.2605396950 |
| Directory | /workspace/36.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.2844001987 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 2053867706 ps |
| CPU time | 3.37 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-71390e1e-6091-428e-b619-01a3945b077d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844001987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2844001987 |
| Directory | /workspace/36.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.4186055528 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2526618698 ps |
| CPU time | 2.51 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:13 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-8f3aacee-00f0-417d-9638-12494e887ae1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186055528 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.4186055528 |
| Directory | /workspace/36.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_smoke.1806526994 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2124549551 ps |
| CPU time | 2.11 seconds |
| Started | Jan 21 12:30:00 PM PST 24 |
| Finished | Jan 21 12:30:04 PM PST 24 |
| Peak memory | 200940 kb |
| Host | smart-2ba41a28-478c-4618-a3a5-bac7181b61e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1806526994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1806526994 |
| Directory | /workspace/36.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_stress_all.2651117928 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 6634016867 ps |
| CPU time | 9.42 seconds |
| Started | Jan 21 12:30:23 PM PST 24 |
| Finished | Jan 21 12:30:33 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-b55575bb-1e00-4863-8b94-a747a39c1719 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651117928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s tress_all.2651117928 |
| Directory | /workspace/36.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2145697951 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3961346752 ps |
| CPU time | 6.51 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:30:18 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-081c9146-d5f2-4886-bd73-5f4662d900d7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145697951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ ctrl_ultra_low_pwr.2145697951 |
| Directory | /workspace/36.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_alert_test.1734615477 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 2016094939 ps |
| CPU time | 3.23 seconds |
| Started | Jan 21 12:30:16 PM PST 24 |
| Finished | Jan 21 12:30:21 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-92f6e7ce-3a2f-4f02-a255-0ff2cf135ab7 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734615477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te st.1734615477 |
| Directory | /workspace/37.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.332699143 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3228227558 ps |
| CPU time | 2.78 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:30:24 PM PST 24 |
| Peak memory | 201144 kb |
| Host | smart-c71ec8fb-d5cc-446c-b88a-a0e0bb325dd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=332699143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.332699143 |
| Directory | /workspace/37.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.155931333 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 3179803761 ps |
| CPU time | 8.9 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:30:20 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-8aa2821c-a42e-43cc-9294-8c6fbe5fb60a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155931333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c trl_ec_pwr_on_rst.155931333 |
| Directory | /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_edge_detect.3557711003 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 3227914981 ps |
| CPU time | 3.97 seconds |
| Started | Jan 21 12:30:16 PM PST 24 |
| Finished | Jan 21 12:30:21 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-81bf452c-6831-435b-8117-863587980389 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557711003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct rl_edge_detect.3557711003 |
| Directory | /workspace/37.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.914503450 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2749564055 ps |
| CPU time | 0.99 seconds |
| Started | Jan 21 12:30:12 PM PST 24 |
| Finished | Jan 21 12:30:14 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-139fb0b1-2968-4983-bf53-9ebebce7f63e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=914503450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.914503450 |
| Directory | /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.1954931568 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2451158885 ps |
| CPU time | 3.88 seconds |
| Started | Jan 21 12:30:08 PM PST 24 |
| Finished | Jan 21 12:30:13 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-de85f8ca-2227-426b-87d7-404b1e8090b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954931568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1954931568 |
| Directory | /workspace/37.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.4292848616 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2045027451 ps |
| CPU time | 3.08 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-1cbd32f5-5a2a-4184-81b1-fce514fd6018 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292848616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.4292848616 |
| Directory | /workspace/37.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.2730917944 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 2523817828 ps |
| CPU time | 2.49 seconds |
| Started | Jan 21 12:30:13 PM PST 24 |
| Finished | Jan 21 12:30:17 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-fd635443-d048-4155-9927-f6665e24834b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2730917944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2730917944 |
| Directory | /workspace/37.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_smoke.6666588 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2137895033 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 12:30:12 PM PST 24 |
| Finished | Jan 21 12:30:14 PM PST 24 |
| Peak memory | 200772 kb |
| Host | smart-a8266201-0e2c-4591-9531-24fec3084a78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=6666588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.6666588 |
| Directory | /workspace/37.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_stress_all.1528107383 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 858491123642 ps |
| CPU time | 853.88 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:44:26 PM PST 24 |
| Peak memory | 201116 kb |
| Host | smart-5486f27b-690f-41a6-88ea-4bb68ddcee1d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528107383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s tress_all.1528107383 |
| Directory | /workspace/37.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3396929327 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 29590776085 ps |
| CPU time | 61.02 seconds |
| Started | Jan 21 12:30:10 PM PST 24 |
| Finished | Jan 21 12:31:11 PM PST 24 |
| Peak memory | 209588 kb |
| Host | smart-f14a0854-a197-4f68-a090-aec04b25c635 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396929327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3396929327 |
| Directory | /workspace/37.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3354627966 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 3117118890 ps |
| CPU time | 3.46 seconds |
| Started | Jan 21 12:30:12 PM PST 24 |
| Finished | Jan 21 12:30:16 PM PST 24 |
| Peak memory | 200804 kb |
| Host | smart-d672f4fd-4315-449a-a58a-69d354fc1a6f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354627966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ ctrl_ultra_low_pwr.3354627966 |
| Directory | /workspace/37.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_alert_test.3282058946 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 2010739067 ps |
| CPU time | 5.43 seconds |
| Started | Jan 21 12:30:28 PM PST 24 |
| Finished | Jan 21 12:30:34 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-28e7f73b-da67-4d04-93d6-cef958173903 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282058946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_te st.3282058946 |
| Directory | /workspace/38.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.948236971 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3920079466 ps |
| CPU time | 4.3 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:30:25 PM PST 24 |
| Peak memory | 201204 kb |
| Host | smart-82010e44-0f87-4c2d-af63-06ad616543c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=948236971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.948236971 |
| Directory | /workspace/38.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_combo_detect.996620009 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 36371013894 ps |
| CPU time | 80.73 seconds |
| Started | Jan 21 12:30:13 PM PST 24 |
| Finished | Jan 21 12:31:35 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-34bbbf21-15c2-449b-b857-626f35f9919b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996620009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct rl_combo_detect.996620009 |
| Directory | /workspace/38.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.656650993 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2918832155 ps |
| CPU time | 8.43 seconds |
| Started | Jan 21 12:30:08 PM PST 24 |
| Finished | Jan 21 12:30:17 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-b8485090-a274-4fa0-ae9c-beb40d632a26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656650993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c trl_ec_pwr_on_rst.656650993 |
| Directory | /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_edge_detect.2306770038 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 3175533210 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 12:30:13 PM PST 24 |
| Finished | Jan 21 12:30:17 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-4d6a97db-d391-4045-955c-3a39c6e49d26 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306770038 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct rl_edge_detect.2306770038 |
| Directory | /workspace/38.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2679646568 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 2610869899 ps |
| CPU time | 7.17 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:30:20 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-f76e4797-1f86-4071-91f6-bf6b8346e226 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2679646568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2679646568 |
| Directory | /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3120175812 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2472859227 ps |
| CPU time | 2.23 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:30:15 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-7bf9d48e-f2f7-4978-95a6-ee5629b1778d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120175812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.3120175812 |
| Directory | /workspace/38.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1042485458 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2209106711 ps |
| CPU time | 3.49 seconds |
| Started | Jan 21 12:30:14 PM PST 24 |
| Finished | Jan 21 12:30:19 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-c4f322d5-8be8-4cef-a704-879826591bd8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042485458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.1042485458 |
| Directory | /workspace/38.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3503126994 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 2517576436 ps |
| CPU time | 3.77 seconds |
| Started | Jan 21 12:30:13 PM PST 24 |
| Finished | Jan 21 12:30:18 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-22fb2e66-e0ee-40f9-913b-ecfda6f4be1f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3503126994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.3503126994 |
| Directory | /workspace/38.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_smoke.1833103260 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2110188851 ps |
| CPU time | 6.16 seconds |
| Started | Jan 21 12:30:21 PM PST 24 |
| Finished | Jan 21 12:30:29 PM PST 24 |
| Peak memory | 200976 kb |
| Host | smart-a7156f3d-f3c5-4613-8656-7f0a171c1ff2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1833103260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.1833103260 |
| Directory | /workspace/38.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_stress_all.140478505 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 97063215491 ps |
| CPU time | 94.73 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:31:47 PM PST 24 |
| Peak memory | 201204 kb |
| Host | smart-e1b1855d-367a-48bc-8436-68a1c8aa5bf8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140478505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_st ress_all.140478505 |
| Directory | /workspace/38.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3918433064 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 38713387131 ps |
| CPU time | 23.08 seconds |
| Started | Jan 21 12:30:11 PM PST 24 |
| Finished | Jan 21 12:30:35 PM PST 24 |
| Peak memory | 201404 kb |
| Host | smart-9e4319ce-8965-48c3-8ad0-1d99b3712b90 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918433064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3918433064 |
| Directory | /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3185609184 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 7029442452 ps |
| CPU time | 4.08 seconds |
| Started | Jan 21 12:30:09 PM PST 24 |
| Finished | Jan 21 12:30:14 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-f931076d-7a2c-4714-ba56-175f31927c9d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185609184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ ctrl_ultra_low_pwr.3185609184 |
| Directory | /workspace/38.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_alert_test.1211938995 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 2067498575 ps |
| CPU time | 1.25 seconds |
| Started | Jan 21 12:30:26 PM PST 24 |
| Finished | Jan 21 12:30:28 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-219dff20-cea1-4e0e-8c9d-4a81759c8034 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211938995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_te st.1211938995 |
| Directory | /workspace/39.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1834732191 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 50810262504 ps |
| CPU time | 33.49 seconds |
| Started | Jan 21 12:30:17 PM PST 24 |
| Finished | Jan 21 12:30:51 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-9c4f16dd-35f6-4891-95fe-a5174665caec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1834732191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1 834732191 |
| Directory | /workspace/39.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_combo_detect.268438507 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 108921106768 ps |
| CPU time | 51.21 seconds |
| Started | Jan 21 12:30:19 PM PST 24 |
| Finished | Jan 21 12:31:11 PM PST 24 |
| Peak memory | 201176 kb |
| Host | smart-0b954ae2-cb95-4d99-a423-287d43d6bdb9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268438507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct rl_combo_detect.268438507 |
| Directory | /workspace/39.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1229783938 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 66693934802 ps |
| CPU time | 33.71 seconds |
| Started | Jan 21 12:30:27 PM PST 24 |
| Finished | Jan 21 12:31:01 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-9bc96392-3254-4ee7-bc21-6d73bec5c000 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1229783938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w ith_pre_cond.1229783938 |
| Directory | /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.2816667475 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3804410450 ps |
| CPU time | 10.86 seconds |
| Started | Jan 21 12:30:16 PM PST 24 |
| Finished | Jan 21 12:30:27 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-735bdc91-c2d8-4d52-ae00-90338b0fec6c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816667475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ ctrl_ec_pwr_on_rst.2816667475 |
| Directory | /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_edge_detect.631307927 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 3016658175 ps |
| CPU time | 6.47 seconds |
| Started | Jan 21 12:30:28 PM PST 24 |
| Finished | Jan 21 12:30:35 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-ccd30211-5c5f-4ff2-8e78-8f3393d5a030 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631307927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctr l_edge_detect.631307927 |
| Directory | /workspace/39.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.830181223 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2632850465 ps |
| CPU time | 2.31 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:30:23 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-31954091-cfcb-475f-8ff1-5af1cd46bbfe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=830181223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.830181223 |
| Directory | /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2550292942 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2478274392 ps |
| CPU time | 5.04 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:30:26 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-c47ce739-885b-4578-a57e-5834ea0b22eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2550292942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2550292942 |
| Directory | /workspace/39.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.52171042 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2028547188 ps |
| CPU time | 5.71 seconds |
| Started | Jan 21 12:30:27 PM PST 24 |
| Finished | Jan 21 12:30:33 PM PST 24 |
| Peak memory | 200972 kb |
| Host | smart-2e31db7c-43d4-4313-993e-5968ed877953 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=52171042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.52171042 |
| Directory | /workspace/39.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1055012840 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2510012839 ps |
| CPU time | 7.28 seconds |
| Started | Jan 21 12:30:28 PM PST 24 |
| Finished | Jan 21 12:30:36 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-c09fa19c-3219-4f0f-92a0-9ced86717d74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1055012840 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1055012840 |
| Directory | /workspace/39.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_smoke.686021476 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2132253870 ps |
| CPU time | 1.95 seconds |
| Started | Jan 21 12:30:19 PM PST 24 |
| Finished | Jan 21 12:30:22 PM PST 24 |
| Peak memory | 201372 kb |
| Host | smart-a033b7cb-25eb-4a37-8ecf-3333ddce48a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=686021476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.686021476 |
| Directory | /workspace/39.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_stress_all.969302863 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 191828486513 ps |
| CPU time | 261.87 seconds |
| Started | Jan 21 12:30:21 PM PST 24 |
| Finished | Jan 21 12:34:44 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-47027379-245d-442a-a6d1-3593708ca66c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969302863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_st ress_all.969302863 |
| Directory | /workspace/39.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.322176331 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4697033344 ps |
| CPU time | 2.28 seconds |
| Started | Jan 21 12:30:28 PM PST 24 |
| Finished | Jan 21 12:30:31 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-a5a17a7c-71fc-491d-8a10-9a2336203440 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322176331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c trl_ultra_low_pwr.322176331 |
| Directory | /workspace/39.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_alert_test.3674848189 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2032063184 ps |
| CPU time | 1.96 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-f942907c-1e45-4d31-87ad-8a23eb66b2c5 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674848189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes t.3674848189 |
| Directory | /workspace/4.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2494497004 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3427966859 ps |
| CPU time | 5.5 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:27:18 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-cbd4376a-503a-4035-813f-aa7ff55175a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2494497004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2494497004 |
| Directory | /workspace/4.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_combo_detect.3443592277 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 38436675522 ps |
| CPU time | 25.28 seconds |
| Started | Jan 21 12:27:01 PM PST 24 |
| Finished | Jan 21 12:27:28 PM PST 24 |
| Peak memory | 201108 kb |
| Host | smart-8aa4d308-81a9-4ee3-8523-6bc68f9aff45 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443592277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct rl_combo_detect.3443592277 |
| Directory | /workspace/4.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2060660077 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 2405369762 ps |
| CPU time | 2.11 seconds |
| Started | Jan 21 12:27:00 PM PST 24 |
| Finished | Jan 21 12:27:04 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-dadf6fec-2145-41a0-8de6-f5d2b2944ce2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2060660077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2060660077 |
| Directory | /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2713069787 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 2536020374 ps |
| CPU time | 3.79 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:27:17 PM PST 24 |
| Peak memory | 201108 kb |
| Host | smart-d5f79ca4-51b2-4967-84e3-51534a2199e7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713069787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre _cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de tect_ec_rst_with_pre_cond.2713069787 |
| Directory | /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.2599424731 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 100656496071 ps |
| CPU time | 62.53 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:28:16 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-d091be2c-f262-4222-ac32-730e23dedd0b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2599424731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi th_pre_cond.2599424731 |
| Directory | /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3072248982 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 3499745507 ps |
| CPU time | 1.16 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-9b071ee1-f851-4e65-af9f-374a2e3cbdc3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072248982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c trl_ec_pwr_on_rst.3072248982 |
| Directory | /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_edge_detect.2258115581 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3081184498 ps |
| CPU time | 7.1 seconds |
| Started | Jan 21 12:27:07 PM PST 24 |
| Finished | Jan 21 12:27:20 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-96fe5fe4-8e18-4c38-bbdd-6acba405a949 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258115581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr l_edge_detect.2258115581 |
| Directory | /workspace/4.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2702590201 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2625893603 ps |
| CPU time | 3.43 seconds |
| Started | Jan 21 12:27:04 PM PST 24 |
| Finished | Jan 21 12:27:13 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-0f79a5c8-f8fc-4497-b1e6-f74b060ed846 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702590201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2702590201 |
| Directory | /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3995703774 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2469343835 ps |
| CPU time | 4.01 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:14 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-1031c6da-a63a-47df-953d-1a0cc0d0090b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3995703774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3995703774 |
| Directory | /workspace/4.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1796147883 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2094737969 ps |
| CPU time | 2.26 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:11 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-fd4d8ac9-a6b1-41bf-bff9-36b933e93a56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796147883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.1796147883 |
| Directory | /workspace/4.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.2412390717 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2534049055 ps |
| CPU time | 2.4 seconds |
| Started | Jan 21 12:27:03 PM PST 24 |
| Finished | Jan 21 12:27:12 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-6227fcd2-10b2-4bbb-99e8-129ad827f3d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2412390717 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.2412390717 |
| Directory | /workspace/4.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_sec_cm.1891323900 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 22010949118 ps |
| CPU time | 55.23 seconds |
| Started | Jan 21 12:27:07 PM PST 24 |
| Finished | Jan 21 12:28:08 PM PST 24 |
| Peak memory | 220740 kb |
| Host | smart-b60ac0b2-f4a8-45c5-ba2d-61e37b4b8a26 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891323900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1891323900 |
| Directory | /workspace/4.sysrst_ctrl_sec_cm/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_smoke.1279857827 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 2111627081 ps |
| CPU time | 4.24 seconds |
| Started | Jan 21 12:27:08 PM PST 24 |
| Finished | Jan 21 12:27:17 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-3e3e7060-3ff7-4326-9de4-d3cb52da3522 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1279857827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.1279857827 |
| Directory | /workspace/4.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_stress_all.2723387347 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 14868686359 ps |
| CPU time | 36.78 seconds |
| Started | Jan 21 12:27:00 PM PST 24 |
| Finished | Jan 21 12:27:38 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-143928a7-c05f-44b6-8424-6452546f73b5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723387347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st ress_all.2723387347 |
| Directory | /workspace/4.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.1919417525 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 4228512285 ps |
| CPU time | 2.13 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:20 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-649d98ac-794a-4c78-b6d5-d61fc417266a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919417525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_c trl_ultra_low_pwr.1919417525 |
| Directory | /workspace/4.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_alert_test.1654614363 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2036010867 ps |
| CPU time | 1.94 seconds |
| Started | Jan 21 12:30:30 PM PST 24 |
| Finished | Jan 21 12:30:32 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-614e4133-c2cd-44a6-8d7a-fc4b97426fb0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654614363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_te st.1654614363 |
| Directory | /workspace/40.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.2018728899 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 3106439147 ps |
| CPU time | 8.39 seconds |
| Started | Jan 21 12:30:28 PM PST 24 |
| Finished | Jan 21 12:30:37 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-6a07bd39-6671-4dc6-9d65-f0dedef13fcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2018728899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.2 018728899 |
| Directory | /workspace/40.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2765906771 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 61289376601 ps |
| CPU time | 157.9 seconds |
| Started | Jan 21 12:30:28 PM PST 24 |
| Finished | Jan 21 12:33:07 PM PST 24 |
| Peak memory | 201268 kb |
| Host | smart-d21877aa-839c-4dcb-9721-ebc8516ea7eb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2765906771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w ith_pre_cond.2765906771 |
| Directory | /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1395178208 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 4065811885 ps |
| CPU time | 10.49 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:30:31 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-8724789c-ad41-4721-bf5c-8116c2f0c221 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395178208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ ctrl_ec_pwr_on_rst.1395178208 |
| Directory | /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_edge_detect.3578892070 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3055788332 ps |
| CPU time | 7.97 seconds |
| Started | Jan 21 12:30:15 PM PST 24 |
| Finished | Jan 21 12:30:24 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-4ce79025-86f9-4f32-9315-b04974e2b05c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578892070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct rl_edge_detect.3578892070 |
| Directory | /workspace/40.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.1356957750 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 2613150839 ps |
| CPU time | 5.4 seconds |
| Started | Jan 21 12:30:21 PM PST 24 |
| Finished | Jan 21 12:30:27 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-df84c4d8-4681-47e8-895f-b5e7804a7561 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356957750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.1356957750 |
| Directory | /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.4096583358 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2489479371 ps |
| CPU time | 4.29 seconds |
| Started | Jan 21 12:30:18 PM PST 24 |
| Finished | Jan 21 12:30:23 PM PST 24 |
| Peak memory | 201060 kb |
| Host | smart-6f9babd7-8af7-4f2b-81d4-5643dbb7d2d8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096583358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.4096583358 |
| Directory | /workspace/40.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3110410922 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2348166506 ps |
| CPU time | 0.93 seconds |
| Started | Jan 21 12:30:21 PM PST 24 |
| Finished | Jan 21 12:30:23 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-32abf1bd-d114-4414-9587-0cb9586f0973 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3110410922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.3110410922 |
| Directory | /workspace/40.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.3953419903 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2511185712 ps |
| CPU time | 4.58 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:30:26 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-3f4d4820-b27f-44c4-82c2-13f1d7cfbe2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3953419903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3953419903 |
| Directory | /workspace/40.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_smoke.3461537445 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 2110358201 ps |
| CPU time | 5.9 seconds |
| Started | Jan 21 12:30:20 PM PST 24 |
| Finished | Jan 21 12:30:28 PM PST 24 |
| Peak memory | 201076 kb |
| Host | smart-516e8650-2c5d-42da-8d51-8500225df192 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461537445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.3461537445 |
| Directory | /workspace/40.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_stress_all.274049735 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 21495688433 ps |
| CPU time | 53.71 seconds |
| Started | Jan 21 12:30:31 PM PST 24 |
| Finished | Jan 21 12:31:25 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-1852ff97-8d18-47f9-8e44-fd8e90268493 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274049735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_st ress_all.274049735 |
| Directory | /workspace/40.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2549607337 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 218125833603 ps |
| CPU time | 140.21 seconds |
| Started | Jan 21 12:30:31 PM PST 24 |
| Finished | Jan 21 12:32:52 PM PST 24 |
| Peak memory | 217644 kb |
| Host | smart-bd69b6ad-38db-4794-8548-4bc68541c08e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549607337 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2549607337 |
| Directory | /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_alert_test.1752398214 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2034958555 ps |
| CPU time | 1.98 seconds |
| Started | Jan 21 12:30:47 PM PST 24 |
| Finished | Jan 21 12:30:50 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-e098e3a4-76c0-49db-86a4-73c147c9794f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752398214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te st.1752398214 |
| Directory | /workspace/41.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2671630175 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 271990431060 ps |
| CPU time | 342.56 seconds |
| Started | Jan 21 12:30:33 PM PST 24 |
| Finished | Jan 21 12:36:17 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-4cbfc1d3-9f34-445a-a159-694e58da15ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2671630175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.2 671630175 |
| Directory | /workspace/41.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3367498433 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 101149374414 ps |
| CPU time | 266.94 seconds |
| Started | Jan 21 12:30:44 PM PST 24 |
| Finished | Jan 21 12:35:11 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-9d734245-6c3f-4b9a-b56e-fbd698c28ff7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367498433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w ith_pre_cond.3367498433 |
| Directory | /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1699646432 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 768978753799 ps |
| CPU time | 1997.4 seconds |
| Started | Jan 21 12:30:34 PM PST 24 |
| Finished | Jan 21 01:03:52 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-f9efa36a-4c3a-4151-8749-6b2d62af1ec3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699646432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ ctrl_ec_pwr_on_rst.1699646432 |
| Directory | /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_edge_detect.4120718630 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 2808736591 ps |
| CPU time | 2.73 seconds |
| Started | Jan 21 12:30:31 PM PST 24 |
| Finished | Jan 21 12:30:35 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-07510cca-56c0-4e47-8dbe-bfe1749315a4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120718630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct rl_edge_detect.4120718630 |
| Directory | /workspace/41.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.4183797210 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2626827738 ps |
| CPU time | 2.32 seconds |
| Started | Jan 21 12:30:33 PM PST 24 |
| Finished | Jan 21 12:30:36 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-caf10c2e-deda-41ca-8217-8662a595c65b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4183797210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.4183797210 |
| Directory | /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.968101994 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2456381338 ps |
| CPU time | 6.88 seconds |
| Started | Jan 21 12:30:23 PM PST 24 |
| Finished | Jan 21 12:30:31 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-5dbdd7f5-2928-4c2d-87ee-34d6599147a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968101994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.968101994 |
| Directory | /workspace/41.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1840209857 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 2264712064 ps |
| CPU time | 6.53 seconds |
| Started | Jan 21 12:30:26 PM PST 24 |
| Finished | Jan 21 12:30:34 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-b8cfb20b-b5fc-4700-9181-08b334ce8f6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1840209857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1840209857 |
| Directory | /workspace/41.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.3011873747 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2511305968 ps |
| CPU time | 5.11 seconds |
| Started | Jan 21 12:30:28 PM PST 24 |
| Finished | Jan 21 12:30:34 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-c096e998-00b3-4ab1-8095-8315e9deb65b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011873747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.3011873747 |
| Directory | /workspace/41.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_smoke.2889985797 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 2132707378 ps |
| CPU time | 1.9 seconds |
| Started | Jan 21 12:30:30 PM PST 24 |
| Finished | Jan 21 12:30:33 PM PST 24 |
| Peak memory | 200936 kb |
| Host | smart-477dffd2-643b-4802-bf23-7542be147a5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2889985797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.2889985797 |
| Directory | /workspace/41.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_stress_all.661829261 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 85945474662 ps |
| CPU time | 53.89 seconds |
| Started | Jan 21 12:30:47 PM PST 24 |
| Finished | Jan 21 12:31:42 PM PST 24 |
| Peak memory | 201216 kb |
| Host | smart-75a3fd39-5893-4f24-9374-75255a0561ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661829261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_st ress_all.661829261 |
| Directory | /workspace/41.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.1323405208 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 9420927354 ps |
| CPU time | 4.23 seconds |
| Started | Jan 21 12:30:37 PM PST 24 |
| Finished | Jan 21 12:30:42 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-ad68f0b2-9f70-443b-9047-447ada10374b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323405208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ ctrl_ultra_low_pwr.1323405208 |
| Directory | /workspace/41.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_alert_test.2026104643 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2018169805 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 12:30:34 PM PST 24 |
| Finished | Jan 21 12:30:38 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-a23b009a-7004-4a91-82c3-5dd29f069fe3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026104643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te st.2026104643 |
| Directory | /workspace/42.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.180578946 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 3180481075 ps |
| CPU time | 8.89 seconds |
| Started | Jan 21 12:30:39 PM PST 24 |
| Finished | Jan 21 12:30:49 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-ac6d1300-6ab3-4704-a942-c4416a0c36ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=180578946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.180578946 |
| Directory | /workspace/42.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_combo_detect.1445084922 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 152423027457 ps |
| CPU time | 263.82 seconds |
| Started | Jan 21 12:30:33 PM PST 24 |
| Finished | Jan 21 12:34:57 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-3469b021-db6e-4e4e-bdf6-71593ce830be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445084922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c trl_combo_detect.1445084922 |
| Directory | /workspace/42.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.955293171 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 36393701311 ps |
| CPU time | 84.43 seconds |
| Started | Jan 21 12:30:50 PM PST 24 |
| Finished | Jan 21 12:32:15 PM PST 24 |
| Peak memory | 201228 kb |
| Host | smart-ad6162c6-d9fe-4065-b274-e6af81efb250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=955293171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_wi th_pre_cond.955293171 |
| Directory | /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.4098952450 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 3257920896 ps |
| CPU time | 9.02 seconds |
| Started | Jan 21 12:30:35 PM PST 24 |
| Finished | Jan 21 12:30:44 PM PST 24 |
| Peak memory | 201068 kb |
| Host | smart-427b9dcb-3d8a-4309-929a-e1dbea897300 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098952450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ ctrl_ec_pwr_on_rst.4098952450 |
| Directory | /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1682603393 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 4583575100 ps |
| CPU time | 2.8 seconds |
| Started | Jan 21 12:30:36 PM PST 24 |
| Finished | Jan 21 12:30:40 PM PST 24 |
| Peak memory | 201452 kb |
| Host | smart-de2d4090-0085-4aa4-8b57-aa24908d279a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682603393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct rl_edge_detect.1682603393 |
| Directory | /workspace/42.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.956424432 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2610105432 ps |
| CPU time | 6.88 seconds |
| Started | Jan 21 12:30:50 PM PST 24 |
| Finished | Jan 21 12:30:58 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-a89f84c6-15fe-4594-8c65-06510478ec03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=956424432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.956424432 |
| Directory | /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.2590105564 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2465382323 ps |
| CPU time | 4.13 seconds |
| Started | Jan 21 12:30:35 PM PST 24 |
| Finished | Jan 21 12:30:39 PM PST 24 |
| Peak memory | 200516 kb |
| Host | smart-b989477c-612e-4d67-8da2-c5f64ed70126 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2590105564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.2590105564 |
| Directory | /workspace/42.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1410622925 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2198874287 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 12:30:33 PM PST 24 |
| Finished | Jan 21 12:30:38 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-3f2ae8d6-aeab-41aa-aad5-4608a912ba6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1410622925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1410622925 |
| Directory | /workspace/42.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1330487557 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 2510404137 ps |
| CPU time | 7.43 seconds |
| Started | Jan 21 12:30:35 PM PST 24 |
| Finished | Jan 21 12:30:43 PM PST 24 |
| Peak memory | 200548 kb |
| Host | smart-d5538f46-571a-4eea-abd2-c61d264a978b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1330487557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.1330487557 |
| Directory | /workspace/42.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_smoke.2849558936 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2134766697 ps |
| CPU time | 2.01 seconds |
| Started | Jan 21 12:30:34 PM PST 24 |
| Finished | Jan 21 12:30:37 PM PST 24 |
| Peak memory | 200924 kb |
| Host | smart-6b6bd684-32e0-4e7e-a2ff-97cfcb2b2bae |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2849558936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2849558936 |
| Directory | /workspace/42.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1078095526 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 5934540200 ps |
| CPU time | 6.56 seconds |
| Started | Jan 21 12:30:50 PM PST 24 |
| Finished | Jan 21 12:30:57 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-b313d242-4e90-449d-be14-d973d7ca3f11 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078095526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ ctrl_ultra_low_pwr.1078095526 |
| Directory | /workspace/42.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_alert_test.4101475399 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2033801413 ps |
| CPU time | 1.86 seconds |
| Started | Jan 21 12:30:44 PM PST 24 |
| Finished | Jan 21 12:30:46 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-638fe867-29ff-4344-86e8-aff123dfd547 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101475399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te st.4101475399 |
| Directory | /workspace/43.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3488567177 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 3714626398 ps |
| CPU time | 5.77 seconds |
| Started | Jan 21 12:30:42 PM PST 24 |
| Finished | Jan 21 12:30:49 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-71a2cdb5-e133-4b2e-849a-5b8e6fa64608 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3488567177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.3 488567177 |
| Directory | /workspace/43.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_combo_detect.1443382253 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 135757974836 ps |
| CPU time | 362.9 seconds |
| Started | Jan 21 12:30:47 PM PST 24 |
| Finished | Jan 21 12:36:51 PM PST 24 |
| Peak memory | 201200 kb |
| Host | smart-c064087c-0761-4d08-ba3e-3d0b14f3d648 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443382253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c trl_combo_detect.1443382253 |
| Directory | /workspace/43.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.4018100986 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 86095789641 ps |
| CPU time | 56.32 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:31:49 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-273c7864-0c5e-4a2a-9758-502cbe36f6a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018100986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_w ith_pre_cond.4018100986 |
| Directory | /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.278163751 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 6078193470 ps |
| CPU time | 4.24 seconds |
| Started | Jan 21 12:30:52 PM PST 24 |
| Finished | Jan 21 12:30:57 PM PST 24 |
| Peak memory | 200980 kb |
| Host | smart-7fdb5394-c18b-4bc2-a133-dcde3b6202a1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278163751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c trl_ec_pwr_on_rst.278163751 |
| Directory | /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_edge_detect.646116515 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 3528357385 ps |
| CPU time | 2.65 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:30:55 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-b61b6008-9995-40ca-9653-279e91082bfd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646116515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctr l_edge_detect.646116515 |
| Directory | /workspace/43.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.282218505 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2609332206 ps |
| CPU time | 7.85 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:31:00 PM PST 24 |
| Peak memory | 200496 kb |
| Host | smart-f26c490b-c010-4185-b32e-5ba06f05ab4d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=282218505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.282218505 |
| Directory | /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2701208752 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2463049881 ps |
| CPU time | 7.46 seconds |
| Started | Jan 21 12:30:49 PM PST 24 |
| Finished | Jan 21 12:30:57 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-1196fb1e-1a3b-4408-bb68-28638e8393e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2701208752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.2701208752 |
| Directory | /workspace/43.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3544811344 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2056183230 ps |
| CPU time | 5.9 seconds |
| Started | Jan 21 12:30:49 PM PST 24 |
| Finished | Jan 21 12:30:55 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-b3de47ff-c744-4ed0-8406-1930ca141412 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3544811344 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.3544811344 |
| Directory | /workspace/43.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2768011788 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2522374344 ps |
| CPU time | 2.6 seconds |
| Started | Jan 21 12:30:49 PM PST 24 |
| Finished | Jan 21 12:30:52 PM PST 24 |
| Peak memory | 201108 kb |
| Host | smart-1784d234-03a5-4fa1-8c3a-81a2bf5dc057 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2768011788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.2768011788 |
| Directory | /workspace/43.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_smoke.1551322278 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 2113584259 ps |
| CPU time | 3.19 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:30:55 PM PST 24 |
| Peak memory | 200952 kb |
| Host | smart-e68ffa57-825d-453b-8060-5f8a497ff38f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1551322278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.1551322278 |
| Directory | /workspace/43.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_stress_all.636338723 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 203333938014 ps |
| CPU time | 513.77 seconds |
| Started | Jan 21 12:30:43 PM PST 24 |
| Finished | Jan 21 12:39:17 PM PST 24 |
| Peak memory | 201192 kb |
| Host | smart-17d389a0-8caf-43f1-a344-822fc8401bd7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636338723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_st ress_all.636338723 |
| Directory | /workspace/43.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4023120857 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 63603912877 ps |
| CPU time | 161.82 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:33:34 PM PST 24 |
| Peak memory | 209008 kb |
| Host | smart-27647ed3-7ad3-45f2-a5b6-78448d9eac47 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023120857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.4023120857 |
| Directory | /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2865575438 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 3993794326 ps |
| CPU time | 1.89 seconds |
| Started | Jan 21 12:30:52 PM PST 24 |
| Finished | Jan 21 12:30:55 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-62c0d02b-5ca1-4fa8-891d-a24d25952eeb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865575438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ ctrl_ultra_low_pwr.2865575438 |
| Directory | /workspace/43.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_alert_test.2866030401 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 2010355847 ps |
| CPU time | 5.5 seconds |
| Started | Jan 21 12:30:50 PM PST 24 |
| Finished | Jan 21 12:30:57 PM PST 24 |
| Peak memory | 200972 kb |
| Host | smart-781df42e-20ea-40c0-b434-9090f6d84de4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866030401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te st.2866030401 |
| Directory | /workspace/44.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.320802548 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3590765018 ps |
| CPU time | 2.83 seconds |
| Started | Jan 21 12:30:54 PM PST 24 |
| Finished | Jan 21 12:30:57 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-615e53b3-6d0d-4b80-ae4f-214258ac890b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320802548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.320802548 |
| Directory | /workspace/44.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1393249293 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 99894349449 ps |
| CPU time | 62.65 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:31:55 PM PST 24 |
| Peak memory | 201316 kb |
| Host | smart-2bd80a03-6ff9-4e6b-8d87-673c5638a2d1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393249293 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c trl_combo_detect.1393249293 |
| Directory | /workspace/44.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3881092161 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 28355606850 ps |
| CPU time | 19.09 seconds |
| Started | Jan 21 12:30:55 PM PST 24 |
| Finished | Jan 21 12:31:15 PM PST 24 |
| Peak memory | 201236 kb |
| Host | smart-21c9089c-112f-4724-a386-a48e2b4c442d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3881092161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_w ith_pre_cond.3881092161 |
| Directory | /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.205485493 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 3093442761 ps |
| CPU time | 7.45 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:30:59 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-eef9fd73-370e-4417-aa4d-c20a91273638 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205485493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c trl_ec_pwr_on_rst.205485493 |
| Directory | /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_edge_detect.525303041 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 4783378467 ps |
| CPU time | 7.87 seconds |
| Started | Jan 21 12:30:54 PM PST 24 |
| Finished | Jan 21 12:31:02 PM PST 24 |
| Peak memory | 201072 kb |
| Host | smart-0ba8f1be-84f1-4ab3-8cbb-5cbb3618d49d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525303041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctr l_edge_detect.525303041 |
| Directory | /workspace/44.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2917152446 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2626123506 ps |
| CPU time | 2.35 seconds |
| Started | Jan 21 12:30:54 PM PST 24 |
| Finished | Jan 21 12:30:57 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-fed87388-a0df-4b85-921c-3c660ccdd40c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2917152446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.2917152446 |
| Directory | /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2842184558 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2489052498 ps |
| CPU time | 2.23 seconds |
| Started | Jan 21 12:30:44 PM PST 24 |
| Finished | Jan 21 12:30:47 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-f9ed90de-03fd-4f65-ab26-0c58e620726b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2842184558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2842184558 |
| Directory | /workspace/44.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2788885578 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 2238957692 ps |
| CPU time | 6.33 seconds |
| Started | Jan 21 12:30:39 PM PST 24 |
| Finished | Jan 21 12:30:47 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-31b2d8fa-39f1-49d8-8f04-d3c015d14a4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2788885578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.2788885578 |
| Directory | /workspace/44.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3897056 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2538462111 ps |
| CPU time | 2.25 seconds |
| Started | Jan 21 12:30:52 PM PST 24 |
| Finished | Jan 21 12:30:56 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-a22c1b57-46ad-48c5-badc-3c1589bf0e2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3897056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3897056 |
| Directory | /workspace/44.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_smoke.313923787 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2140687245 ps |
| CPU time | 1.79 seconds |
| Started | Jan 21 12:30:49 PM PST 24 |
| Finished | Jan 21 12:30:51 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-770b51da-ea8a-48ad-b41e-af77126d5dfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=313923787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.313923787 |
| Directory | /workspace/44.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_stress_all.3155679046 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 13098630166 ps |
| CPU time | 30.06 seconds |
| Started | Jan 21 12:30:52 PM PST 24 |
| Finished | Jan 21 12:31:23 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-5835197c-fba8-4d6a-a1b9-ece2e3d20281 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155679046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s tress_all.3155679046 |
| Directory | /workspace/44.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.950427807 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 21726993046 ps |
| CPU time | 51.89 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:31:43 PM PST 24 |
| Peak memory | 217796 kb |
| Host | smart-3e364b1d-5b77-42dd-a0f8-8ae2a565871b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950427807 -assert n opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.950427807 |
| Directory | /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3239979165 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 6390563668 ps |
| CPU time | 6.48 seconds |
| Started | Jan 21 12:30:51 PM PST 24 |
| Finished | Jan 21 12:30:58 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-ff2bc760-453a-4d6f-b4d9-202fbf87b303 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239979165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ ctrl_ultra_low_pwr.3239979165 |
| Directory | /workspace/44.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_alert_test.1686322562 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 2066526864 ps |
| CPU time | 1.2 seconds |
| Started | Jan 21 12:31:01 PM PST 24 |
| Finished | Jan 21 12:31:03 PM PST 24 |
| Peak memory | 200960 kb |
| Host | smart-99cd8452-1dc9-4ac3-9216-9ea2c120149f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686322562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_te st.1686322562 |
| Directory | /workspace/45.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.525828903 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 3613572936 ps |
| CPU time | 1.45 seconds |
| Started | Jan 21 12:30:57 PM PST 24 |
| Finished | Jan 21 12:31:00 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-76f441b8-658d-4183-aecf-d8b593df2cc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=525828903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.525828903 |
| Directory | /workspace/45.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_combo_detect.152016156 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 76372934895 ps |
| CPU time | 116.4 seconds |
| Started | Jan 21 12:31:00 PM PST 24 |
| Finished | Jan 21 12:32:58 PM PST 24 |
| Peak memory | 201232 kb |
| Host | smart-a0837f3b-ac90-41c5-98c8-25b1574ad8f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152016156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct rl_combo_detect.152016156 |
| Directory | /workspace/45.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1589458478 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 62250456784 ps |
| CPU time | 74.11 seconds |
| Started | Jan 21 12:30:59 PM PST 24 |
| Finished | Jan 21 12:32:14 PM PST 24 |
| Peak memory | 201644 kb |
| Host | smart-d58200dc-ca88-4bbe-9b92-216455063fb0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1589458478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_w ith_pre_cond.1589458478 |
| Directory | /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2902023780 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 3083880629 ps |
| CPU time | 8.57 seconds |
| Started | Jan 21 12:30:55 PM PST 24 |
| Finished | Jan 21 12:31:04 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-f2ac1afa-45bf-4351-9fcc-76ff0ea3020a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902023780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ ctrl_ec_pwr_on_rst.2902023780 |
| Directory | /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_edge_detect.1510385617 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2402828490 ps |
| CPU time | 2.05 seconds |
| Started | Jan 21 12:31:00 PM PST 24 |
| Finished | Jan 21 12:31:04 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-c08a2bec-0e09-4f51-b838-3cea01b5f077 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510385617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct rl_edge_detect.1510385617 |
| Directory | /workspace/45.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2491007843 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 2612950423 ps |
| CPU time | 7.49 seconds |
| Started | Jan 21 12:30:52 PM PST 24 |
| Finished | Jan 21 12:31:00 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-5f85dad0-3016-4db8-96c7-c50c6bda1e76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2491007843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2491007843 |
| Directory | /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3150871676 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2475476317 ps |
| CPU time | 7.62 seconds |
| Started | Jan 21 12:30:49 PM PST 24 |
| Finished | Jan 21 12:30:58 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-30c75f99-39bc-41cf-ae98-d214560dcd63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150871676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3150871676 |
| Directory | /workspace/45.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1585555523 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2187607785 ps |
| CPU time | 6.48 seconds |
| Started | Jan 21 12:30:54 PM PST 24 |
| Finished | Jan 21 12:31:01 PM PST 24 |
| Peak memory | 201052 kb |
| Host | smart-7e08b312-c235-4704-befe-d3c492891e48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1585555523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.1585555523 |
| Directory | /workspace/45.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.982332776 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2516702769 ps |
| CPU time | 4.19 seconds |
| Started | Jan 21 12:30:52 PM PST 24 |
| Finished | Jan 21 12:30:57 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-c408459b-4a86-4043-8b75-3aff102f3eeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=982332776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.982332776 |
| Directory | /workspace/45.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_smoke.4144555284 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2135420668 ps |
| CPU time | 2.09 seconds |
| Started | Jan 21 12:30:52 PM PST 24 |
| Finished | Jan 21 12:30:55 PM PST 24 |
| Peak memory | 200944 kb |
| Host | smart-ca2d1a97-5def-4d1c-9fd2-fb1a61abf94b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144555284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.4144555284 |
| Directory | /workspace/45.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_stress_all.2386775664 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 251931368039 ps |
| CPU time | 354.69 seconds |
| Started | Jan 21 12:31:01 PM PST 24 |
| Finished | Jan 21 12:36:57 PM PST 24 |
| Peak memory | 201168 kb |
| Host | smart-2bfc26a9-789c-4146-a046-27b2feb2eeeb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386775664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s tress_all.2386775664 |
| Directory | /workspace/45.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2958986471 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 74964284453 ps |
| CPU time | 47.25 seconds |
| Started | Jan 21 12:31:16 PM PST 24 |
| Finished | Jan 21 12:32:04 PM PST 24 |
| Peak memory | 209468 kb |
| Host | smart-e3981339-c6a9-4f13-97b3-fa697620518d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958986471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2958986471 |
| Directory | /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2954604134 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 6926268284 ps |
| CPU time | 2.39 seconds |
| Started | Jan 21 12:30:56 PM PST 24 |
| Finished | Jan 21 12:31:00 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-b42764c2-d31b-4049-b220-b23c9fc512a2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954604134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ ctrl_ultra_low_pwr.2954604134 |
| Directory | /workspace/45.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_alert_test.1512833144 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2022253819 ps |
| CPU time | 3.12 seconds |
| Started | Jan 21 12:31:03 PM PST 24 |
| Finished | Jan 21 12:31:07 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-35d7c709-3020-4bd7-9fa5-9e5b4ece05d0 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512833144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te st.1512833144 |
| Directory | /workspace/46.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1234579374 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3103474018 ps |
| CPU time | 4.78 seconds |
| Started | Jan 21 12:30:58 PM PST 24 |
| Finished | Jan 21 12:31:03 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-599c02f5-3b1a-4747-8688-0c7158485a74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1234579374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.1 234579374 |
| Directory | /workspace/46.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_combo_detect.738650892 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 138694439355 ps |
| CPU time | 380.23 seconds |
| Started | Jan 21 12:31:15 PM PST 24 |
| Finished | Jan 21 12:37:36 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-3445210d-350d-4d1c-a420-e1a7e934b109 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738650892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct rl_combo_detect.738650892 |
| Directory | /workspace/46.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3039127943 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 26790279342 ps |
| CPU time | 11.94 seconds |
| Started | Jan 21 12:31:10 PM PST 24 |
| Finished | Jan 21 12:31:23 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-9de19da1-2f47-4d6d-abea-96ee4314a2e3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039127943 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w ith_pre_cond.3039127943 |
| Directory | /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3285017405 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 3175427938 ps |
| CPU time | 1.75 seconds |
| Started | Jan 21 12:31:10 PM PST 24 |
| Finished | Jan 21 12:31:13 PM PST 24 |
| Peak memory | 201200 kb |
| Host | smart-5a252762-9d62-41e2-bc18-54e648da803f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285017405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ ctrl_ec_pwr_on_rst.3285017405 |
| Directory | /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_edge_detect.466199641 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2656932947 ps |
| CPU time | 2.22 seconds |
| Started | Jan 21 12:31:16 PM PST 24 |
| Finished | Jan 21 12:31:18 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-3a7c0550-9d00-41d1-abbc-4a48a7355944 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466199641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctr l_edge_detect.466199641 |
| Directory | /workspace/46.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1582455532 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2615029191 ps |
| CPU time | 4.4 seconds |
| Started | Jan 21 12:30:59 PM PST 24 |
| Finished | Jan 21 12:31:06 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-b2225b93-4a44-43cf-9b82-bafaf0eb76e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582455532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1582455532 |
| Directory | /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.387722207 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2457079628 ps |
| CPU time | 6.59 seconds |
| Started | Jan 21 12:31:16 PM PST 24 |
| Finished | Jan 21 12:31:23 PM PST 24 |
| Peak memory | 201064 kb |
| Host | smart-43df5c4c-9b4e-46b7-904e-c32fb20a0475 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387722207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.387722207 |
| Directory | /workspace/46.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1242838896 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2212748345 ps |
| CPU time | 1.99 seconds |
| Started | Jan 21 12:30:59 PM PST 24 |
| Finished | Jan 21 12:31:02 PM PST 24 |
| Peak memory | 201148 kb |
| Host | smart-72e0b3ce-a303-49eb-a819-fc0330025c81 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242838896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1242838896 |
| Directory | /workspace/46.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.220243775 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2512779600 ps |
| CPU time | 7.06 seconds |
| Started | Jan 21 12:30:59 PM PST 24 |
| Finished | Jan 21 12:31:08 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-f77edd47-35cd-4d46-a8bc-b8f838835d0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220243775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.220243775 |
| Directory | /workspace/46.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_smoke.1750544491 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 2127663077 ps |
| CPU time | 1.78 seconds |
| Started | Jan 21 12:30:58 PM PST 24 |
| Finished | Jan 21 12:31:00 PM PST 24 |
| Peak memory | 200956 kb |
| Host | smart-1aad1bdb-29f3-40cf-a397-0d7ecc5928fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1750544491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.1750544491 |
| Directory | /workspace/46.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_stress_all.1078501306 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 9364224365 ps |
| CPU time | 13.62 seconds |
| Started | Jan 21 12:31:11 PM PST 24 |
| Finished | Jan 21 12:31:25 PM PST 24 |
| Peak memory | 201168 kb |
| Host | smart-e4aa001d-6d2c-47fb-8e46-80221c2321c8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078501306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_s tress_all.1078501306 |
| Directory | /workspace/46.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3274740096 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 36122063443 ps |
| CPU time | 5.73 seconds |
| Started | Jan 21 12:30:59 PM PST 24 |
| Finished | Jan 21 12:31:06 PM PST 24 |
| Peak memory | 209540 kb |
| Host | smart-52e0a788-283b-4c1c-99de-9a2a3b0e7cab |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274740096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.3274740096 |
| Directory | /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3469938059 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 6299276235 ps |
| CPU time | 5.28 seconds |
| Started | Jan 21 12:30:59 PM PST 24 |
| Finished | Jan 21 12:31:05 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-bc93613a-a1df-4ab5-9442-e04b2b1fdc91 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469938059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ ctrl_ultra_low_pwr.3469938059 |
| Directory | /workspace/46.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_alert_test.3366374844 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2038821422 ps |
| CPU time | 1.78 seconds |
| Started | Jan 21 12:31:11 PM PST 24 |
| Finished | Jan 21 12:31:14 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-17207daa-db75-4f12-9956-d2eafb126cf2 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366374844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te st.3366374844 |
| Directory | /workspace/47.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.4186362928 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 3843337937 ps |
| CPU time | 3.1 seconds |
| Started | Jan 21 12:31:13 PM PST 24 |
| Finished | Jan 21 12:31:17 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-09c03251-2d52-403d-99e1-b7fd336641de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186362928 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.4 186362928 |
| Directory | /workspace/47.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_combo_detect.1933831433 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 67016767861 ps |
| CPU time | 30.06 seconds |
| Started | Jan 21 12:31:02 PM PST 24 |
| Finished | Jan 21 12:31:33 PM PST 24 |
| Peak memory | 201136 kb |
| Host | smart-a01ab949-88f7-4185-b493-61446dea702c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933831433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c trl_combo_detect.1933831433 |
| Directory | /workspace/47.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2651384805 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 106145518220 ps |
| CPU time | 250.76 seconds |
| Started | Jan 21 12:31:11 PM PST 24 |
| Finished | Jan 21 12:35:23 PM PST 24 |
| Peak memory | 201284 kb |
| Host | smart-97ceec17-5251-4c12-a01e-4e31260fe523 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2651384805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w ith_pre_cond.2651384805 |
| Directory | /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1673729045 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 3817529415 ps |
| CPU time | 9.88 seconds |
| Started | Jan 21 12:31:02 PM PST 24 |
| Finished | Jan 21 12:31:13 PM PST 24 |
| Peak memory | 201456 kb |
| Host | smart-f2078dc7-fbd5-4add-a054-03cf4c45d834 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673729045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ ctrl_ec_pwr_on_rst.1673729045 |
| Directory | /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1150012971 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2652550001 ps |
| CPU time | 8.18 seconds |
| Started | Jan 21 12:31:06 PM PST 24 |
| Finished | Jan 21 12:31:15 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-ac691a92-c66d-4051-b2d9-eb836262a754 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150012971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct rl_edge_detect.1150012971 |
| Directory | /workspace/47.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.818778624 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2643449297 ps |
| CPU time | 1.67 seconds |
| Started | Jan 21 12:31:11 PM PST 24 |
| Finished | Jan 21 12:31:13 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-f607413b-b7c2-4788-8476-351563f0f914 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=818778624 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.818778624 |
| Directory | /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.524805148 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2431837174 ps |
| CPU time | 7.87 seconds |
| Started | Jan 21 12:31:10 PM PST 24 |
| Finished | Jan 21 12:31:19 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-29a51071-9a68-448f-b843-eafe52b8396f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524805148 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.524805148 |
| Directory | /workspace/47.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2012451189 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 2244357205 ps |
| CPU time | 1.67 seconds |
| Started | Jan 21 12:31:11 PM PST 24 |
| Finished | Jan 21 12:31:14 PM PST 24 |
| Peak memory | 201028 kb |
| Host | smart-8d639896-19b3-413a-bf5f-a84eee394338 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012451189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2012451189 |
| Directory | /workspace/47.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4230855015 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 2562092762 ps |
| CPU time | 1.72 seconds |
| Started | Jan 21 12:31:16 PM PST 24 |
| Finished | Jan 21 12:31:19 PM PST 24 |
| Peak memory | 200820 kb |
| Host | smart-557d5c4e-2a52-460a-9cd0-55324bc57508 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4230855015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.4230855015 |
| Directory | /workspace/47.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_smoke.1247761661 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2118148577 ps |
| CPU time | 3.58 seconds |
| Started | Jan 21 12:31:06 PM PST 24 |
| Finished | Jan 21 12:31:11 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-9646c18d-340f-465e-984e-79e97b18b461 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1247761661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.1247761661 |
| Directory | /workspace/47.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3610350581 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4823541607 ps |
| CPU time | 7.62 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:31:28 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-1635acb1-aa9e-48ff-b07f-fd210d309780 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610350581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ ctrl_ultra_low_pwr.3610350581 |
| Directory | /workspace/47.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_alert_test.4086697948 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 2014180215 ps |
| CPU time | 5.99 seconds |
| Started | Jan 21 12:31:16 PM PST 24 |
| Finished | Jan 21 12:31:23 PM PST 24 |
| Peak memory | 200888 kb |
| Host | smart-9bf69d48-5052-45f9-bc68-94217753bc36 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086697948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te st.4086697948 |
| Directory | /workspace/48.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.324470878 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 3303393774 ps |
| CPU time | 2 seconds |
| Started | Jan 21 12:31:05 PM PST 24 |
| Finished | Jan 21 12:31:07 PM PST 24 |
| Peak memory | 201128 kb |
| Host | smart-dfddb06b-b540-4fc1-8441-dcffd6885267 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324470878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.324470878 |
| Directory | /workspace/48.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_combo_detect.1108284191 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 120407555796 ps |
| CPU time | 328.06 seconds |
| Started | Jan 21 12:31:05 PM PST 24 |
| Finished | Jan 21 12:36:34 PM PST 24 |
| Peak memory | 201116 kb |
| Host | smart-dcb3ef96-af59-4daa-b9cb-ca7e0a4486b3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108284191 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c trl_combo_detect.1108284191 |
| Directory | /workspace/48.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4217012567 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 30523321675 ps |
| CPU time | 20.78 seconds |
| Started | Jan 21 12:31:06 PM PST 24 |
| Finished | Jan 21 12:31:28 PM PST 24 |
| Peak memory | 201236 kb |
| Host | smart-5514f9ca-d3a3-4c0c-8f19-c979244f4212 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217012567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w ith_pre_cond.4217012567 |
| Directory | /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.735819888 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3040188286 ps |
| CPU time | 2.64 seconds |
| Started | Jan 21 12:31:16 PM PST 24 |
| Finished | Jan 21 12:31:20 PM PST 24 |
| Peak memory | 200712 kb |
| Host | smart-3bc9a9ae-7571-4241-8c4c-6ca3f1aa81f3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735819888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c trl_ec_pwr_on_rst.735819888 |
| Directory | /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_edge_detect.1096040754 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 4691037194 ps |
| CPU time | 2.82 seconds |
| Started | Jan 21 12:31:04 PM PST 24 |
| Finished | Jan 21 12:31:07 PM PST 24 |
| Peak memory | 201212 kb |
| Host | smart-78501216-690a-4e79-8943-eddefb982e48 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096040754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct rl_edge_detect.1096040754 |
| Directory | /workspace/48.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1152435159 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 2634624141 ps |
| CPU time | 2.59 seconds |
| Started | Jan 21 12:31:07 PM PST 24 |
| Finished | Jan 21 12:31:10 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-a8ff1adc-7a03-4332-94b0-f499f9b72b7e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152435159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1152435159 |
| Directory | /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.4242464083 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2462196962 ps |
| CPU time | 2.35 seconds |
| Started | Jan 21 12:31:14 PM PST 24 |
| Finished | Jan 21 12:31:17 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-41618e04-6098-45c7-8250-678543831ecd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242464083 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.4242464083 |
| Directory | /workspace/48.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.4096616758 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2259462247 ps |
| CPU time | 6.61 seconds |
| Started | Jan 21 12:31:06 PM PST 24 |
| Finished | Jan 21 12:31:13 PM PST 24 |
| Peak memory | 200996 kb |
| Host | smart-6a473eea-e36e-4935-a661-4891fc3ddaf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4096616758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.4096616758 |
| Directory | /workspace/48.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4090787492 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2526784858 ps |
| CPU time | 3.13 seconds |
| Started | Jan 21 12:31:13 PM PST 24 |
| Finished | Jan 21 12:31:17 PM PST 24 |
| Peak memory | 201100 kb |
| Host | smart-c8e85c1f-920a-4a6a-b50d-d804673196a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4090787492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.4090787492 |
| Directory | /workspace/48.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_smoke.514636174 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2124005564 ps |
| CPU time | 2.15 seconds |
| Started | Jan 21 12:31:08 PM PST 24 |
| Finished | Jan 21 12:31:11 PM PST 24 |
| Peak memory | 201004 kb |
| Host | smart-fff084b5-f814-4ce1-807b-7b079cf1fc80 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=514636174 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.514636174 |
| Directory | /workspace/48.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_stress_all.1710996537 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 10127069464 ps |
| CPU time | 25.06 seconds |
| Started | Jan 21 12:31:09 PM PST 24 |
| Finished | Jan 21 12:31:34 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-806210f6-0c93-4fb1-a8dc-b4d170d6e28b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710996537 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s tress_all.1710996537 |
| Directory | /workspace/48.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1797624650 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 13022875369 ps |
| CPU time | 27.1 seconds |
| Started | Jan 21 12:31:07 PM PST 24 |
| Finished | Jan 21 12:31:35 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-43fcc1de-a085-4c41-8345-c6cc5b1717ce |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797624650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1797624650 |
| Directory | /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3899810263 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 7009723842 ps |
| CPU time | 1.28 seconds |
| Started | Jan 21 12:31:06 PM PST 24 |
| Finished | Jan 21 12:31:08 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-dccc9b23-eb87-4ed4-b76e-e21df527460a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899810263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ ctrl_ultra_low_pwr.3899810263 |
| Directory | /workspace/48.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_alert_test.1783716238 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2010769379 ps |
| CPU time | 6.06 seconds |
| Started | Jan 21 12:31:11 PM PST 24 |
| Finished | Jan 21 12:31:18 PM PST 24 |
| Peak memory | 201000 kb |
| Host | smart-e46cefab-1d1e-4175-ac62-c6cdd9207995 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783716238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te st.1783716238 |
| Directory | /workspace/49.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3889730956 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 122329739170 ps |
| CPU time | 77.97 seconds |
| Started | Jan 21 12:31:18 PM PST 24 |
| Finished | Jan 21 12:32:37 PM PST 24 |
| Peak memory | 201548 kb |
| Host | smart-6cbdf3ed-db63-4586-bd93-ad6b61ab7035 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3889730956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.3 889730956 |
| Directory | /workspace/49.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_combo_detect.1331402997 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 46590094063 ps |
| CPU time | 29.8 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:31:51 PM PST 24 |
| Peak memory | 201128 kb |
| Host | smart-d6e2f3e5-8a42-4b2f-ba65-a84a113e72ec |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331402997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c trl_combo_detect.1331402997 |
| Directory | /workspace/49.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3140507702 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 32685829991 ps |
| CPU time | 23.37 seconds |
| Started | Jan 21 12:31:14 PM PST 24 |
| Finished | Jan 21 12:31:38 PM PST 24 |
| Peak memory | 201312 kb |
| Host | smart-8128e251-b479-4cb7-a3c0-e76a3c6e7ff9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140507702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w ith_pre_cond.3140507702 |
| Directory | /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1772766741 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 3748754899 ps |
| CPU time | 10.75 seconds |
| Started | Jan 21 12:31:14 PM PST 24 |
| Finished | Jan 21 12:31:26 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-c1a3fdad-ed7e-43f0-8f20-28c044e1d35b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772766741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ ctrl_ec_pwr_on_rst.1772766741 |
| Directory | /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_edge_detect.1712437060 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 4010632463 ps |
| CPU time | 1.52 seconds |
| Started | Jan 21 12:31:11 PM PST 24 |
| Finished | Jan 21 12:31:13 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-27123917-795e-49df-a477-5eb2072dc2e4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712437060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct rl_edge_detect.1712437060 |
| Directory | /workspace/49.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.203073282 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2733287314 ps |
| CPU time | 0.95 seconds |
| Started | Jan 21 12:31:23 PM PST 24 |
| Finished | Jan 21 12:31:24 PM PST 24 |
| Peak memory | 201076 kb |
| Host | smart-adeb79c6-34ff-4c49-b156-68212a69ec2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=203073282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.203073282 |
| Directory | /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3658104319 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2475278638 ps |
| CPU time | 3.86 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:31:25 PM PST 24 |
| Peak memory | 201044 kb |
| Host | smart-4efa4ecd-2e0c-4e33-ba31-b0910239643c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658104319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3658104319 |
| Directory | /workspace/49.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3094142642 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2122914737 ps |
| CPU time | 1.13 seconds |
| Started | Jan 21 12:31:19 PM PST 24 |
| Finished | Jan 21 12:31:21 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-a5203d7f-7080-486c-b8a8-c66bd49fd066 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3094142642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.3094142642 |
| Directory | /workspace/49.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2596837288 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 2531355381 ps |
| CPU time | 2.38 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:31:23 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-1de4ce83-e970-4457-afc9-9cd6cbbea916 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596837288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.2596837288 |
| Directory | /workspace/49.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_smoke.864537118 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2131452349 ps |
| CPU time | 1.85 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:31:23 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-7d31a369-c4b0-45b6-9bc4-662372e2f39b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=864537118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.864537118 |
| Directory | /workspace/49.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_stress_all.2827731504 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 16870361574 ps |
| CPU time | 7.73 seconds |
| Started | Jan 21 12:31:12 PM PST 24 |
| Finished | Jan 21 12:31:20 PM PST 24 |
| Peak memory | 201084 kb |
| Host | smart-8bb9201d-3a3b-4bbc-b143-9ea8f25ff42a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827731504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s tress_all.2827731504 |
| Directory | /workspace/49.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3138638113 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 81389058265 ps |
| CPU time | 55.06 seconds |
| Started | Jan 21 12:31:14 PM PST 24 |
| Finished | Jan 21 12:32:09 PM PST 24 |
| Peak memory | 209444 kb |
| Host | smart-de57d3e4-428c-4dff-84bf-ff137ca8c658 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138638113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.3138638113 |
| Directory | /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3392302724 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 4894902857 ps |
| CPU time | 8.47 seconds |
| Started | Jan 21 12:31:17 PM PST 24 |
| Finished | Jan 21 12:31:26 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-62b0541a-641b-47b0-b8e0-6b0712bf83af |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392302724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ ctrl_ultra_low_pwr.3392302724 |
| Directory | /workspace/49.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_alert_test.2998254433 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2064244216 ps |
| CPU time | 1.19 seconds |
| Started | Jan 21 12:27:11 PM PST 24 |
| Finished | Jan 21 12:27:16 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-25f5cd4f-6903-4c3b-a985-505016553ec4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998254433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_tes t.2998254433 |
| Directory | /workspace/5.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.712831984 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3008308590 ps |
| CPU time | 8.45 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:10 PM PST 24 |
| Peak memory | 201460 kb |
| Host | smart-7c6f2fee-1c13-406c-b000-d5aaaf1d6ac5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=712831984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.712831984 |
| Directory | /workspace/5.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_combo_detect.543483509 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 66030497080 ps |
| CPU time | 43.4 seconds |
| Started | Jan 21 12:27:06 PM PST 24 |
| Finished | Jan 21 12:27:56 PM PST 24 |
| Peak memory | 201196 kb |
| Host | smart-30f979a5-0c2b-4690-9485-685d435e0aa6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543483509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr l_combo_detect.543483509 |
| Directory | /workspace/5.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3693527075 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 22600336210 ps |
| CPU time | 22.66 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:40 PM PST 24 |
| Peak memory | 201292 kb |
| Host | smart-e514c717-694f-40ae-9f7e-5cd385fe648c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3693527075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi th_pre_cond.3693527075 |
| Directory | /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3929083150 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 3061102406 ps |
| CPU time | 2.46 seconds |
| Started | Jan 21 12:27:07 PM PST 24 |
| Finished | Jan 21 12:27:15 PM PST 24 |
| Peak memory | 201016 kb |
| Host | smart-18e91da1-ba9b-4e3b-97ac-e6d90fc21045 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929083150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c trl_ec_pwr_on_rst.3929083150 |
| Directory | /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_edge_detect.1872646854 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 854207687976 ps |
| CPU time | 303.39 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:32:21 PM PST 24 |
| Peak memory | 201112 kb |
| Host | smart-5b7956e6-b4d6-4d8c-bdc0-62bafce8b8ab |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872646854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr l_edge_detect.1872646854 |
| Directory | /workspace/5.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2303631152 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2614377266 ps |
| CPU time | 7.88 seconds |
| Started | Jan 21 12:27:04 PM PST 24 |
| Finished | Jan 21 12:27:18 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-9837b82f-4b5b-45e5-b4f0-5007a89c4e55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303631152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2303631152 |
| Directory | /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1280775690 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2481518827 ps |
| CPU time | 2.2 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:27:16 PM PST 24 |
| Peak memory | 200680 kb |
| Host | smart-df3f8bc3-390a-4552-9053-54157d5b6748 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1280775690 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.1280775690 |
| Directory | /workspace/5.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.287194296 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2243992939 ps |
| CPU time | 2.04 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:27:18 PM PST 24 |
| Peak memory | 200620 kb |
| Host | smart-b8a4a4c6-27f8-42cb-be06-16f6fd899051 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=287194296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.287194296 |
| Directory | /workspace/5.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1063273286 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 2511676491 ps |
| CPU time | 7.41 seconds |
| Started | Jan 21 12:27:01 PM PST 24 |
| Finished | Jan 21 12:27:11 PM PST 24 |
| Peak memory | 200940 kb |
| Host | smart-9c03194a-9ad9-4c06-8b2c-fde444d3ebed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063273286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1063273286 |
| Directory | /workspace/5.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_smoke.1710433469 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2216780431 ps |
| CPU time | 0.97 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:02 PM PST 24 |
| Peak memory | 201436 kb |
| Host | smart-2bf57981-b341-454d-ab6c-cd31c7e04166 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710433469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1710433469 |
| Directory | /workspace/5.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_stress_all.1144058404 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 19072432100 ps |
| CPU time | 43.99 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:28:00 PM PST 24 |
| Peak memory | 200964 kb |
| Host | smart-6e009cca-4439-47c4-9f03-54dbfb75818b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144058404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_st ress_all.1144058404 |
| Directory | /workspace/5.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3795146664 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 6598653981 ps |
| CPU time | 2.3 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-1b63e2a6-cdd5-4b86-8034-a1fc1a56becb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795146664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c trl_ultra_low_pwr.3795146664 |
| Directory | /workspace/5.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.149614460 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 36980800472 ps |
| CPU time | 101.3 seconds |
| Started | Jan 21 12:31:21 PM PST 24 |
| Finished | Jan 21 12:33:03 PM PST 24 |
| Peak memory | 201288 kb |
| Host | smart-4cd15c58-3f79-447b-819a-6340868bd6f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=149614460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_wi th_pre_cond.149614460 |
| Directory | /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3340818160 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 41144593339 ps |
| CPU time | 26.3 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:31:47 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-a69e3a0f-1e27-4d68-be20-278d675c0988 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3340818160 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w ith_pre_cond.3340818160 |
| Directory | /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.528284425 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 176193654841 ps |
| CPU time | 470.33 seconds |
| Started | Jan 21 12:31:14 PM PST 24 |
| Finished | Jan 21 12:39:05 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-b987100e-4b7f-417e-a541-b4f34b30eb54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=528284425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_wi th_pre_cond.528284425 |
| Directory | /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1802125741 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 66336934387 ps |
| CPU time | 89.79 seconds |
| Started | Jan 21 12:31:21 PM PST 24 |
| Finished | Jan 21 12:32:51 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-d924498f-7dd2-4545-ba1c-de1da72bb321 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1802125741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w ith_pre_cond.1802125741 |
| Directory | /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.624256919 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 82684288025 ps |
| CPU time | 53.89 seconds |
| Started | Jan 21 12:31:12 PM PST 24 |
| Finished | Jan 21 12:32:07 PM PST 24 |
| Peak memory | 201260 kb |
| Host | smart-de65405c-3e0e-4ec5-9335-5123ecfee585 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624256919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_wi th_pre_cond.624256919 |
| Directory | /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3740389217 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 64582897224 ps |
| CPU time | 13.16 seconds |
| Started | Jan 21 12:31:18 PM PST 24 |
| Finished | Jan 21 12:31:32 PM PST 24 |
| Peak memory | 201412 kb |
| Host | smart-0c768f55-8ba1-4afd-be97-36ef588bb427 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740389217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w ith_pre_cond.3740389217 |
| Directory | /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1342719453 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 152339386317 ps |
| CPU time | 102.77 seconds |
| Started | Jan 21 12:31:15 PM PST 24 |
| Finished | Jan 21 12:32:59 PM PST 24 |
| Peak memory | 201340 kb |
| Host | smart-e9769264-0613-4c9b-af48-7728be962a09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1342719453 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w ith_pre_cond.1342719453 |
| Directory | /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_alert_test.2162478301 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2040624994 ps |
| CPU time | 1.81 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:27:18 PM PST 24 |
| Peak memory | 200836 kb |
| Host | smart-1139e632-7d40-4880-b02d-e185651517c3 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162478301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_tes t.2162478301 |
| Directory | /workspace/6.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3275315093 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3672689752 ps |
| CPU time | 4.52 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:27:18 PM PST 24 |
| Peak memory | 200688 kb |
| Host | smart-5548a6c8-ad5c-42a8-9dbe-9646fdfa3f5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275315093 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.3275315093 |
| Directory | /workspace/6.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_combo_detect.2869007311 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 161870150689 ps |
| CPU time | 105.97 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:28:59 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-31d76afb-6058-435a-aa78-08ca9252c95f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869007311 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct rl_combo_detect.2869007311 |
| Directory | /workspace/6.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3533649795 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 5090600251 ps |
| CPU time | 13.73 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:27:30 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-f6d0a457-4438-4908-87b0-4426031e87be |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533649795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c trl_ec_pwr_on_rst.3533649795 |
| Directory | /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_edge_detect.2706197437 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3444935044 ps |
| CPU time | 2.35 seconds |
| Started | Jan 21 12:26:59 PM PST 24 |
| Finished | Jan 21 12:27:03 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-8198304b-500f-46e3-af68-ad0143489c66 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706197437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr l_edge_detect.2706197437 |
| Directory | /workspace/6.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3684369807 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 2615252763 ps |
| CPU time | 7.78 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:26 PM PST 24 |
| Peak memory | 201048 kb |
| Host | smart-785e824f-9080-4bdb-b456-c0d3c866c217 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3684369807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3684369807 |
| Directory | /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.4139638978 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2517697429 ps |
| CPU time | 1.43 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 200988 kb |
| Host | smart-c74476d8-1994-44b3-984c-afef0f44e9a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139638978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.4139638978 |
| Directory | /workspace/6.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.631451263 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2063987825 ps |
| CPU time | 5.97 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:23 PM PST 24 |
| Peak memory | 200864 kb |
| Host | smart-203cc930-9a77-46d2-a853-fc273b12178f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=631451263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.631451263 |
| Directory | /workspace/6.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1612591731 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 2515348391 ps |
| CPU time | 4.09 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:21 PM PST 24 |
| Peak memory | 200956 kb |
| Host | smart-e26a9248-7bbc-40d7-8534-961bd95245b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1612591731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.1612591731 |
| Directory | /workspace/6.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_smoke.3018299657 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2129044716 ps |
| CPU time | 1.98 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 200988 kb |
| Host | smart-4bd578bf-bad9-420c-adcd-0b8c2d7e4bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3018299657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3018299657 |
| Directory | /workspace/6.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_stress_all.2367474049 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 128209033577 ps |
| CPU time | 306.05 seconds |
| Started | Jan 21 12:27:25 PM PST 24 |
| Finished | Jan 21 12:32:32 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-59f3b4b9-e002-476d-a8cb-2abcb83368fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367474049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st ress_all.2367474049 |
| Directory | /workspace/6.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1801969783 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 82884694859 ps |
| CPU time | 48.51 seconds |
| Started | Jan 21 12:27:16 PM PST 24 |
| Finished | Jan 21 12:28:06 PM PST 24 |
| Peak memory | 209508 kb |
| Host | smart-701d5f47-a05b-4018-94bd-6d169b325eca |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801969783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.1801969783 |
| Directory | /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.350703671 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 4286675439 ps |
| CPU time | 3.76 seconds |
| Started | Jan 21 12:27:10 PM PST 24 |
| Finished | Jan 21 12:27:17 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-27c68c3c-c85e-453b-911d-e5feed3761dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350703671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct rl_ultra_low_pwr.350703671 |
| Directory | /workspace/6.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.581860736 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 80682338074 ps |
| CPU time | 51.68 seconds |
| Started | Jan 21 12:31:21 PM PST 24 |
| Finished | Jan 21 12:32:13 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-51a9dacb-6ef0-4456-b949-c7b00aba9ec5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=581860736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_wi th_pre_cond.581860736 |
| Directory | /workspace/60.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2088958158 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 157533289412 ps |
| CPU time | 100.87 seconds |
| Started | Jan 21 12:31:22 PM PST 24 |
| Finished | Jan 21 12:33:04 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-3de8a145-3ce7-40a8-bfa2-b8ed8eb27be0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088958158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_w ith_pre_cond.2088958158 |
| Directory | /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.698141812 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 26752880024 ps |
| CPU time | 4.95 seconds |
| Started | Jan 21 12:31:22 PM PST 24 |
| Finished | Jan 21 12:31:28 PM PST 24 |
| Peak memory | 201384 kb |
| Host | smart-fb2580bb-3093-4d8f-b0f3-87a475f6f790 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=698141812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_wi th_pre_cond.698141812 |
| Directory | /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1769235437 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 158510592643 ps |
| CPU time | 161.89 seconds |
| Started | Jan 21 12:31:20 PM PST 24 |
| Finished | Jan 21 12:34:03 PM PST 24 |
| Peak memory | 201244 kb |
| Host | smart-2f4e9a8d-745e-4b01-a774-25bf448b8182 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769235437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w ith_pre_cond.1769235437 |
| Directory | /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2933605548 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 104463850277 ps |
| CPU time | 72.26 seconds |
| Started | Jan 21 12:31:21 PM PST 24 |
| Finished | Jan 21 12:32:34 PM PST 24 |
| Peak memory | 201268 kb |
| Host | smart-5d3ab2bc-5168-4d44-8ed8-e161a7801d82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2933605548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w ith_pre_cond.2933605548 |
| Directory | /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1114503718 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 27106861317 ps |
| CPU time | 19.09 seconds |
| Started | Jan 21 12:31:18 PM PST 24 |
| Finished | Jan 21 12:31:38 PM PST 24 |
| Peak memory | 201268 kb |
| Host | smart-a602b91e-c304-452a-9403-015aff4a3c52 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1114503718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_w ith_pre_cond.1114503718 |
| Directory | /workspace/65.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3244756639 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 65548139309 ps |
| CPU time | 43.25 seconds |
| Started | Jan 21 12:31:17 PM PST 24 |
| Finished | Jan 21 12:32:01 PM PST 24 |
| Peak memory | 201232 kb |
| Host | smart-4b232657-ca37-4325-9d42-0dfefef43e85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3244756639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_w ith_pre_cond.3244756639 |
| Directory | /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.725004074 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 27349913949 ps |
| CPU time | 18.36 seconds |
| Started | Jan 21 12:31:21 PM PST 24 |
| Finished | Jan 21 12:31:40 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-dfb9cc7b-5c52-4772-ab62-ef1308e2dcef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725004074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_wi th_pre_cond.725004074 |
| Directory | /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_alert_test.2973774157 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 2022985936 ps |
| CPU time | 2.75 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 200580 kb |
| Host | smart-eacfd0c4-16a2-4784-a30f-fc5ba04558fd |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973774157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_tes t.2973774157 |
| Directory | /workspace/7.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.736464767 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 3323443533 ps |
| CPU time | 1.87 seconds |
| Started | Jan 21 12:27:11 PM PST 24 |
| Finished | Jan 21 12:27:16 PM PST 24 |
| Peak memory | 201108 kb |
| Host | smart-4f3955bf-126a-472e-a4a0-f5eb314b6a0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736464767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.736464767 |
| Directory | /workspace/7.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_combo_detect.844577260 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 111710806714 ps |
| CPU time | 277.02 seconds |
| Started | Jan 21 12:27:25 PM PST 24 |
| Finished | Jan 21 12:32:03 PM PST 24 |
| Peak memory | 201180 kb |
| Host | smart-1c631ed7-dcaa-4f4f-829a-dde2e98c01e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844577260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr l_combo_detect.844577260 |
| Directory | /workspace/7.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.116366034 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 2996227372 ps |
| CPU time | 2.61 seconds |
| Started | Jan 21 12:27:11 PM PST 24 |
| Finished | Jan 21 12:27:16 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-92af0b85-9715-41e0-8b30-b3c455a69118 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116366034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct rl_ec_pwr_on_rst.116366034 |
| Directory | /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2625158386 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 4898268966 ps |
| CPU time | 9.69 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:27:40 PM PST 24 |
| Peak memory | 201056 kb |
| Host | smart-b286df67-778b-4504-b761-e6e49b9c55f2 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625158386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr l_edge_detect.2625158386 |
| Directory | /workspace/7.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.674066766 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2620840512 ps |
| CPU time | 4.43 seconds |
| Started | Jan 21 12:27:11 PM PST 24 |
| Finished | Jan 21 12:27:18 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-5d263817-a362-4136-bd08-d86165b6ef71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674066766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.674066766 |
| Directory | /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3354580948 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2435620747 ps |
| CPU time | 3.57 seconds |
| Started | Jan 21 12:27:05 PM PST 24 |
| Finished | Jan 21 12:27:16 PM PST 24 |
| Peak memory | 201032 kb |
| Host | smart-38c1d30e-655c-4d1e-9926-555bb46cd0c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3354580948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3354580948 |
| Directory | /workspace/7.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.151800640 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 2017320460 ps |
| CPU time | 5.85 seconds |
| Started | Jan 21 12:27:24 PM PST 24 |
| Finished | Jan 21 12:27:30 PM PST 24 |
| Peak memory | 200932 kb |
| Host | smart-be550ce9-5997-486c-a182-183a974f7f6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=151800640 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.151800640 |
| Directory | /workspace/7.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1772724916 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2512740136 ps |
| CPU time | 5.65 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:27:36 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-58dd4b47-fdd4-4068-b6e5-763a5fd2b313 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772724916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.1772724916 |
| Directory | /workspace/7.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_smoke.4101484675 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 2137093489 ps |
| CPU time | 2.12 seconds |
| Started | Jan 21 12:27:05 PM PST 24 |
| Finished | Jan 21 12:27:15 PM PST 24 |
| Peak memory | 200960 kb |
| Host | smart-bc4ef37b-35f8-44af-b992-fc3271ece30a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101484675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.4101484675 |
| Directory | /workspace/7.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_stress_all.284412007 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 9215354230 ps |
| CPU time | 6.65 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:27:23 PM PST 24 |
| Peak memory | 200900 kb |
| Host | smart-dd4d181e-4a0b-4ab1-8d9a-70eaf78cfa90 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284412007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_str ess_all.284412007 |
| Directory | /workspace/7.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2681445814 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 194128569442 ps |
| CPU time | 127.41 seconds |
| Started | Jan 21 12:27:11 PM PST 24 |
| Finished | Jan 21 12:29:21 PM PST 24 |
| Peak memory | 214592 kb |
| Host | smart-725ef1a8-7c5b-4a0b-ac06-006ec4e9776a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681445814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2681445814 |
| Directory | /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.977207648 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5204339236 ps |
| CPU time | 2.61 seconds |
| Started | Jan 21 12:27:15 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 200860 kb |
| Host | smart-9e94020a-84b9-42fd-b9e1-141d6c5e5e8f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977207648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ct rl_ultra_low_pwr.977207648 |
| Directory | /workspace/7.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2275132044 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 120126595200 ps |
| CPU time | 317.1 seconds |
| Started | Jan 21 12:31:21 PM PST 24 |
| Finished | Jan 21 12:36:38 PM PST 24 |
| Peak memory | 201232 kb |
| Host | smart-89e1564f-d12a-4251-9665-76b8ce76ac5b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2275132044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_w ith_pre_cond.2275132044 |
| Directory | /workspace/70.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2492056095 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 53521171556 ps |
| CPU time | 39.2 seconds |
| Started | Jan 21 12:31:18 PM PST 24 |
| Finished | Jan 21 12:31:58 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-8f1b7f9e-51d8-44dc-a36d-519aa37a0a49 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2492056095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w ith_pre_cond.2492056095 |
| Directory | /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.103565684 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 22329723984 ps |
| CPU time | 61.57 seconds |
| Started | Jan 21 12:31:38 PM PST 24 |
| Finished | Jan 21 12:32:41 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-0b774ee5-73ba-419e-91ae-611ff5348c79 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=103565684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_wi th_pre_cond.103565684 |
| Directory | /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2521754092 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 23581031081 ps |
| CPU time | 59.42 seconds |
| Started | Jan 21 12:31:38 PM PST 24 |
| Finished | Jan 21 12:32:39 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-58cbbeea-4641-4481-bce3-de9f93a8b782 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2521754092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_w ith_pre_cond.2521754092 |
| Directory | /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2772843611 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 38639300281 ps |
| CPU time | 47.52 seconds |
| Started | Jan 21 12:31:38 PM PST 24 |
| Finished | Jan 21 12:32:27 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-fc8b31f4-6e5a-444e-8e37-de4bd6027252 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772843611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_w ith_pre_cond.2772843611 |
| Directory | /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4083493965 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 88415504748 ps |
| CPU time | 215 seconds |
| Started | Jan 21 12:31:21 PM PST 24 |
| Finished | Jan 21 12:34:57 PM PST 24 |
| Peak memory | 201252 kb |
| Host | smart-ae8cc7d4-a231-46d1-a713-facbc71228ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083493965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w ith_pre_cond.4083493965 |
| Directory | /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1836699450 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 90903960008 ps |
| CPU time | 63.96 seconds |
| Started | Jan 21 12:31:23 PM PST 24 |
| Finished | Jan 21 12:32:27 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-2f959838-3f53-4f70-88ed-5babce915e70 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1836699450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w ith_pre_cond.1836699450 |
| Directory | /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_alert_test.2557660156 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2040659383 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 12:27:46 PM PST 24 |
| Finished | Jan 21 12:27:49 PM PST 24 |
| Peak memory | 200992 kb |
| Host | smart-06024d41-3768-4d3e-887e-1d6d4b7d6bee |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557660156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes t.2557660156 |
| Directory | /workspace/8.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1062521213 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 3971570045 ps |
| CPU time | 5.79 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:27:36 PM PST 24 |
| Peak memory | 201104 kb |
| Host | smart-9dc0a5b0-f90e-47c6-b746-711bbb681c14 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1062521213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1062521213 |
| Directory | /workspace/8.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3553227653 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 65711295470 ps |
| CPU time | 174.89 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:30:25 PM PST 24 |
| Peak memory | 201152 kb |
| Host | smart-4d57b740-c911-49c6-aedf-c352cb121ffb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553227653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct rl_combo_detect.3553227653 |
| Directory | /workspace/8.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3156775517 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3303356540 ps |
| CPU time | 5.06 seconds |
| Started | Jan 21 12:27:25 PM PST 24 |
| Finished | Jan 21 12:27:30 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-f1caefef-39d9-48d6-a1ef-7c0867e5dba1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156775517 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c trl_ec_pwr_on_rst.3156775517 |
| Directory | /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_edge_detect.3092204892 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 3934792432 ps |
| CPU time | 8.84 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:27:40 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-a1a09707-1231-4b2a-8314-96d21967a9b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092204892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr l_edge_detect.3092204892 |
| Directory | /workspace/8.sysrst_ctrl_edge_detect/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1619551419 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 2614449690 ps |
| CPU time | 7.27 seconds |
| Started | Jan 21 12:27:25 PM PST 24 |
| Finished | Jan 21 12:27:33 PM PST 24 |
| Peak memory | 200764 kb |
| Host | smart-b63aa903-81cf-4238-b456-9e3176edc7c0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619551419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1619551419 |
| Directory | /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3139957671 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2476551154 ps |
| CPU time | 3.94 seconds |
| Started | Jan 21 12:27:11 PM PST 24 |
| Finished | Jan 21 12:27:19 PM PST 24 |
| Peak memory | 201012 kb |
| Host | smart-a1bdab35-4654-4000-9f97-c23938d781f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3139957671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.3139957671 |
| Directory | /workspace/8.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.414376405 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2232324875 ps |
| CPU time | 1.33 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:27:31 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-89f889d5-3c72-43c3-ad18-b33c5cb6e7dc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=414376405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.414376405 |
| Directory | /workspace/8.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3692046761 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2510219406 ps |
| CPU time | 6.92 seconds |
| Started | Jan 21 12:27:11 PM PST 24 |
| Finished | Jan 21 12:27:22 PM PST 24 |
| Peak memory | 201040 kb |
| Host | smart-151f5997-3e42-4698-ad4f-afd076fadfc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3692046761 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.3692046761 |
| Directory | /workspace/8.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_smoke.2932684057 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2128170845 ps |
| CPU time | 1.91 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:27:32 PM PST 24 |
| Peak memory | 200960 kb |
| Host | smart-b47762dc-9eb3-45a4-8776-1664dbbfd075 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932684057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.2932684057 |
| Directory | /workspace/8.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_stress_all.888545708 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 8218984066 ps |
| CPU time | 5.46 seconds |
| Started | Jan 21 12:27:33 PM PST 24 |
| Finished | Jan 21 12:27:39 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-c0a8b4d6-d10f-40fa-8cd1-05586ed2a713 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888545708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_str ess_all.888545708 |
| Directory | /workspace/8.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3841398254 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 7061466924 ps |
| CPU time | 7.57 seconds |
| Started | Jan 21 12:27:29 PM PST 24 |
| Finished | Jan 21 12:27:38 PM PST 24 |
| Peak memory | 201080 kb |
| Host | smart-6cbfdfe3-2388-4dba-aebe-f7a091f3ce77 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841398254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c trl_ultra_low_pwr.3841398254 |
| Directory | /workspace/8.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1634064758 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 77361746292 ps |
| CPU time | 193.09 seconds |
| Started | Jan 21 12:31:26 PM PST 24 |
| Finished | Jan 21 12:34:40 PM PST 24 |
| Peak memory | 201220 kb |
| Host | smart-d927941e-47bb-474b-9aec-36c8b01ac905 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634064758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w ith_pre_cond.1634064758 |
| Directory | /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.167049457 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 64682144824 ps |
| CPU time | 41.74 seconds |
| Started | Jan 21 12:31:37 PM PST 24 |
| Finished | Jan 21 12:32:21 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-b37ec5f5-2bad-4ac7-bdc3-486fb87de7bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167049457 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_wi th_pre_cond.167049457 |
| Directory | /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.4164938975 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 47350556267 ps |
| CPU time | 127.14 seconds |
| Started | Jan 21 12:31:38 PM PST 24 |
| Finished | Jan 21 12:33:46 PM PST 24 |
| Peak memory | 200784 kb |
| Host | smart-c2396e4d-fc1d-44d4-b218-d54e98b03b90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4164938975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w ith_pre_cond.4164938975 |
| Directory | /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1703543378 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 29588294890 ps |
| CPU time | 42.85 seconds |
| Started | Jan 21 12:31:40 PM PST 24 |
| Finished | Jan 21 12:32:42 PM PST 24 |
| Peak memory | 201092 kb |
| Host | smart-75871e5c-8de3-43e9-a45f-0ba220135998 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703543378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_w ith_pre_cond.1703543378 |
| Directory | /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1545312579 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 56466615520 ps |
| CPU time | 154.75 seconds |
| Started | Jan 21 12:31:36 PM PST 24 |
| Finished | Jan 21 12:34:13 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-bddfed0b-4287-48b1-aae3-8f4f46286e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545312579 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w ith_pre_cond.1545312579 |
| Directory | /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.551110776 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 73719371782 ps |
| CPU time | 97.9 seconds |
| Started | Jan 21 12:31:40 PM PST 24 |
| Finished | Jan 21 12:33:37 PM PST 24 |
| Peak memory | 201172 kb |
| Host | smart-5d6ff3ba-c6e9-498a-9846-b437325e74b9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=551110776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_wi th_pre_cond.551110776 |
| Directory | /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2969919249 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 27084821437 ps |
| CPU time | 72.3 seconds |
| Started | Jan 21 12:31:35 PM PST 24 |
| Finished | Jan 21 12:32:48 PM PST 24 |
| Peak memory | 201656 kb |
| Host | smart-7c950b2d-16ed-4f41-ae61-b4c381317066 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2969919249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w ith_pre_cond.2969919249 |
| Directory | /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.293159172 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 112887144653 ps |
| CPU time | 262.01 seconds |
| Started | Jan 21 12:31:34 PM PST 24 |
| Finished | Jan 21 12:35:57 PM PST 24 |
| Peak memory | 201224 kb |
| Host | smart-e78dad10-1c1c-443c-b99c-0edcf6bc3e3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=293159172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_wi th_pre_cond.293159172 |
| Directory | /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.725114700 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 21098435658 ps |
| CPU time | 13.19 seconds |
| Started | Jan 21 12:31:35 PM PST 24 |
| Finished | Jan 21 12:31:49 PM PST 24 |
| Peak memory | 201568 kb |
| Host | smart-b3725ae9-9b0c-4072-97b9-863bfa720a97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=725114700 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_wi th_pre_cond.725114700 |
| Directory | /workspace/88.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1963790166 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 70368871971 ps |
| CPU time | 51.85 seconds |
| Started | Jan 21 12:31:31 PM PST 24 |
| Finished | Jan 21 12:32:23 PM PST 24 |
| Peak memory | 201240 kb |
| Host | smart-f7d668e5-d6f6-478d-b1da-052a8877ad61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963790166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w ith_pre_cond.1963790166 |
| Directory | /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_alert_test.1652867012 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2014938312 ps |
| CPU time | 5.78 seconds |
| Started | Jan 21 12:27:53 PM PST 24 |
| Finished | Jan 21 12:27:59 PM PST 24 |
| Peak memory | 201024 kb |
| Host | smart-986b423d-0645-49d5-88d9-5c7208efe432 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652867012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes t.1652867012 |
| Directory | /workspace/9.sysrst_ctrl_alert_test/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3845159011 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 3759130227 ps |
| CPU time | 7.33 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:28:04 PM PST 24 |
| Peak memory | 201124 kb |
| Host | smart-7b09213c-b251-428d-8867-7a583999de3c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3845159011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.3845159011 |
| Directory | /workspace/9.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3673479816 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 67466231099 ps |
| CPU time | 43.75 seconds |
| Started | Jan 21 12:27:45 PM PST 24 |
| Finished | Jan 21 12:28:30 PM PST 24 |
| Peak memory | 201160 kb |
| Host | smart-26eb52be-d859-4751-baa9-25988e135669 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673479816 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct rl_combo_detect.3673479816 |
| Directory | /workspace/9.sysrst_ctrl_combo_detect/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1267687405 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 36133465206 ps |
| CPU time | 104.5 seconds |
| Started | Jan 21 12:27:56 PM PST 24 |
| Finished | Jan 21 12:29:41 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-a40e9b94-6c1c-40a8-8729-8731dea35e97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1267687405 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi th_pre_cond.1267687405 |
| Directory | /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1883117834 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 4336445213 ps |
| CPU time | 3.34 seconds |
| Started | Jan 21 12:27:42 PM PST 24 |
| Finished | Jan 21 12:27:46 PM PST 24 |
| Peak memory | 201156 kb |
| Host | smart-82f3e0d4-9f81-4776-81f0-0cbb27fed3f8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883117834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_c trl_ec_pwr_on_rst.1883117834 |
| Directory | /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2202406664 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2615482353 ps |
| CPU time | 7.09 seconds |
| Started | Jan 21 12:27:40 PM PST 24 |
| Finished | Jan 21 12:27:48 PM PST 24 |
| Peak memory | 201036 kb |
| Host | smart-a82cd449-8343-4209-affc-c260c86c1781 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2202406664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2202406664 |
| Directory | /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.32105719 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2471547777 ps |
| CPU time | 7.33 seconds |
| Started | Jan 21 12:27:48 PM PST 24 |
| Finished | Jan 21 12:27:56 PM PST 24 |
| Peak memory | 201020 kb |
| Host | smart-3124388f-67bf-4103-a13b-38bc09ef78f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=32105719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.32105719 |
| Directory | /workspace/9.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1772072566 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 2073570790 ps |
| CPU time | 6.03 seconds |
| Started | Jan 21 12:27:42 PM PST 24 |
| Finished | Jan 21 12:27:49 PM PST 24 |
| Peak memory | 201376 kb |
| Host | smart-282b4bec-73f1-4c70-bdb8-7988fe0d3585 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1772072566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1772072566 |
| Directory | /workspace/9.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2551590376 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2514368902 ps |
| CPU time | 6.76 seconds |
| Started | Jan 21 12:27:42 PM PST 24 |
| Finished | Jan 21 12:27:49 PM PST 24 |
| Peak memory | 201472 kb |
| Host | smart-2778b925-11a4-48d2-83cd-90752bb2ee35 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551590376 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2551590376 |
| Directory | /workspace/9.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_smoke.364557742 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2112750881 ps |
| CPU time | 6.08 seconds |
| Started | Jan 21 12:27:45 PM PST 24 |
| Finished | Jan 21 12:27:52 PM PST 24 |
| Peak memory | 200968 kb |
| Host | smart-00d7c602-8fe8-4aa2-aab5-9bd24bceaef4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=364557742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.364557742 |
| Directory | /workspace/9.sysrst_ctrl_smoke/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_stress_all.1039103675 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 9542882134 ps |
| CPU time | 26.12 seconds |
| Started | Jan 21 12:27:42 PM PST 24 |
| Finished | Jan 21 12:28:09 PM PST 24 |
| Peak memory | 201440 kb |
| Host | smart-cdfa8f2a-3910-4f8a-a0e9-54390c801c33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039103675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl _stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st ress_all.1039103675 |
| Directory | /workspace/9.sysrst_ctrl_stress_all/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2170143094 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 56161573294 ps |
| CPU time | 33.02 seconds |
| Started | Jan 21 12:27:52 PM PST 24 |
| Finished | Jan 21 12:28:25 PM PST 24 |
| Peak memory | 209608 kb |
| Host | smart-b9cf14a5-47da-4d36-b45f-1a952fd94eb6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170143094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.2170143094 |
| Directory | /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.700952918 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3036410704268 ps |
| CPU time | 30.75 seconds |
| Started | Jan 21 12:27:46 PM PST 24 |
| Finished | Jan 21 12:28:17 PM PST 24 |
| Peak memory | 201008 kb |
| Host | smart-90002624-1157-4acb-b613-01a341af8643 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700952918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct rl_ultra_low_pwr.700952918 |
| Directory | /workspace/9.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3653082601 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 80837546291 ps |
| CPU time | 12.29 seconds |
| Started | Jan 21 12:31:34 PM PST 24 |
| Finished | Jan 21 12:31:47 PM PST 24 |
| Peak memory | 201232 kb |
| Host | smart-30987bd0-84ad-478e-ad20-d8a7d751c103 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3653082601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w ith_pre_cond.3653082601 |
| Directory | /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1403582250 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 96759324658 ps |
| CPU time | 239.31 seconds |
| Started | Jan 21 12:31:36 PM PST 24 |
| Finished | Jan 21 12:35:36 PM PST 24 |
| Peak memory | 201208 kb |
| Host | smart-fd6a2e7c-0462-46d0-8732-f4f45064d2e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403582250 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w ith_pre_cond.1403582250 |
| Directory | /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4025629296 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 61061472985 ps |
| CPU time | 158.75 seconds |
| Started | Jan 21 12:31:33 PM PST 24 |
| Finished | Jan 21 12:34:12 PM PST 24 |
| Peak memory | 201188 kb |
| Host | smart-f3ff88db-5411-4b67-afef-17700a5124d2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4025629296 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_w ith_pre_cond.4025629296 |
| Directory | /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1278577299 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 52623467897 ps |
| CPU time | 136.91 seconds |
| Started | Jan 21 12:31:59 PM PST 24 |
| Finished | Jan 21 12:34:37 PM PST 24 |
| Peak memory | 201396 kb |
| Host | smart-bed5cb7e-8425-475e-8b35-79aacf4b8071 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1278577299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w ith_pre_cond.1278577299 |
| Directory | /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1001776746 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 39415428002 ps |
| CPU time | 56.91 seconds |
| Started | Jan 21 12:31:58 PM PST 24 |
| Finished | Jan 21 12:33:17 PM PST 24 |
| Peak memory | 201296 kb |
| Host | smart-b0e0024f-c2e7-40c4-a54f-14df8ce736f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1001776746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w ith_pre_cond.1001776746 |
| Directory | /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.4012117336 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 129788205075 ps |
| CPU time | 318.57 seconds |
| Started | Jan 21 12:31:51 PM PST 24 |
| Finished | Jan 21 12:37:30 PM PST 24 |
| Peak memory | 201264 kb |
| Host | smart-4346781a-9ed1-4434-8a36-279c6cdd4d07 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4012117336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_w ith_pre_cond.4012117336 |
| Directory | /workspace/95.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.878475491 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 94085649782 ps |
| CPU time | 207.99 seconds |
| Started | Jan 21 12:31:58 PM PST 24 |
| Finished | Jan 21 12:35:47 PM PST 24 |
| Peak memory | 201248 kb |
| Host | smart-707a10ef-7107-486d-9f8d-bd72fc96e22b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=878475491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_wi th_pre_cond.878475491 |
| Directory | /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1653405541 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 65347839327 ps |
| CPU time | 177.76 seconds |
| Started | Jan 21 12:32:00 PM PST 24 |
| Finished | Jan 21 12:35:18 PM PST 24 |
| Peak memory | 201272 kb |
| Host | smart-cf55016d-ea67-45e1-b37d-0a64dec33bdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1653405541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w ith_pre_cond.1653405541 |
| Directory | /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest |
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