Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.54 98.96 96.49 100.00 97.44 98.33 99.72 91.87


Total tests in report: 916
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
52.51 52.51 49.54 49.54 39.16 39.16 80.18 80.18 97.44 97.44 56.18 56.18 42.79 42.79 2.26 2.26 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3200331034
68.30 15.79 72.72 23.18 66.28 27.12 85.19 5.01 97.44 0.00 76.12 19.94 58.71 15.92 21.64 19.38 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2344218520
83.96 15.66 92.26 19.53 84.07 17.79 92.94 7.74 97.44 0.00 92.62 16.50 88.86 30.15 39.56 17.92 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.3214254499
88.51 4.55 96.67 4.41 88.19 4.13 97.27 4.33 97.44 0.00 95.44 2.82 96.16 7.30 48.44 8.88 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1463951853
90.46 1.95 96.86 0.19 88.93 0.74 97.27 0.00 97.44 0.00 95.65 0.21 96.44 0.28 60.66 12.22 /workspace/coverage/default/47.sysrst_ctrl_stress_all.3873431667
91.74 1.28 96.93 0.07 89.01 0.07 97.27 0.00 97.44 0.00 95.72 0.07 96.63 0.19 69.21 8.56 /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1670886217
92.64 0.89 97.27 0.35 89.53 0.52 97.27 0.00 97.44 0.00 96.14 0.42 97.28 0.66 73.52 4.31 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1306451763
93.43 0.80 97.27 0.00 92.87 3.34 98.63 1.37 97.44 0.00 96.14 0.00 97.47 0.19 74.22 0.70 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2320364380
94.04 0.60 97.43 0.16 93.08 0.21 98.63 0.00 97.44 0.00 96.24 0.10 98.03 0.56 77.40 3.18 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.1430965613
94.44 0.41 97.46 0.03 93.27 0.19 98.86 0.23 97.44 0.00 96.31 0.07 98.03 0.00 79.71 2.31 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.595350892
94.82 0.38 97.46 0.00 93.30 0.02 98.86 0.00 97.44 0.00 96.31 0.00 98.03 0.00 82.35 2.64 /workspace/coverage/default/10.sysrst_ctrl_stress_all.2429783088
95.18 0.36 98.16 0.69 93.99 0.69 98.86 0.00 97.44 0.00 97.08 0.77 98.41 0.37 82.35 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.1851941120
95.47 0.29 98.16 0.00 94.82 0.83 99.32 0.46 97.44 0.00 97.11 0.03 98.41 0.00 83.05 0.70 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.466373323
95.74 0.27 98.16 0.00 94.85 0.02 99.32 0.00 97.44 0.00 97.11 0.00 98.50 0.09 84.82 1.78 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.626854856
95.98 0.24 98.44 0.28 95.61 0.76 99.32 0.00 97.44 0.00 97.67 0.56 98.60 0.09 84.82 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2891975240
96.14 0.16 98.45 0.02 95.73 0.12 99.32 0.00 97.44 0.00 97.67 0.00 98.60 0.00 85.79 0.97 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2885347169
96.27 0.13 98.45 0.00 95.75 0.02 100.00 0.68 97.44 0.00 97.67 0.00 98.69 0.09 85.90 0.11 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2677877311
96.39 0.11 98.52 0.07 95.80 0.05 100.00 0.00 97.44 0.00 97.74 0.07 98.88 0.19 86.33 0.43 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.900959539
96.49 0.10 98.56 0.03 95.80 0.00 100.00 0.00 97.44 0.00 97.77 0.03 98.88 0.00 86.98 0.65 /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1102916690
96.58 0.09 98.56 0.00 95.80 0.00 100.00 0.00 97.44 0.00 97.77 0.00 98.88 0.00 87.62 0.65 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.3577459090
96.65 0.07 98.56 0.00 95.80 0.00 100.00 0.00 97.44 0.00 97.77 0.00 98.88 0.00 88.11 0.48 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2813753839
96.72 0.07 98.56 0.00 95.80 0.00 100.00 0.00 97.44 0.00 97.77 0.00 98.88 0.00 88.59 0.48 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1140875427
96.78 0.06 98.65 0.09 95.85 0.05 100.00 0.00 97.44 0.00 97.88 0.10 99.06 0.19 88.59 0.00 /workspace/coverage/default/42.sysrst_ctrl_stress_all.677163415
96.84 0.06 98.72 0.07 95.87 0.02 100.00 0.00 97.44 0.00 97.98 0.10 99.16 0.09 88.70 0.11 /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.4205400539
96.89 0.05 98.75 0.03 95.87 0.00 100.00 0.00 97.44 0.00 98.02 0.03 99.16 0.00 88.97 0.27 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.3172603810
96.93 0.04 98.77 0.02 95.92 0.05 100.00 0.00 97.44 0.00 98.05 0.03 99.34 0.19 88.97 0.00 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3385675475
96.97 0.04 98.77 0.00 95.92 0.00 100.00 0.00 97.44 0.00 98.05 0.00 99.34 0.00 89.24 0.27 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1409973803
97.00 0.03 98.77 0.00 95.92 0.00 100.00 0.00 97.44 0.00 98.05 0.00 99.34 0.00 89.45 0.22 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2447380577
97.03 0.03 98.77 0.00 95.92 0.00 100.00 0.00 97.44 0.00 98.05 0.00 99.34 0.00 89.67 0.22 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.307649013
97.06 0.03 98.77 0.00 95.92 0.00 100.00 0.00 97.44 0.00 98.05 0.00 99.34 0.00 89.88 0.22 /workspace/coverage/default/20.sysrst_ctrl_stress_all.3507168993
97.09 0.03 98.77 0.00 95.92 0.00 100.00 0.00 97.44 0.00 98.05 0.00 99.34 0.00 90.10 0.22 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.1197464119
97.12 0.03 98.77 0.00 96.14 0.21 100.00 0.00 97.44 0.00 98.05 0.00 99.34 0.00 90.10 0.00 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.1566888733
97.15 0.03 98.80 0.03 96.16 0.02 100.00 0.00 97.44 0.00 98.09 0.03 99.44 0.09 90.10 0.00 /workspace/coverage/default/11.sysrst_ctrl_stress_all.1353091021
97.17 0.03 98.84 0.03 96.18 0.02 100.00 0.00 97.44 0.00 98.12 0.03 99.53 0.09 90.10 0.00 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.2598297542
97.20 0.03 98.87 0.03 96.21 0.02 100.00 0.00 97.44 0.00 98.16 0.03 99.63 0.09 90.10 0.00 /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1081951964
97.22 0.02 98.87 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.16 0.00 99.63 0.00 90.26 0.16 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2364976972
97.25 0.02 98.87 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.16 0.00 99.63 0.00 90.42 0.16 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.714842853
97.27 0.02 98.91 0.03 96.21 0.00 100.00 0.00 97.44 0.00 98.22 0.07 99.63 0.00 90.47 0.05 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.3901105206
97.29 0.02 98.91 0.00 96.21 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.09 90.53 0.05 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.2984095362
97.31 0.02 98.91 0.00 96.35 0.14 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 90.53 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3196567681
97.32 0.02 98.91 0.00 96.35 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 90.64 0.11 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.281622149
97.34 0.02 98.91 0.00 96.35 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 90.74 0.11 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1286105722
97.36 0.02 98.91 0.00 96.35 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 90.85 0.11 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3961744702
97.37 0.02 98.91 0.00 96.35 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 90.96 0.11 /workspace/coverage/default/37.sysrst_ctrl_combo_detect.3598484643
97.39 0.02 98.91 0.00 96.35 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.07 0.11 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3947209982
97.40 0.01 98.91 0.00 96.37 0.02 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.12 0.05 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.359492163
97.41 0.01 98.91 0.00 96.40 0.02 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.17 0.05 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.1319377772
97.42 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.23 0.05 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3062193810
97.42 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.28 0.05 /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.1763872528
97.43 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.33 0.05 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1215681783
97.44 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.39 0.05 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3813972699
97.45 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.44 0.05 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.482183645
97.45 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.50 0.05 /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2487519086
97.46 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.55 0.05 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1639748638
97.47 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.60 0.05 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3274266434
97.48 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.66 0.05 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3123714470
97.49 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.71 0.05 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2993542387
97.49 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.77 0.05 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.4018928038
97.50 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.82 0.05 /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3486326821
97.51 0.01 98.91 0.00 96.40 0.00 100.00 0.00 97.44 0.00 98.22 0.00 99.72 0.00 91.87 0.05 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2157513275
97.52 0.01 98.92 0.02 96.40 0.00 100.00 0.00 97.44 0.00 98.26 0.03 99.72 0.00 91.87 0.00 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.1203057106
97.52 0.01 98.94 0.02 96.40 0.00 100.00 0.00 97.44 0.00 98.29 0.03 99.72 0.00 91.87 0.00 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3175609390
97.53 0.01 98.96 0.02 96.40 0.00 100.00 0.00 97.44 0.00 98.33 0.03 99.72 0.00 91.87 0.00 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.8105738
97.54 0.01 98.96 0.00 96.45 0.05 100.00 0.00 97.44 0.00 98.33 0.00 99.72 0.00 91.87 0.00 /workspace/coverage/default/1.sysrst_ctrl_alert_test.90479044
97.54 0.01 98.96 0.00 96.47 0.02 100.00 0.00 97.44 0.00 98.33 0.00 99.72 0.00 91.87 0.00 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.1897141051

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3655507542
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3249756559
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.692948848
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3755583896
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2816405025
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.197820926
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2379890719
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2860275498
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.594371879
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3942161220
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2444609158
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.577503300
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4177180807
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2341820279
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.814806851
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3192139719
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1403072299
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.3544275494
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1298531861
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.2190184408
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1198432115
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3887386278
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2513392378
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.902192947
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2649898511
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.4036300001
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1582508070
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.3791196161
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.538500155
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2025772463
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1759660749
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2606059069
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.929666311
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.42617686
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3043695211
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2396174145
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.1607190654
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2063774298
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.2338426054
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.646047800
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.203682752
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1956860770
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3748945294
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3118224499
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2427172857
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.319161765
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3773238103
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.388078732
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1706800882
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2189439605
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.4182298636
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3092991725
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1016013162
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.946224107
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.360614424
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3741186431
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.424543434
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1879322715
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3848460687
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1844938794
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.2882343185
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3114425616
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2433712211
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.536576659
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2681632746
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2276282414
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.4272343999
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1208196782
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.394267563
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.4093033948
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.2052964166
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2914410648
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2905394092
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1747505142
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.446993428
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1399088329
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3760984165
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3892389436
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.1038099337
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1577179324
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.2802483188
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.2330877721
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.1044474067
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.4278932405
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.2350210391
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3423510556
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3377054006
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2471598043
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.617205868
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/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1410622925
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1330487557
/workspace/coverage/default/42.sysrst_ctrl_smoke.2849558936
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1078095526
/workspace/coverage/default/43.sysrst_ctrl_alert_test.4101475399
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.3488567177
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1443382253
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.4018100986
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.278163751
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.646116515
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.282218505
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2701208752
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3544811344
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2768011788
/workspace/coverage/default/43.sysrst_ctrl_smoke.1551322278
/workspace/coverage/default/43.sysrst_ctrl_stress_all.636338723
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.4023120857
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2865575438
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2866030401
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.320802548
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1393249293
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3881092161
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.205485493
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.525303041
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2917152446
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2842184558
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2788885578
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.3897056
/workspace/coverage/default/44.sysrst_ctrl_smoke.313923787
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3155679046
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.950427807
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3239979165
/workspace/coverage/default/45.sysrst_ctrl_alert_test.1686322562
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.525828903
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.152016156
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1589458478
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2902023780
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1510385617
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2491007843
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3150871676
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1585555523
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.982332776
/workspace/coverage/default/45.sysrst_ctrl_smoke.4144555284
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2386775664
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2958986471
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2954604134
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1512833144
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1234579374
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.738650892
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3039127943
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3285017405
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.466199641
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1582455532
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.387722207
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.1242838896
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.220243775
/workspace/coverage/default/46.sysrst_ctrl_smoke.1750544491
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1078501306
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3274740096
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3469938059
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3366374844
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.4186362928
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.1933831433
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2651384805
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1673729045
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1150012971
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.818778624
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.524805148
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2012451189
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.4230855015
/workspace/coverage/default/47.sysrst_ctrl_smoke.1247761661
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3610350581
/workspace/coverage/default/48.sysrst_ctrl_alert_test.4086697948
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.324470878
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.1108284191
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.4217012567
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.735819888
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1096040754
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1152435159
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.4242464083
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.4096616758
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.4090787492
/workspace/coverage/default/48.sysrst_ctrl_smoke.514636174
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1710996537
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1797624650
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3899810263
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1783716238
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3889730956
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.1331402997
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.3140507702
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1772766741
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1712437060
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.203073282
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3658104319
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.3094142642
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2596837288
/workspace/coverage/default/49.sysrst_ctrl_smoke.864537118
/workspace/coverage/default/49.sysrst_ctrl_stress_all.2827731504
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3138638113
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3392302724
/workspace/coverage/default/5.sysrst_ctrl_alert_test.2998254433
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.712831984
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.543483509
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3693527075
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.3929083150
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1872646854
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2303631152
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.1280775690
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.287194296
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1063273286
/workspace/coverage/default/5.sysrst_ctrl_smoke.1710433469
/workspace/coverage/default/5.sysrst_ctrl_stress_all.1144058404
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3795146664
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.149614460
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3340818160
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.528284425
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1802125741
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.624256919
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3740389217
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1342719453
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2162478301
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3275315093
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2869007311
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3533649795
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.2706197437
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3684369807
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.4139638978
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.631451263
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1612591731
/workspace/coverage/default/6.sysrst_ctrl_smoke.3018299657
/workspace/coverage/default/6.sysrst_ctrl_stress_all.2367474049
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1801969783
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.350703671
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.581860736
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.2088958158
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.698141812
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1769235437
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.2933605548
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1114503718
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3244756639
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.725004074
/workspace/coverage/default/7.sysrst_ctrl_alert_test.2973774157
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.736464767
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.844577260
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.116366034
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2625158386
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.674066766
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3354580948
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.151800640
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1772724916
/workspace/coverage/default/7.sysrst_ctrl_smoke.4101484675
/workspace/coverage/default/7.sysrst_ctrl_stress_all.284412007
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2681445814
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.977207648
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2275132044
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2492056095
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.103565684
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2521754092
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2772843611
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.4083493965
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1836699450
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2557660156
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1062521213
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3553227653
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3156775517
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.3092204892
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1619551419
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3139957671
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.414376405
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.3692046761
/workspace/coverage/default/8.sysrst_ctrl_smoke.2932684057
/workspace/coverage/default/8.sysrst_ctrl_stress_all.888545708
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3841398254
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1634064758
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.167049457
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.4164938975
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1703543378
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1545312579
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.551110776
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.2969919249
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.293159172
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.725114700
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1963790166
/workspace/coverage/default/9.sysrst_ctrl_alert_test.1652867012
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.3845159011
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3673479816
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1267687405
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1883117834
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2202406664
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.32105719
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.1772072566
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2551590376
/workspace/coverage/default/9.sysrst_ctrl_smoke.364557742
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1039103675
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2170143094
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.700952918
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3653082601
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1403582250
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.4025629296
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1278577299
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1001776746
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.4012117336
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.878475491
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1653405541



Total test records in report: 916
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T7 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3200331034 Jan 21 12:42:10 PM PST 24 Jan 21 12:42:19 PM PST 24 4017545215 ps
T1 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.3118224499 Jan 21 12:21:03 PM PST 24 Jan 21 12:21:08 PM PST 24 2043165857 ps
T8 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.1428163008 Jan 21 12:24:19 PM PST 24 Jan 21 12:25:40 PM PST 24 40557595976 ps
T24 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.902192947 Jan 21 12:23:10 PM PST 24 Jan 21 12:23:13 PM PST 24 2025867739 ps
T25 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.281622149 Jan 21 12:24:43 PM PST 24 Jan 21 12:24:47 PM PST 24 2018232961 ps
T2 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2018794102 Jan 21 12:43:01 PM PST 24 Jan 21 12:43:04 PM PST 24 2100686586 ps
T26 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.424543434 Jan 21 12:24:40 PM PST 24 Jan 21 12:24:47 PM PST 24 2011382932 ps
T27 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.2320364380 Jan 21 12:21:27 PM PST 24 Jan 21 12:24:19 PM PST 24 37840894855 ps
T28 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.4099971795 Jan 21 12:32:20 PM PST 24 Jan 21 12:32:35 PM PST 24 2011887776 ps
T3 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.407516555 Jan 21 12:22:42 PM PST 24 Jan 21 12:22:50 PM PST 24 2035915330 ps
T29 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.595350892 Jan 21 12:24:46 PM PST 24 Jan 21 12:24:49 PM PST 24 2043375751 ps
T30 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.970699765 Jan 21 12:22:58 PM PST 24 Jan 21 12:23:02 PM PST 24 2026801350 ps
T41 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.197820926 Jan 21 12:54:16 PM PST 24 Jan 21 12:54:22 PM PST 24 2015254132 ps
T4 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.156698672 Jan 21 12:37:18 PM PST 24 Jan 21 12:37:23 PM PST 24 2062733022 ps
T42 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.1883899108 Jan 21 12:22:43 PM PST 24 Jan 21 12:22:50 PM PST 24 2014680447 ps
T372 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.2663583052 Jan 21 01:08:00 PM PST 24 Jan 21 01:08:04 PM PST 24 2073945900 ps
T5 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.646047800 Jan 21 01:13:54 PM PST 24 Jan 21 01:14:01 PM PST 24 2057901613 ps
T9 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1706800882 Jan 21 01:10:33 PM PST 24 Jan 21 01:10:37 PM PST 24 2136241028 ps
T373 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.2705923326 Jan 21 12:44:53 PM PST 24 Jan 21 12:44:59 PM PST 24 2013635103 ps
T374 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3263107470 Jan 21 12:59:56 PM PST 24 Jan 21 01:00:00 PM PST 24 2016828388 ps
T307 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3423510556 Jan 21 12:22:58 PM PST 24 Jan 21 12:23:00 PM PST 24 2060402630 ps
T375 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.698069956 Jan 21 12:46:42 PM PST 24 Jan 21 12:46:45 PM PST 24 2033522741 ps
T288 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2492889024 Jan 21 12:21:49 PM PST 24 Jan 21 12:22:04 PM PST 24 2025490388 ps
T10 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2344218520 Jan 21 12:47:31 PM PST 24 Jan 21 12:48:02 PM PST 24 42877426512 ps
T11 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2364976972 Jan 21 12:59:07 PM PST 24 Jan 21 01:01:01 PM PST 24 42453819959 ps
T291 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2379890719 Jan 21 12:25:01 PM PST 24 Jan 21 12:25:06 PM PST 24 2203743128 ps
T304 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.1809496853 Jan 21 12:47:12 PM PST 24 Jan 21 12:47:14 PM PST 24 2036682883 ps
T6 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1403072299 Jan 21 01:01:08 PM PST 24 Jan 21 01:01:11 PM PST 24 2136803947 ps
T305 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1082354682 Jan 21 12:40:21 PM PST 24 Jan 21 12:40:23 PM PST 24 2024540470 ps
T292 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.3848460687 Jan 21 12:48:07 PM PST 24 Jan 21 12:48:16 PM PST 24 2242492291 ps
T12 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.1298431784 Jan 21 12:24:46 PM PST 24 Jan 21 12:24:53 PM PST 24 2037884719 ps
T306 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.3760984165 Jan 21 12:24:49 PM PST 24 Jan 21 12:24:53 PM PST 24 2023898693 ps
T294 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.2699693997 Jan 21 01:25:54 PM PST 24 Jan 21 01:25:57 PM PST 24 2236068192 ps
T376 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.2471598043 Jan 21 12:22:44 PM PST 24 Jan 21 12:22:48 PM PST 24 2023718065 ps
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