Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1239

1

T12

14

T13

9

T14

6

auto[1]

1863

1

T12

14

T13

29

T14

24

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2533

1

T12

13

T13

6

T14

27

auto[1]

569

1

T12

15

T13

32

T14

3

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2967

1

T12

28

T13

38

T14

26

auto[1]

135

1

T14

4

T40

1

T41

4

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2931

1

T12

28

T13

26

T14

24

auto[1]

171

1

T13

12

T14

6

T18

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2912

1

T12

28

T13

29

T14

30

auto[1]

190

1

T13

9

T17

7

T19

8

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1974

1

T12

1

T13

4

T14

20

auto[1]

1128

1

T12

27

T13

34

T14

10

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1259

1

T12

8

T13

15

T14

24

auto[1]

1843

1

T12

20

T13

23

T14

6

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1282

1

T12

3

T13

8

T14

16

auto[1]

1820

1

T12

25

T13

30

T14

14

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1313

1

T12

11

T13

15

T14

16

auto[1]

1789

1

T12

17

T13

23

T14

14

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1220

1

T12

13

T13

12

T14

21

auto[1]

1882

1

T12

15

T13

26

T14

9

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T48

1

T38

1

T53

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T18

1

T38

1

T40

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T14

4

T17

1

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T13

1

T38

1

T235

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T14

1

T17

3

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T44

1

T235

2

T64

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T14

2

T17

1

T50

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T18

1

T235

2

T64

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T14

2

T17

1

T53

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T12

1

T18

1

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T14

1

T45

1

T50

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T12

1

T40

1

T64

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

48

1

T220

1

T236

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

18

1

T40

2

T155

1

T124

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T17

1

T41

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32

1

T19

1

T38

2

T40

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T12

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T12

2

T44

1

T235

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T13

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T18

1

T19

1

T38

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

36

1

T231

1

T64

5

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T40

1

T235

1

T64

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T236

1

T231

1

T64

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

23

1

T38

1

T44

1

T64

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T14

1

T53

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T64

1

T232

1

T283

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T14

6

T53

2

T50

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

25

1

T14

2

T19

2

T179

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

57

1

T19

1

T44

1

T71

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T12

1

T64

1

T72

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T179

1

T41

1

T236

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

51

1

T19

1

T51

9

T64

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

46

1

T18

1

T48

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T38

1

T235

1

T237

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T48

9

T53

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T19

1

T220

1

T64

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T17

2

T248

2

T220

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T40

1

T64

1

T232

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55

1

T14

1

T17

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T14

5

T19

1

T44

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43

1

T17

1

T53

1

T220

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

23

1

T38

1

T44

1

T40

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T231

1

T64

2

T223

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T18

1

T19

2

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T248

1

T220

1

T231

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T44

1

T179

1

T155

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

69

1

T54

9

T236

2

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

56

1

T18

1

T179

1

T220

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

40

1

T53

1

T44

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T12

2

T19

2

T40

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

36

1

T52

2

T179

1

T235

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

15

1

T12

1

T18

2

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

66

1

T236

1

T231

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

27

1

T12

1

T18

1

T64

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

82

1

T17

2

T52

3

T92

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

36

1

T12

1

T64

2

T232

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

26

1

T40

1

T52

1

T248

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

16

1

T18

1

T40

1

T232

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

70

1

T53

7

T175

2

T73

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

45

1

T12

1

T13

1

T19

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T52

8

T248

1

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

48

1

T12

1

T18

1

T40

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

305

1

T13

3

T17

7

T19

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T64

1

T72

1

T247

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T13

1

T283

1

T247

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T13

2

T64

1

T232

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T13

1

T155

1

T284

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T40

1

T237

1

T284

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T13

1

T38

1

T179

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T38

1

T72

1

T237

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T13

1

T19

1

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T206

1

T285

2

T286

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T12

1

T14

1

T18

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T13

2

T19

1

T284

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T13

2

T72

1

T237

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T13

2

T235

1

T155

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6

1

T12

1

T13

1

T283

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T14

2

T18

1

T64

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T19

1

T237

1

T234

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T19

1

T38

1

T287

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

5

1

T18

1

T19

1

T288

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T226

3

T288

1

T289

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T12

1

T38

1

T44

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11

1

T18

1

T40

1

T179

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

11

1

T19

1

T44

1

T290

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T38

1

T237

1

T247

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T13

1

T18

1

T40

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T220

3

T283

1

T229

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T12

1

T13

1

T247

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T13

1

T18

1

T155

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T38

1

T64

2

T291

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T13

1

T18

1

T40

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T40

1

T247

1

T292

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T12

1

T232

1

T155

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

12

1

T12

1

T232

1

T290

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

149

1

T12

9

T13

15

T18

10

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T48

1

T38

1

T53

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T13

1

T18

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T14

4

T17

1

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T13

3

T38

1

T235

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T14

1

T17

4

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T13

1

T44

1

T235

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T14

2

T17

1

T50

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T18

1

T40

1

T235

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T14

2

T17

1

T53

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T12

1

T13

1

T18

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T14

1

T17

1

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T12

1

T38

1

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T220

1

T236

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T13

1

T19

1

T40

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T17

1

T41

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T19

1

T38

2

T40

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T12

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T12

3

T18

1

T19

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T13

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T13

2

T18

1

T19

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T231

1

T64

5

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T13

2

T40

1

T235

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T236

1

T231

1

T64

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T13

2

T38

1

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T14

1

T53

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T12

1

T13

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T14

3

T53

2

T50

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T14

4

T18

1

T19

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T19

1

T44

1

T71

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T12

1

T19

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T179

1

T41

1

T236

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

55

1

T19

2

T38

1

T51

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T18

1

T48

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T18

1

T19

1

T38

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T48

9

T53

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T19

1

T220

1

T64

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T17

3

T248

2

T220

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T12

1

T38

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

59

1

T14

1

T17

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T14

5

T18

1

T19

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T17

1

T53

1

T220

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T19

1

T38

1

T44

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T231

1

T64

2

T223

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T18

1

T19

2

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T17

1

T248

1

T220

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T13

1

T18

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

76

1

T54

9

T236

2

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

69

1

T18

1

T179

1

T220

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T53

1

T44

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

32

1

T12

3

T13

1

T19

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T52

2

T179

1

T235

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T12

1

T13

1

T18

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

72

1

T236

1

T231

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

36

1

T12

1

T18

1

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

86

1

T17

3

T52

3

T92

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T12

1

T13

1

T18

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

29

1

T17

1

T40

1

T52

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T18

1

T40

2

T232

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

76

1

T53

7

T41

2

T175

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

57

1

T12

2

T13

1

T19

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

70

1

T52

8

T248

1

T41

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T12

2

T18

1

T40

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

206

1

T13

3

T17

8

T19

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

147

1

T12

9

T13

15

T18

10

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2

1

T14

1

T227

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T40

1

T288

2

T247

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	28	68	70.83	28
Automatically Generated Cross Bins	96	28	68	70.83	28
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T48

1

T38

1

T53

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T13

1

T18

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

63

1

T14

2

T17

1

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T13

3

T38

1

T235

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T14

1

T17

4

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T13

1

T44

1

T235

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T14

2

T17

1

T50

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T18

1

T40

1

T235

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T14

2

T17

1

T53

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T12

1

T13

1

T18

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T14

1

T17

1

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T12

1

T38

1

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T220

1

T236

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T13

1

T19

1

T40

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

49

1

T17

1

T41

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T19

1

T38

2

T40

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T12

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T12

3

T14

1

T18

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T13

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T13

2

T18

1

T19

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

36

1

T231

1

T64

5

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T13

2

T40

1

T235

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T236

1

T231

1

T64

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T13

2

T38

1

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T14

1

T53

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T12

1

T13

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T14

2

T53

2

T50

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T14

4

T18

1

T19

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T19

1

T44

1

T71

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T12

1

T19

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

59

1

T179

1

T41

1

T236

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

55

1

T19

2

T38

1

T51

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T18

1

T48

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T18

1

T19

1

T38

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

50

1

T48

9

T53

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T19

1

T220

1

T64

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T17

3

T248

2

T220

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T12

1

T38

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T14

1

T17

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T14

5

T18

1

T19

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T17

1

T53

1

T220

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T19

1

T38

1

T44

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T231

1

T64

2

T223

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T18

1

T19

2

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T17

1

T248

1

T220

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T13

1

T18

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

78

1

T54

9

T236

2

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

69

1

T18

1

T179

1

T220

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T53

1

T44

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

32

1

T12

3

T13

1

T19

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T52

2

T179

1

T235

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

22

1

T12

1

T13

1

T18

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

67

1

T236

1

T231

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

32

1

T12

1

T18

1

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

88

1

T17

3

T52

3

T92

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T12

1

T13

1

T18

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

29

1

T17

1

T40

1

T52

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

26

1

T18

1

T40

2

T232

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

69

1

T41

2

T175

2

T95

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

57

1

T12

2

T13

1

T19

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

69

1

T52

7

T248

1

T41

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T12

2

T18

1

T40

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

223

1

T17

8

T19

8

T38

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

121

1

T12

9

T13

6

T18

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T227

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1

1

T293

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T294

4

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

34

1

T13

9

T18

2

T38

1

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T48

1

T38

1

T53

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T13

1

T18

1

T38

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

65

1

T14

4

T17

1

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T13

3

T38

1

T235

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T14

1

T17

4

T48

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T13

1

T44

1

T235

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T14

2

T17

1

T50

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T18

1

T40

1

T235

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T14

2

T17

1

T53

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T12

1

T13

1

T18

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T14

1

T17

1

T45

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T12

1

T38

1

T40

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T220

1

T236

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T13

1

T19

1

T40

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

50

1

T17

1

T41

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T19

1

T38

2

T40

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T12

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T12

3

T14

1

T18

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T13

1

T14

1

T52

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T13

2

T18

1

T19

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

37

1

T231

1

T64

5

T245

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T13

2

T40

1

T235

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

50

1

T236

1

T231

1

T64

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T13

2

T38

1

T44

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T14

1

T53

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T12

1

T13

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T14

6

T53

2

T50

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

37

1

T14

4

T18

1

T19

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T19

1

T44

1

T71

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T12

1

T19

1

T64

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

58

1

T179

1

T41

1

T236

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

55

1

T19

2

T38

1

T51

9

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T18

1

T48

2

T53

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T18

1

T19

1

T38

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T48

8

T53

1

T248

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T19

1

T220

1

T64

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T17

3

T248

2

T220

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

21

1

T12

1

T38

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

58

1

T14

1

T17

1

T54

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

44

1

T14

5

T18

1

T19

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T17

1

T53

1

T220

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T19

1

T38

1

T44

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

28

1

T231

1

T64

2

T223

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

19

1

T18

1

T19

2

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

46

1

T17

1

T248

1

T220

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T13

1

T18

1

T44

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

78

1

T54

9

T236

2

T64

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

69

1

T18

1

T179

1

T220

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T53

1

T44

1

T92

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

32

1

T12

3

T13

1

T19

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T52

1

T179

1

T235

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

21

1

T12

1

T13

1

T18

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

72

1

T236

1

T231

1

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

36

1

T12

1

T18

1

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

85

1

T17

3

T52

2

T92

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T12

1

T13

1

T18

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

27

1

T17

1

T40

1

T52

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T18

1

T40

2

T232

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

76

1

T53

7

T41

2

T175

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

57

1

T12

2

T13

1

T19

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

63

1

T52

8

T248

1

T41

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T12

2

T18

1

T40

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

178

1

T13

1

T17

1

T44

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

135

1

T12

9

T13

8

T18

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T224

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T295

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

20

1

T13

7

T64

1

T237

3

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded