Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
807 |
1 |
|
|
T56 |
12 |
|
T21 |
9 |
|
T68 |
14 |
| auto[1] |
773 |
1 |
|
|
T56 |
8 |
|
T21 |
11 |
|
T68 |
6 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T56 |
11 |
|
T21 |
12 |
|
T68 |
15 |
| auto[1] |
767 |
1 |
|
|
T56 |
9 |
|
T21 |
8 |
|
T68 |
5 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T56 |
9 |
|
T21 |
8 |
|
T68 |
9 |
| auto[1] |
802 |
1 |
|
|
T56 |
11 |
|
T21 |
12 |
|
T68 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
794 |
1 |
|
|
T56 |
10 |
|
T21 |
9 |
|
T68 |
11 |
| auto[1] |
786 |
1 |
|
|
T56 |
10 |
|
T21 |
11 |
|
T68 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T56 |
12 |
|
T21 |
11 |
|
T68 |
10 |
| auto[1] |
793 |
1 |
|
|
T56 |
8 |
|
T21 |
9 |
|
T68 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T56 |
10 |
|
T21 |
8 |
|
T68 |
7 |
| auto[1] |
808 |
1 |
|
|
T56 |
10 |
|
T21 |
12 |
|
T68 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
774 |
1 |
|
|
T56 |
12 |
|
T21 |
11 |
|
T68 |
8 |
| auto[1] |
806 |
1 |
|
|
T56 |
8 |
|
T21 |
9 |
|
T68 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
786 |
1 |
|
|
T56 |
9 |
|
T21 |
13 |
|
T68 |
14 |
| auto[1] |
794 |
1 |
|
|
T56 |
11 |
|
T21 |
7 |
|
T68 |
6 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
778 |
1 |
|
|
T56 |
7 |
|
T21 |
10 |
|
T68 |
13 |
| auto[1] |
802 |
1 |
|
|
T56 |
13 |
|
T21 |
10 |
|
T68 |
7 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T56 |
13 |
|
T21 |
9 |
|
T68 |
10 |
| auto[1] |
781 |
1 |
|
|
T56 |
7 |
|
T21 |
11 |
|
T68 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
790 |
1 |
|
|
T56 |
13 |
|
T21 |
10 |
|
T68 |
13 |
| auto[1] |
790 |
1 |
|
|
T56 |
7 |
|
T21 |
10 |
|
T68 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T56 |
12 |
|
T21 |
12 |
|
T68 |
11 |
| auto[1] |
772 |
1 |
|
|
T56 |
8 |
|
T21 |
8 |
|
T68 |
9 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T56 |
12 |
|
T21 |
13 |
|
T68 |
10 |
| auto[1] |
785 |
1 |
|
|
T56 |
8 |
|
T21 |
7 |
|
T68 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T56 |
11 |
|
T21 |
12 |
|
T68 |
15 |
| auto[1] |
767 |
1 |
|
|
T56 |
9 |
|
T21 |
8 |
|
T68 |
5 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T56 |
10 |
|
T21 |
9 |
|
T68 |
14 |
| auto[1] |
793 |
1 |
|
|
T56 |
10 |
|
T21 |
11 |
|
T68 |
6 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T56 |
7 |
|
T21 |
14 |
|
T68 |
10 |
| auto[1] |
793 |
1 |
|
|
T56 |
13 |
|
T21 |
6 |
|
T68 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
800 |
1 |
|
|
T56 |
8 |
|
T21 |
12 |
|
T68 |
12 |
| auto[1] |
780 |
1 |
|
|
T56 |
12 |
|
T21 |
8 |
|
T68 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
793 |
1 |
|
|
T56 |
10 |
|
T21 |
9 |
|
T68 |
9 |
| auto[1] |
787 |
1 |
|
|
T56 |
10 |
|
T21 |
11 |
|
T68 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T56 |
5 |
|
T21 |
7 |
|
T68 |
8 |
| auto[1] |
808 |
1 |
|
|
T56 |
15 |
|
T21 |
13 |
|
T68 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
742 |
1 |
|
|
T56 |
10 |
|
T21 |
13 |
|
T68 |
14 |
| auto[1] |
838 |
1 |
|
|
T56 |
10 |
|
T21 |
7 |
|
T68 |
6 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T56 |
9 |
|
T21 |
8 |
|
T68 |
13 |
| auto[1] |
781 |
1 |
|
|
T56 |
11 |
|
T21 |
12 |
|
T68 |
7 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T56 |
12 |
|
T21 |
6 |
|
T68 |
10 |
| auto[1] |
793 |
1 |
|
|
T56 |
8 |
|
T21 |
14 |
|
T68 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T56 |
12 |
|
T21 |
9 |
|
T68 |
9 |
| auto[1] |
768 |
1 |
|
|
T56 |
8 |
|
T21 |
11 |
|
T68 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T56 |
12 |
|
T21 |
12 |
|
T68 |
11 |
| auto[1] |
772 |
1 |
|
|
T56 |
8 |
|
T21 |
8 |
|
T68 |
9 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
411 |
1 |
|
|
T56 |
4 |
|
T21 |
5 |
|
T68 |
9 |
| auto[0] |
auto[1] |
376 |
1 |
|
|
T56 |
6 |
|
T21 |
4 |
|
T68 |
5 |
| auto[1] |
auto[0] |
367 |
1 |
|
|
T56 |
5 |
|
T21 |
3 |
|
T38 |
3 |
| auto[1] |
auto[1] |
426 |
1 |
|
|
T56 |
5 |
|
T21 |
8 |
|
T68 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
419 |
1 |
|
|
T56 |
3 |
|
T21 |
8 |
|
T68 |
8 |
| auto[0] |
auto[1] |
368 |
1 |
|
|
T56 |
4 |
|
T21 |
6 |
|
T68 |
2 |
| auto[1] |
auto[0] |
375 |
1 |
|
|
T56 |
7 |
|
T21 |
1 |
|
T68 |
3 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T56 |
6 |
|
T21 |
5 |
|
T68 |
7 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
388 |
1 |
|
|
T56 |
4 |
|
T21 |
6 |
|
T68 |
5 |
| auto[0] |
auto[1] |
412 |
1 |
|
|
T56 |
4 |
|
T21 |
6 |
|
T68 |
7 |
| auto[1] |
auto[0] |
399 |
1 |
|
|
T56 |
8 |
|
T21 |
5 |
|
T68 |
5 |
| auto[1] |
auto[1] |
381 |
1 |
|
|
T56 |
4 |
|
T21 |
3 |
|
T68 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
377 |
1 |
|
|
T56 |
4 |
|
T21 |
3 |
|
T68 |
2 |
| auto[0] |
auto[1] |
416 |
1 |
|
|
T56 |
6 |
|
T21 |
6 |
|
T68 |
7 |
| auto[1] |
auto[0] |
395 |
1 |
|
|
T56 |
6 |
|
T21 |
5 |
|
T68 |
5 |
| auto[1] |
auto[1] |
392 |
1 |
|
|
T56 |
4 |
|
T21 |
6 |
|
T68 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
377 |
1 |
|
|
T56 |
1 |
|
T21 |
3 |
|
T68 |
3 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T56 |
4 |
|
T21 |
4 |
|
T68 |
5 |
| auto[1] |
auto[0] |
397 |
1 |
|
|
T56 |
11 |
|
T21 |
8 |
|
T68 |
5 |
| auto[1] |
auto[1] |
411 |
1 |
|
|
T56 |
4 |
|
T21 |
5 |
|
T68 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
368 |
1 |
|
|
T56 |
2 |
|
T21 |
7 |
|
T68 |
9 |
| auto[0] |
auto[1] |
374 |
1 |
|
|
T56 |
8 |
|
T21 |
6 |
|
T68 |
5 |
| auto[1] |
auto[0] |
418 |
1 |
|
|
T56 |
7 |
|
T21 |
6 |
|
T68 |
5 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T56 |
3 |
|
T21 |
1 |
|
T68 |
1 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
398 |
1 |
|
|
T56 |
8 |
|
T21 |
2 |
|
T68 |
5 |
| auto[0] |
auto[1] |
389 |
1 |
|
|
T56 |
4 |
|
T21 |
4 |
|
T68 |
5 |
| auto[1] |
auto[0] |
401 |
1 |
|
|
T56 |
5 |
|
T21 |
7 |
|
T68 |
5 |
| auto[1] |
auto[1] |
392 |
1 |
|
|
T56 |
3 |
|
T21 |
7 |
|
T68 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
406 |
1 |
|
|
T56 |
8 |
|
T21 |
4 |
|
T68 |
6 |
| auto[0] |
auto[1] |
406 |
1 |
|
|
T56 |
4 |
|
T21 |
5 |
|
T68 |
3 |
| auto[1] |
auto[0] |
384 |
1 |
|
|
T56 |
5 |
|
T21 |
6 |
|
T68 |
7 |
| auto[1] |
auto[1] |
384 |
1 |
|
|
T56 |
3 |
|
T21 |
5 |
|
T68 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
398 |
1 |
|
|
T56 |
7 |
|
T21 |
5 |
|
T68 |
8 |
| auto[0] |
auto[1] |
397 |
1 |
|
|
T56 |
5 |
|
T21 |
8 |
|
T68 |
2 |
| auto[1] |
auto[0] |
409 |
1 |
|
|
T56 |
5 |
|
T21 |
4 |
|
T68 |
6 |
| auto[1] |
auto[1] |
376 |
1 |
|
|
T56 |
3 |
|
T21 |
3 |
|
T68 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
813 |
1 |
|
|
T56 |
11 |
|
T21 |
12 |
|
T68 |
15 |
| auto[1] |
auto[1] |
767 |
1 |
|
|
T56 |
9 |
|
T21 |
8 |
|
T68 |
5 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
400 |
1 |
|
|
T56 |
4 |
|
T21 |
3 |
|
T68 |
8 |
| auto[0] |
auto[1] |
399 |
1 |
|
|
T56 |
5 |
|
T21 |
5 |
|
T68 |
5 |
| auto[1] |
auto[0] |
378 |
1 |
|
|
T56 |
3 |
|
T21 |
7 |
|
T68 |
5 |
| auto[1] |
auto[1] |
403 |
1 |
|
|
T56 |
8 |
|
T21 |
5 |
|
T68 |
2 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
808 |
1 |
|
|
T56 |
12 |
|
T21 |
12 |
|
T68 |
11 |
| auto[1] |
auto[1] |
772 |
1 |
|
|
T56 |
8 |
|
T21 |
8 |
|
T68 |
9 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
179 |
1 |
|
|
T21 |
10 |
|
T38 |
10 |
|
T45 |
7 |
| auto[1] |
201 |
1 |
|
|
T21 |
10 |
|
T38 |
10 |
|
T45 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T21 |
11 |
|
T38 |
11 |
|
T45 |
10 |
| auto[1] |
197 |
1 |
|
|
T21 |
9 |
|
T38 |
9 |
|
T45 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
196 |
1 |
|
|
T21 |
9 |
|
T38 |
13 |
|
T45 |
9 |
| auto[1] |
184 |
1 |
|
|
T21 |
11 |
|
T38 |
7 |
|
T45 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
189 |
1 |
|
|
T21 |
9 |
|
T38 |
10 |
|
T45 |
9 |
| auto[1] |
191 |
1 |
|
|
T21 |
11 |
|
T38 |
10 |
|
T45 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
190 |
1 |
|
|
T21 |
11 |
|
T38 |
8 |
|
T45 |
12 |
| auto[1] |
190 |
1 |
|
|
T21 |
9 |
|
T38 |
12 |
|
T45 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
204 |
1 |
|
|
T21 |
9 |
|
T38 |
12 |
|
T45 |
12 |
| auto[1] |
176 |
1 |
|
|
T21 |
11 |
|
T38 |
8 |
|
T45 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T21 |
11 |
|
T38 |
8 |
|
T45 |
11 |
| auto[1] |
197 |
1 |
|
|
T21 |
9 |
|
T38 |
12 |
|
T45 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
174 |
1 |
|
|
T21 |
11 |
|
T38 |
8 |
|
T45 |
4 |
| auto[1] |
206 |
1 |
|
|
T21 |
9 |
|
T38 |
12 |
|
T45 |
16 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
184 |
1 |
|
|
T21 |
12 |
|
T38 |
7 |
|
T45 |
12 |
| auto[1] |
196 |
1 |
|
|
T21 |
8 |
|
T38 |
13 |
|
T45 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
218 |
1 |
|
|
T21 |
10 |
|
T38 |
13 |
|
T45 |
14 |
| auto[1] |
162 |
1 |
|
|
T21 |
10 |
|
T38 |
7 |
|
T45 |
6 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
188 |
1 |
|
|
T21 |
11 |
|
T38 |
7 |
|
T45 |
6 |
| auto[1] |
192 |
1 |
|
|
T21 |
9 |
|
T38 |
13 |
|
T45 |
14 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T21 |
10 |
|
T38 |
11 |
|
T45 |
12 |
| auto[1] |
178 |
1 |
|
|
T21 |
10 |
|
T38 |
9 |
|
T45 |
8 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
192 |
1 |
|
|
T21 |
12 |
|
T38 |
10 |
|
T45 |
13 |
| auto[1] |
188 |
1 |
|
|
T21 |
8 |
|
T38 |
10 |
|
T45 |
7 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T21 |
11 |
|
T38 |
11 |
|
T45 |
10 |
| auto[1] |
197 |
1 |
|
|
T21 |
9 |
|
T38 |
9 |
|
T45 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
203 |
1 |
|
|
T21 |
6 |
|
T38 |
10 |
|
T45 |
11 |
| auto[1] |
177 |
1 |
|
|
T21 |
14 |
|
T38 |
10 |
|
T45 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
182 |
1 |
|
|
T21 |
12 |
|
T38 |
13 |
|
T45 |
9 |
| auto[1] |
198 |
1 |
|
|
T21 |
8 |
|
T38 |
7 |
|
T45 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
173 |
1 |
|
|
T21 |
8 |
|
T38 |
10 |
|
T45 |
7 |
| auto[1] |
207 |
1 |
|
|
T21 |
12 |
|
T38 |
10 |
|
T45 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
189 |
1 |
|
|
T21 |
10 |
|
T38 |
8 |
|
T45 |
13 |
| auto[1] |
191 |
1 |
|
|
T21 |
10 |
|
T38 |
12 |
|
T45 |
7 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
206 |
1 |
|
|
T21 |
8 |
|
T38 |
12 |
|
T45 |
9 |
| auto[1] |
174 |
1 |
|
|
T21 |
12 |
|
T38 |
8 |
|
T45 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T21 |
6 |
|
T38 |
8 |
|
T45 |
8 |
| auto[1] |
199 |
1 |
|
|
T21 |
14 |
|
T38 |
12 |
|
T45 |
12 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
193 |
1 |
|
|
T21 |
14 |
|
T38 |
10 |
|
T45 |
10 |
| auto[1] |
187 |
1 |
|
|
T21 |
6 |
|
T38 |
10 |
|
T45 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
183 |
1 |
|
|
T21 |
9 |
|
T38 |
9 |
|
T45 |
10 |
| auto[1] |
197 |
1 |
|
|
T21 |
11 |
|
T38 |
11 |
|
T45 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
181 |
1 |
|
|
T21 |
8 |
|
T38 |
13 |
|
T45 |
6 |
| auto[1] |
199 |
1 |
|
|
T21 |
12 |
|
T38 |
7 |
|
T45 |
14 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
202 |
1 |
|
|
T21 |
10 |
|
T38 |
11 |
|
T45 |
12 |
| auto[1] |
178 |
1 |
|
|
T21 |
10 |
|
T38 |
9 |
|
T45 |
8 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
111 |
1 |
|
|
T21 |
4 |
|
T38 |
6 |
|
T45 |
7 |
| auto[0] |
auto[1] |
92 |
1 |
|
|
T21 |
2 |
|
T38 |
4 |
|
T45 |
4 |
| auto[1] |
auto[0] |
85 |
1 |
|
|
T21 |
5 |
|
T38 |
7 |
|
T45 |
2 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T21 |
9 |
|
T38 |
3 |
|
T45 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
97 |
1 |
|
|
T21 |
7 |
|
T38 |
6 |
|
T45 |
6 |
| auto[0] |
auto[1] |
85 |
1 |
|
|
T21 |
5 |
|
T38 |
7 |
|
T45 |
3 |
| auto[1] |
auto[0] |
92 |
1 |
|
|
T21 |
2 |
|
T38 |
4 |
|
T45 |
3 |
| auto[1] |
auto[1] |
106 |
1 |
|
|
T21 |
6 |
|
T38 |
3 |
|
T45 |
8 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
93 |
1 |
|
|
T21 |
4 |
|
T38 |
5 |
|
T45 |
4 |
| auto[0] |
auto[1] |
80 |
1 |
|
|
T21 |
4 |
|
T38 |
5 |
|
T45 |
3 |
| auto[1] |
auto[0] |
97 |
1 |
|
|
T21 |
7 |
|
T38 |
3 |
|
T45 |
8 |
| auto[1] |
auto[1] |
110 |
1 |
|
|
T21 |
5 |
|
T38 |
7 |
|
T45 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
108 |
1 |
|
|
T21 |
4 |
|
T38 |
6 |
|
T45 |
7 |
| auto[0] |
auto[1] |
81 |
1 |
|
|
T21 |
6 |
|
T38 |
2 |
|
T45 |
6 |
| auto[1] |
auto[0] |
96 |
1 |
|
|
T21 |
5 |
|
T38 |
6 |
|
T45 |
5 |
| auto[1] |
auto[1] |
95 |
1 |
|
|
T21 |
5 |
|
T38 |
6 |
|
T45 |
2 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
101 |
1 |
|
|
T21 |
5 |
|
T38 |
4 |
|
T45 |
4 |
| auto[0] |
auto[1] |
105 |
1 |
|
|
T21 |
3 |
|
T38 |
8 |
|
T45 |
5 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T21 |
6 |
|
T38 |
4 |
|
T45 |
7 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T21 |
6 |
|
T38 |
4 |
|
T45 |
4 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
84 |
1 |
|
|
T21 |
4 |
|
T38 |
2 |
|
T44 |
3 |
| auto[0] |
auto[1] |
97 |
1 |
|
|
T21 |
2 |
|
T38 |
6 |
|
T45 |
8 |
| auto[1] |
auto[0] |
90 |
1 |
|
|
T21 |
7 |
|
T38 |
6 |
|
T45 |
4 |
| auto[1] |
auto[1] |
109 |
1 |
|
|
T21 |
7 |
|
T38 |
6 |
|
T45 |
8 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
106 |
1 |
|
|
T21 |
5 |
|
T38 |
4 |
|
T45 |
8 |
| auto[0] |
auto[1] |
77 |
1 |
|
|
T21 |
4 |
|
T38 |
5 |
|
T45 |
2 |
| auto[1] |
auto[0] |
112 |
1 |
|
|
T21 |
5 |
|
T38 |
9 |
|
T45 |
6 |
| auto[1] |
auto[1] |
85 |
1 |
|
|
T21 |
6 |
|
T38 |
2 |
|
T45 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
90 |
1 |
|
|
T21 |
5 |
|
T38 |
3 |
|
T45 |
2 |
| auto[0] |
auto[1] |
91 |
1 |
|
|
T21 |
3 |
|
T38 |
10 |
|
T45 |
4 |
| auto[1] |
auto[0] |
98 |
1 |
|
|
T21 |
6 |
|
T38 |
4 |
|
T45 |
4 |
| auto[1] |
auto[1] |
101 |
1 |
|
|
T21 |
6 |
|
T38 |
3 |
|
T45 |
10 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
96 |
1 |
|
|
T21 |
7 |
|
T38 |
6 |
|
T45 |
4 |
| auto[0] |
auto[1] |
96 |
1 |
|
|
T21 |
5 |
|
T38 |
4 |
|
T45 |
9 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T21 |
3 |
|
T38 |
4 |
|
T45 |
3 |
| auto[1] |
auto[1] |
105 |
1 |
|
|
T21 |
5 |
|
T38 |
6 |
|
T45 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
183 |
1 |
|
|
T21 |
11 |
|
T38 |
11 |
|
T45 |
10 |
| auto[1] |
auto[1] |
197 |
1 |
|
|
T21 |
9 |
|
T38 |
9 |
|
T45 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
89 |
1 |
|
|
T21 |
9 |
|
T38 |
4 |
|
T45 |
7 |
| auto[0] |
auto[1] |
104 |
1 |
|
|
T21 |
5 |
|
T38 |
6 |
|
T45 |
3 |
| auto[1] |
auto[0] |
95 |
1 |
|
|
T21 |
3 |
|
T38 |
3 |
|
T45 |
5 |
| auto[1] |
auto[1] |
92 |
1 |
|
|
T21 |
3 |
|
T38 |
7 |
|
T45 |
5 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
202 |
1 |
|
|
T21 |
10 |
|
T38 |
11 |
|
T45 |
12 |
| auto[1] |
auto[1] |
178 |
1 |
|
|
T21 |
10 |
|
T38 |
9 |
|
T45 |
8 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T44 |
11 |
|
T83 |
11 |
|
T79 |
9 |
| auto[1] |
76 |
1 |
|
|
T44 |
9 |
|
T83 |
9 |
|
T79 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T44 |
13 |
|
T83 |
13 |
|
T79 |
8 |
| auto[1] |
58 |
1 |
|
|
T44 |
7 |
|
T83 |
7 |
|
T79 |
12 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
71 |
1 |
|
|
T44 |
12 |
|
T83 |
10 |
|
T79 |
8 |
| auto[1] |
69 |
1 |
|
|
T44 |
8 |
|
T83 |
10 |
|
T79 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T44 |
13 |
|
T83 |
8 |
|
T79 |
7 |
| auto[1] |
65 |
1 |
|
|
T44 |
7 |
|
T83 |
12 |
|
T79 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
72 |
1 |
|
|
T44 |
12 |
|
T83 |
9 |
|
T79 |
12 |
| auto[1] |
68 |
1 |
|
|
T44 |
8 |
|
T83 |
11 |
|
T79 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T44 |
11 |
|
T83 |
12 |
|
T79 |
13 |
| auto[1] |
61 |
1 |
|
|
T44 |
9 |
|
T83 |
8 |
|
T79 |
7 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
65 |
1 |
|
|
T44 |
8 |
|
T83 |
9 |
|
T79 |
11 |
| auto[1] |
75 |
1 |
|
|
T44 |
12 |
|
T83 |
11 |
|
T79 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T44 |
11 |
|
T83 |
10 |
|
T79 |
8 |
| auto[1] |
74 |
1 |
|
|
T44 |
9 |
|
T83 |
10 |
|
T79 |
12 |