Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
816 |
1 |
|
|
T29 |
11 |
|
T30 |
9 |
|
T17 |
10 |
| auto[1] |
801 |
1 |
|
|
T29 |
9 |
|
T30 |
11 |
|
T17 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T29 |
8 |
|
T30 |
10 |
|
T17 |
11 |
| auto[1] |
804 |
1 |
|
|
T29 |
12 |
|
T30 |
10 |
|
T17 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T29 |
10 |
|
T30 |
12 |
|
T17 |
10 |
| auto[1] |
788 |
1 |
|
|
T29 |
10 |
|
T30 |
8 |
|
T17 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T29 |
12 |
|
T30 |
6 |
|
T17 |
11 |
| auto[1] |
804 |
1 |
|
|
T29 |
8 |
|
T30 |
14 |
|
T17 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T29 |
9 |
|
T30 |
7 |
|
T17 |
11 |
| auto[1] |
819 |
1 |
|
|
T29 |
11 |
|
T30 |
13 |
|
T17 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T29 |
12 |
|
T30 |
7 |
|
T17 |
8 |
| auto[1] |
796 |
1 |
|
|
T29 |
8 |
|
T30 |
13 |
|
T17 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
827 |
1 |
|
|
T29 |
11 |
|
T30 |
8 |
|
T17 |
6 |
| auto[1] |
790 |
1 |
|
|
T29 |
9 |
|
T30 |
12 |
|
T17 |
14 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
834 |
1 |
|
|
T29 |
12 |
|
T30 |
14 |
|
T17 |
10 |
| auto[1] |
783 |
1 |
|
|
T29 |
8 |
|
T30 |
6 |
|
T17 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T29 |
8 |
|
T30 |
13 |
|
T17 |
7 |
| auto[1] |
811 |
1 |
|
|
T29 |
12 |
|
T30 |
7 |
|
T17 |
13 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
791 |
1 |
|
|
T29 |
11 |
|
T30 |
10 |
|
T17 |
9 |
| auto[1] |
826 |
1 |
|
|
T29 |
9 |
|
T30 |
10 |
|
T17 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T29 |
7 |
|
T30 |
7 |
|
T17 |
16 |
| auto[1] |
822 |
1 |
|
|
T29 |
13 |
|
T30 |
13 |
|
T17 |
4 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T29 |
10 |
|
T30 |
12 |
|
T17 |
10 |
| auto[1] |
804 |
1 |
|
|
T29 |
10 |
|
T30 |
8 |
|
T17 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
779 |
1 |
|
|
T29 |
10 |
|
T30 |
7 |
|
T17 |
10 |
| auto[1] |
838 |
1 |
|
|
T29 |
10 |
|
T30 |
13 |
|
T17 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T29 |
8 |
|
T30 |
10 |
|
T17 |
11 |
| auto[1] |
804 |
1 |
|
|
T29 |
12 |
|
T30 |
10 |
|
T17 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T29 |
15 |
|
T30 |
13 |
|
T17 |
9 |
| auto[1] |
781 |
1 |
|
|
T29 |
5 |
|
T30 |
7 |
|
T17 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T29 |
13 |
|
T30 |
9 |
|
T17 |
8 |
| auto[1] |
787 |
1 |
|
|
T29 |
7 |
|
T30 |
11 |
|
T17 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
807 |
1 |
|
|
T29 |
11 |
|
T30 |
12 |
|
T17 |
9 |
| auto[1] |
810 |
1 |
|
|
T29 |
9 |
|
T30 |
8 |
|
T17 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
814 |
1 |
|
|
T29 |
8 |
|
T30 |
8 |
|
T17 |
10 |
| auto[1] |
803 |
1 |
|
|
T29 |
12 |
|
T30 |
12 |
|
T17 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T29 |
9 |
|
T30 |
11 |
|
T17 |
11 |
| auto[1] |
794 |
1 |
|
|
T29 |
11 |
|
T30 |
9 |
|
T17 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
816 |
1 |
|
|
T29 |
12 |
|
T30 |
11 |
|
T17 |
7 |
| auto[1] |
801 |
1 |
|
|
T29 |
8 |
|
T30 |
9 |
|
T17 |
13 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T29 |
8 |
|
T30 |
10 |
|
T17 |
10 |
| auto[1] |
805 |
1 |
|
|
T29 |
12 |
|
T30 |
10 |
|
T17 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
846 |
1 |
|
|
T29 |
9 |
|
T30 |
11 |
|
T17 |
11 |
| auto[1] |
771 |
1 |
|
|
T29 |
11 |
|
T30 |
9 |
|
T17 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
820 |
1 |
|
|
T29 |
11 |
|
T30 |
12 |
|
T17 |
16 |
| auto[1] |
797 |
1 |
|
|
T29 |
9 |
|
T30 |
8 |
|
T17 |
4 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T29 |
10 |
|
T30 |
12 |
|
T17 |
10 |
| auto[1] |
804 |
1 |
|
|
T29 |
10 |
|
T30 |
8 |
|
T17 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
452 |
1 |
|
|
T29 |
8 |
|
T30 |
7 |
|
T17 |
3 |
| auto[0] |
auto[1] |
384 |
1 |
|
|
T29 |
7 |
|
T30 |
6 |
|
T17 |
6 |
| auto[1] |
auto[0] |
377 |
1 |
|
|
T29 |
2 |
|
T30 |
5 |
|
T17 |
7 |
| auto[1] |
auto[1] |
404 |
1 |
|
|
T29 |
3 |
|
T30 |
2 |
|
T17 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
441 |
1 |
|
|
T29 |
8 |
|
T30 |
2 |
|
T17 |
3 |
| auto[0] |
auto[1] |
389 |
1 |
|
|
T29 |
5 |
|
T30 |
7 |
|
T17 |
5 |
| auto[1] |
auto[0] |
372 |
1 |
|
|
T29 |
4 |
|
T30 |
4 |
|
T17 |
8 |
| auto[1] |
auto[1] |
415 |
1 |
|
|
T29 |
3 |
|
T30 |
7 |
|
T17 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
400 |
1 |
|
|
T29 |
5 |
|
T30 |
4 |
|
T17 |
7 |
| auto[0] |
auto[1] |
407 |
1 |
|
|
T29 |
6 |
|
T30 |
8 |
|
T17 |
2 |
| auto[1] |
auto[0] |
398 |
1 |
|
|
T29 |
4 |
|
T30 |
3 |
|
T17 |
4 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T29 |
5 |
|
T30 |
5 |
|
T17 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
415 |
1 |
|
|
T29 |
5 |
|
T30 |
2 |
|
T17 |
6 |
| auto[0] |
auto[1] |
399 |
1 |
|
|
T29 |
3 |
|
T30 |
6 |
|
T17 |
4 |
| auto[1] |
auto[0] |
406 |
1 |
|
|
T29 |
7 |
|
T30 |
5 |
|
T17 |
2 |
| auto[1] |
auto[1] |
397 |
1 |
|
|
T29 |
5 |
|
T30 |
7 |
|
T17 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T29 |
6 |
|
T30 |
5 |
|
T17 |
3 |
| auto[0] |
auto[1] |
384 |
1 |
|
|
T29 |
3 |
|
T30 |
6 |
|
T17 |
8 |
| auto[1] |
auto[0] |
388 |
1 |
|
|
T29 |
5 |
|
T30 |
3 |
|
T17 |
3 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T29 |
6 |
|
T30 |
6 |
|
T17 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T29 |
8 |
|
T30 |
8 |
|
T17 |
3 |
| auto[0] |
auto[1] |
377 |
1 |
|
|
T29 |
4 |
|
T30 |
3 |
|
T17 |
4 |
| auto[1] |
auto[0] |
395 |
1 |
|
|
T29 |
4 |
|
T30 |
6 |
|
T17 |
7 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T29 |
4 |
|
T30 |
3 |
|
T17 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
426 |
1 |
|
|
T29 |
5 |
|
T30 |
4 |
|
T17 |
6 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T29 |
4 |
|
T30 |
7 |
|
T17 |
5 |
| auto[1] |
auto[0] |
365 |
1 |
|
|
T29 |
6 |
|
T30 |
6 |
|
T17 |
3 |
| auto[1] |
auto[1] |
406 |
1 |
|
|
T29 |
5 |
|
T30 |
3 |
|
T17 |
6 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
415 |
1 |
|
|
T29 |
4 |
|
T30 |
3 |
|
T17 |
12 |
| auto[0] |
auto[1] |
405 |
1 |
|
|
T29 |
7 |
|
T30 |
9 |
|
T17 |
4 |
| auto[1] |
auto[0] |
380 |
1 |
|
|
T29 |
3 |
|
T30 |
4 |
|
T17 |
4 |
| auto[1] |
auto[1] |
417 |
1 |
|
|
T29 |
6 |
|
T30 |
4 |
|
T86 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
391 |
1 |
|
|
T29 |
5 |
|
T30 |
4 |
|
T17 |
4 |
| auto[0] |
auto[1] |
388 |
1 |
|
|
T29 |
5 |
|
T30 |
3 |
|
T17 |
6 |
| auto[1] |
auto[0] |
425 |
1 |
|
|
T29 |
6 |
|
T30 |
5 |
|
T17 |
6 |
| auto[1] |
auto[1] |
413 |
1 |
|
|
T29 |
4 |
|
T30 |
8 |
|
T17 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
813 |
1 |
|
|
T29 |
8 |
|
T30 |
10 |
|
T17 |
11 |
| auto[1] |
auto[1] |
804 |
1 |
|
|
T29 |
12 |
|
T30 |
10 |
|
T17 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
413 |
1 |
|
|
T29 |
4 |
|
T30 |
6 |
|
T17 |
4 |
| auto[0] |
auto[1] |
399 |
1 |
|
|
T29 |
4 |
|
T30 |
4 |
|
T17 |
6 |
| auto[1] |
auto[0] |
393 |
1 |
|
|
T29 |
4 |
|
T30 |
7 |
|
T17 |
3 |
| auto[1] |
auto[1] |
412 |
1 |
|
|
T29 |
8 |
|
T30 |
3 |
|
T17 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
813 |
1 |
|
|
T29 |
10 |
|
T30 |
12 |
|
T17 |
10 |
| auto[1] |
auto[1] |
804 |
1 |
|
|
T29 |
10 |
|
T30 |
8 |
|
T17 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T86 |
9 |
|
T160 |
11 |
|
T396 |
6 |
| auto[1] |
109 |
1 |
|
|
T86 |
11 |
|
T160 |
9 |
|
T396 |
14 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T86 |
9 |
|
T160 |
12 |
|
T396 |
11 |
| auto[1] |
91 |
1 |
|
|
T86 |
11 |
|
T160 |
8 |
|
T396 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
104 |
1 |
|
|
T86 |
11 |
|
T160 |
10 |
|
T396 |
9 |
| auto[1] |
96 |
1 |
|
|
T86 |
9 |
|
T160 |
10 |
|
T396 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
106 |
1 |
|
|
T86 |
13 |
|
T160 |
6 |
|
T396 |
10 |
| auto[1] |
94 |
1 |
|
|
T86 |
7 |
|
T160 |
14 |
|
T396 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T86 |
16 |
|
T160 |
10 |
|
T396 |
13 |
| auto[1] |
101 |
1 |
|
|
T86 |
4 |
|
T160 |
10 |
|
T396 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T86 |
10 |
|
T160 |
11 |
|
T396 |
7 |
| auto[1] |
101 |
1 |
|
|
T86 |
10 |
|
T160 |
9 |
|
T396 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T86 |
10 |
|
T160 |
7 |
|
T396 |
14 |
| auto[1] |
82 |
1 |
|
|
T86 |
10 |
|
T160 |
13 |
|
T396 |
6 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T86 |
6 |
|
T160 |
15 |
|
T396 |
10 |
| auto[1] |
101 |
1 |
|
|
T86 |
14 |
|
T160 |
5 |
|
T396 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T86 |
13 |
|
T160 |
12 |
|
T396 |
5 |
| auto[1] |
101 |
1 |
|
|
T86 |
7 |
|
T160 |
8 |
|
T396 |
15 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
110 |
1 |
|
|
T86 |
12 |
|
T160 |
10 |
|
T396 |
12 |
| auto[1] |
90 |
1 |
|
|
T86 |
8 |
|
T160 |
10 |
|
T396 |
8 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
107 |
1 |
|
|
T86 |
10 |
|
T160 |
11 |
|
T396 |
10 |
| auto[1] |
93 |
1 |
|
|
T86 |
10 |
|
T160 |
9 |
|
T396 |
10 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T86 |
10 |
|
T160 |
10 |
|
T396 |
9 |
| auto[1] |
100 |
1 |
|
|
T86 |
10 |
|
T160 |
10 |
|
T396 |
11 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T86 |
10 |
|
T160 |
11 |
|
T396 |
7 |
| auto[1] |
105 |
1 |
|
|
T86 |
10 |
|
T160 |
9 |
|
T396 |
13 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
109 |
1 |
|
|
T86 |
9 |
|
T160 |
12 |
|
T396 |
11 |
| auto[1] |
91 |
1 |
|
|
T86 |
11 |
|
T160 |
8 |
|
T396 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T86 |
9 |
|
T160 |
6 |
|
T396 |
12 |
| auto[1] |
105 |
1 |
|
|
T86 |
11 |
|
T160 |
14 |
|
T396 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
111 |
1 |
|
|
T86 |
13 |
|
T160 |
8 |
|
T396 |
9 |
| auto[1] |
89 |
1 |
|
|
T86 |
7 |
|
T160 |
12 |
|
T396 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
97 |
1 |
|
|
T86 |
11 |
|
T160 |
11 |
|
T396 |
6 |
| auto[1] |
103 |
1 |
|
|
T86 |
9 |
|
T160 |
9 |
|
T396 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
93 |
1 |
|
|
T86 |
11 |
|
T160 |
8 |
|
T396 |
10 |
| auto[1] |
107 |
1 |
|
|
T86 |
9 |
|
T160 |
12 |
|
T396 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T86 |
10 |
|
T160 |
12 |
|
T396 |
10 |
| auto[1] |
105 |
1 |
|
|
T86 |
10 |
|
T160 |
8 |
|
T396 |
10 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
82 |
1 |
|
|
T86 |
6 |
|
T160 |
8 |
|
T396 |
10 |
| auto[1] |
118 |
1 |
|
|
T86 |
14 |
|
T160 |
12 |
|
T396 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
108 |
1 |
|
|
T86 |
10 |
|
T160 |
11 |
|
T396 |
9 |
| auto[1] |
92 |
1 |
|
|
T86 |
10 |
|
T160 |
9 |
|
T396 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
101 |
1 |
|
|
T86 |
13 |
|
T160 |
10 |
|
T396 |
12 |
| auto[1] |
99 |
1 |
|
|
T86 |
7 |
|
T160 |
10 |
|
T396 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T86 |
9 |
|
T160 |
11 |
|
T396 |
4 |
| auto[1] |
112 |
1 |
|
|
T86 |
11 |
|
T160 |
9 |
|
T396 |
16 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T86 |
10 |
|
T160 |
10 |
|
T396 |
9 |
| auto[1] |
100 |
1 |
|
|
T86 |
10 |
|
T160 |
10 |
|
T396 |
11 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
49 |
1 |
|
|
T86 |
6 |
|
T160 |
4 |
|
T396 |
4 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T86 |
3 |
|
T160 |
2 |
|
T396 |
8 |
| auto[1] |
auto[0] |
55 |
1 |
|
|
T86 |
5 |
|
T160 |
6 |
|
T396 |
5 |
| auto[1] |
auto[1] |
50 |
1 |
|
|
T86 |
6 |
|
T160 |
8 |
|
T396 |
3 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
58 |
1 |
|
|
T86 |
9 |
|
T160 |
3 |
|
T396 |
3 |
| auto[0] |
auto[1] |
53 |
1 |
|
|
T86 |
4 |
|
T160 |
5 |
|
T396 |
6 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T86 |
4 |
|
T160 |
3 |
|
T396 |
7 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T86 |
3 |
|
T160 |
9 |
|
T396 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
47 |
1 |
|
|
T86 |
8 |
|
T160 |
5 |
|
T396 |
4 |
| auto[0] |
auto[1] |
50 |
1 |
|
|
T86 |
3 |
|
T160 |
6 |
|
T396 |
2 |
| auto[1] |
auto[0] |
52 |
1 |
|
|
T86 |
8 |
|
T160 |
5 |
|
T396 |
9 |
| auto[1] |
auto[1] |
51 |
1 |
|
|
T86 |
1 |
|
T160 |
4 |
|
T396 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T86 |
5 |
|
T160 |
4 |
|
T396 |
3 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T86 |
6 |
|
T160 |
4 |
|
T396 |
7 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T86 |
5 |
|
T160 |
7 |
|
T396 |
4 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T86 |
4 |
|
T160 |
5 |
|
T396 |
6 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
55 |
1 |
|
|
T86 |
4 |
|
T160 |
5 |
|
T396 |
7 |
| auto[0] |
auto[1] |
40 |
1 |
|
|
T86 |
6 |
|
T160 |
7 |
|
T396 |
3 |
| auto[1] |
auto[0] |
63 |
1 |
|
|
T86 |
6 |
|
T160 |
2 |
|
T396 |
7 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T86 |
4 |
|
T160 |
6 |
|
T396 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
39 |
1 |
|
|
T160 |
7 |
|
T396 |
5 |
|
T141 |
2 |
| auto[0] |
auto[1] |
43 |
1 |
|
|
T86 |
6 |
|
T160 |
1 |
|
T396 |
5 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T86 |
6 |
|
T160 |
8 |
|
T396 |
5 |
| auto[1] |
auto[1] |
58 |
1 |
|
|
T86 |
8 |
|
T160 |
4 |
|
T396 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
56 |
1 |
|
|
T86 |
8 |
|
T160 |
4 |
|
T396 |
8 |
| auto[0] |
auto[1] |
45 |
1 |
|
|
T86 |
5 |
|
T160 |
6 |
|
T396 |
4 |
| auto[1] |
auto[0] |
54 |
1 |
|
|
T86 |
4 |
|
T160 |
6 |
|
T396 |
4 |
| auto[1] |
auto[1] |
45 |
1 |
|
|
T86 |
3 |
|
T160 |
4 |
|
T396 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
48 |
1 |
|
|
T86 |
5 |
|
T160 |
5 |
|
T396 |
3 |
| auto[0] |
auto[1] |
40 |
1 |
|
|
T86 |
4 |
|
T160 |
6 |
|
T396 |
1 |
| auto[1] |
auto[0] |
59 |
1 |
|
|
T86 |
5 |
|
T160 |
6 |
|
T396 |
7 |
| auto[1] |
auto[1] |
53 |
1 |
|
|
T86 |
6 |
|
T160 |
3 |
|
T396 |
9 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
47 |
1 |
|
|
T86 |
5 |
|
T160 |
6 |
|
T396 |
2 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T86 |
5 |
|
T160 |
5 |
|
T396 |
5 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T86 |
4 |
|
T160 |
5 |
|
T396 |
4 |
| auto[1] |
auto[1] |
61 |
1 |
|
|
T86 |
6 |
|
T160 |
4 |
|
T396 |
9 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
109 |
1 |
|
|
T86 |
9 |
|
T160 |
12 |
|
T396 |
11 |
| auto[1] |
auto[1] |
91 |
1 |
|
|
T86 |
11 |
|
T160 |
8 |
|
T396 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
50 |
1 |
|
|
T86 |
8 |
|
T160 |
5 |
|
T396 |
1 |
| auto[0] |
auto[1] |
58 |
1 |
|
|
T86 |
2 |
|
T160 |
6 |
|
T396 |
8 |
| auto[1] |
auto[0] |
49 |
1 |
|
|
T86 |
5 |
|
T160 |
7 |
|
T396 |
4 |
| auto[1] |
auto[1] |
43 |
1 |
|
|
T86 |
5 |
|
T160 |
2 |
|
T396 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
100 |
1 |
|
|
T86 |
10 |
|
T160 |
10 |
|
T396 |
9 |
| auto[1] |
auto[1] |
100 |
1 |
|
|
T86 |
10 |
|
T160 |
10 |
|
T396 |
11 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T86 |
9 |
|
T160 |
11 |
|
T396 |
9 |
| auto[1] |
65 |
1 |
|
|
T86 |
11 |
|
T160 |
9 |
|
T396 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
80 |
1 |
|
|
T86 |
10 |
|
T160 |
9 |
|
T396 |
13 |
| auto[1] |
60 |
1 |
|
|
T86 |
10 |
|
T160 |
11 |
|
T396 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
75 |
1 |
|
|
T86 |
15 |
|
T160 |
11 |
|
T396 |
8 |
| auto[1] |
65 |
1 |
|
|
T86 |
5 |
|
T160 |
9 |
|
T396 |
12 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T86 |
11 |
|
T160 |
9 |
|
T396 |
11 |
| auto[1] |
61 |
1 |
|
|
T86 |
9 |
|
T160 |
11 |
|
T396 |
9 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
66 |
1 |
|
|
T86 |
9 |
|
T160 |
10 |
|
T396 |
10 |
| auto[1] |
74 |
1 |
|
|
T86 |
11 |
|
T160 |
10 |
|
T396 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
70 |
1 |
|
|
T86 |
9 |
|
T160 |
14 |
|
T396 |
8 |
| auto[1] |
70 |
1 |
|
|
T86 |
11 |
|
T160 |
6 |
|
T396 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
79 |
1 |
|
|
T86 |
9 |
|
T160 |
11 |
|
T396 |
11 |
| auto[1] |
61 |
1 |
|
|
T86 |
11 |
|
T160 |
9 |
|
T396 |
9 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
61 |
1 |
|
|
T86 |
7 |
|
T160 |
7 |
|
T396 |
7 |
| auto[1] |
79 |
1 |
|
|
T86 |
13 |
|
T160 |
13 |
|
T396 |
13 |