Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.99	99.41	96.38	100.00	97.44	98.82	99.63	94.27

Total tests in report: 921

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
46.72	46.72	60.34	60.34	54.04	54.04	82.12	82.12	0.00	0.00	65.02	65.02	54.49	54.49	11.01	11.01	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1979170567
60.95	14.23	60.43	0.09	54.26	0.21	82.35	0.23	97.44	97.44	65.09	0.07	54.59	0.09	12.49	1.47	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3761560864
71.55	10.60	74.74	14.31	67.80	13.55	90.09	7.74	97.44	0.00	76.89	11.80	72.10	17.51	21.81	9.32	/workspace/coverage/default/35.sysrst_ctrl_stress_all.736009032
79.07	7.52	87.06	12.33	80.06	12.26	94.76	4.67	97.44	0.00	87.99	11.10	72.57	0.47	33.64	11.83	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.626226331
84.35	5.27	91.16	4.10	84.07	4.01	96.13	1.37	97.44	0.00	91.09	3.10	80.81	8.24	49.73	16.09	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2541396214
87.39	3.04	91.49	0.33	84.43	0.36	96.81	0.68	97.44	0.00	91.40	0.31	81.46	0.66	68.70	18.97	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2892872931
89.97	2.58	93.77	2.27	86.60	2.17	98.63	1.82	97.44	0.00	92.93	1.53	85.21	3.75	75.19	6.49	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3535072768
91.23	1.27	95.45	1.68	88.03	1.43	98.63	0.00	97.44	0.00	94.33	1.39	89.51	4.31	75.25	0.05	/workspace/coverage/default/22.sysrst_ctrl_edge_detect.4121984045
92.34	1.11	96.82	1.37	89.22	1.19	99.09	0.46	97.44	0.00	95.44	1.11	92.70	3.18	75.68	0.44	/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3234351360
93.35	1.01	97.03	0.21	92.75	3.53	99.09	0.00	97.44	0.00	95.86	0.42	95.60	2.90	75.68	0.00	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2115970754
93.85	0.50	97.12	0.09	92.92	0.17	99.09	0.00	97.44	0.00	95.93	0.07	95.69	0.09	78.79	3.11	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1549910655
94.22	0.37	98.23	1.11	93.13	0.21	99.09	0.00	97.44	0.00	97.11	1.18	95.79	0.09	78.79	0.00	/workspace/coverage/default/1.sysrst_ctrl_feature_disable.3965753763
94.58	0.36	98.30	0.07	93.25	0.12	99.09	0.00	97.44	0.00	97.22	0.10	95.97	0.19	80.81	2.02	/workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.798834144
94.93	0.34	98.37	0.07	93.39	0.14	99.09	0.00	97.44	0.00	97.29	0.07	95.97	0.00	82.93	2.13	/workspace/coverage/default/20.sysrst_ctrl_stress_all.3322580328
95.24	0.31	98.37	0.00	93.42	0.02	99.09	0.00	97.44	0.00	97.29	0.00	96.07	0.09	85.01	2.07	/workspace/coverage/default/13.sysrst_ctrl_stress_all.1881294369
95.46	0.22	98.58	0.21	93.66	0.24	99.09	0.00	97.44	0.00	97.53	0.24	96.91	0.84	85.01	0.00	/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.4029046620
95.66	0.21	98.58	0.00	94.63	0.98	99.09	0.00	97.44	0.00	97.56	0.03	96.91	0.00	85.44	0.44	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1783479088
95.84	0.18	98.61	0.03	94.68	0.05	99.09	0.00	97.44	0.00	97.60	0.03	97.00	0.09	86.48	1.04	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3558918369
96.01	0.17	98.65	0.03	94.82	0.14	99.09	0.00	97.44	0.00	97.67	0.07	97.94	0.94	86.48	0.00	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3071678036
96.15	0.14	98.75	0.10	94.94	0.12	99.09	0.00	97.44	0.00	97.77	0.10	98.22	0.28	86.86	0.38	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1513283063
96.29	0.14	98.75	0.00	94.94	0.00	99.09	0.00	97.44	0.00	97.77	0.00	98.22	0.00	87.84	0.98	/workspace/coverage/default/38.sysrst_ctrl_stress_all.129061296
96.43	0.13	98.75	0.00	94.94	0.00	99.09	0.00	97.44	0.00	97.77	0.00	98.22	0.00	88.77	0.93	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.973182452
96.54	0.12	98.80	0.05	95.02	0.07	99.09	0.00	97.44	0.00	97.84	0.07	98.41	0.19	89.20	0.44	/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.1402268905
96.64	0.10	98.87	0.07	95.11	0.10	99.09	0.00	97.44	0.00	97.95	0.10	98.50	0.09	89.53	0.33	/workspace/coverage/default/31.sysrst_ctrl_combo_detect.1398320743
96.74	0.10	98.87	0.00	95.13	0.02	99.54	0.46	97.44	0.00	97.95	0.00	98.60	0.09	89.64	0.11	/workspace/coverage/default/0.sysrst_ctrl_sec_cm.3554557095
96.82	0.08	98.87	0.00	95.13	0.00	99.54	0.00	97.44	0.00	97.95	0.00	98.60	0.00	90.19	0.55	/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.687102489
96.89	0.07	98.92	0.05	95.18	0.05	99.54	0.00	97.44	0.00	98.05	0.10	98.69	0.09	90.40	0.22	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1192809396
96.96	0.07	98.96	0.03	95.33	0.14	99.77	0.23	97.44	0.00	98.12	0.07	98.69	0.00	90.40	0.00	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3931270947
97.02	0.06	98.96	0.00	95.33	0.00	99.77	0.00	97.44	0.00	98.12	0.00	98.69	0.00	90.84	0.44	/workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.378552869
97.08	0.06	98.96	0.00	95.73	0.41	99.77	0.00	97.44	0.00	98.12	0.00	98.69	0.00	90.84	0.00	/workspace/coverage/default/0.sysrst_ctrl_feature_disable.955934763
97.13	0.06	98.96	0.00	95.75	0.02	99.77	0.00	97.44	0.00	98.16	0.03	98.69	0.00	91.17	0.33	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.514415840
97.19	0.05	98.96	0.00	95.75	0.00	99.77	0.00	97.44	0.00	98.16	0.00	98.69	0.00	91.55	0.38	/workspace/coverage/default/15.sysrst_ctrl_combo_detect.2958502687
97.24	0.05	99.03	0.07	95.80	0.05	99.77	0.00	97.44	0.00	98.22	0.07	98.88	0.19	91.55	0.00	/workspace/coverage/default/33.sysrst_ctrl_edge_detect.3074963577
97.29	0.05	99.10	0.07	95.85	0.05	99.77	0.00	97.44	0.00	98.29	0.07	99.06	0.19	91.55	0.00	/workspace/coverage/default/7.sysrst_ctrl_edge_detect.740316084
97.34	0.05	99.15	0.05	95.87	0.02	99.77	0.00	97.44	0.00	98.36	0.07	99.16	0.09	91.66	0.11	/workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.945632146
97.39	0.04	99.15	0.00	95.92	0.05	100.00	0.23	97.44	0.00	98.40	0.03	99.16	0.00	91.66	0.00	/workspace/coverage/default/15.sysrst_ctrl_alert_test.1533450893
97.43	0.04	99.15	0.00	95.92	0.00	100.00	0.00	97.44	0.00	98.40	0.00	99.16	0.00	91.93	0.27	/workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.4171965382
97.46	0.03	99.15	0.00	95.95	0.02	100.00	0.00	97.44	0.00	98.40	0.00	99.16	0.00	92.15	0.22	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2736945973
97.50	0.03	99.20	0.05	95.97	0.02	100.00	0.00	97.44	0.00	98.47	0.07	99.25	0.09	92.15	0.00	/workspace/coverage/default/16.sysrst_ctrl_stress_all.290708261
97.53	0.03	99.20	0.00	95.99	0.02	100.00	0.00	97.44	0.00	98.47	0.00	99.34	0.09	92.26	0.11	/workspace/coverage/default/30.sysrst_ctrl_combo_detect.4291127746
97.56	0.03	99.20	0.00	95.99	0.00	100.00	0.00	97.44	0.00	98.47	0.00	99.34	0.00	92.48	0.22	/workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.968535305
97.59	0.03	99.20	0.00	95.99	0.00	100.00	0.00	97.44	0.00	98.47	0.00	99.34	0.00	92.69	0.22	/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2947285370
97.62	0.03	99.20	0.00	96.09	0.10	100.00	0.00	97.44	0.00	98.47	0.00	99.44	0.09	92.69	0.00	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.416466724
97.64	0.03	99.20	0.00	96.11	0.02	100.00	0.00	97.44	0.00	98.47	0.00	99.44	0.00	92.86	0.16	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.429000215
97.67	0.03	99.24	0.03	96.14	0.02	100.00	0.00	97.44	0.00	98.50	0.03	99.53	0.09	92.86	0.00	/workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3386406407
97.70	0.03	99.27	0.03	96.16	0.02	100.00	0.00	97.44	0.00	98.54	0.03	99.63	0.09	92.86	0.00	/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.1080267319
97.72	0.02	99.32	0.05	96.16	0.00	100.00	0.00	97.44	0.00	98.64	0.10	99.63	0.00	92.86	0.00	/workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1037766621
97.74	0.02	99.32	0.00	96.30	0.14	100.00	0.00	97.44	0.00	98.64	0.00	99.63	0.00	92.86	0.00	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1350541706
97.76	0.02	99.32	0.00	96.30	0.00	100.00	0.00	97.44	0.00	98.64	0.00	99.63	0.00	92.97	0.11	/workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.3949288750
97.77	0.02	99.32	0.00	96.30	0.00	100.00	0.00	97.44	0.00	98.64	0.00	99.63	0.00	93.08	0.11	/workspace/coverage/default/49.sysrst_ctrl_combo_detect.3442049171
97.79	0.02	99.32	0.00	96.30	0.00	100.00	0.00	97.44	0.00	98.64	0.00	99.63	0.00	93.18	0.11	/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.140853990
97.80	0.02	99.32	0.00	96.30	0.00	100.00	0.00	97.44	0.00	98.64	0.00	99.63	0.00	93.29	0.11	/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2151353086
97.82	0.02	99.32	0.00	96.30	0.00	100.00	0.00	97.44	0.00	98.64	0.00	99.63	0.00	93.40	0.11	/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1764466292
97.83	0.02	99.34	0.02	96.30	0.00	100.00	0.00	97.44	0.00	98.68	0.03	99.63	0.00	93.46	0.05	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1717147231
97.85	0.01	99.34	0.00	96.33	0.02	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.51	0.05	/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.1495380657
97.85	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.57	0.05	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.598140009
97.86	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.62	0.05	/workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2738530939
97.87	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.68	0.05	/workspace/coverage/default/13.sysrst_ctrl_combo_detect.942346930
97.88	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.73	0.05	/workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.4026089513
97.88	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.78	0.05	/workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3493544055
97.89	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.84	0.05	/workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.757555960
97.90	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.89	0.05	/workspace/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.52549012
97.91	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	93.95	0.05	/workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.682332457
97.92	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	94.00	0.05	/workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.4144472546
97.92	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	94.06	0.05	/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.463970593
97.93	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	94.11	0.05	/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.2928465311
97.94	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	94.17	0.05	/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.2306406391
97.95	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	94.22	0.05	/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1906375204
97.95	0.01	99.34	0.00	96.33	0.00	100.00	0.00	97.44	0.00	98.68	0.00	99.63	0.00	94.27	0.05	/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.4267740449
97.96	0.01	99.36	0.02	96.33	0.00	100.00	0.00	97.44	0.00	98.71	0.03	99.63	0.00	94.27	0.00	/workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.427808998
97.97	0.01	99.37	0.02	96.33	0.00	100.00	0.00	97.44	0.00	98.75	0.03	99.63	0.00	94.27	0.00	/workspace/coverage/default/14.sysrst_ctrl_edge_detect.3254911356
97.98	0.01	99.39	0.02	96.33	0.00	100.00	0.00	97.44	0.00	98.78	0.03	99.63	0.00	94.27	0.00	/workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2857402530
97.98	0.01	99.41	0.02	96.33	0.00	100.00	0.00	97.44	0.00	98.82	0.03	99.63	0.00	94.27	0.00	/workspace/coverage/default/39.sysrst_ctrl_edge_detect.2073214874
97.99	0.01	99.41	0.00	96.35	0.02	100.00	0.00	97.44	0.00	98.82	0.00	99.63	0.00	94.27	0.00	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.626931522

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.722602963
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3292392215
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.2911219172
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1300287583
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1846236362
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3589509828
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1941282728
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1617015707
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.593974088
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4218066296
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1857393343
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3106686109
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2634859251
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2566929793
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.77304288
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.846485690
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3708344481
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2414407115
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1365150246
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2477638575
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.3874067946
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3943398836
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.423179028
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3061652649
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1200983209
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.533556717
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3179697981
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2742993966
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1600767294
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/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.2715622393
/workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1413889670
/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1839545937
/workspace/coverage/default/38.sysrst_ctrl_smoke.1571210181
/workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3433715146
/workspace/coverage/default/39.sysrst_ctrl_alert_test.1462847445
/workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2205495436
/workspace/coverage/default/39.sysrst_ctrl_combo_detect.2390932380
/workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1214585293
/workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.843983426
/workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1561031776
/workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.2574313061
/workspace/coverage/default/39.sysrst_ctrl_pin_access_test.3702796402
/workspace/coverage/default/39.sysrst_ctrl_pin_override_test.2829153445
/workspace/coverage/default/39.sysrst_ctrl_smoke.3173590477
/workspace/coverage/default/39.sysrst_ctrl_stress_all.560771112
/workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3254569333
/workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3955909615
/workspace/coverage/default/4.sysrst_ctrl_alert_test.4140993824
/workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.132085807
/workspace/coverage/default/4.sysrst_ctrl_combo_detect.672222047
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.268218985
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3561475462
/workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3716591815
/workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3034428443
/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3293588788
/workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1953899735
/workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.2948919834
/workspace/coverage/default/4.sysrst_ctrl_pin_access_test.477217443
/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1984173018
/workspace/coverage/default/4.sysrst_ctrl_sec_cm.193017893
/workspace/coverage/default/4.sysrst_ctrl_smoke.2770079274
/workspace/coverage/default/4.sysrst_ctrl_stress_all.4257480654
/workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1927331193
/workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.4170591059
/workspace/coverage/default/40.sysrst_ctrl_alert_test.4115358716
/workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.125165606
/workspace/coverage/default/40.sysrst_ctrl_combo_detect.458968563
/workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.2315227829
/workspace/coverage/default/40.sysrst_ctrl_edge_detect.3596276150
/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2693665238
/workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.764831725
/workspace/coverage/default/40.sysrst_ctrl_pin_access_test.4042556924
/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2382652377
/workspace/coverage/default/40.sysrst_ctrl_smoke.3593480818
/workspace/coverage/default/40.sysrst_ctrl_stress_all.214832980
/workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.3680943016
/workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.3719735362
/workspace/coverage/default/41.sysrst_ctrl_alert_test.770223997
/workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.1510294905
/workspace/coverage/default/41.sysrst_ctrl_combo_detect.1558661145
/workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2241040130
/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1867273432
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.778523954
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.850603684
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3261803294
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.458019567
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2521884377
/workspace/coverage/default/41.sysrst_ctrl_smoke.1881437324
/workspace/coverage/default/41.sysrst_ctrl_stress_all.3982501542
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2361031948
/workspace/coverage/default/42.sysrst_ctrl_alert_test.3167592651
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4256778440
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1031494760
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2150876779
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.459130351
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3465226346
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.158184547
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.3323253297
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.1039601323
/workspace/coverage/default/42.sysrst_ctrl_smoke.1017823799
/workspace/coverage/default/42.sysrst_ctrl_stress_all.3557338726
/workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3692397214
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3931358809
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1926880106
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.545049176
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.1753137327
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.21080474
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.761373522
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.286986954
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2563032510
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2838213520
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.1104540280
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3993900242
/workspace/coverage/default/43.sysrst_ctrl_smoke.3610902564
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2726654233
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.4126708328
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3624278081
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.1858067119
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1894044422
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.3779816861
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.4236759502
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.1468914388
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2099390335
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2140079813
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2704009361
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.519934680
/workspace/coverage/default/44.sysrst_ctrl_smoke.2309323755
/workspace/coverage/default/44.sysrst_ctrl_stress_all.3195872151
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1761085503
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.2952064772
/workspace/coverage/default/45.sysrst_ctrl_alert_test.602627881
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.750666384
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3696662538
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.228424497
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3699807162
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3159692750
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.221725762
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.1095176368
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.785619862
/workspace/coverage/default/45.sysrst_ctrl_smoke.2071838351
/workspace/coverage/default/45.sysrst_ctrl_stress_all.3277107868
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3361948426
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2719781515
/workspace/coverage/default/46.sysrst_ctrl_alert_test.751674780
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.769194489
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3100326330
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1671919614
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.1342598484
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.3905667504
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1181111284
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.622007199
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3272791614
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1724433102
/workspace/coverage/default/46.sysrst_ctrl_smoke.4059604732
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1934737461
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.2575909715
/workspace/coverage/default/47.sysrst_ctrl_alert_test.3945853764
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.301403371
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.1828129102
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3499185969
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.152586865
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1922129224
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2824764228
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.4125602281
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2814403158
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.3303452684
/workspace/coverage/default/47.sysrst_ctrl_smoke.3969052206
/workspace/coverage/default/47.sysrst_ctrl_stress_all.4110389741
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3642633432
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1603310721
/workspace/coverage/default/48.sysrst_ctrl_alert_test.1855171276
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3518394554
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.457349087
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.867082089
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3047611199
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1803863515
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.2276557788
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2813833161
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.130047663
/workspace/coverage/default/48.sysrst_ctrl_smoke.2239399020
/workspace/coverage/default/48.sysrst_ctrl_stress_all.652830895
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3919539162
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3873666175
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1984283345
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2673415780
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.480801061
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.798818475
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1019835347
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3236401848
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.191247360
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.2812451941
/workspace/coverage/default/49.sysrst_ctrl_smoke.4019800403
/workspace/coverage/default/49.sysrst_ctrl_stress_all.4218995747
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2349923825
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1911480985
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2538875585
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2558708448
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.23724404
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.15889498
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.1836587609
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2174958714
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.4175148422
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3389282188
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1907310036
/workspace/coverage/default/5.sysrst_ctrl_smoke.1666233613
/workspace/coverage/default/5.sysrst_ctrl_stress_all.2488379927
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2156226820
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2781635757
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.167888791
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1247787388
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.467220073
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.271664248
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.322870412
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.2880086562
/workspace/coverage/default/6.sysrst_ctrl_alert_test.2578003879
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.2832371958
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3807604617
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2279109483
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1659044520
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.504054984
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.806255952
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.2203136923
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.4001106160
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.2512899519
/workspace/coverage/default/6.sysrst_ctrl_smoke.2025540307
/workspace/coverage/default/6.sysrst_ctrl_stress_all.27950254
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2573925369
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.833266246
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1340396734
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.75078043
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1994087706
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3566341037
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4137779198
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.880167149
/workspace/coverage/default/7.sysrst_ctrl_alert_test.3447085704
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.1330140542
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2339931261
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2676555252
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.3535915203
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3224470942
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1918140003
/workspace/coverage/default/7.sysrst_ctrl_smoke.1315020255
/workspace/coverage/default/7.sysrst_ctrl_stress_all.3692906769
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1298874871
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2650443490
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2333581217
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2358782241
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3730554087
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.735976467
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.2523020253
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2973486081
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.748875683
/workspace/coverage/default/8.sysrst_ctrl_alert_test.337360570
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3366604625
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.3975544239
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1703256233
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3132746955
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.817255757
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.509199985
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3925195753
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3991044691
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.35572608
/workspace/coverage/default/8.sysrst_ctrl_smoke.614608596
/workspace/coverage/default/8.sysrst_ctrl_stress_all.2964584911
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3346808987
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.18740593
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3385841890
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1316502702
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.2476692366
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2273241979
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.599021623
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.3079567112
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3364474583
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4129034939
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3406951248
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1291966488
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3475171228
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.512817055
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.1688234371
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2257693343
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.2551948911
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1036506309
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.1834001817
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.2641882102
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.496214247
/workspace/coverage/default/9.sysrst_ctrl_smoke.2391095235
/workspace/coverage/default/9.sysrst_ctrl_stress_all.2438324653
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3829984442
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.3111094599
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2936012958
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.954260791
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4280511982
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.101745900
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3030373518
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3321871071
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.990459407
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1606785446

Total test records in report: 921

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T6	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3761560864	Feb 04 04:25:09 PM PST 24	Feb 04 04:25:14 PM PST 24	2023337626 ps
T7	/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.2029958878	Feb 04 04:24:57 PM PST 24	Feb 04 04:25:06 PM PST 24	2017253483 ps
T8	/workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2716310951	Feb 04 04:25:12 PM PST 24	Feb 04 04:25:16 PM PST 24	2023423739 ps
T1	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.2430616587	Feb 04 04:24:23 PM PST 24	Feb 04 04:25:04 PM PST 24	9758313819 ps
T2	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.4212258738	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:13 PM PST 24	2130731159 ps
T3	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.237257807	Feb 04 04:24:25 PM PST 24	Feb 04 04:24:30 PM PST 24	6098750804 ps
T4	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.1979170567	Feb 04 04:24:19 PM PST 24	Feb 04 04:24:24 PM PST 24	2621730122 ps
T24	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2122889019	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:14 PM PST 24	2176105760 ps
T25	/workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2754330454	Feb 04 04:25:14 PM PST 24	Feb 04 04:25:18 PM PST 24	2016823263 ps
T26	/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1031701741	Feb 04 04:25:10 PM PST 24	Feb 04 04:25:12 PM PST 24	2031135847 ps
T27	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.973182452	Feb 04 04:24:19 PM PST 24	Feb 04 04:24:27 PM PST 24	2014641079 ps
T28	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3072708812	Feb 04 04:24:32 PM PST 24	Feb 04 04:24:39 PM PST 24	2019331649 ps
T9	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3349244699	Feb 04 04:25:00 PM PST 24	Feb 04 04:25:04 PM PST 24	2185733824 ps
T10	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.3951103250	Feb 04 04:24:41 PM PST 24	Feb 04 04:25:10 PM PST 24	22240553336 ps
T11	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2593528862	Feb 04 04:25:07 PM PST 24	Feb 04 04:26:07 PM PST 24	22186660473 ps
T12	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.2137067736	Feb 04 04:24:21 PM PST 24	Feb 04 04:24:26 PM PST 24	2199971365 ps
T304	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.3751079962	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:45 PM PST 24	2138386221 ps
T291	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.1286476909	Feb 04 04:24:52 PM PST 24	Feb 04 04:24:57 PM PST 24	2455061235 ps
T387	/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.3280372141	Feb 04 04:25:10 PM PST 24	Feb 04 04:25:13 PM PST 24	2023108731 ps
T59	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.4218066296	Feb 04 04:24:19 PM PST 24	Feb 04 04:24:26 PM PST 24	4021885948 ps
T5	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.416466724	Feb 04 04:25:00 PM PST 24	Feb 04 04:25:17 PM PST 24	11422245555 ps
T294	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3733782085	Feb 04 04:24:56 PM PST 24	Feb 04 04:25:02 PM PST 24	2462484662 ps
T323	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1803619582	Feb 04 04:24:30 PM PST 24	Feb 04 04:24:33 PM PST 24	2069012532 ps
T13	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.626226331	Feb 04 04:24:55 PM PST 24	Feb 04 04:25:56 PM PST 24	42439556014 ps
T35	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2718992515	Feb 04 04:24:28 PM PST 24	Feb 04 04:24:34 PM PST 24	3268960734 ps
T297	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.2941163021	Feb 04 04:24:23 PM PST 24	Feb 04 04:24:50 PM PST 24	22243879509 ps
T405	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.212830740	Feb 04 04:24:53 PM PST 24	Feb 04 04:25:01 PM PST 24	2023609067 ps
T36	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2220964887	Feb 04 04:24:28 PM PST 24	Feb 04 04:24:31 PM PST 24	2065004942 ps
T406	/workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.714641371	Feb 04 04:25:09 PM PST 24	Feb 04 04:25:14 PM PST 24	2021650440 ps
T324	/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.3513248330	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:15 PM PST 24	2027125311 ps
T395	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.598140009	Feb 04 04:24:40 PM PST 24	Feb 04 04:24:49 PM PST 24	2013127338 ps
T37	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.374071117	Feb 04 04:25:00 PM PST 24	Feb 04 04:25:30 PM PST 24	9688253347 ps
T38	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2663114957	Feb 04 04:24:31 PM PST 24	Feb 04 04:24:38 PM PST 24	5255478179 ps
T407	/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.3395022146	Feb 04 04:24:59 PM PST 24	Feb 04 04:25:08 PM PST 24	2010016474 ps
T325	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.2310663125	Feb 04 04:25:02 PM PST 24	Feb 04 04:25:07 PM PST 24	2023486664 ps
T408	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.857378314	Feb 04 04:24:30 PM PST 24	Feb 04 04:24:33 PM PST 24	2024471074 ps
T327	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3708344481	Feb 04 04:24:39 PM PST 24	Feb 04 04:24:47 PM PST 24	2039575101 ps
T305	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.722602963	Feb 04 04:24:20 PM PST 24	Feb 04 04:24:27 PM PST 24	3329853799 ps
T295	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3096573865	Feb 04 04:24:47 PM PST 24	Feb 04 04:24:54 PM PST 24	2379097277 ps
T409	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.3179697981	Feb 04 04:24:38 PM PST 24	Feb 04 04:24:49 PM PST 24	2011826811 ps
T410	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1288471672	Feb 04 04:24:22 PM PST 24	Feb 04 04:24:29 PM PST 24	2078560598 ps
T312	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3071678036	Feb 04 04:24:58 PM PST 24	Feb 04 04:25:03 PM PST 24	2232401936 ps
T335	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1657084303	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:49 PM PST 24	2045348125 ps
T311	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2256526270	Feb 04 04:24:24 PM PST 24	Feb 04 04:24:43 PM PST 24	22265695545 ps
T313	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2115970754	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:58 PM PST 24	5280300349 ps
T303	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3061652649	Feb 04 04:24:49 PM PST 24	Feb 04 04:25:25 PM PST 24	42782028567 ps
T328	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.4071571254	Feb 04 04:24:32 PM PST 24	Feb 04 04:24:52 PM PST 24	19272111710 ps
T411	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3658852621	Feb 04 04:24:21 PM PST 24	Feb 04 04:24:24 PM PST 24	2035768379 ps
T412	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3780758327	Feb 04 04:24:53 PM PST 24	Feb 04 04:25:02 PM PST 24	2036734555 ps
T299	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1941282728	Feb 04 04:24:13 PM PST 24	Feb 04 04:24:20 PM PST 24	2098928261 ps
T296	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1783479088	Feb 04 04:24:52 PM PST 24	Feb 04 04:24:58 PM PST 24	2090853780 ps
T298	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2010572029	Feb 04 04:24:22 PM PST 24	Feb 04 04:24:27 PM PST 24	2224392070 ps
T413	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.824872896	Feb 04 04:24:39 PM PST 24	Feb 04 04:24:45 PM PST 24	2043857452 ps
T329	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.533556717	Feb 04 04:24:42 PM PST 24	Feb 04 04:24:50 PM PST 24	2053364114 ps
T326	/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.3126160697	Feb 04 04:25:09 PM PST 24	Feb 04 04:25:13 PM PST 24	2028668149 ps
T300	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2736388508	Feb 04 04:25:00 PM PST 24	Feb 04 04:26:03 PM PST 24	22241898211 ps
T314	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3479962601	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:45 PM PST 24	2192812600 ps
T414	/workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2726272067	Feb 04 04:25:18 PM PST 24	Feb 04 04:25:23 PM PST 24	2025629128 ps
T415	/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.700593395	Feb 04 04:24:57 PM PST 24	Feb 04 04:25:06 PM PST 24	2010616013 ps
T416	/workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1086377590	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:14 PM PST 24	2031284261 ps
T417	/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.665697478	Feb 04 04:25:09 PM PST 24	Feb 04 04:25:12 PM PST 24	2039271482 ps
T418	/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.354195074	Feb 04 04:25:09 PM PST 24	Feb 04 04:25:15 PM PST 24	2011126814 ps
T419	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.1577152405	Feb 04 04:24:31 PM PST 24	Feb 04 04:25:01 PM PST 24	10685816863 ps
T420	/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.4236203598	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:15 PM PST 24	2019517500 ps
T421	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3404113845	Feb 04 04:24:46 PM PST 24	Feb 04 04:24:54 PM PST 24	2069002357 ps
T330	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.61797451	Feb 04 04:24:31 PM PST 24	Feb 04 04:24:39 PM PST 24	2041339221 ps
T422	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.3684227951	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:47 PM PST 24	2077387739 ps
T423	/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.2627741640	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:13 PM PST 24	2032203083 ps
T424	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2414407115	Feb 04 04:24:40 PM PST 24	Feb 04 04:24:50 PM PST 24	2013451173 ps
T331	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.2924330470	Feb 04 04:24:32 PM PST 24	Feb 04 04:24:50 PM PST 24	6011859312 ps
T301	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.2701229884	Feb 04 04:24:32 PM PST 24	Feb 04 04:24:40 PM PST 24	2301393951 ps
T315	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.1300287583	Feb 04 04:24:17 PM PST 24	Feb 04 04:24:21 PM PST 24	2082263748 ps
T425	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2882108458	Feb 04 04:24:20 PM PST 24	Feb 04 04:24:23 PM PST 24	2123065906 ps
T426	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2224451737	Feb 04 04:24:47 PM PST 24	Feb 04 04:24:53 PM PST 24	2051380299 ps
T359	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1455463602	Feb 04 04:24:37 PM PST 24	Feb 04 04:25:21 PM PST 24	22268904901 ps
T316	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1857393343	Feb 04 04:24:20 PM PST 24	Feb 04 04:24:23 PM PST 24	2120000984 ps
T302	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.626931522	Feb 04 04:24:51 PM PST 24	Feb 04 04:24:58 PM PST 24	2060968332 ps
T334	/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2076389145	Feb 04 04:25:01 PM PST 24	Feb 04 04:25:07 PM PST 24	2080788564 ps
T427	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.160876289	Feb 04 04:24:46 PM PST 24	Feb 04 04:24:52 PM PST 24	2069063629 ps
T428	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.846485690	Feb 04 04:24:40 PM PST 24	Feb 04 04:24:45 PM PST 24	2126366975 ps
T317	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3931270947	Feb 04 04:24:17 PM PST 24	Feb 04 04:24:54 PM PST 24	8602470754 ps
T429	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1473366864	Feb 04 04:24:58 PM PST 24	Feb 04 04:26:38 PM PST 24	42375672306 ps
T430	/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1182205388	Feb 04 04:24:52 PM PST 24	Feb 04 04:24:55 PM PST 24	2049044757 ps
T431	/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.2539614550	Feb 04 04:25:13 PM PST 24	Feb 04 04:25:16 PM PST 24	2099352439 ps
T318	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.593974088	Feb 04 04:24:18 PM PST 24	Feb 04 04:24:50 PM PST 24	37823905456 ps
T332	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3292392215	Feb 04 04:24:21 PM PST 24	Feb 04 04:24:30 PM PST 24	18398961867 ps
T319	/workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.818832333	Feb 04 04:24:38 PM PST 24	Feb 04 04:24:47 PM PST 24	2056254571 ps
T432	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.2207623863	Feb 04 04:24:29 PM PST 24	Feb 04 04:24:31 PM PST 24	2324966495 ps
T433	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.775133889	Feb 04 04:24:57 PM PST 24	Feb 04 04:25:11 PM PST 24	9983959953 ps
T434	/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2742993966	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:52 PM PST 24	8136896843 ps
T435	/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.1846236362	Feb 04 04:24:19 PM PST 24	Feb 04 04:24:23 PM PST 24	2042078933 ps
T320	/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2318306235	Feb 04 04:24:52 PM PST 24	Feb 04 04:25:04 PM PST 24	9939441883 ps
T321	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.1350541706	Feb 04 04:24:21 PM PST 24	Feb 04 04:24:25 PM PST 24	3031398027 ps
T436	/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.1365150246	Feb 04 04:24:45 PM PST 24	Feb 04 04:25:02 PM PST 24	11266461306 ps
T437	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2670109530	Feb 04 04:24:50 PM PST 24	Feb 04 04:25:11 PM PST 24	5098127674 ps
T322	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2733664602	Feb 04 04:24:44 PM PST 24	Feb 04 04:24:48 PM PST 24	2279678105 ps
T438	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2060067519	Feb 04 04:24:22 PM PST 24	Feb 04 04:25:07 PM PST 24	38495521403 ps
T439	/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2101344335	Feb 04 04:25:04 PM PST 24	Feb 04 04:25:11 PM PST 24	2016135490 ps
T440	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2566929793	Feb 04 04:24:18 PM PST 24	Feb 04 04:24:24 PM PST 24	9895007996 ps
T441	/workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2713869120	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:15 PM PST 24	2028356801 ps
T442	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2222636501	Feb 04 04:24:55 PM PST 24	Feb 04 04:25:02 PM PST 24	2059252288 ps
T443	/workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.1510958073	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:50 PM PST 24	2011756239 ps
T356	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2736945973	Feb 04 04:24:32 PM PST 24	Feb 04 04:25:03 PM PST 24	42901775068 ps
T444	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.77304288	Feb 04 04:24:21 PM PST 24	Feb 04 04:24:54 PM PST 24	42907049187 ps
T445	/workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3237660833	Feb 04 04:25:11 PM PST 24	Feb 04 04:25:18 PM PST 24	2012496700 ps
T446	/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3106686109	Feb 04 04:24:21 PM PST 24	Feb 04 04:24:28 PM PST 24	2050402468 ps
T447	/workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.558046266	Feb 04 04:25:17 PM PST 24	Feb 04 04:25:23 PM PST 24	2021398352 ps
T448	/workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.1004486672	Feb 04 04:25:09 PM PST 24	Feb 04 04:25:16 PM PST 24	2013125590 ps
T333	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3048534696	Feb 04 04:24:33 PM PST 24	Feb 04 04:24:42 PM PST 24	2366968004 ps
T449	/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1295652150	Feb 04 04:24:20 PM PST 24	Feb 04 04:24:28 PM PST 24	4015442582 ps
T404	/workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3133785108	Feb 04 04:24:31 PM PST 24	Feb 04 04:24:36 PM PST 24	2149525277 ps
T450	/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.4267522497	Feb 04 04:24:52 PM PST 24	Feb 04 04:26:49 PM PST 24	42459512328 ps
T357	/workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1686032539	Feb 04 04:24:34 PM PST 24	Feb 04 04:24:53 PM PST 24	22465951361 ps
T451	/workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1542712451	Feb 04 04:25:13 PM PST 24	Feb 04 04:25:20 PM PST 24	2009472155 ps
T452	/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.2700824540	Feb 04 04:24:25 PM PST 24	Feb 04 04:30:24 PM PST 24	76626930448 ps
T453	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2687971487	Feb 04 04:24:32 PM PST 24	Feb 04 04:24:38 PM PST 24	2212572999 ps
T454	/workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3761664582	Feb 04 04:24:41 PM PST 24	Feb 04 04:24:45 PM PST 24	2076300464 ps
T455	/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.3685134692	Feb 04 04:24:50 PM PST 24	Feb 04 04:24:55 PM PST 24	2394588373 ps
T456	/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1101804755	Feb 04 04:25:12 PM PST 24	Feb 04 04:25:20 PM PST 24	2037244215 ps
T457	/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.423179028	Feb 04 04:24:40 PM PST 24	Feb 04 04:25:03 PM PST 24	8323149700 ps
T458	/workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.366275204	Feb 04 04:24:29 PM PST 24	Feb 04 04:24:35 PM PST 24	7496475077 ps
T39	/workspace/coverage/default/28.sysrst_ctrl_smoke.1059470783	Feb 04 01:30:09 PM PST 24	Feb 04 01:30:14 PM PST 24	2118418359 ps
T40	/workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2988518152	Feb 04 01:28:49 PM PST 24	Feb 04 01:28:58 PM PST 24	2615687147 ps
T41	/workspace/coverage/default/4.sysrst_ctrl_smoke.2770079274	Feb 04 01:27:53 PM PST 24	Feb 04 01:27:58 PM PST 24	2118756181 ps
T14	/workspace/coverage/default/47.sysrst_ctrl_edge_detect.1922129224	Feb 04 01:31:42 PM PST 24	Feb 04 01:31:52 PM PST 24	5416864402 ps
T29	/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.622007199	Feb 04 01:31:35 PM PST 24	Feb 04 01:31:44 PM PST 24	2451777803 ps
T30	/workspace/coverage/default/48.sysrst_ctrl_stress_all.652830895	Feb 04 01:31:36 PM PST 24	Feb 04 01:32:09 PM PST 24	11192440200 ps
T31	/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.769194489	Feb 04 01:31:37 PM PST 24	Feb 04 01:31:43 PM PST 24	3352234971 ps
T15	/workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1881242453	Feb 04 01:29:03 PM PST 24	Feb 04 01:29:09 PM PST 24	3431306342 ps
T32	/workspace/coverage/default/23.sysrst_ctrl_alert_test.504934144	Feb 04 01:29:39 PM PST 24	Feb 04 01:29:42 PM PST 24	2037455264 ps
T16	/workspace/coverage/default/35.sysrst_ctrl_stress_all.736009032	Feb 04 01:30:15 PM PST 24	Feb 04 01:31:51 PM PST 24	147401957181 ps
T33	/workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3929994530	Feb 04 01:30:33 PM PST 24	Feb 04 01:30:46 PM PST 24	2619430277 ps
T17	/workspace/coverage/default/30.sysrst_ctrl_stress_all.465554253	Feb 04 01:30:15 PM PST 24	Feb 04 01:30:23 PM PST 24	7400170679 ps
T34	/workspace/coverage/default/25.sysrst_ctrl_alert_test.3107483336	Feb 04 01:29:53 PM PST 24	Feb 04 01:30:00 PM PST 24	2011373015 ps
T18	/workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.103985126	Feb 04 01:30:15 PM PST 24	Feb 04 01:31:12 PM PST 24	46385336980 ps
T62	/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.750666384	Feb 04 01:31:15 PM PST 24	Feb 04 01:31:28 PM PST 24	3684984650 ps
T63	/workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1534673897	Feb 04 01:30:12 PM PST 24	Feb 04 01:30:22 PM PST 24	2611369946 ps
T55	/workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.508445157	Feb 04 01:27:19 PM PST 24	Feb 04 01:27:24 PM PST 24	2352391937 ps
T19	/workspace/coverage/default/28.sysrst_ctrl_edge_detect.1888124905	Feb 04 01:30:10 PM PST 24	Feb 04 01:30:13 PM PST 24	3345370206 ps
T20	/workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.514415840	Feb 04 01:30:33 PM PST 24	Feb 04 01:32:52 PM PST 24	50123812269 ps
T90	/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.2150876779	Feb 04 01:30:57 PM PST 24	Feb 04 01:31:09 PM PST 24	3076102856 ps
T459	/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.867082089	Feb 04 01:31:36 PM PST 24	Feb 04 01:31:49 PM PST 24	3978367259 ps
T21	/workspace/coverage/default/37.sysrst_ctrl_edge_detect.3348532475	Feb 04 01:30:34 PM PST 24	Feb 04 01:30:51 PM PST 24	4043838513 ps
T187	/workspace/coverage/default/15.sysrst_ctrl_alert_test.1533450893	Feb 04 01:29:01 PM PST 24	Feb 04 01:29:10 PM PST 24	2012134365 ps
T22	/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2573925369	Feb 04 01:28:07 PM PST 24	Feb 04 01:28:19 PM PST 24	7296466783 ps
T23	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.268218985	Feb 04 01:27:47 PM PST 24	Feb 04 01:27:59 PM PST 24	2433492426 ps
T188	/workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2800813443	Feb 04 01:28:49 PM PST 24	Feb 04 01:28:53 PM PST 24	2178026076 ps
T189	/workspace/coverage/default/28.sysrst_ctrl_pin_access_test.842508685	Feb 04 01:30:11 PM PST 24	Feb 04 01:30:19 PM PST 24	2161971689 ps
T190	/workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.138908207	Feb 04 01:29:52 PM PST 24	Feb 04 01:29:56 PM PST 24	6266594717 ps
T56	/workspace/coverage/default/48.sysrst_ctrl_combo_detect.457349087	Feb 04 01:31:38 PM PST 24	Feb 04 01:32:44 PM PST 24	140407250573 ps
T86	/workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2892872931	Feb 04 01:29:39 PM PST 24	Feb 04 01:30:30 PM PST 24	78564188648 ps
T42	/workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3234351360	Feb 04 01:30:31 PM PST 24	Feb 04 01:33:22 PM PST 24	690016735646 ps
T43	/workspace/coverage/default/14.sysrst_ctrl_combo_detect.3135957006	Feb 04 01:28:58 PM PST 24	Feb 04 01:35:35 PM PST 24	162734114375 ps
T111	/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3272791614	Feb 04 01:31:41 PM PST 24	Feb 04 01:31:51 PM PST 24	2172301969 ps
T112	/workspace/coverage/default/23.sysrst_ctrl_pin_access_test.253038874	Feb 04 01:29:45 PM PST 24	Feb 04 01:29:51 PM PST 24	2146784176 ps
T44	/workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3134173510	Feb 04 01:27:21 PM PST 24	Feb 04 01:30:18 PM PST 24	72058213886 ps
T91	/workspace/coverage/default/9.sysrst_ctrl_smoke.2391095235	Feb 04 01:28:27 PM PST 24	Feb 04 01:28:31 PM PST 24	2129699073 ps
T92	/workspace/coverage/default/44.sysrst_ctrl_alert_test.3624278081	Feb 04 01:31:11 PM PST 24	Feb 04 01:31:15 PM PST 24	2030415582 ps
T60	/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4280511982	Feb 04 01:32:01 PM PST 24	Feb 04 01:34:40 PM PST 24	78755491071 ps
T53	/workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1549910655	Feb 04 01:29:01 PM PST 24	Feb 04 01:29:48 PM PST 24	237079566001 ps
T121	/workspace/coverage/default/33.sysrst_ctrl_pin_override_test.4223437952	Feb 04 01:30:14 PM PST 24	Feb 04 01:30:19 PM PST 24	2527022352 ps
T460	/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2719781515	Feb 04 01:31:13 PM PST 24	Feb 04 01:31:16 PM PST 24	3085183088 ps
T87	/workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.146202593	Feb 04 01:29:43 PM PST 24	Feb 04 01:30:49 PM PST 24	22311021971 ps
T403	/workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1984173018	Feb 04 01:27:47 PM PST 24	Feb 04 01:27:56 PM PST 24	2528557057 ps
T88	/workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.3797586462	Feb 04 01:29:42 PM PST 24	Feb 04 01:29:51 PM PST 24	3241559471 ps
T461	/workspace/coverage/default/30.sysrst_ctrl_smoke.213427881	Feb 04 01:30:09 PM PST 24	Feb 04 01:30:16 PM PST 24	2111786153 ps
T78	/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3321871071	Feb 04 01:32:05 PM PST 24	Feb 04 01:39:18 PM PST 24	152550854107 ps
T45	/workspace/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.309585041	Feb 04 01:30:39 PM PST 24	Feb 04 01:31:30 PM PST 24	69469396068 ps
T113	/workspace/coverage/default/17.sysrst_ctrl_smoke.871347049	Feb 04 01:28:59 PM PST 24	Feb 04 01:29:08 PM PST 24	2112114034 ps
T114	/workspace/coverage/default/8.sysrst_ctrl_alert_test.337360570	Feb 04 01:28:26 PM PST 24	Feb 04 01:28:29 PM PST 24	2097429124 ps
T115	/workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1839545937	Feb 04 01:30:30 PM PST 24	Feb 04 01:30:40 PM PST 24	2509323419 ps
T116	/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2704009361	Feb 04 01:31:04 PM PST 24	Feb 04 01:31:13 PM PST 24	2162198199 ps
T117	/workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.2715622393	Feb 04 01:30:31 PM PST 24	Feb 04 01:30:35 PM PST 24	2558438908 ps
T118	/workspace/coverage/default/29.sysrst_ctrl_pin_access_test.4218625261	Feb 04 01:30:11 PM PST 24	Feb 04 01:30:19 PM PST 24	2156300791 ps
T48	/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2541396214	Feb 04 01:30:56 PM PST 24	Feb 04 01:31:34 PM PST 24	35191066594 ps
T119	/workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1377185458	Feb 04 01:30:15 PM PST 24	Feb 04 01:30:22 PM PST 24	2619910658 ps
T159	/workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.2576529462	Feb 04 01:29:05 PM PST 24	Feb 04 01:29:16 PM PST 24	3354765067 ps
T210	/workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1312367736	Feb 04 01:30:34 PM PST 24	Feb 04 01:30:50 PM PST 24	2041042893 ps
T211	/workspace/coverage/default/18.sysrst_ctrl_alert_test.3477464927	Feb 04 01:29:04 PM PST 24	Feb 04 01:29:11 PM PST 24	2065005769 ps
T61	/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.2650443490	Feb 04 01:28:11 PM PST 24	Feb 04 01:28:38 PM PST 24	982572486450 ps
T57	/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3535072768	Feb 04 01:31:40 PM PST 24	Feb 04 01:33:22 PM PST 24	185650193826 ps
T462	/workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2493916172	Feb 04 01:29:52 PM PST 24	Feb 04 01:29:55 PM PST 24	2681540237 ps
T463	/workspace/coverage/default/21.sysrst_ctrl_stress_all.1452509760	Feb 04 01:29:18 PM PST 24	Feb 04 01:29:37 PM PST 24	9133528825 ps
T72	/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1031494760	Feb 04 01:31:04 PM PST 24	Feb 04 01:32:49 PM PST 24	76284040003 ps
T51	/workspace/coverage/default/33.sysrst_ctrl_stress_all.3585615568	Feb 04 01:30:14 PM PST 24	Feb 04 01:30:37 PM PST 24	15052498218 ps
T254	/workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3561475462	Feb 04 01:27:50 PM PST 24	Feb 04 01:28:01 PM PST 24	2524358336 ps
T264	/workspace/coverage/default/13.sysrst_ctrl_smoke.2811113498	Feb 04 01:28:54 PM PST 24	Feb 04 01:29:05 PM PST 24	2108562458 ps
T46	/workspace/coverage/default/12.sysrst_ctrl_stress_all.2988265281	Feb 04 01:28:49 PM PST 24	Feb 04 01:28:58 PM PST 24	13404354914 ps
T89	/workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2023348023	Feb 04 01:28:55 PM PST 24	Feb 04 01:29:00 PM PST 24	3697301478 ps
T168	/workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3385256566	Feb 04 01:29:02 PM PST 24	Feb 04 01:29:07 PM PST 24	2118038389 ps
T64	/workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.663500585	Feb 04 01:28:48 PM PST 24	Feb 04 01:28:55 PM PST 24	6235836138 ps
T47	/workspace/coverage/default/18.sysrst_ctrl_edge_detect.730901834	Feb 04 01:29:05 PM PST 24	Feb 04 01:29:18 PM PST 24	3811254882 ps
T169	/workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1130520288	Feb 04 01:29:48 PM PST 24	Feb 04 01:29:57 PM PST 24	2453065399 ps
T170	/workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.2055041705	Feb 04 01:27:21 PM PST 24	Feb 04 01:27:25 PM PST 24	2626000397 ps
T65	/workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.372830561	Feb 04 01:28:57 PM PST 24	Feb 04 01:29:06 PM PST 24	5578643478 ps
T58	/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3406951248	Feb 04 01:31:55 PM PST 24	Feb 04 01:35:48 PM PST 24	93700560458 ps
T93	/workspace/coverage/default/10.sysrst_ctrl_combo_detect.960284955	Feb 04 01:28:55 PM PST 24	Feb 04 01:30:57 PM PST 24	47155736215 ps
T49	/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3047611199	Feb 04 01:31:43 PM PST 24	Feb 04 01:31:51 PM PST 24	2412549744 ps
T269	/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1724433102	Feb 04 01:31:36 PM PST 24	Feb 04 01:31:39 PM PST 24	2635754304 ps
T270	/workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2151544890	Feb 04 01:30:11 PM PST 24	Feb 04 01:30:19 PM PST 24	2513692275 ps
T271	/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.4125602281	Feb 04 01:31:42 PM PST 24	Feb 04 01:31:50 PM PST 24	2511180043 ps
T464	/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3346808987	Feb 04 01:28:24 PM PST 24	Feb 04 01:28:48 PM PST 24	10362631606 ps
T465	/workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.2523085333	Feb 04 01:30:23 PM PST 24	Feb 04 01:30:27 PM PST 24	2490104732 ps
T466	/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.480801061	Feb 04 01:31:37 PM PST 24	Feb 04 01:31:40 PM PST 24	3095986548 ps
T467	/workspace/coverage/default/4.sysrst_ctrl_alert_test.4140993824	Feb 04 01:27:55 PM PST 24	Feb 04 01:28:02 PM PST 24	2039128830 ps
T468	/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1803863515	Feb 04 01:31:43 PM PST 24	Feb 04 01:31:56 PM PST 24	2611909748 ps
T66	/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1717147231	Feb 04 01:30:56 PM PST 24	Feb 04 01:41:31 PM PST 24	1671058033920 ps
T469	/workspace/coverage/default/3.sysrst_ctrl_stress_all.3643258415	Feb 04 01:27:43 PM PST 24	Feb 04 01:28:08 PM PST 24	12203034868 ps
T52	/workspace/coverage/default/36.sysrst_ctrl_edge_detect.2607207824	Feb 04 01:30:16 PM PST 24	Feb 04 01:30:26 PM PST 24	2446845677 ps
T76	/workspace/coverage/default/23.sysrst_ctrl_edge_detect.2572942033	Feb 04 01:29:42 PM PST 24	Feb 04 01:29:51 PM PST 24	4221722955 ps
T191	/workspace/coverage/default/11.sysrst_ctrl_combo_detect.3302794196	Feb 04 01:28:56 PM PST 24	Feb 04 01:32:40 PM PST 24	191998191920 ps
T186	/workspace/coverage/default/4.sysrst_ctrl_edge_detect.3293588788	Feb 04 01:27:51 PM PST 24	Feb 04 01:28:02 PM PST 24	3200002067 ps
T94	/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3807604617	Feb 04 01:28:10 PM PST 24	Feb 04 01:29:13 PM PST 24	24824690025 ps
T192	/workspace/coverage/default/22.sysrst_ctrl_combo_detect.1031335647	Feb 04 01:29:41 PM PST 24	Feb 04 01:31:36 PM PST 24	44426124176 ps
T193	/workspace/coverage/default/20.sysrst_ctrl_stress_all.3322580328	Feb 04 01:29:17 PM PST 24	Feb 04 01:32:23 PM PST 24	190848416548 ps
T194	/workspace/coverage/default/40.sysrst_ctrl_pin_override_test.2382652377	Feb 04 01:30:47 PM PST 24	Feb 04 01:30:52 PM PST 24	2532296231 ps
T195	/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.4175148422	Feb 04 01:27:55 PM PST 24	Feb 04 01:28:03 PM PST 24	2468967711 ps
T196	/workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3001087571	Feb 04 01:30:10 PM PST 24	Feb 04 01:32:20 PM PST 24	92715170889 ps
T197	/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.2814403158	Feb 04 01:31:40 PM PST 24	Feb 04 01:31:48 PM PST 24	2034893846 ps
T470	/workspace/coverage/default/28.sysrst_ctrl_pin_override_test.2751352703	Feb 04 01:30:14 PM PST 24	Feb 04 01:30:18 PM PST 24	2529750378 ps
T471	/workspace/coverage/default/33.sysrst_ctrl_smoke.2799995392	Feb 04 01:30:26 PM PST 24	Feb 04 01:30:28 PM PST 24	2128248609 ps
T265	/workspace/coverage/default/28.sysrst_ctrl_combo_detect.4016786225	Feb 04 01:30:08 PM PST 24	Feb 04 01:31:37 PM PST 24	134881001040 ps
T472	/workspace/coverage/default/15.sysrst_ctrl_pin_override_test.1284223966	Feb 04 01:29:00 PM PST 24	Feb 04 01:29:05 PM PST 24	2537607806 ps
T67	/workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.914959168	Feb 04 01:30:16 PM PST 24	Feb 04 01:30:28 PM PST 24	9096656431 ps
T473	/workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.4280159921	Feb 04 01:29:05 PM PST 24	Feb 04 01:29:18 PM PST 24	2612517221 ps
T54	/workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1192809396	Feb 04 01:30:14 PM PST 24	Feb 04 01:32:53 PM PST 24	90744406090 ps
T474	/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.2257693343	Feb 04 01:28:22 PM PST 24	Feb 04 01:28:32 PM PST 24	3722767988 ps
T155	/workspace/coverage/default/25.sysrst_ctrl_edge_detect.2159734985	Feb 04 01:29:53 PM PST 24	Feb 04 01:29:55 PM PST 24	2498492330 ps
T475	/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.158184547	Feb 04 01:30:55 PM PST 24	Feb 04 01:31:03 PM PST 24	2462892223 ps
T198	/workspace/coverage/default/2.sysrst_ctrl_edge_detect.4184836783	Feb 04 01:27:35 PM PST 24	Feb 04 01:27:39 PM PST 24	3146727543 ps
T476	/workspace/coverage/default/37.sysrst_ctrl_alert_test.1036278036	Feb 04 01:30:31 PM PST 24	Feb 04 01:30:36 PM PST 24	2031832630 ps
T120	/workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3402371004	Feb 04 01:28:59 PM PST 24	Feb 04 01:31:00 PM PST 24	48212652194 ps
T477	/workspace/coverage/default/31.sysrst_ctrl_alert_test.3042029999	Feb 04 01:30:34 PM PST 24	Feb 04 01:30:45 PM PST 24	2031967467 ps
T255	/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.429000215	Feb 04 01:31:47 PM PST 24	Feb 04 01:32:29 PM PST 24	60539519452 ps
T478	/workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3948218418	Feb 04 01:29:24 PM PST 24	Feb 04 01:29:34 PM PST 24	2514401979 ps
T85	/workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3220279470	Feb 04 01:27:34 PM PST 24	Feb 04 01:29:14 PM PST 24	41331538474 ps
T479	/workspace/coverage/default/3.sysrst_ctrl_alert_test.2542500702	Feb 04 01:27:48 PM PST 24	Feb 04 01:27:57 PM PST 24	2023445391 ps
T480	/workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3081328390	Feb 04 01:27:37 PM PST 24	Feb 04 01:27:40 PM PST 24	2267815006 ps
T481	/workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.2881506169	Feb 04 01:27:45 PM PST 24	Feb 04 01:27:56 PM PST 24	3738625069 ps
T482	/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.152586865	Feb 04 01:31:35 PM PST 24	Feb 04 01:31:37 PM PST 24	3165503424 ps
T483	/workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.340078897	Feb 04 01:27:31 PM PST 24	Feb 04 01:27:33 PM PST 24	4908069398 ps
T95	/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1513283063	Feb 04 01:31:38 PM PST 24	Feb 04 01:32:19 PM PST 24	59734004264 ps
T272	/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.3389282188	Feb 04 01:27:46 PM PST 24	Feb 04 01:27:58 PM PST 24	2055689888 ps
T256	/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.4129034939	Feb 04 01:31:55 PM PST 24	Feb 04 01:32:40 PM PST 24	48054490199 ps
T273	/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.1918140003	Feb 04 01:28:14 PM PST 24	Feb 04 01:28:19 PM PST 24	2515537474 ps
T484	/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.301403371	Feb 04 01:31:37 PM PST 24	Feb 04 01:31:50 PM PST 24	3528915953 ps
T257	/workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.731204481	Feb 04 01:29:18 PM PST 24	Feb 04 01:31:56 PM PST 24	56127627742 ps
T485	/workspace/coverage/default/23.sysrst_ctrl_smoke.2862578689	Feb 04 01:29:45 PM PST 24	Feb 04 01:29:54 PM PST 24	2110335680 ps
T486	/workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.2693665238	Feb 04 01:30:55 PM PST 24	Feb 04 01:30:59 PM PST 24	2614652545 ps
T156	/workspace/coverage/default/27.sysrst_ctrl_edge_detect.672348352	Feb 04 01:30:05 PM PST 24	Feb 04 01:30:14 PM PST 24	3448609309 ps