Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1279

1

T15

9

T35

1

T17

1

auto[1]

1858

1

T15

17

T35

10

T17

1

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2570

1

T15

14

T35

11

T17

2

auto[1]

567

1

T15

12

T19

24

T21

1

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2986

1

T15

26

T35

11

T17

2

auto[1]

151

1

T19

6

T20

7

T21

1

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2980

1

T15

24

T35

11

T17

2

auto[1]

157

1

T15

2

T19

3

T20

2

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2984

1

T15

26

T35

11

T17

1

auto[1]

153

1

T17

1

T19

5

T21

1

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1914

1

T15

1

T35

2

T17

2

auto[1]

1223

1

T15

25

T35

9

T19

30

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1279

1

T15

11

T35

11

T17

1

auto[1]

1858

1

T15

15

T17

1

T19

24

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1306

1

T15

9

T35

11

T17

1

auto[1]

1831

1

T15

17

T17

1

T19

24

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1276

1

T15

12

T35

1

T19

12

auto[1]

1861

1

T15

14

T35

10

T17

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1304

1

T15

6

T19

11

T20

4

auto[1]

1833

1

T15

20

T35

11

T17

2

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

50

1

T65

1

T66

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T71

1

T113

1

T326

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T65

2

T66

1

T64

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

17

1

T19

1

T51

3

T113

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

55

1

T35

1

T20

2

T63

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T15

1

T70

1

T83

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T21

1

T69

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T15

1

T19

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

13

1

T15

1

T22

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T69

1

T66

1

T266

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T22

1

T113

2

T167

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T17

1

T20

9

T69

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T19

1

T22

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

35

1

T35

1

T51

1

T59

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

32

1

T35

9

T51

1

T87

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

35

1

T20

1

T69

1

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

21

1

T15

1

T19

1

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T21

1

T24

1

T69

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T113

2

T167

1

T327

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32

1

T21

1

T63

1

T59

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T22

1

T51

1

T326

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T15

1

T63

1

T69

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T326

1

T145

1

T184

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T15

1

T65

2

T87

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T21

2

T24

2

T266

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T22

1

T83

1

T87

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

64

1

T20

2

T24

1

T69

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

32

1

T63

1

T83

3

T87

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

45

1

T24

1

T59

1

T268

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

60

1

T63

8

T51

1

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

45

1

T24

1

T65

2

T66

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T71

1

T133

1

T327

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T21

2

T24

1

T59

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

16

1

T83

3

T95

1

T326

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T20

5

T22

1

T69

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

10

1

T15

1

T51

1

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

54

1

T69

2

T71

1

T263

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T15

2

T22

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T20

1

T21

1

T24

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

19

1

T19

1

T70

1

T113

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

39

1

T59

1

T71

1

T328

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T51

1

T83

1

T113

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

42

1

T20

8

T66

3

T59

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

17

1

T66

2

T71

1

T269

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

69

1

T69

3

T255

1

T284

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

68

1

T15

1

T87

1

T113

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T21

1

T69

1

T66

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T66

7

T70

1

T113

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T21

2

T65

1

T266

11

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

23

1

T71

1

T83

1

T87

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T19

1

T21

2

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T15

1

T267

1

T83

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

88

1

T24

1

T69

1

T64

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T15

1

T70

1

T71

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

55

1

T21

1

T65

1

T77

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T19

1

T22

1

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

71

1

T21

1

T77

1

T59

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

56

1

T15

1

T65

7

T70

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T21

1

T267

2

T95

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

47

1

T15

1

T267

6

T83

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

259

1

T17

1

T19

2

T21

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T51

1

T95

1

T146

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T19

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T15

1

T87

1

T327

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T51

1

T83

1

T87

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T326

1

T289

1

T329

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T51

1

T95

1

T326

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T19

1

T330

3

T331

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T98

1

T332

1

T333

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T15

1

T22

1

T327

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3

1

T70

1

T332

1

T334

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T19

1

T22

1

T133

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T15

1

T19

2

T51

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T22

1

T83

1

T326

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T15

1

T22

1

T71

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T331

1

T332

1

T335

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T83

1

T95

1

T327

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19

1

T15

1

T83

1

T87

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T19

1

T83

2

T133

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T22

1

T336

1

T146

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T184

1

T289

2

T98

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T83

2

T327

1

T332

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T22

1

T184

1

T98

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T19

1

T22

2

T98

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T19

1

T269

3

T337

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T87

1

T281

3

T338

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

12

1

T22

1

T66

4

T95

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T19

1

T327

2

T146

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T19

1

T22

1

T51

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T15

1

T19

1

T71

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

7

1

T19

1

T71

1

T339

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T340

4

T91

1

T184

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T19

1

T51

1

T327

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

158

1

T15

6

T19

11

T22

13

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	29	67	69.79	29
Automatically Generated Cross Bins	96	29	67	69.79	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	*	*	*	*	[auto[1]]	--	--	16
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T65

1

T66

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T19

1

T71

1

T113

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T65

2

T66

1

T71

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T15

1

T19

1

T51

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T35

1

T20

2

T63

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T15

1

T51

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

43

1

T21

1

T69

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T15

1

T19

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T15

1

T22

1

T51

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T69

1

T66

1

T266

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35

1

T19

1

T22

1

T113

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51

1

T17

1

T20

6

T69

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T19

1

T22

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T35

1

T51

1

T59

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T15

1

T35

9

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

40

1

T20

1

T69

1

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T15

1

T19

1

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

48

1

T21

1

T24

2

T69

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T19

1

T22

1

T133

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T21

1

T63

1

T24

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T15

1

T19

2

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T15

1

T63

1

T69

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T22

1

T83

1

T326

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

50

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T15

2

T22

1

T65

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

51

1

T21

3

T24

3

T266

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T22

1

T83

1

T87

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

67

1

T20

2

T24

1

T69

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T63

1

T83

4

T87

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

49

1

T24

1

T59

1

T268

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

79

1

T15

1

T63

8

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T24

1

T65

2

T66

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T19

1

T71

1

T83

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T21

2

T24

1

T59

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T22

1

T83

3

T95

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T20

4

T22

1

T69

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T15

1

T51

1

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55

1

T69

2

T71

1

T263

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T15

2

T22

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T20

1

T21

1

T24

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T19

1

T22

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

38

1

T59

1

T71

1

T328

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T19

1

T22

2

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T20

5

T69

1

T66

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T19

1

T66

2

T71

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

70

1

T24

1

T69

3

T255

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

78

1

T15

1

T87

2

T113

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T21

1

T69

1

T66

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T22

1

T66

11

T70

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

54

1

T21

2

T24

1

T65

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T19

1

T71

1

T83

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T19

1

T21

2

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T15

1

T19

1

T22

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

84

1

T24

1

T69

1

T64

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

43

1

T15

2

T19

1

T70

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T21

1

T65

1

T77

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T19

2

T22

1

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

69

1

T21

1

T77

1

T59

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

71

1

T15

1

T65

7

T70

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

58

1

T21

1

T267

2

T95

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

57

1

T15

1

T19

1

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

182

1

T17

1

T19

2

T21

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

159

1

T15

6

T19

5

T22

13

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T341

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T342

2

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T19

6

T70

1

T80

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	27	69	71.88	27
Automatically Generated Cross Bins	96	27	69	71.88	27
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T65

1

T66

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T19

1

T71

1

T113

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T65

2

T66

1

T71

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T15

1

T19

1

T51

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T35

1

T20

2

T63

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T15

1

T51

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T21

1

T69

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T15

1

T19

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T15

1

T22

1

T51

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T69

1

T266

2

T71

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35

1

T19

1

T22

1

T113

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

52

1

T17

1

T20

9

T69

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T19

1

T22

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39

1

T35

1

T51

1

T59

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T15

1

T35

9

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

39

1

T20

1

T69

1

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T15

1

T19

1

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T21

1

T24

2

T69

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T19

1

T22

1

T133

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T21

1

T63

1

T24

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T15

1

T19

2

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T15

1

T63

1

T69

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T22

1

T83

1

T326

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T15

2

T22

1

T65

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T21

3

T24

3

T266

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T22

1

T83

1

T87

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

65

1

T20

2

T24

1

T69

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T63

1

T83

4

T87

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

45

1

T24

1

T59

1

T268

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

79

1

T15

1

T63

8

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T24

1

T65

2

T66

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T19

1

T71

1

T83

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T21

2

T24

1

T59

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T22

1

T83

3

T95

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

50

1

T20

3

T22

1

T69

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T15

1

T51

1

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55

1

T69

2

T71

1

T263

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T15

2

T22

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T20

1

T21

1

T24

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T19

1

T22

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T59

1

T71

1

T328

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T19

1

T22

2

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T20

8

T69

1

T66

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T19

1

T66

2

T71

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

72

1

T24

1

T69

3

T255

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

78

1

T15

1

T87

2

T113

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

43

1

T21

1

T69

1

T66

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T22

1

T66

11

T70

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

57

1

T21

2

T24

1

T65

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T19

1

T71

1

T83

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

49

1

T19

1

T21

2

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

36

1

T15

1

T19

1

T22

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

92

1

T24

1

T69

1

T64

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T15

2

T19

1

T70

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

56

1

T21

1

T65

1

T77

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T19

2

T22

1

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

72

1

T21

1

T77

1

T59

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

70

1

T15

1

T65

7

T70

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T21

1

T267

2

T95

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

57

1

T15

1

T19

1

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

167

1

T17

1

T19

2

T21

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

148

1

T15

4

T19

8

T22

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T343

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1

1

T341

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

1

1

T344

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T340

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

29

1

T15

2

T19

3

T22

6

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

52

1

T65

1

T66

1

T64

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T19

1

T71

1

T113

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

59

1

T65

2

T66

1

T71

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T15

1

T19

1

T51

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

57

1

T35

1

T20

2

T63

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

14

1

T15

1

T51

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T21

1

T69

1

T70

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

30

1

T15

1

T19

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

51

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T15

1

T22

1

T51

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T69

1

T66

1

T266

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

35

1

T19

1

T22

1

T113

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T17

1

T20

9

T69

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

24

1

T19

1

T22

1

T51

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

37

1

T35

1

T51

1

T59

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

37

1

T15

1

T35

9

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

40

1

T20

1

T69

1

T65

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T15

1

T19

1

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T21

1

T24

2

T69

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T19

1

T22

1

T133

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

34

1

T21

1

T63

1

T24

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

30

1

T15

1

T19

2

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

38

1

T15

1

T63

1

T69

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

35

1

T22

1

T83

1

T326

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T20

1

T21

1

T24

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T15

2

T22

1

T65

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T21

3

T24

3

T266

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T22

1

T83

1

T87

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

67

1

T20

2

T24

1

T69

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

45

1

T63

1

T83

4

T87

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

46

1

T24

1

T59

1

T268

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

79

1

T15

1

T63

8

T51

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T24

1

T65

2

T66

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T19

1

T71

1

T83

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

56

1

T21

2

T24

1

T59

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

26

1

T22

1

T83

3

T95

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T20

5

T22

1

T69

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T15

1

T51

1

T87

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

57

1

T69

2

T71

1

T263

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T15

2

T22

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T20

1

T21

1

T24

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

29

1

T19

1

T22

1

T70

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T59

1

T71

1

T328

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T19

1

T22

2

T51

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

47

1

T20

8

T69

1

T66

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T19

1

T66

2

T71

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

74

1

T24

1

T69

3

T255

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

78

1

T15

1

T87

2

T113

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T21

1

T69

1

T66

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

31

1

T22

1

T66

11

T70

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

49

1

T21

2

T24

1

T65

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T19

1

T71

1

T83

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T19

1

T21

2

T64

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T15

1

T19

1

T22

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

91

1

T24

1

T69

1

T64

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T15

2

T19

1

T70

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T21

1

T65

1

T77

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T19

2

T22

1

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

73

1

T21

1

T77

1

T59

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

71

1

T15

1

T65

7

T70

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T21

1

T95

1

T255

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

57

1

T15

1

T19

1

T51

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

172

1

T21

1

T24

7

T69

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

150

1

T15

6

T19

8

T22

13

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3

1

T93

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T19

3

T71

1

T95

1

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded